From: Prarit Bhargava <prarit@redhat.com>

Subject: mcelog: Add decoding for Optane DC persistent memory mode

commit d1f37aae14d476af6260af01904aed0f2e942542
Author: Tony Luck <tony.luck@intel.com>
Date:   Tue Feb 5 10:10:38 2019 -0800

    mcelog: Add decoding for Optane DC persistent memory mode
    
    Recognise the new MCACOD for errors in DDR memory in use as a cache
    for Optane DC persistent memory.
    
    In binary the new code looks similar to the old memory controller
    compound error code. The only difference is that bit 9 is set in
    addition to bit 7:
    
            000F 0010 1MMM CCCC
    
    Signed-off-by: Tony Luck <tony.luck@intel.com>
    Signed-off-by: Andi Kleen <ak@linux.intel.com>

diff --git a/p4.c b/p4.c
index adb4c5eab976edf2c99efddd65e6abfcfeb97da2..8e1ec2fe435f0883c5146fa55e8e703713236d0a 100644
--- a/p4.c
+++ b/p4.c
@@ -199,6 +199,9 @@ static int decode_mca(u64 status, u64 misc, u64 track, int cpu, int *ismemerr, i
 					      CACHE_RRRR_SHIFT));
 		if (track == 2)
 			run_yellow_trigger(cpu, typenum, levelnum, type, level,socket);
+	} else if (test_prefix(9, mca) && EXTRACT(mca, 7, 8) == 1) {
+		Wprintf("Memory as cache: ");
+		decode_memory_controller(mca, bank);
 	} else if (test_prefix(10, mca)) {
 		if (mca == 0x400)
 			Wprintf("Internal Timer error\n");