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From: Prarit Bhargava <prarit@redhat.com>
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Subject: mcelog: Add decoding for Optane DC persistent memory mode
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commit d1f37aae14d476af6260af01904aed0f2e942542
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Author: Tony Luck <tony.luck@intel.com>
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Date: Tue Feb 5 10:10:38 2019 -0800
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mcelog: Add decoding for Optane DC persistent memory mode
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Recognise the new MCACOD for errors in DDR memory in use as a cache
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for Optane DC persistent memory.
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In binary the new code looks similar to the old memory controller
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compound error code. The only difference is that bit 9 is set in
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addition to bit 7:
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000F 0010 1MMM CCCC
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Signed-off-by: Tony Luck <tony.luck@intel.com>
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Signed-off-by: Andi Kleen <ak@linux.intel.com>
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diff --git a/p4.c b/p4.c
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index adb4c5eab976edf2c99efddd65e6abfcfeb97da2..8e1ec2fe435f0883c5146fa55e8e703713236d0a 100644
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--- a/p4.c
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+++ b/p4.c
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@@ -199,6 +199,9 @@ static int decode_mca(u64 status, u64 misc, u64 track, int cpu, int *ismemerr, i
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CACHE_RRRR_SHIFT));
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if (track == 2)
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run_yellow_trigger(cpu, typenum, levelnum, type, level,socket);
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+ } else if (test_prefix(9, mca) && EXTRACT(mca, 7, 8) == 1) {
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+ Wprintf("Memory as cache: ");
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+ decode_memory_controller(mca, bank);
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} else if (test_prefix(10, mca)) {
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if (mca == 0x400)
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Wprintf("Internal Timer error\n");
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