Blob Blame History Raw
diff --git a/src/papi_events.csv b/src/papi_events.csv
index dbbc8d8..1d91bb0 100644
--- a/src/papi_events.csv
+++ b/src/papi_events.csv
@@ -1497,6 +1497,29 @@ PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS
 PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL
 PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL
 #
+CPU,arm_xgene
+#
+PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
+PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
+PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP
+PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD
+PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC
+PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
+PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS
+PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS
+PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS
+PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_CACHE_REFILL
+PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS
+PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS
+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
+PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
+PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS
+PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
+PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS
+PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS
+PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL
+PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL
+#
 CPU,mips_74k
 #
 PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES