From f39735be3c1157fdfa7dd5c781048a411ebe4dc5 Mon Sep 17 00:00:00 2001
From: Dan Williams <dan.j.williams@intel.com>
Date: Sun, 23 Jan 2022 16:53:34 -0800
Subject: [PATCH 106/217] cxl/list: Add 'host' entries for port-like objects

Add the device name of the "host" device for a given CXL port object. The
kernel calls this the 'uport' attribute.

Link: https://lore.kernel.org/r/164298561473.3021641.16508989603599026269.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
---
 Documentation/cxl/cxl-list.txt   |  9 +++++++++
 Documentation/cxl/lib/libcxl.txt |  5 +++++
 cxl/json.c                       |  4 ++++
 cxl/lib/libcxl.c                 | 10 ++++++++++
 cxl/lib/libcxl.sym               |  2 ++
 cxl/libcxl.h                     |  2 ++
 6 files changed, 32 insertions(+)

diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt
index d342da2..30b6161 100644
--- a/Documentation/cxl/cxl-list.txt
+++ b/Documentation/cxl/cxl-list.txt
@@ -210,6 +210,15 @@ OPTIONS
 --endpoints::
 	Include endpoint objects (CXL Memory Device decoders) in the
 	listing.
+----
+# cxl list -E
+[
+  {
+    "endpoint":"endpoint2",
+    "host":"mem0"
+  }
+]
+----
 
 -e::
 --endpoint::
diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
index eebab37..e4b372d 100644
--- a/Documentation/cxl/lib/libcxl.txt
+++ b/Documentation/cxl/lib/libcxl.txt
@@ -178,6 +178,7 @@ struct cxl_port *cxl_port_get_next(struct cxl_port *port);
 struct cxl_port *cxl_port_get_parent(struct cxl_port *port);
 struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
 struct cxl_ctx *cxl_port_get_ctx(struct cxl_port *port);
+const char *cxl_port_get_host(struct cxl_port *port);
 
 #define cxl_port_foreach(parent, port)                                      \
        for (port = cxl_port_get_first(parent); port != NULL;                \
@@ -192,6 +193,9 @@ as a parent object retrievable via cxl_port_get_parent().
 The root port of a hiearchy can be retrieved via any port instance in
 that hierarchy via cxl_port_get_bus().
 
+The host of a port is the corresponding device name of the PCIe Root
+Port, or Switch Upstream Port with CXL capabilities.
+
 === PORT: Attributes
 ----
 const char *cxl_port_get_devname(struct cxl_port *port);
@@ -222,6 +226,7 @@ struct cxl_endpoint *cxl_endpoint_get_next(struct cxl_endpoint *endpoint);
 struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint);
 struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
 struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
+const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint);
 
 #define cxl_endpoint_foreach(port, endpoint)                                 \
        for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL;       \
diff --git a/cxl/json.c b/cxl/json.c
index 08f6192..af3b4fe 100644
--- a/cxl/json.c
+++ b/cxl/json.c
@@ -258,6 +258,10 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port,
 	if (jobj)
 		json_object_object_add(jport, name_key, jobj);
 
+	jobj = json_object_new_string(cxl_port_get_host(port));
+	if (jobj)
+		json_object_object_add(jport, "host", jobj);
+
 	if (!cxl_port_is_enabled(port)) {
 		jobj = json_object_new_string("disabled");
 		if (jobj)
diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
index a25e715..5f48202 100644
--- a/cxl/lib/libcxl.c
+++ b/cxl/lib/libcxl.c
@@ -626,6 +626,11 @@ CXL_EXPORT struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint)
 	return &endpoint->port;
 }
 
+CXL_EXPORT const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint)
+{
+	return cxl_port_get_host(&endpoint->port);
+}
+
 CXL_EXPORT int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint)
 {
 	return cxl_port_is_enabled(&endpoint->port);
@@ -744,6 +749,11 @@ CXL_EXPORT struct cxl_bus *cxl_port_get_bus(struct cxl_port *port)
 	return bus;
 }
 
+CXL_EXPORT const char *cxl_port_get_host(struct cxl_port *port)
+{
+	return devpath_to_devname(port->uport);
+}
+
 CXL_EXPORT int cxl_port_is_enabled(struct cxl_port *port)
 {
 	struct cxl_ctx *ctx = cxl_port_get_ctx(port);
diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
index 7a51a0c..dc2863e 100644
--- a/cxl/lib/libcxl.sym
+++ b/cxl/lib/libcxl.sym
@@ -95,6 +95,7 @@ global:
 	cxl_port_to_bus;
 	cxl_port_is_endpoint;
 	cxl_port_get_bus;
+	cxl_port_get_host;
 	cxl_endpoint_get_first;
 	cxl_endpoint_get_next;
 	cxl_endpoint_get_devname;
@@ -103,4 +104,5 @@ global:
 	cxl_endpoint_is_enabled;
 	cxl_endpoint_get_parent;
 	cxl_endpoint_get_port;
+	cxl_endpoint_get_host;
 } LIBCXL_1;
diff --git a/cxl/libcxl.h b/cxl/libcxl.h
index f6ba9a1..a60777e 100644
--- a/cxl/libcxl.h
+++ b/cxl/libcxl.h
@@ -83,6 +83,7 @@ bool cxl_port_is_switch(struct cxl_port *port);
 struct cxl_bus *cxl_port_to_bus(struct cxl_port *port);
 bool cxl_port_is_endpoint(struct cxl_port *port);
 struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
+const char *cxl_port_get_host(struct cxl_port *port);
 
 #define cxl_port_foreach(parent, port)                                         \
 	for (port = cxl_port_get_first(parent); port != NULL;                  \
@@ -97,6 +98,7 @@ struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint);
 int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint);
 struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
 struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
+const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint);
 
 #define cxl_endpoint_foreach(port, endpoint)                                   \
 	for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL;        \
-- 
2.27.0