commit 773759843a1c66b9b829da21d45f7bb76aa802bc
Author: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Date: Wed Feb 19 11:17:59 2014 +0100
s390/cpumf: update event defintions
Update the cpumf counter (event) definitions. The changes are required to
easily update the defintions in future.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h
index 9628cee..b1ad8fc 100644
--- a/lib/events/s390x_cpumf_events.h
+++ b/lib/events/s390x_cpumf_events.h
@@ -6,14 +6,14 @@
#define STRINGIFY(x) __stringify(x)
/* CPUMF counter sets */
-#define CPUMF_CTRSET_BASIC 0
-#define CPUMF_CTRSET_PROBLEM_STATE 1
-#define CPUMF_CTRSET_CRYPTO 2
-#define CPUMF_CTRSET_EXTENDED 3
+#define CPUMF_CTRSET_NONE 0
+#define CPUMF_CTRSET_BASIC 2
+#define CPUMF_CTRSET_PROBLEM_STATE 4
+#define CPUMF_CTRSET_CRYPTO 8
+#define CPUMF_CTRSET_EXTENDED 1
-static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
- /* Basic counter set */
+static const pme_cpumf_ctr_t cpumcf_generic_counters[] = {
{
.ctrnum = 0,
.ctrset = CPUMF_CTRSET_BASIC,
@@ -29,7 +29,7 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
{
.ctrnum = 2,
.ctrset = CPUMF_CTRSET_BASIC,
- .name = "L1I_DRCT_WRITES",
+ .name = "L1I_DIR_WRITES",
.desc = "Level-1 I-Cache Directory Write Count",
},
{
@@ -41,7 +41,7 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
{
.ctrnum = 4,
.ctrset = CPUMF_CTRSET_BASIC,
- .name = "L1D_DRCT_WRITES",
+ .name = "L1D_DIR_WRITES",
.desc = "Level-1 D-Cache Directory Write Count",
},
{
@@ -50,7 +50,6 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
.name = "L1D_PENALTY_CYCLES",
.desc = "Level-1 D-Cache Penalty Cycle Count",
},
- /* Problem-state counter set */
{
.ctrnum = 32,
.ctrset = CPUMF_CTRSET_PROBLEM_STATE,
@@ -66,7 +65,7 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
{
.ctrnum = 34,
.ctrset = CPUMF_CTRSET_PROBLEM_STATE,
- .name = "PROBLEM_STATE_L1I_DRCT_WRITES",
+ .name = "PROBLEM_STATE_L1I_DIR_WRITES",
.desc = "Problem-State Level-1 I-Cache Directory Write Count",
},
{
@@ -78,7 +77,7 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
{
.ctrnum = 36,
.ctrset = CPUMF_CTRSET_PROBLEM_STATE,
- .name = "PROBLEM_STATE_L1D_DRCT_WRITES",
+ .name = "PROBLEM_STATE_L1D_DIR_WRITES",
.desc = "Problem-State Level-1 D-Cache Directory Write Count",
},
{
@@ -87,38 +86,38 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
.name = "PROBLEM_STATE_L1D_PENALTY_CYCLES",
.desc = "Problem-State Level-1 D-Cache Penalty Cycle Count",
},
- /* Crypto-activity counter set */
{
.ctrnum = 64,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "PRNG_FUNCTIONS",
- .desc = "Total number of the PRNG functions issued by the CPU",
+ .desc = "Total number of the PRNG functions issued by the"
+ " CPU",
},
{
.ctrnum = 65,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "PRNG_CYCLES",
- .desc = "Total number of CPU cycles when the DEA/AES "
- "coprocessor is busy performing PRNG functions "
- "issued by the CPU",
+ .desc = "Total number of CPU cycles when the DEA/AES"
+ " coprocessor is busy performing PRNG functions"
+ " issued by the CPU",
},
{
.ctrnum = 66,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "PRNG_BLOCKED_FUNCTIONS",
- .desc = "Total number of the PRNG functions that are issued "
- "by the CPU and are blocked because the DEA/AES "
- "coprocessor is busy performing a function issued "
- "by another CPU",
+ .desc = "Total number of the PRNG functions that are issued"
+ " by the CPU and are blocked because the DEA/AES"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 67,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "PRNG_BLOCKED_CYCLES",
- .desc = "Total number of CPU cycles blocked for the PRNG "
- "functions issued by the CPU because the DEA/AES "
- "coprocessor is busy performing a function issued "
- "by another CPU",
+ .desc = "Total number of CPU cycles blocked for the PRNG"
+ " functions issued by the CPU because the DEA/AES"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 68,
@@ -130,26 +129,27 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
.ctrnum = 69,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "SHA_CYCLES",
- .desc = "Total number of CPU cycles when the SHA coprocessor "
- "is busy performing the SHA functions issued by the "
- "CPU",
+ .desc = "Total number of CPU cycles when the SHA coprocessor"
+ " is busy performing the SHA functions issued by the"
+ " CPU",
},
{
.ctrnum = 70,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "SHA_BLOCKED_FUNCTIONS",
- .desc = "Total number of the SHA functions that are issued by "
- "the CPU and are blocked because the SHA coprocessor "
- "is busy performing a function issued by another CPU",
+ .desc = "Total number of the SHA functions that are issued"
+ " by the CPU and are blocked because the SHA"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 71,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "SHA_BLOCKED_CYCLES",
- .desc = "Total number of CPU cycles blocked for the SHA "
- "functions issued by the CPU because the SHA "
- "coprocessor is busy performing a function issued by "
- "another CPU",
+ .desc = "Total number of CPU cycles blocked for the SHA"
+ " functions issued by the CPU because the SHA"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 72,
@@ -161,24 +161,27 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
.ctrnum = 73,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "DEA_CYCLES",
- .desc = "Total number of CPU cycles when the DEA/AES coprocessor"
- " is busy performing the DEA functions issued by the CPU",
+ .desc = "Total number of CPU cycles when the DEA/AES"
+ " coprocessor is busy performing the DEA functions"
+ " issued by the CPU",
},
{
.ctrnum = 74,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "DEA_BLOCKED_FUNCTIONS",
- .desc = "Total number of the DEA functions that are issued by "
- "the CPU and are blocked because the DEA/AES coprocessor"
- " is busy performing a function issued by another CPU",
+ .desc = "Total number of the DEA functions that are issued"
+ " by the CPU and are blocked because the DEA/AES"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 75,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "DEA_BLOCKED_CYCLES",
- .desc = "Total number of CPU cycles blocked for the DEA functions"
- " issued by the CPU because the DEA/AES coprocessor is "
- "busy performing a function issued by another CPU",
+ .desc = "Total number of CPU cycles blocked for the DEA"
+ " functions issued by the CPU because the DEA/AES"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 76,
@@ -190,29 +193,31 @@ static const pme_cpumf_ctr_t cpumf_generic_ctr[] = {
.ctrnum = 77,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "AES_CYCLES",
- .desc = "Total number of CPU cycles when the DEA/AES coprocessor"
- " is busy performing the AES functions issued by the CPU",
+ .desc = "Total number of CPU cycles when the DEA/AES"
+ " coprocessor is busy performing the AES functions"
+ " issued by the CPU",
},
{
.ctrnum = 78,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "AES_BLOCKED_FUNCTIONS",
- .desc = "Total number of AES functions that are issued by the CPU"
- " and are blocked because the DEA/AES coprocessor is"
- " busy performing a function issued by another CPU",
+ .desc = "Total number of AES functions that are issued by"
+ " the CPU and are blocked because the DEA/AES"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
{
.ctrnum = 79,
.ctrset = CPUMF_CTRSET_CRYPTO,
.name = "AES_BLOCKED_CYCLES",
- .desc = "Total number of CPU cycles blocked for the AES functions"
- " issued by the CPU because the DEA/AES coprocessor is"
- " busy performing a function issued by another CPU",
+ .desc = "Total number of CPU cycles blocked for the AES"
+ " functions issued by the CPU because the DEA/AES"
+ " coprocessor is busy performing a function issued by"
+ " another CPU",
},
};
-/* Extended counter set for IBM System z10 */
-static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z10[] = {
+static const pme_cpumf_ctr_t cpumcf_z10_counters[] = {
{
.ctrnum = 128,
.ctrset = CPUMF_CTRSET_EXTENDED,
@@ -243,9 +248,9 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z10[] = {
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "L1D_L3_LOCAL_WRITES",
.desc = "A directory write to the Level-1 D-Cache directory"
- " where the installtion cache line was source from the"
- " Level-3 cache that is on the same book as the Data"
- " cache (Local L2 cache)",
+ " where the installtion cache line was source from"
+ " the Level-3 cache that is on the same book as the"
+ " Data cache (Local L2 cache)",
},
{
.ctrnum = 132,
@@ -297,15 +302,15 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z10[] = {
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "L1I_CACHELINE_INVALIDATES",
.desc = "A cache line in the Level-1 I-Cache has been"
- " invalidated by a store on the same CPU as the Level-1"
- " I-Cache",
+ " invalidated by a store on the same CPU as the"
+ " Level-1 I-Cache",
},
{
.ctrnum = 138,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "ITLB1_WRITES",
- .desc = "A translation entry has been written into the Level-1"
- " Instruction Translation Lookaside Buffer",
+ .desc = "A translation entry has been written into the"
+ " Level-1 Instruction Translation Lookaside Buffer",
},
{
.ctrnum = 139,
@@ -340,27 +345,27 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z10[] = {
.ctrnum = 145,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "ITLB1_MISSES",
- .desc = "Level-1 Instruction TLB miss in progress. Incremented"
- " by one for every cycle an ITLB1 miss is in progress",
+ .desc = "Level-1 Instruction TLB miss in progress."
+ " Incremented by one for every cycle an ITLB1 miss is"
+ " in progress",
},
{
.ctrnum = 146,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "DTLB1_MISSES",
- .desc = "Level-1 Data TLB miss in progress. Incremented by one"
- " for every cycle an DTLB1 miss is in progress",
+ .desc = "Level-1 Data TLB miss in progress. Incremented by"
+ " one for every cycle an DTLB1 miss is in progress",
},
{
.ctrnum = 147,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "L2C_STORES_SENT",
- .desc = "Incremented by one for every store sent to"
- " Level-2 (L1.5) cache",
+ .desc = "Incremented by one for every store sent to Level-2"
+ " (L1.5) cache",
},
};
-/* Extended counter set for IBM zEnterprise 196 */
-static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
+static const pme_cpumf_ctr_t cpumcf_z196_counters[] = {
{
.ctrnum = 128,
.ctrset = CPUMF_CTRSET_EXTENDED,
@@ -374,29 +379,30 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "L1I_L2_SOURCED_WRITES",
.desc = "A directory write to the Level-1 I-Cache directory"
- " where the returned cache line was sourced from"
- " the Level-2 cache",
+ " where the returned cache line was sourced from the"
+ " Level-2 cache",
},
{
.ctrnum = 130,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "DTLB1_MISSES",
- .desc = "Level-1 Data TLB miss in progress. Incremented by one"
- " for every cycle a DTLB1 miss is in progress.",
+ .desc = "Level-1 Data TLB miss in progress. Incremented by"
+ " one for every cycle a DTLB1 miss is in progress.",
},
{
.ctrnum = 131,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "ITLB1_MISSES",
- .desc = "Level-1 Instruction TLB miss in progress. Incremented"
- " by one for every cycle a ITLB1 miss is in progress.",
+ .desc = "Level-1 Instruction TLB miss in progress."
+ " Incremented by one for every cycle a ITLB1 miss is"
+ " in progress.",
},
{
.ctrnum = 133,
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "L2C_STORES_SENT",
- .desc = "Incremented by one for every store sent to"
- " Level-2 cache",
+ .desc = "Incremented by one for every store sent to Level-2"
+ " cache",
},
{
.ctrnum = 134,
@@ -452,8 +458,8 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
.ctrset = CPUMF_CTRSET_EXTENDED,
.name = "DTLB1_HPAGE_WRITES",
.desc = "A translation entry has been written to the Level-1"
- " Data Translation Lookaside Buffer for a one-megabyte"
- " page",
+ " Data Translation Lookaside Buffer for a one-"
+ " megabyte page",
},
{
.ctrnum = 141,
@@ -520,7 +526,7 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
{
.ctrnum = 150,
.ctrset = CPUMF_CTRSET_EXTENDED,
- .name = "L1D_ONCHIP_L3_WRITES",
+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES",
.desc = "A directory write to the Level-1 D-Cache directory"
" where the returned cache line was sourced from an"
" On Chip Level-3 cache",
@@ -528,7 +534,7 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
{
.ctrnum = 152,
.ctrset = CPUMF_CTRSET_EXTENDED,
- .name = "L1D_OFFCHIP_L3_WRITES",
+ .name = "L1D_OFFCHIP_L3_SOURCED_WRITES",
.desc = "A directory write to the Level-1 D-Cache directory"
" where the returned cache line was sourced from an"
" Off Chip/On Book Level-3 cache",
@@ -536,7 +542,7 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
{
.ctrnum = 153,
.ctrset = CPUMF_CTRSET_EXTENDED,
- .name = "L1I_ONCHIP_L3_WRITES",
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES",
.desc = "A directory write to the Level-1 I-Cache directory"
" where the returned cache line was sourced from an"
" On Chip Level-3 cache",
@@ -544,19 +550,11 @@ static const pme_cpumf_ctr_t cpumf_ctr_set_ext_z196[] = {
{
.ctrnum = 155,
.ctrset = CPUMF_CTRSET_EXTENDED,
- .name = "L1I_OFFCHIP_L3_WRITES",
+ .name = "L1I_OFFCHIP_L3_SOURCED_WRITES",
.desc = "A directory write to the Level-1 I-Cache directory"
" where the returned cache line was sourced from an"
" Off Chip/On Book Level-3 cache",
},
};
-#if 0
- {
- .ctrnum = ,
- .ctrset = CPUMF_CTRSET_EXTENDED,
- .name = "",
- .desc = "",
- },
-#endif
#endif /* __S390X_CPUMF_EVENTS_H__ */
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
index d424466..e216bd2 100644
--- a/lib/pfmlib_s390x_cpumf.c
+++ b/lib/pfmlib_s390x_cpumf.c
@@ -107,13 +107,13 @@ static int pfm_cpumcf_init(void *this)
switch (get_machine_type()) {
case 2097: /* IBM System z10 EC */
case 2098: /* IBM System z10 BC */
- ext_set = cpumf_ctr_set_ext_z10;
- ext_set_count = LIBPFM_ARRAY_SIZE(cpumf_ctr_set_ext_z10);
+ ext_set = cpumcf_z10_counters,
+ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z10_counters);
break;
case 2817: /* IBM zEnterprise 196 */
case 2818: /* IBM zEnterprise 114 */
- ext_set = cpumf_ctr_set_ext_z196;
- ext_set_count = LIBPFM_ARRAY_SIZE(cpumf_ctr_set_ext_z196);
+ ext_set = cpumcf_z196_counters;
+ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z196_counters);
break;
default:
/* No extended counter set for this machine type or there
@@ -123,13 +123,14 @@ static int pfm_cpumcf_init(void *this)
break;
}
- generic_count = LIBPFM_ARRAY_SIZE(cpumf_generic_ctr);
+ generic_count = LIBPFM_ARRAY_SIZE(cpumcf_generic_counters);
cpumcf_pe = calloc(sizeof(*cpumcf_pe), generic_count + ext_set_count);
if (cpumcf_pe == NULL)
return PFM_ERR_NOMEM;
- memcpy(cpumcf_pe, cpumf_generic_ctr, sizeof(*cpumcf_pe) * generic_count);
+ memcpy(cpumcf_pe, cpumcf_generic_counters,
+ sizeof(*cpumcf_pe) * generic_count);
if (ext_set_count)
memcpy((void *) (cpumcf_pe + generic_count),
ext_set, sizeof(*cpumcf_pe) * ext_set_count);
@@ -250,8 +251,8 @@ pfmlib_pmu_t s390x_cpum_cf_support = {
.num_fixed_cntrs = CPUMF_COUNTER_MAX, /* fixed counters only */
.max_encoding = 1,
- .pe = cpumf_generic_ctr,
- .pme_count = LIBPFM_ARRAY_SIZE(cpumf_generic_ctr),
+ .pe = cpumcf_generic_counters,
+ .pme_count = LIBPFM_ARRAY_SIZE(cpumcf_generic_counters),
.pmu_detect = pfm_cpumcf_detect,
.pmu_init = pfm_cpumcf_init,
commit a4b9c236d635c62bbe94e9d504efac9b8db20961
Author: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Date: Wed Feb 19 11:18:00 2014 +0100
s390/cpumf: add extended counter support for IBM zEC12
Add counter definitions for IBM zEnterprise EC12 specific counters in the
extended counter set.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h
index b1ad8fc..5e27fe6 100644
--- a/lib/events/s390x_cpumf_events.h
+++ b/lib/events/s390x_cpumf_events.h
@@ -557,4 +557,287 @@ static const pme_cpumf_ctr_t cpumcf_z196_counters[] = {
},
};
+static const pme_cpumf_ctr_t cpumcf_zec12_counters[] = {
+ {
+ .ctrnum = 128,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "DTLB1_MISSES",
+ .desc = "Level-1 Data TLB miss in progress. Incremented by"
+ " one for every cycle a DTLB1 miss is in progress.",
+ },
+ {
+ .ctrnum = 129,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "ITLB1_MISSES",
+ .desc = "Level-1 Instruction TLB miss in progress."
+ " Incremented by one for every cycle a ITLB1 miss is"
+ " in progress.",
+ },
+ {
+ .ctrnum = 130,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_L2I_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from the Level-2 Instruction cache",
+ },
+ {
+ .ctrnum = 131,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_L2I_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from the Level-2 Instruction cache",
+ },
+ {
+ .ctrnum = 132,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_L2D_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from the Level-2 Data cache",
+ },
+ {
+ .ctrnum = 133,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "DTLB1_WRITES",
+ .desc = "A translation entry has been written to the Level-1"
+ " Data Translation Lookaside Buffer",
+ },
+ {
+ .ctrnum = 135,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_LMEM_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache where"
+ " the installed cache line was sourced from memory"
+ " that is attached to the same book as the Data cache"
+ " (Local Memory)",
+ },
+ {
+ .ctrnum = 137,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_LMEM_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " where the installed cache line was sourced from"
+ " memory that is attached to the same book as the"
+ " Instruction cache (Local Memory)",
+ },
+ {
+ .ctrnum = 138,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_RO_EXCL_WRITES",
+ .desc = "A directory write to the Level-1 D-Cache where the"
+ " line was originally in a Read-Only state in the"
+ " cache but has been updated to be in the Exclusive"
+ " state that allows stores to the cache line",
+ },
+ {
+ .ctrnum = 139,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "DTLB1_HPAGE_WRITES",
+ .desc = "A translation entry has been written to the Level-1"
+ " Data Translation Lookaside Buffer for a one-"
+ " megabyte page",
+ },
+ {
+ .ctrnum = 140,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "ITLB1_WRITES",
+ .desc = "A translation entry has been written to the Level-1"
+ " Instruction Translation Lookaside Buffer",
+ },
+ {
+ .ctrnum = 141,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TLB2_PTE_WRITES",
+ .desc = "A translation entry has been written to the Level-2"
+ " TLB Page Table Entry arrays",
+ },
+ {
+ .ctrnum = 142,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TLB2_CRSTE_HPAGE_WRITES",
+ .desc = "A translation entry has been written to the Level-2"
+ " TLB Common Region Segment Table Entry arrays for a"
+ " one-megabyte large page translation",
+ },
+ {
+ .ctrnum = 143,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TLB2_CRSTE_WRITES",
+ .desc = "A translation entry has been written to the Level-2"
+ " TLB Common Region Segment Table Entry arrays",
+ },
+ {
+ .ctrnum = 144,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an On Chip Level-3 cache without intervention",
+ },
+ {
+ .ctrnum = 145,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_OFFCHIP_L3_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Chip/On Book Level-3 cache without"
+ " intervention",
+ },
+ {
+ .ctrnum = 146,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_OFFBOOK_L3_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Book Level-3 cache without intervention",
+ },
+ {
+ .ctrnum = 147,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_ONBOOK_L4_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an On Book Level-4 cache",
+ },
+ {
+ .ctrnum = 148,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_OFFBOOK_L4_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Book Level-4 cache",
+ },
+ {
+ .ctrnum = 149,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TX_NC_TEND",
+ .desc = "A TEND instruction has completed in a"
+ " nonconstrained transactional-execution mode",
+ },
+ {
+ .ctrnum = 150,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from a On Chip Level-3 cache with intervention",
+ },
+ {
+ .ctrnum = 151,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Chip/On Book Level-3 cache with"
+ " intervention",
+ },
+ {
+ .ctrnum = 152,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
+ .desc = "A directory write to the Level-1 Data cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Book Level-3 cache with intervention",
+ },
+ {
+ .ctrnum = 153,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an On Chip Level-3 cache without intervention",
+ },
+ {
+ .ctrnum = 154,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_OFFCHIP_L3_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Chip/On Book Level-3 cache without"
+ " intervention",
+ },
+ {
+ .ctrnum = 155,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_OFFBOOK_L3_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Book Level-3 cache without intervention",
+ },
+ {
+ .ctrnum = 156,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_ONBOOK_L4_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an On Book Level-4 cache",
+ },
+ {
+ .ctrnum = 157,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_OFFBOOK_L4_SOURCED_WRITES",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Book Level-4 cache",
+ },
+ {
+ .ctrnum = 158,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TX_C_TEND",
+ .desc = "A TEND instruction has completed in a constrained"
+ " transactional-execution mode",
+ },
+ {
+ .ctrnum = 159,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an On Chip Level-3 cache with intervention",
+ },
+ {
+ .ctrnum = 160,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Chip/On Book Level-3 cache with"
+ " intervention",
+ },
+ {
+ .ctrnum = 161,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
+ .desc = "A directory write to the Level-1 Instruction cache"
+ " directory where the returned cache line was sourced"
+ " from an Off Book Level-3 cache with intervention",
+ },
+ {
+ .ctrnum = 177,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TX_NC_TABORT",
+ .desc = "A transaction abort has occurred in a"
+ " nonconstrained transactional-execution mode",
+ },
+ {
+ .ctrnum = 178,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TX_C_TABORT_NO_SPECIAL",
+ .desc = "A transaction abort has occurred in a constrained"
+ " transactional-execution mode and the CPU is not"
+ " using any special logic to allow the transaction to"
+ " complete",
+ },
+ {
+ .ctrnum = 179,
+ .ctrset = CPUMF_CTRSET_EXTENDED,
+ .name = "TX_C_TABORT_SPECIAL",
+ .desc = "A transaction abort has occurred in a constrained"
+ " transactional-execution mode and the CPU is using"
+ " special logic to allow the transaction to complete",
+ },
+};
+
#endif /* __S390X_CPUMF_EVENTS_H__ */
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
index e216bd2..e3aaaf0 100644
--- a/lib/pfmlib_s390x_cpumf.c
+++ b/lib/pfmlib_s390x_cpumf.c
@@ -115,6 +115,11 @@ static int pfm_cpumcf_init(void *this)
ext_set = cpumcf_z196_counters;
ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z196_counters);
break;
+ case 2827: /* IBM zEnterprise EC12 */
+ case 2828: /* IBM zEnterprise BC12 */
+ ext_set = cpumcf_zec12_counters;
+ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_zec12_counters);
+ break;
default:
/* No extended counter set for this machine type or there
* was an error retrieving the machine type */
diff --git a/lib/pfmlib_s390x_priv.h b/lib/pfmlib_s390x_priv.h
index 45259f2..22c775a 100644
--- a/lib/pfmlib_s390x_priv.h
+++ b/lib/pfmlib_s390x_priv.h
@@ -1,7 +1,7 @@
#ifndef __PFMLIB_S390X_PRIV_H__
#define __PFMLIB_S390X_PRIV_H__
-#define CPUMF_COUNTER_MAX 160
+#define CPUMF_COUNTER_MAX 256
typedef struct {
uint64_t ctrnum; /* counter number */
unsigned int ctrset; /* counter set */
commit 85a82c1343ded403ce9d3c16fc5cd5ab16e3e85c
Author: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Date: Wed Feb 19 11:18:01 2014 +0100
s390/cpumf: add support for the CPU-measurement sampling facility
Add support for the sampling facility to allow hardware-based sampling using
CPU cycles. The cpum_sf PMU provides two perf events supporting available
sampling functions.
Many existing pfmlib functions of the counter facility support (cpum_cf) have
been reused.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h
index ccd3211..dfdd471 100644
--- a/include/perfmon/pfmlib.h
+++ b/include/perfmon/pfmlib.h
@@ -235,6 +235,8 @@ typedef enum {
PFM_PMU_ARM_CORTEX_A53, /* ARM Cortex A53 (ARMv8) */
PFM_PMU_ARM_XGENE, /* Applied Micro X-Gene (ARMv8) */
+ PFM_PMU_S390X_CPUM_SF, /* s390x: CPU-M sampling facility */
+
/* MUST ADD NEW PMU MODELS HERE */
PFM_PMU_MAX /* end marker */
diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h
index 5e27fe6..e00b088 100644
--- a/lib/events/s390x_cpumf_events.h
+++ b/lib/events/s390x_cpumf_events.h
@@ -840,4 +840,20 @@ static const pme_cpumf_ctr_t cpumcf_zec12_counters[] = {
},
};
+static const pme_cpumf_ctr_t cpumsf_counters[] = {
+ {
+ .ctrnum = 720896,
+ .ctrset = CPUMF_CTRSET_NONE,
+ .name = "SF_CYCLES_BASIC",
+ .desc = "Sample CPU cycles using basic-sampling mode",
+ },
+ {
+ .ctrnum = 774144,
+ .ctrset = CPUMF_CTRSET_NONE,
+ .name = "SF_CYCLES_BASIC_DIAG",
+ .desc = "Sample CPU cycle using diagnostic-sampling mode"
+ " (not for ordinary use)",
+ },
+};
+
#endif /* __S390X_CPUMF_EVENTS_H__ */
diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c
index cd68301..8e4b1a1 100644
--- a/lib/pfmlib_common.c
+++ b/lib/pfmlib_common.c
@@ -202,6 +202,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]=
#ifdef CONFIG_PFMLIB_ARCH_S390X
&s390x_cpum_cf_support,
+ &s390x_cpum_sf_support,
#endif
#ifdef __linux__
&perf_event_support,
diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h
index 2b5d33e..715c4b0 100644
--- a/lib/pfmlib_priv.h
+++ b/lib/pfmlib_priv.h
@@ -334,6 +334,7 @@ extern pfmlib_pmu_t arm_1176_support;
extern pfmlib_pmu_t arm_xgene_support;
extern pfmlib_pmu_t mips_74k_support;
extern pfmlib_pmu_t s390x_cpum_cf_support;
+extern pfmlib_pmu_t s390x_cpum_sf_support;
extern pfmlib_os_t *pfmlib_os;
extern pfmlib_os_t pfmlib_os_perf;
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
index e3aaaf0..db2a215 100644
--- a/lib/pfmlib_s390x_cpumf.c
+++ b/lib/pfmlib_s390x_cpumf.c
@@ -1,7 +1,7 @@
/*
- * PMU support for the CPU-measurement counter facility
+ * PMU support for the CPU-measurement facilities
*
- * Copyright IBM Corp. 2012
+ * Copyright IBM Corp. 2012, 2014
* Contributed by Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -34,17 +34,25 @@
#include "events/s390x_cpumf_events.h"
-#define CPUMF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_cf"
-#define SYS_INFO "/proc/sysinfo"
+#define CPUM_CF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_cf"
+#define CPUM_SF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_sf"
+#define SYS_INFO "/proc/sysinfo"
/* CPU-measurement counter list (pmu events) */
static pme_cpumf_ctr_t *cpumcf_pe = NULL;
-/* Detect the CPU-measurement facility */
+/* Detect the CPU-measurement counter and sampling facilities */
static int pfm_cpumcf_detect(void *this)
{
- if (access(CPUMF_DEVICE_DIR, R_OK))
+ if (access(CPUM_CF_DEVICE_DIR, R_OK))
+ return PFM_ERR_NOTSUPP;
+ return PFM_SUCCESS;
+}
+
+static int pfm_cpumsf_detect(void *this)
+{
+ if (access(CPUM_SF_DEVICE_DIR, R_OK))
return PFM_ERR_NOTSUPP;
return PFM_SUCCESS;
}
@@ -156,7 +164,7 @@ static void pfm_cpumcf_exit(void *this)
free(cpumcf_pe);
}
-static int pfm_cpumcf_get_encoding(void *this, pfmlib_event_desc_t *e)
+static int pfm_cpumf_get_encoding(void *this, pfmlib_event_desc_t *e)
{
const pme_cpumf_ctr_t *pe = this_pe(this);
@@ -167,12 +175,12 @@ static int pfm_cpumcf_get_encoding(void *this, pfmlib_event_desc_t *e)
return PFM_SUCCESS;
}
-static int pfm_cpumcf_get_event_first(void *this)
+static int pfm_cpumf_get_event_first(void *this)
{
return 0;
}
-static int pfm_cpumcf_get_event_next(void *this, int idx)
+static int pfm_cpumf_get_event_next(void *this, int idx)
{
pfmlib_pmu_t *pmu = this;
@@ -181,26 +189,20 @@ static int pfm_cpumcf_get_event_next(void *this, int idx)
return idx + 1;
}
-static int pfm_cpumcf_event_is_valid(void *this, int idx)
+static int pfm_cpumf_event_is_valid(void *this, int idx)
{
pfmlib_pmu_t *pmu = this;
return (idx >= 0 && idx < pmu->pme_count);
}
-static int pfm_cpumcf_validate_table(void *this, FILE *fp)
+static int pfm_cpumf_validate_table(void *this, FILE *fp)
{
pfmlib_pmu_t *pmu = this;
const pme_cpumf_ctr_t *pe = this_pe(this);
int i, rc;
rc = PFM_ERR_INVAL;
- if (pmu->pme_count > CPUMF_COUNTER_MAX) {
- fprintf(fp, "pmu: %s: pme number exceeded maximum\n",
- pmu->name);
- goto failed;
- }
-
for (i = 0; i < pmu->pme_count; i++) {
if (!pe[i].name) {
fprintf(fp, "pmu: %s event: %i: No name\n",
@@ -219,7 +221,20 @@ failed:
return rc;
}
-static int pfm_cpumcf_get_event_info(void *this, int idx,
+static int pfm_cpumcf_validate_table(void *this, FILE *fp)
+{
+ pfmlib_pmu_t *pmu = this;
+
+ if (pmu->pme_count > CPUMF_COUNTER_MAX) {
+ fprintf(fp, "pmu: %s: pme number exceeded maximum\n",
+ pmu->name);
+ return PFM_ERR_INVAL;
+ }
+
+ return pfm_cpumf_validate_table(this, fp);
+}
+
+static int pfm_cpumf_get_event_info(void *this, int idx,
pfm_event_info_t *info)
{
pfmlib_pmu_t *pmu = this;
@@ -238,7 +253,7 @@ static int pfm_cpumcf_get_event_info(void *this, int idx,
return PFM_SUCCESS;
}
-static int pfm_cpumcf_get_event_attr_info(void *this, int idx, int umask_idx,
+static int pfm_cpumf_get_event_attr_info(void *this, int idx, int umask_idx,
pfm_event_attr_info_t *info)
{
/* Attributes are not supported */
@@ -263,12 +278,38 @@ pfmlib_pmu_t s390x_cpum_cf_support = {
.pmu_init = pfm_cpumcf_init,
.pmu_terminate = pfm_cpumcf_exit,
- .get_event_encoding[PFM_OS_NONE] = pfm_cpumcf_get_encoding,
+ .get_event_encoding[PFM_OS_NONE] = pfm_cpumf_get_encoding,
PFMLIB_ENCODE_PERF(pfm_s390x_get_perf_encoding),
- .get_event_first = pfm_cpumcf_get_event_first,
- .get_event_next = pfm_cpumcf_get_event_next,
- .event_is_valid = pfm_cpumcf_event_is_valid,
+ .get_event_first = pfm_cpumf_get_event_first,
+ .get_event_next = pfm_cpumf_get_event_next,
+ .event_is_valid = pfm_cpumf_event_is_valid,
.validate_table = pfm_cpumcf_validate_table,
- .get_event_info = pfm_cpumcf_get_event_info,
- .get_event_attr_info = pfm_cpumcf_get_event_attr_info,
+ .get_event_info = pfm_cpumf_get_event_info,
+ .get_event_attr_info = pfm_cpumf_get_event_attr_info,
+};
+
+pfmlib_pmu_t s390x_cpum_sf_support = {
+ .desc = "CPU-measurement sampling facility",
+ .name = "cpum_sf",
+ .pmu = PFM_PMU_S390X_CPUM_SF,
+ .type = PFM_PMU_TYPE_CORE,
+ .flags = PFMLIB_PMU_FL_ARCH_DFL,
+
+ .num_cntrs = 0, /* no general-purpose counters */
+ .num_fixed_cntrs = 2, /* fixed counters only */
+ .max_encoding = 1,
+
+ .pe = cpumsf_counters,
+ .pme_count = LIBPFM_ARRAY_SIZE(cpumsf_counters),
+
+ .pmu_detect = pfm_cpumsf_detect,
+
+ .get_event_encoding[PFM_OS_NONE] = pfm_cpumf_get_encoding,
+ PFMLIB_ENCODE_PERF(pfm_s390x_get_perf_encoding),
+ .get_event_first = pfm_cpumf_get_event_first,
+ .get_event_next = pfm_cpumf_get_event_next,
+ .event_is_valid = pfm_cpumf_event_is_valid,
+ .validate_table = pfm_cpumf_validate_table,
+ .get_event_info = pfm_cpumf_get_event_info,
+ .get_event_attr_info = pfm_cpumf_get_event_attr_info,
};