commit c95b3011018893fcc473279768a67a24a73bbef2
Author: Wilco <wdijkstr@arm.com>
Date:   Mon Jun 2 12:20:17 2014 +0100

    [AArch64] Rewrite feupdateenv (BZ 17009).

diff --git a/ports/sysdeps/aarch64/fpu/feupdateenv.c b/ports/sysdeps/aarch64/fpu/feupdateenv.c
index 6d64a9b..ac2f6fe 100644
--- a/ports/sysdeps/aarch64/fpu/feupdateenv.c
+++ b/ports/sysdeps/aarch64/fpu/feupdateenv.c
@@ -22,16 +22,65 @@
 int
 feupdateenv (const fenv_t *envp)
 {
+  fpu_control_t fpcr;
+  fpu_control_t fpcr_new;
+  fpu_control_t updated_fpcr;
   fpu_fpsr_t fpsr;
+  fpu_fpsr_t fpsr_new;
+  int excepts;
 
-  /* Get the current exception state.  */
+  _FPU_GETCW (fpcr);
   _FPU_GETFPSR (fpsr);
+  excepts = fpsr & FE_ALL_EXCEPT;
 
-  /* Install new environment.  */
-  fesetenv (envp);
+  if ((envp != FE_DFL_ENV) && (envp != FE_NOMASK_ENV))
+    {
+      fpcr_new = envp->__fpcr;
+      fpsr_new = envp->__fpsr | excepts;
 
-  /* Raise the saved exceptions.  */
-  feraiseexcept (fpsr & FE_ALL_EXCEPT);
+      if (fpcr != fpcr_new)
+        _FPU_SETCW (fpcr_new);
+
+      if (fpsr != fpsr_new)
+        _FPU_SETFPSR (fpsr_new);
+
+      if (excepts & (fpcr_new >> FE_EXCEPT_SHIFT))
+        return feraiseexcept (excepts);
+
+      return 0;
+    }
+
+  fpcr_new = fpcr & _FPU_RESERVED;
+  fpsr_new = fpsr & (_FPU_FPSR_RESERVED | FE_ALL_EXCEPT);
+
+  if (envp == FE_DFL_ENV)
+    {
+      fpcr_new |= _FPU_DEFAULT;
+      fpsr_new |= _FPU_FPSR_DEFAULT;
+    }
+  else
+    {
+      fpcr_new |= _FPU_FPCR_IEEE;
+      fpsr_new |= _FPU_FPSR_IEEE;
+    }
+
+  _FPU_SETFPSR (fpsr_new);
+
+  if (fpcr != fpcr_new)
+    {
+      _FPU_SETCW (fpcr_new);
+
+      /* Trapping exceptions are optional in AArch64; the relevant enable
+	 bits in FPCR are RES0 hence the absence of support can be detected
+	 by reading back the FPCR and comparing with the required value.  */
+      _FPU_GETCW (updated_fpcr);
+
+      if (fpcr_new & ~updated_fpcr)
+        return 1;
+    }
+
+  if (excepts & (fpcr_new >> FE_EXCEPT_SHIFT))
+    return feraiseexcept (excepts);
 
   return 0;
 }