commit e68b1151f7460d5fa88c3a567c13f66052da79a7
Author: Paul A. Clarke <pc@us.ibm.com>
Date:   Thu Sep 19 11:39:44 2019 -0500
 
    [powerpc] __fesetround_inline optimizations
    
    On POWER9, use more efficient means to update the 2-bit rounding mode
    via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions
    or one 'mtfsfi' instruction that modifies 4 bits).
    
    Suggested-by: Paul E. Murphy  <murphyp@linux.ibm.com>
    Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
 
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index 86ae7fda016abd8b..c3f541c08440b20e 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -149,7 +149,12 @@ typedef union
 static inline int
 __fesetround_inline (int round)
 {
-  if ((unsigned int) round < 2)
+#ifdef _ARCH_PWR9
+  __fe_mffscrn (round);
+#else
+  if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
+    __fe_mffscrn (round);
+  else if ((unsigned int) round < 2)
     {
        asm volatile ("mtfsb0 30");
        if ((unsigned int) round == 0)
@@ -165,7 +170,7 @@ __fesetround_inline (int round)
        else
          asm volatile ("mtfsb1 31");
     }
-
+#endif
   return 0;
 }
 
@@ -174,7 +179,14 @@ __fesetround_inline (int round)
 static inline void
 __fesetround_inline_nocheck (const int round)
 {
-  asm volatile ("mtfsfi 7,%0" : : "i" (round));
+#ifdef _ARCH_PWR9
+  __fe_mffscrn (round);
+#else
+  if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
+    __fe_mffscrn (round);
+  else
+    asm volatile ("mtfsfi 7,%0" : : "i" (round));
+#endif
 }
 
 #define FPSCR_MASK(bit) (1 << (31 - (bit)))