From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
From: Andreas Krebbel <krebbel@linux.ibm.com>
Date: Fri, 4 Dec 2020 09:00:43 +0100
Subject: gdb-rhbz2012818-ibmz-update-2of5.patch

;; IBM Z: Add risbgz and risbgnz extended mnemonics
;; (Andreas Krebbel, RHBZ 2012818)

These two extended mnemonics are documented in the Principles of
Operations manual but currently not supported by Binutils. They
provide aliases for already supported instructions with the zero flag
being set.  The flag otherwise is mingled into one of the immediate
operands what makes asm code much harder to read.

opcodes/

	* s390-opc.txt: Add risbgz and risbgnz.
	* s390-opc.c (U6_26): New operand type.
	(INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
	mask.

gas/

	* testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
	* testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
	* testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
	* testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.

diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -218,32 +218,34 @@ const struct s390_operand s390_operands[] =
   { 8, 8, 0 },
 #define U8_16       68            /* 8 bit unsigned value starting at 16 */
   { 8, 16, 0 },
-#define U8_24       69            /* 8 bit unsigned value starting at 24 */
+#define U6_26       69            /* 6 bit unsigned value starting at 26 */
+  { 6, 26, 0 },
+#define U8_24       70            /* 8 bit unsigned value starting at 24 */
   { 8, 24, 0 },
-#define U8_28       70            /* 8 bit unsigned value starting at 28 */
+#define U8_28       71            /* 8 bit unsigned value starting at 28 */
   { 8, 28, 0 },
-#define U8_32       71            /* 8 bit unsigned value starting at 32 */
+#define U8_32       72            /* 8 bit unsigned value starting at 32 */
   { 8, 32, 0 },
-#define U12_16      72            /* 12 bit unsigned value starting at 16 */
+#define U12_16      73            /* 12 bit unsigned value starting at 16 */
   { 12, 16, 0 },
-#define U16_16      73            /* 16 bit unsigned value starting at 16 */
+#define U16_16      74            /* 16 bit unsigned value starting at 16 */
   { 16, 16, 0 },
-#define U16_32      74		  /* 16 bit unsigned value starting at 32 */
+#define U16_32      75		  /* 16 bit unsigned value starting at 32 */
   { 16, 32, 0 },
-#define U32_16      75		  /* 32 bit unsigned value starting at 16 */
+#define U32_16      76		  /* 32 bit unsigned value starting at 16 */
   { 32, 16, 0 },
 
 /* PC-relative address operands.  */
 
-#define J12_12      76            /* 12 bit PC relative offset at 12 */
+#define J12_12      77            /* 12 bit PC relative offset at 12 */
   { 12, 12, S390_OPERAND_PCREL },
-#define J16_16      77            /* 16 bit PC relative offset at 16 */
+#define J16_16      78            /* 16 bit PC relative offset at 16 */
   { 16, 16, S390_OPERAND_PCREL },
-#define J16_32      78            /* 16 bit PC relative offset at 32 */
+#define J16_32      79            /* 16 bit PC relative offset at 32 */
   { 16, 32, S390_OPERAND_PCREL },
-#define J24_24      79            /* 24 bit PC relative offset at 24 */
+#define J24_24      80            /* 24 bit PC relative offset at 24 */
   { 24, 24, S390_OPERAND_PCREL },
-#define J32_16      80            /* 32 bit PC relative offset at 16 */
+#define J32_16      81            /* 32 bit PC relative offset at 16 */
   { 32, 16, S390_OPERAND_PCREL },
 
 };
@@ -313,6 +315,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RIE_R0U0     6, { R_8,U16_16,0,0,0,0 }             /* e.g. clfitne */
 #define INSTR_RIE_RUI0     6, { R_8,I16_16,U4_12,0,0,0 }         /* e.g. lochi */
 #define INSTR_RIE_RRUUU    6, { R_8,R_12,U8_16,U8_24,U8_32,0 }   /* e.g. rnsbg */
+#define INSTR_RIE_RRUUU2   6, { R_8,R_12,U8_16,U6_26,U8_32,0 }   /* e.g. rnsbg */
 #define INSTR_RIL_0P       6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
 #define INSTR_RIL_RP       6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
 #define INSTR_RIL_UP       6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
@@ -534,6 +537,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RIE_R0U0     { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RIE_RUI0     { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RIE_RRUUU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRUUU2   { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
 #define MASK_RIL_0P       { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIL_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIL_UP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -970,6 +970,7 @@ ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
 ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
 ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
 ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
+ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
 c40f strl RIL_RP "store relative long (32)" z10 zarch
 c40b stgrl RIL_RP "store relative long (64)" z10 zarch
 c407 sthrl RIL_RP "store halfword relative long" z10 zarch
@@ -1153,6 +1154,7 @@ eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zar
 eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
 eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
 ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
+ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
 ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
 ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
 ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch