commit 4bc0608a8b693f033555aa5705fdd5fc44cb9a9a
Author: Peter Bergner <bergner@vnet.ibm.com>
Date:   Thu May 14 20:57:50 2015 -0500

    Fix some PPC assembler errors.
    
    Remove the wait instructions for server processors, since they were never
    implemented.  Also add the extra operands added to the tlbie and slbia
    instructions with ISA 2.06 and ISA 2.05 respectively.
    
    binutils/
            * MAINTAINERS: Add myself as PPC maintainer.
    
    opcodes/
            * ppc-opc.c (IH) New define.
            (powerpc_opcodes) <wait>: Do not enable for POWER7.
            <tlbie>: Add RS operand for POWER7.
            <slbia>: Add IH operand for POWER6.
    
    gas/testsuite/
            * gas/ppc/power4.d: Add a slbia test.
            * gas/ppc/power4.s: Likewise.
            * gas/ppc/power6.d: Add slbia and tlbie tests.
            * gas/ppc/power6.s: Likewise.
            * gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
            * gas/ppc/power7.s: Likewise.

### a/opcodes/ChangeLog
### b/opcodes/ChangeLog
## -1,3 +1,10 @@
+2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc-opc.c (IH) New define.
+	(powerpc_opcodes) <wait>: Do not enable for POWER7.
+	<tlbie>: Add RS operand for POWER7.
+	<slbia>: Add IH operand for POWER6.
+
 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -866,6 +866,9 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define ERAT_T UIM + 1
   { 0x7, 21, NULL, NULL, 0 },
+
+#define IH ERAT_T + 1
+  { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 };
 
 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4486,7 +4489,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"waitrsv",	X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,	{0}},
 {"waitimpl",	X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,	{0}},
-{"wait",	X(31,62),	XWC_MASK,    POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
+{"wait",	X(31,62),	XWC_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
  
 {"dcbstep",	XRT(31,63,0),	XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
 
@@ -4780,7 +4783,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mfbhrbe",	X(31,302),	X_MASK,      POWER8,	PPCNONE,	{RT, BHRBE}},
 
-{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	TITAN,  	{RB, L}},
+{"tlbie",	X(31,306),	XRA_MASK,    POWER7,	TITAN,  	{RB, RS}},
+{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	POWER7|TITAN,  	{RB, L}},
 {"tlbi",	X(31,306),	XRT_MASK,    POWER,	PPCNONE,	{RA0, RB}},
 
 {"eciwx",	X(31,310),	X_MASK,      PPC,	TITAN,  	{RT, RA0, RB}},
@@ -5372,7 +5376,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icbtlse",	X(31,494),	X_MASK,      PPCCHLK,	E500MC,		{CT, RA, RB}},
 
-{"slbia",	X(31,498),	0xffffffff,  PPC64,	PPCNONE,	{0}},
+{"slbia",	X(31,498),	0xff1fffff,  POWER6,	PPCNONE,	{IH}},
+{"slbia",	X(31,498),	0xffffffff,  PPC64,	POWER6,		{0}},
 
 {"cli",		X(31,502),	XRB_MASK,    POWER,	PPCNONE,	{RT, RA}},