commit 54a2f1efc188660df9da78523b6925aab4c3a668
Author: rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue Jan 13 14:11:15 2015 +0000
gcc/
* config/aarch64/aarch64.md (subsi3, *subsi3_uxtw, subdi3)
(*sub_<optab><ALLX:mode>_<GPI:mode>, *sub_<optab><SHORT:mode>_si_uxtw)
(*sub_<optab><ALLX:mode>_shft_<GPI:mode>)
(*sub_<optab><SHORT:mode>_shft_si_uxtw, *sub_<optab><mode>_multp2)
(*sub_<optab>si_multp2_uxtw, *sub_uxt<mode>_multp2)
(*sub_uxtsi_multp2_uxtw): Add stack pointer sources.
gcc/testsuite/
* gcc.target/aarch64/subsp.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219533 138bc75d-0d04-0410-961f-82ee72b054a4
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 17082486ac8..a085c6acaf5 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1610,8 +1610,8 @@
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=rk")
- (minus:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "register_operand" "r")))]
+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
+ (match_operand:SI 2 "register_operand" "r")))]
""
"sub\\t%w0, %w1, %w2"
[(set_attr "v8type" "alu")
@@ -1622,7 +1622,7 @@
(define_insn "*subsi3_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
- (minus:SI (match_operand:SI 1 "register_operand" "r")
+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
(match_operand:SI 2 "register_operand" "r"))))]
""
"sub\\t%w0, %w1, %w2"
@@ -1632,7 +1632,7 @@
(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=rk,!w")
- (minus:DI (match_operand:DI 1 "register_operand" "r,!w")
+ (minus:DI (match_operand:DI 1 "register_operand" "rk,!w")
(match_operand:DI 2 "register_operand" "r,!w")))]
""
"@
@@ -1725,7 +1725,7 @@
(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
[(set (match_operand:GPI 0 "register_operand" "=rk")
- (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
(ANY_EXTEND:GPI
(match_operand:ALLX 2 "register_operand" "r"))))]
""
@@ -1738,7 +1738,7 @@
(define_insn "*sub_<optab><SHORT:mode>_si_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
- (minus:SI (match_operand:SI 1 "register_operand" "r")
+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
(ANY_EXTEND:SI
(match_operand:SHORT 2 "register_operand" "r")))))]
""
@@ -1749,7 +1749,7 @@
(define_insn "*sub_<optab><ALLX:mode>_shft_<GPI:mode>"
[(set (match_operand:GPI 0 "register_operand" "=rk")
- (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
(ashift:GPI (ANY_EXTEND:GPI
(match_operand:ALLX 2 "register_operand" "r"))
(match_operand 3 "aarch64_imm3" "Ui3"))))]
@@ -1763,7 +1763,7 @@
(define_insn "*sub_<optab><SHORT:mode>_shft_si_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
- (minus:SI (match_operand:SI 1 "register_operand" "r")
+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
(ashift:SI (ANY_EXTEND:SI
(match_operand:SHORT 2 "register_operand" "r"))
(match_operand 3 "aarch64_imm3" "Ui3")))))]
@@ -1775,7 +1775,7 @@
(define_insn "*sub_<optab><mode>_multp2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
- (minus:GPI (match_operand:GPI 4 "register_operand" "r")
+ (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
(ANY_EXTRACT:GPI
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
@@ -1791,7 +1791,7 @@
(define_insn "*sub_<optab>si_multp2_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
- (minus:SI (match_operand:SI 4 "register_operand" "r")
+ (minus:SI (match_operand:SI 4 "register_operand" "rk")
(ANY_EXTRACT:SI
(mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
@@ -1805,7 +1805,7 @@
(define_insn "*sub_uxt<mode>_multp2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
- (minus:GPI (match_operand:GPI 4 "register_operand" "r")
+ (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
(and:GPI
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
@@ -1823,7 +1823,7 @@
(define_insn "*sub_uxtsi_multp2_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
- (minus:SI (match_operand:SI 4 "register_operand" "r")
+ (minus:SI (match_operand:SI 4 "register_operand" "rk")
(and:SI
(mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
diff --git a/gcc/testsuite/gcc.target/aarch64/subsp.c b/gcc/testsuite/gcc.target/aarch64/subsp.c
new file mode 100644
index 00000000000..70d848c59d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/subsp.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O" } */
+
+int foo (void *);
+
+int
+f1 (int *x, long y)
+{
+ return foo (__builtin_alloca (y));
+}
+
+int
+f2 (int *x, int y)
+{
+ char a[y + 1][16];
+ return foo (a);
+}
+
+/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*\n" } } */
+/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*, sxtw 4\n" } } */