diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.25.1/gas/testsuite/gas/ppc/power9.d
--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2017-09-13 09:58:05.090339261 +0100
+++ binutils-2.25.1/gas/testsuite/gas/ppc/power9.d 2017-09-13 09:59:54.284098233 +0100
@@ -320,8 +320,9 @@ Disassembly of section \.text:
.*: (f1 31 9d 6f|6f 9d 31 f1) xscvdphp vs41,vs51
.*: (f1 58 a7 6f|6f a7 58 f1) xvcvhpsp vs42,vs52
.*: (f1 79 af 6f|6f af 79 f1) xvcvsphp vs43,vs53
-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0
-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0
+.*: (4c 60 00 04|04 00 60 4c) lnia r3
+.*: (4c 60 00 04|04 00 60 4c) lnia r3
+.*: (4c 60 00 04|04 00 60 4c) lnia r3
.*: (4c 80 00 05|05 00 80 4c) addpcis r4,1
.*: (4c 80 00 05|05 00 80 4c) addpcis r4,1
.*: (4c bf ff c4|c4 ff bf 4c) addpcis r5,-2
@@ -418,4 +419,7 @@ Disassembly of section \.text:
.*: (11 6a 60 34|34 60 6a 11) rldixor r10,r11,0,r12
.*: (11 6a 66 f4|f4 66 6a 11) rldixor r10,r11,27,r12
.*: (11 6a 67 f5|f5 67 6a 11) rldixor r10,r11,63,r12
+.*: (01 00 00 44|44 00 00 01) scv 0
+.*: (e1 0f 00 44|44 00 0f e1) scv 127
+.*: (a4 00 00 4c|4c 00 00 a4) rfscv
#pass
Only in binutils-2.25.1/gas/testsuite/gas/ppc: power9.d.orig
Only in binutils-2.25.1/gas/testsuite/gas/ppc: power9.d.rej
diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.s binutils-2.25.1/gas/testsuite/gas/ppc/power9.s
--- binutils.orig/gas/testsuite/gas/ppc/power9.s 2017-09-13 09:58:05.090339261 +0100
+++ binutils-2.25.1/gas/testsuite/gas/ppc/power9.s 2017-09-13 10:00:14.077873268 +0100
@@ -311,6 +311,7 @@ power9:
xscvdphp 41,51
xvcvhpsp 42,52
xvcvsphp 43,53
+ lnia 3
addpcis 3,0
subpcis 3,0
addpcis 4,1
@@ -409,3 +410,6 @@ power9:
rldixor 10,11,0,12
rldixor 10,11,27,12
rldixor 10,11,63,12
+ scv 0
+ scv 127
+ rfscv
Only in binutils-2.25.1/gas/testsuite/gas/ppc: power9.s.orig
Only in binutils-2.25.1/gas/testsuite/gas/ppc: power9.s.rej
diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.25.1/opcodes/ppc-opc.c
--- binutils.orig/opcodes/ppc-opc.c 2017-09-13 09:58:05.356336238 +0100
+++ binutils-2.25.1/opcodes/ppc-opc.c 2017-09-13 10:01:15.410176204 +0100
@@ -440,7 +440,7 @@ const struct powerpc_operand powerpc_ope
#define L1 L0 + 1
{ 0x1, 21, insert_l1, extract_l1, 0 },
- /* The LEV field in a POWER SVC form instruction. */
+ /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
#define SVC_LEV L1 + 1
{ 0x7f, 5, NULL, NULL, 0 },
@@ -2480,6 +2480,9 @@ extract_vleil (unsigned long insn,
#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
#define DX_MASK DX (0x3f, 0x1f)
+/* An DX form instruction with the D bits specified. */
+#define NODX_MASK (DX_MASK | 0x1fffc1)
+
/* An EVSEL form instruction. */
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
#define EVSEL_MASK EVSEL(0x3f, 0xff)
@@ -4181,6 +4184,7 @@ const struct powerpc_opcode powerpc_opco
{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
+{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
@@ -4193,6 +4197,7 @@ const struct powerpc_opcode powerpc_opco
{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
+{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
{"addpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, DXD}},
{"subpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, NDXD}},
@@ -4430,6 +4435,7 @@ const struct powerpc_opcode powerpc_opco
{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
+{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
Only in binutils-2.25.1/opcodes: ppc-opc.c.orig
Only in binutils-2.25.1/opcodes: ppc-opc.c.rej