From 3d461e82d134f7370f28ff2def581d39a3e19729 Mon Sep 17 00:00:00 2001
Message-Id: <3d461e82d134f7370f28ff2def581d39a3e19729.1387298827.git.minovotn@redhat.com>
In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
From: "Michael S. Tsirkin" <mst@redhat.com>
Date: Tue, 17 Dec 2013 15:18:09 +0100
Subject: [PATCH 31/56] q35: expose mmcfg size as a property

RH-Author: Michael S. Tsirkin <mst@redhat.com>
Message-id: <1387293161-4085-32-git-send-email-mst@redhat.com>
Patchwork-id: 56337
O-Subject: [PATCH qemu-kvm RHEL7.0 v2 31/57] q35: expose mmcfg size as a property
Bugzilla: 1034876
RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
RH-Acked-by: Laszlo Ersek <lersek@redhat.com>

Address is already exposed, expose size for symmetry.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
(cherry picked from commit cbcaf79e3ce1b14084f3e3f4f64365e9bfd70e6a)
---
 include/hw/pci/pcie_host.h |  1 +
 hw/pci-host/q35.c          | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

Signed-off-by: Michal Novotny <minovotn@redhat.com>
---
 hw/pci-host/q35.c          | 14 ++++++++++++++
 include/hw/pci/pcie_host.h |  1 +
 2 files changed, 15 insertions(+)

diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 72d97c8..87691d1 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -108,6 +108,16 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
     visit_type_uint64(v, &w64.end, name, errp);
 }
 
+static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
+                                    void *opaque, const char *name,
+                                    Error **errp)
+{
+    PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
+    uint32_t value = e->size;
+
+    visit_type_uint32(v, &value, name, errp);
+}
+
 static Property mch_props[] = {
     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, host.base_addr,
                        MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
@@ -152,6 +162,10 @@ static void q35_host_initfn(Object *obj)
                         q35_host_get_pci_hole64_end,
                         NULL, NULL, NULL, NULL);
 
+    object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
+                        q35_host_get_mmcfg_size,
+                        NULL, NULL, NULL, NULL);
+
     /* Leave enough space for the biggest MCFG BAR */
     /* TODO: this matches current bios behaviour, but
      * it's not a power of two, which means an MTRR
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 33d75bd..acca45e 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -29,6 +29,7 @@
     OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
 
 #define PCIE_HOST_MCFG_BASE "MCFG"
+#define PCIE_HOST_MCFG_SIZE "mcfg_size"
 
 /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
 #define PCIE_BASE_ADDR_UNMAPPED  ((hwaddr)-1ULL)
-- 
1.7.11.7