From 9875f9aaef996083064bf6a7afa1bfa30ff7d953 Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 13 Dec 2017 15:43:40 -0200
Subject: [PATCH 2/3] target-i386: add support for SPEC_CTRL MSR
RH-Author: Eduardo Habkost <ehabkost@redhat.com>
Message-id: <20171213174341.20684-3-ehabkost@redhat.com>
Patchwork-id: n/a
O-Subject: [CONFIDENTIAL][RHEL-7.5 qemu-kvm PATCH v2 2/3] target-i386: add
support for SPEC_CTRL MSR
Bugzilla: CVE-2017-5715
RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
---
target-i386/cpu.h | 4 ++++
target-i386/kvm.c | 14 ++++++++++++++
target-i386/machine.c | 21 +++++++++++++++++++++
3 files changed, 39 insertions(+)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 1e5c980..7d815cd 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -304,6 +304,7 @@
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
#define MSR_TSC_ADJUST 0x0000003b
+#define MSR_IA32_SPEC_CTRL 0x48
#define MSR_IA32_TSCDEADLINE 0x6e0
#define MSR_P6_PERFCTR0 0xc1
@@ -963,6 +964,7 @@ typedef struct CPUX86State {
uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
uint64_t msr_gp_counters[MAX_GP_COUNTERS];
uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
+
uint64_t msr_hv_hypercall;
uint64_t msr_hv_guest_os_id;
uint64_t msr_hv_vapic;
@@ -1037,6 +1039,8 @@ typedef struct CPUX86State {
uint32_t pkru;
+ uint64_t spec_ctrl;
+
TPRAccess tpr_access_type;
} CPUX86State;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 0dc0e79..24d17ad 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -77,6 +77,7 @@ static bool has_msr_hv_vapic;
static bool has_msr_hv_tsc;
static bool has_msr_mtrr;
static bool has_msr_xss;
+static bool has_msr_spec_ctrl;
static bool has_msr_architectural_pmu;
static uint32_t num_architectural_pmu_counters;
@@ -800,6 +801,10 @@ static int kvm_get_supported_msrs(KVMState *s)
has_msr_xss = true;
continue;
}
+ if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) {
+ has_msr_spec_ctrl = true;
+ continue;
+ }
}
}
@@ -1187,6 +1192,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_xss) {
kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
}
+ if (has_msr_spec_ctrl) {
+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl);
+ }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1544,6 +1552,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_xss) {
msrs[n++].index = MSR_IA32_XSS;
}
+ if (has_msr_spec_ctrl) {
+ msrs[n++].index = MSR_IA32_SPEC_CTRL;
+ }
if (!env->tsc_valid) {
@@ -1786,6 +1797,9 @@ static int kvm_get_msrs(X86CPU *cpu)
env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
}
break;
+ case MSR_IA32_SPEC_CTRL:
+ env->spec_ctrl = msrs[i].data;
+ break;
}
}
diff --git a/target-i386/machine.c b/target-i386/machine.c
index ba34088..d883c86 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -742,6 +742,24 @@ static const VMStateDescription vmstate_pkru = {
};
#endif
+static bool spec_ctrl_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->spec_ctrl != 0;
+}
+
+static const VMStateDescription vmstate_spec_ctrl = {
+ .name = "cpu/spec_ctrl",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]){
+ VMSTATE_UINT64(env.spec_ctrl, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -896,6 +914,9 @@ const VMStateDescription vmstate_x86_cpu = {
.vmsd = &vmstate_pkru,
.needed = pkru_needed,
#endif
+ }, {
+ .vmsd = &vmstate_spec_ctrl,
+ .needed = spec_ctrl_needed,
} , {
/* empty */
}
--
1.8.3.1