x86info v1.12.  Dave Jones 2001, 2002
Feedback to <davej@suse.de>.

Found 1 CPU
MP Table:
#	APIC ID	Version	State		Family	Model	Step	Flags
#	 0	 0x11	 BSP, usable	 6	 8	 0	 0xfbff

--------------------------------------------------------------------------
eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65
eax in: 0x00000001, eax = 00000680 ebx = 00000000 ecx = 00000000 edx = 0383fbff

eax in: 0x80000000, eax = 80000008 ebx = 68747541 ecx = 444d4163 edx = 69746e65
eax in: 0x80000001, eax = 00000780 ebx = 00000000 ecx = 00000000 edx = c1c3fbff
eax in: 0x80000002, eax = 20444d41 ebx = 6c687441 ecx = 74286e6f edx = 5820296d
eax in: 0x80000003, eax = 37312050 ebx = 002b3030 ecx = 00000000 edx = 00000000
eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000005, eax = 0408ff08 ebx = ff20ff10 ecx = 40020140 edx = 40020140
eax in: 0x80000006, eax = 00000000 ebx = 41004100 ecx = 01008140 edx = 00000000
eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000001
eax in: 0x80000008, eax = 00002022 ebx = 00000000 ecx = 00000000 edx = 00000000

Family: 6 Model: 8 Stepping: 0
CPU Model : Athlon XP (Thoroughbred)[A0]
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction
	Page Attribute Table
	36-bit PSEs
	MMX support
	FXSAVE and FXRESTORE instructions
	SSE support

Extended feature flags:
 syscall mmxext 3dnowext 3dnow
MSR: 0x0000002a=0x00000000 : 00000000 00000000 00000000 00000000
MSR: 0xc0000080=0x00000000 : 00000000 00000000 00000000 00000000
MSR: 0xc0010010=0x00140604 : 00000000 00010100 00000110 00000100
MSR: 0xc0010015=0x00031008 : 00000000 00000011 00010000 00001000
MSR: 0xc001001b=0x6003d223 : 01100000 00000011 11010010 00100011

Number of reporting banks : 4

MCG_CTL:
 Data cache check enabled
  ECC 1 bit error reporting enabled
  ECC multi bit error reporting enabled
  Data cache data parity enabled
  Data cache main tag parity enabled
  Data cache snoop tag parity enabled
  L1 TLB parity enabled
  L2 TLB parity enabled
 Instruction cache check enabled
  ECC 1 bit error reporting enabled
  ECC multi bit error reporting enabled
  Instruction cache data parity enabled
  IC main tag parity enabled
  IC snoop tag parity enabled
  L1 TLB parity enabled
  L2 TLB parity enabled
  Predecode array parity enabled
  Target selector parity enabled
  Read data error enabled
 Bus unit check enabled
  External L2 tag parity error enabled
  L2 partial tag parity error enabled
  System ECC TLB reload error enabled
  L2 ECC TLB reload error enabled
  L2 ECC K7 deallocate enabled
  L2 ECC probe deallocate enabled
  System datareaderror reporting enabled
 Load/Store unit check enabled
  Read data error enable (loads) enabled
  Read data error enable (stores) enabled

           31       23       15       7 
Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 01111111
MC0STATUS: 00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
MC0MISC:   00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    11111111 11111111 11111111 11111111
MC1STATUS: 00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00001000 01100000 00000100
MC1MISC:   00000000 00000000 00000000 00000000

Bank: 2 (0x408)
MC2CTL:    00000000 00000000 00000111 11111111
MC2STATUS: 00000000 00000000 00000000 00000000
MC2ADDR:   00100101 11101010 00001110 10001111
MC2MISC:   00100101 11101010 00001110 10001111

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000111
MC3STATUS: 00000000 00000000 00000000 00000000
MC3ADDR:   11111111 11111111 01111111 11111111
MC3MISC:   00000000 00000000 00000000 00000000

Instruction TLB: Fully associative. 16 entries.
Data TLB: Fully associative. 32 entries.
L1 Data cache:
	Size: 64Kb	2-way associative. 
	lines per tag=1	line size=64 bytes.
L1 Instruction cache:
	Size: 64Kb	2-way associative. 
	lines per tag=1	line size=64 bytes.
L2 (on CPU) cache:
	Size: 256Kb	8-way associative. 
	lines per tag=1	line size=64 bytes.

PowerNOW! Technology information
Available features:
	Temperature sensing diode present.
Connector type: Socket A (462 Pin PGA)


MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000006
MTRRphysMask0 (0x201): 0x0000000ff8000800
MTRRphysBase1 (0x202): 0x00000000d0000001
MTRRphysMask1 (0x203): 0x0000000ff8000800
MTRRphysBase2 (0x204): 0x00000000d8000001
MTRRphysMask2 (0x205): 0x0000000ff8000800
MTRRphysBase3 (0x206): 0x0000000000000000
MTRRphysMask3 (0x207): 0x0000000000000000
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x00000000d0000001
MTRRphysMask5 (0x20b): 0x0000000ff8000800
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0000000000000000
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0505050505050505
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0000000000000000
MTRRfix4K_F8000 0x26f: 0x0000000000000000
MTRRdefType (0x2ff): 0x0000000000000c00


1462.49 MHz processor (estimate).

int 0x80: 273 cycles
cpuid: 64 cycles
locked add: 11 cycles
