x86info v1.12.  Dave Jones 2001, 2002
Feedback to <davej@suse.de>.

Found 1 CPU
--------------------------------------------------------------------------
eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65
eax in: 0x00000001, eax = 00000680 ebx = 00000000 ecx = 00000000 edx = 0383fbff

eax in: 0x80000000, eax = 80000008 ebx = 68747541 ecx = 444d4163 edx = 69746e65
eax in: 0x80000001, eax = 00000780 ebx = 00000000 ecx = 00000000 edx = c1cbfbff
eax in: 0x80000002, eax = 69626f4d ebx = 4120656c ecx = 4120444d edx = 6f6c6874
eax in: 0x80000003, eax = 6d74286e ebx = 50582029 ecx = 30363120 edx = 00002b30
eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000005, eax = 0408ff08 ebx = ff20ff10 ecx = 40020140 edx = 40020140
eax in: 0x80000006, eax = 00000000 ebx = 41004100 ecx = 01008140 edx = 00000000
eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000007
eax in: 0x80000008, eax = 00002022 ebx = 00000000 ecx = 00000000 edx = 00000000

Family: 6 Model: 8 Stepping: 0
CPU Model : Mobile Athlon XP (Thoroughbred)[A0]
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction
	Page Attribute Table
	36-bit PSEs
	MMX support
	FXSAVE and FXRESTORE instructions
	SSE support

Extended feature flags:
 syscall mp mmxext 3dnowext 3dnow
MSR: 0x0000002a=0x00000000 : 00000000 00000000 00000000 00000000
MSR: 0xc0000080=0x00000000 : 00000000 00000000 00000000 00000000
MSR: 0xc0010010=0x00160602 : 00000000 00010110 00000110 00000010
MSR: 0xc0010015=0x06031000 : 00000110 00000011 00010000 00000000
MSR: 0xc001001b=0x60071263 : 01100000 00000111 00010010 01100011

Number of reporting banks : 4

MCG_CTL:
 Data cache check enabled
  ECC 1 bit error reporting enabled
  ECC multi bit error reporting enabled
  Data cache data parity enabled
  Data cache main tag parity enabled
  Data cache snoop tag parity enabled
  L1 TLB parity enabled
  L2 TLB parity enabled
 Instruction cache check enabled
  ECC 1 bit error reporting enabled
  ECC multi bit error reporting enabled
  Instruction cache data parity enabled
  IC main tag parity enabled
  IC snoop tag parity enabled
  L1 TLB parity enabled
  L2 TLB parity enabled
  Predecode array parity enabled
  Target selector parity enabled
  Read data error enabled
 Bus unit check enabled
  External L2 tag parity error enabled
  L2 partial tag parity error enabled
  System ECC TLB reload error enabled
  L2 ECC TLB reload error enabled
  L2 ECC K7 deallocate enabled
  L2 ECC probe deallocate enabled
  System datareaderror reporting enabled
 Load/Store unit check enabled
  Read data error enable (loads) enabled
  Read data error enable (stores) enabled

           31       23       15       7 
Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 01111111
MC0STATUS: 00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
MC0MISC:   00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    11111111 11111111 11111111 11111111
MC1STATUS: 00000000 00000000 00000000 00000000
MC1ADDR:   00000000 01000000 00000000 00000000
MC1MISC:   00000000 00000000 00000000 00000000

Bank: 2 (0x408)
MC2CTL:    00000000 00000000 00000111 11111111
MC2STATUS: 00000000 00000000 00000000 00000000
MC2ADDR:   11111111 11111011 11110111 10001111
MC2MISC:   11111111 11111011 11110111 10001111

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000111
MC3STATUS: 00000000 00000000 00000000 00000000
MC3ADDR:   11111111 11111111 11111111 11111111
MC3MISC:   00000000 00000000 00000000 00000000

Instruction TLB: Fully associative. 16 entries.
Data TLB: Fully associative. 32 entries.
L1 Data cache:
	Size: 64Kb	2-way associative. 
	lines per tag=1	line size=64 bytes.
L1 Instruction cache:
	Size: 64Kb	2-way associative. 
	lines per tag=1	line size=64 bytes.
L2 (on CPU) cache:
	Size: 256Kb	8-way associative. 
	lines per tag=1	line size=64 bytes.

PowerNOW! Technology information
Available features:
	Temperature sensing diode present.
	Bus divisor control
	Voltage ID control

MSR: 0xc0010041=0x0013090f : 00000000 00000000 00000000 00000000
           00000000 00010011 00001001 00001111
MSR: 0xc0010042=0x90909000f060f : 00000000 00001001 00001001 00001001
           00000000 00001111 00000110 00001111

FID changes will happen
VID changes will happen
Current VID multiplier code: 1.550
Current FSB multiplier code: 10.5
Voltage ID codes: Maximum=1.550V Startup=1.550V Currently=1.550V
Frequency ID codes: Maximum=10.5x Startup=6.0x Currently=10.5x
Decoding BIOS PST tables (maxfid=f, startvid=9)
Found PSB header at 0x40158800
Table version: 0x12
Flags: 0x0 (Mobile voltage regulator)
Settling Time: 100 microseconds.
Has 31 PST tables. (Only dumping ones relevant to this CPU).
 PST:26 (@0x401589c2)
  cpuid: 0x780	  fsb: 133	  maxFID: 0xf	  startvid: 0x9
  num of p states in this table: 5
    FID: 0x12 (4.0x [532MHz])	VID: 0x13 (1.200V)
    FID: 0x4 (5.0x [665MHz])	VID: 0x13 (1.200V)
    FID: 0x6 (6.0x [798MHz])	VID: 0x13 (1.200V)
    FID: 0xa (8.0x [1064MHz])	VID: 0xd (1.350V)
    FID: 0xf (10.5x [1396MHz])	VID: 0x9 (1.550V)

Connector type: Socket A (462 Pin PGA)


MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000006
MTRRphysMask0 (0x201): 0x0000000ff8000800
MTRRphysBase1 (0x202): 0x0000000008000006
MTRRphysMask1 (0x203): 0x0000000ffc000800
MTRRphysBase2 (0x204): 0x000000000c000006
MTRRphysMask2 (0x205): 0x0000000ffe000800
MTRRphysBase3 (0x206): 0x000000000e000006
MTRRphysMask3 (0x207): 0x0000000fff000800
MTRRphysBase4 (0x208): 0x00000000f6fe0001
MTRRphysMask4 (0x209): 0x0000000fffff0800
MTRRphysBase5 (0x20a): 0x00000000f6fc0001
MTRRphysMask5 (0x20b): 0x0000000ffffe0800
MTRRphysBase6 (0x20c): 0x00000000f6f80001
MTRRphysMask6 (0x20d): 0x0000000ffffc0800
MTRRphysBase7 (0x20e): 0x00000000f6f00001
MTRRphysMask7 (0x20f): 0x0000000ffff80800
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0005050505050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0500000000000000
MTRRfix4K_E0000 0x26c: 0x0505050506060606
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c00


1391.35 MHz processor (estimate).

int 0x80: 267 cycles
cpuid: 68 cycles
addl: 11 cycles
locked add: 10 cycles
lea 1(%eax),%eax: 11 cycles
