x86info v1.12.  Dave Jones 2001-2003
Feedback to <davej@suse.de>.

Found 4 CPUs
MP Table:
#	APIC ID	Version	State		Family	Model	Step	Flags
#	 3	 0x10	 BSP, usable	 6	 1	 9	 0xfbff
#	 0	 0x10	 AP, usable	 6	 1	 9	 0xfbff
#	 1	 0x10	 AP, usable	 6	 1	 9	 0xfbff
#	 2	 0x10	 AP, usable	 6	 1	 9	 0xfbff

--------------------------------------------------------------------------
CPU #1
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff
eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42

Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0
CPU Model: Pentium Pro [sB1] Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction

Extended feature flags:

Instruction TLB: 4KB pages, 4-way associative, 32 entries
Instruction TLB: 4MB pages, fully associative, 2 entries
Data TLB: 4KB pages, 4-way associative, 64 entries
L2 unified cache:
	Size: 256KB	4-way associative.
	line size=32 bytes.
L1 Data cache:
	Size: 8KB	2-way associative.
	line size=32 bytes.
Data TLB: 4MB pages, 4-way associative, 8 entries
L1 Instruction cache:
	Size: 8KB	4-way associative.
	line size=32 bytes.

Number of reporting banks : 5

Erk, MCG_CTL not present! :0000000000000005:

Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 00000000
           11000000 01110000 00000000 01000000
MC0STATUS: 00010000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000001
MC1STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00110100 00110000 11111111
           00000000 00110100 00110000 11111111

Bank: 2 (0x408)
MC2CTL:    00000000 00110100 01000110 00000000
           00000000 00110100 01000110 00000000
MC2STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC2ADDR:   00000000 00110100 01000110 11111111
           00000000 00110100 01000110 11111111

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3STATUS: 00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3ADDR:   Couldn't read MSR 0x40e

Bank: 4 (0x410)
MC4CTL:    00000000 00000000 00000000 00001000
           00000000 00000000 00000000 00001000
MC4STATUS: 00100010 00000000 00000000 00000000
           00000000 00000000 00000000 00010001
MC4ADDR:   00000000 00110101 00100000 11111111
           00000000 00110101 00100000 11111111

Microcode version: 0x00000000000000d2

Connector type: Socket 8 (387 pin Dual Cavity PGA)


MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000000
MTRRphysMask0 (0x201): 0x0000000000000000
MTRRphysBase1 (0x202): 0x0000000020000000
MTRRphysMask1 (0x203): 0x0000000fe0000800
MTRRphysBase2 (0x204): 0x0000000040000000
MTRRphysMask2 (0x205): 0x0000000fc0000800
MTRRphysBase3 (0x206): 0x0000000080000000
MTRRphysMask3 (0x207): 0x0000000f80000800
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0000000005050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0000000000000000
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c06


200MHz processor (estimate).

--------------------------------------------------------------------------
CPU #2
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff
eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42

Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0
CPU Model: Pentium Pro [sB1] Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction

Extended feature flags:

Instruction TLB: 4KB pages, 4-way associative, 32 entries
Instruction TLB: 4MB pages, fully associative, 2 entries
Data TLB: 4KB pages, 4-way associative, 64 entries
L2 unified cache:
	Size: 256KB	4-way associative.
	line size=32 bytes.
L1 Data cache:
	Size: 8KB	2-way associative.
	line size=32 bytes.
Data TLB: 4MB pages, 4-way associative, 8 entries
L1 Instruction cache:
	Size: 8KB	4-way associative.
	line size=32 bytes.

Number of reporting banks : 5

Erk, MCG_CTL not present! :0000000000000005:

Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 00000000
           11000000 01000000 00000000 01000000
MC0STATUS: 00010000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000001
MC1STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00110100 00110000 11111111
           00000000 00110100 00110000 11111111

Bank: 2 (0x408)
MC2CTL:    00000000 00110100 01000110 00000000
           00000000 00110100 01000110 00000000
MC2STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC2ADDR:   00000000 00110100 01000110 11111111
           00000000 00110100 01000110 11111111

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3STATUS: 00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3ADDR:   Couldn't read MSR 0x40e

Bank: 4 (0x410)
MC4CTL:    00000000 00000000 00000000 00001000
           00000000 00000000 00000000 00001000
MC4STATUS: 00100010 00000000 00000000 00000000
           00000000 00000000 00000000 00010001
MC4ADDR:   00000000 00110101 00100000 11111111
           00000000 00110101 00100000 11111111

Microcode version: 0x00000000000000d2

Connector type: Socket 8 (387 pin Dual Cavity PGA)


MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000000
MTRRphysMask0 (0x201): 0x0000000000000000
MTRRphysBase1 (0x202): 0x0000000020000000
MTRRphysMask1 (0x203): 0x0000000fe0000800
MTRRphysBase2 (0x204): 0x0000000040000000
MTRRphysMask2 (0x205): 0x0000000fc0000800
MTRRphysBase3 (0x206): 0x0000000080000000
MTRRphysMask3 (0x207): 0x0000000f80000800
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0000000005050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0000000000000000
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c06


200MHz processor (estimate).

--------------------------------------------------------------------------
CPU #3
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff
eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42

Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0
CPU Model: Pentium Pro [sB1] Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction

Extended feature flags:

Instruction TLB: 4KB pages, 4-way associative, 32 entries
Instruction TLB: 4MB pages, fully associative, 2 entries
Data TLB: 4KB pages, 4-way associative, 64 entries
L2 unified cache:
	Size: 256KB	4-way associative.
	line size=32 bytes.
L1 Data cache:
	Size: 8KB	2-way associative.
	line size=32 bytes.
Data TLB: 4MB pages, 4-way associative, 8 entries
L1 Instruction cache:
	Size: 8KB	4-way associative.
	line size=32 bytes.

Number of reporting banks : 5

Erk, MCG_CTL not present! :0000000000000005:

Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 00000000
           11000000 01010000 00000000 01000000
MC0STATUS: 00010000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000001
MC1STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00110100 00110000 11111111
           00000000 00110100 00110000 11111111

Bank: 2 (0x408)
MC2CTL:    00000000 00110100 01000110 00000000
           00000000 00110100 01000110 00000000
MC2STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC2ADDR:   00000000 00110100 01000110 11111111
           00000000 00110100 01000110 11111111

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3STATUS: 00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3ADDR:   Couldn't read MSR 0x40e

Bank: 4 (0x410)
MC4CTL:    00000000 00000000 00000000 00001000
           00000000 00000000 00000000 00001000
MC4STATUS: 00100010 00000000 00000000 00000000
           00000000 00000000 00000000 00010001
MC4ADDR:   00000000 00110101 00100000 11111111
           00000000 00110101 00100000 11111111

Microcode version: 0x00000000000000d2

Connector type: Socket 8 (387 pin Dual Cavity PGA)


MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000000
MTRRphysMask0 (0x201): 0x0000000000000000
MTRRphysBase1 (0x202): 0x0000000020000000
MTRRphysMask1 (0x203): 0x0000000fe0000800
MTRRphysBase2 (0x204): 0x0000000040000000
MTRRphysMask2 (0x205): 0x0000000fc0000800
MTRRphysBase3 (0x206): 0x0000000080000000
MTRRphysMask3 (0x207): 0x0000000f80000800
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0000000005050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0000000000000000
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c06


200MHz processor (estimate).

--------------------------------------------------------------------------
CPU #4
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff
eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42

Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0
CPU Model: Pentium Pro [sB1] Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction

Extended feature flags:

Instruction TLB: 4KB pages, 4-way associative, 32 entries
Instruction TLB: 4MB pages, fully associative, 2 entries
Data TLB: 4KB pages, 4-way associative, 64 entries
L2 unified cache:
	Size: 256KB	4-way associative.
	line size=32 bytes.
L1 Data cache:
	Size: 8KB	2-way associative.
	line size=32 bytes.
Data TLB: 4MB pages, 4-way associative, 8 entries
L1 Instruction cache:
	Size: 8KB	4-way associative.
	line size=32 bytes.

Number of reporting banks : 5

Erk, MCG_CTL not present! :0000000000000005:

Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 00000000
           11000000 01100000 00000000 01000000
MC0STATUS: 00010000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000001
MC1STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00110100 00110000 11111111
           00000000 00110100 00110000 11111111

Bank: 2 (0x408)
MC2CTL:    00000000 00110100 01000110 00000000
           00000000 00110100 01000110 00000000
MC2STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC2ADDR:   00000000 00110100 01000110 11111111
           00000000 00110100 01000110 11111111

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3STATUS: 00000000 00000000 00000000 00000001
           00000000 00000000 00000000 00000001
MC3ADDR:   Couldn't read MSR 0x40e

Bank: 4 (0x410)
MC4CTL:    00000000 00000000 00000000 00001000
           00000000 00000000 00000000 00001000
MC4STATUS: 00100010 00000000 00000000 00000000
           00000000 00000000 00000000 00010001
MC4ADDR:   00000000 00110101 00100000 11111111
           00000000 00110101 00100000 11111111

Microcode version: 0x00000000000000d2

Connector type: Socket 8 (387 pin Dual Cavity PGA)


MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000000
MTRRphysMask0 (0x201): 0x0000000000000000
MTRRphysBase1 (0x202): 0x0000000020000000
MTRRphysMask1 (0x203): 0x0000000fe0000800
MTRRphysBase2 (0x204): 0x0000000040000000
MTRRphysMask2 (0x205): 0x0000000fc0000800
MTRRphysBase3 (0x206): 0x0000000080000000
MTRRphysMask3 (0x207): 0x0000000f80000800
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0000000005050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0000000000000000
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c06


200MHz processor (estimate).

--------------------------------------------------------------------------
