/*
 * Copyright (c) 2001-2021, The Ohio State University. All rights
 * reserved.
 *
 * This file is part of the MVAPICH2 software package developed by the
 * team members of The Ohio State University's Network-Based Computing
 * Laboratory (NBCL), headed by Professor Dhabaleswar K. (DK) Panda.
 *
 * For detailed copyright and licensing information, please refer to the
 * copyright file COPYRIGHT in the top level MVAPICH2 directory.
 */

#define GEN2__AMD_OPTERON_6136_32__MLX_CX_QDR__32PPN {		\
	{		\
	  64,		\
	  20,		\
	  {		\
	    {1, &MPIR_Allgather_RD_MV2},		\
	    {2, &MPIR_Allgather_RD_MV2},		\
	    {4, &MPIR_Allgather_RD_MV2},		\
	    {8, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {16, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {32, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {64, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {128, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {256, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {512, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {1024, &MPIR_Allgather_Ring_MV2},		\
	    {2048, &MPIR_Allgather_Ring_MV2},		\
	    {4096, &MPIR_Allgather_Ring_MV2},		\
	    {8192, &MPIR_Allgather_Ring_MV2},		\
	    {16384, &MPIR_Allgather_Ring_MV2},		\
	    {32768, &MPIR_Allgather_Ring_MV2},		\
	    {65536, &MPIR_Allgather_Ring_MV2},		\
	    {131072, &MPIR_Allgather_Ring_MV2},		\
	    {262144, &MPIR_Allgather_Ring_MV2},		\
	    {524288, &MPIR_Allgather_Ring_MV2},		\
	    {1048576, &MPIR_Allgather_Ring_MV2}		\
	  }		\
	},		\
		\
	{		\
	  128,		\
	  20,		\
	  {		\
	    {1, &MPIR_Allgather_RD_MV2},		\
	    {2, &MPIR_Allgather_RD_MV2},		\
	    {4, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {8, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {16, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {32, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {64, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {128, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {256, &MPIR_Allgather_Ring_MV2},		\
	    {512, &MPIR_Allgather_Ring_MV2},		\
	    {1024, &MPIR_Allgather_Ring_MV2},		\
	    {2048, &MPIR_Allgather_Ring_MV2},		\
	    {4096, &MPIR_Allgather_Ring_MV2},		\
	    {8192, &MPIR_Allgather_Ring_MV2},		\
	    {16384, &MPIR_Allgather_Ring_MV2},		\
	    {32768, &MPIR_Allgather_Ring_MV2},		\
	    {65536, &MPIR_Allgather_Ring_MV2},		\
	    {131072, &MPIR_Allgather_Ring_MV2},		\
	    {262144, &MPIR_Allgather_Ring_MV2},		\
	    {524288, &MPIR_Allgather_Ring_MV2},		\
	    {1048576, &MPIR_Allgather_Ring_MV2}		\
	  }		\
	},		\
		\
	{		\
	  256,		\
	  20,		\
	  {		\
	    {1, &MPIR_Allgather_RD_MV2},		\
	    {2, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {4, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {8, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {16, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {32, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {64, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {128, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {256, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {512, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {1024, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {2048, &MPIR_Allgather_Ring_MV2},		\
	    {4096, &MPIR_Allgather_Ring_MV2},		\
	    {8192, &MPIR_Allgather_Ring_MV2},		\
	    {16384, &MPIR_Allgather_Ring_MV2},		\
	    {32768, &MPIR_Allgather_Ring_MV2},		\
	    {65536, &MPIR_Allgather_Ring_MV2},		\
	    {131072, &MPIR_Allgather_Ring_MV2},		\
	    {262144, &MPIR_Allgather_Ring_MV2},		\
	    {524288, &MPIR_Allgather_Ring_MV2},		\
	    {1048576, &MPIR_Allgather_Ring_MV2}		\
	  }		\
	},		\
		\
	{		\
	  512,		\
	  20,		\
	  {		\
	    {1, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {2, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {4, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {8, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {16, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {32, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {64, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {128, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {256, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {512, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {1024, &MPIR_Allgather_RD_Allgather_Comm_MV2},		\
	    {2048, &MPIR_Allgather_Ring_MV2},		\
	    {4096, &MPIR_Allgather_Ring_MV2},		\
	    {8192, &MPIR_Allgather_Ring_MV2},		\
	    {16384, &MPIR_Allgather_Ring_MV2},		\
	    {32768, &MPIR_Allgather_Ring_MV2},		\
	    {65536, &MPIR_Allgather_Ring_MV2},		\
	    {131072, &MPIR_Allgather_Ring_MV2},		\
	    {262144, &MPIR_Allgather_Ring_MV2},		\
	    {524288, &MPIR_Allgather_Ring_MV2},		\
	    {1048576, &MPIR_Allgather_Bruck_MV2}		\
	  }		\
	}		\
};		
