#define fn(...) (&InstructionDecoder_amdgpu_cdna2::__VA_ARGS__)
const operandFactory amdgpu_cdna2_insn_entry::operandTable[] = {
	fn(NOTHING),
};
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_DS_insn_table = {
{amdgpu_cdna2_op_DS_ADD_U32,"DS_ADD_U32",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_DS_SUB_U32,"DS_SUB_U32",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_DS_RSUB_U32,"DS_RSUB_U32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_DS_INC_U32,"DS_INC_U32",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_DS_DEC_U32,"DS_DEC_U32",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_DS_MIN_I32,"DS_MIN_I32",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_DS_MAX_I32,"DS_MAX_I32",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_DS_MIN_U32,"DS_MIN_U32",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_DS_MAX_U32,"DS_MAX_U32",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_DS_AND_B32,"DS_AND_B32",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_DS_OR_B32,"DS_OR_B32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_DS_XOR_B32,"DS_XOR_B32",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_DS_MSKOR_B32,"DS_MSKOR_B32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_DS_WRITE_B32,"DS_WRITE_B32",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_DS_WRITE2_B32,"DS_WRITE2_B32",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_DS_CMPST_B32,"DS_CMPST_B32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_DS_CMPST_F32,"DS_CMPST_F32",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_DS_MIN_F32,"DS_MIN_F32",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_DS_MAX_F32,"DS_MAX_F32",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_DS_NOP,"DS_NOP",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_DS_ADD_F32,"DS_ADD_F32",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_DS_WRITE_B8,"DS_WRITE_B8",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_DS_WRITE_B16,"DS_WRITE_B16",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_DS_INC_RTN_U32,"DS_INC_RTN_U32",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_DS_AND_RTN_B32,"DS_AND_RTN_B32",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_DS_OR_RTN_B32,"DS_OR_RTN_B32",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_DS_READ_B32,"DS_READ_B32",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_DS_READ2_B32,"DS_READ2_B32",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_DS_READ2ST64_B32,"DS_READ2ST64_B32",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_DS_READ_I8,"DS_READ_I8",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_DS_READ_U8,"DS_READ_U8",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_DS_READ_I16,"DS_READ_I16",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_DS_READ_U16,"DS_READ_U16",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_DS_PERMUTE_B32,"DS_PERMUTE_B32",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_DS_ADD_U64,"DS_ADD_U64",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_DS_SUB_U64,"DS_SUB_U64",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_DS_RSUB_U64,"DS_RSUB_U64",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_DS_INC_U64,"DS_INC_U64",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_DS_DEC_U64,"DS_DEC_U64",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_DS_MIN_I64,"DS_MIN_I64",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_DS_MAX_I64,"DS_MAX_I64",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_DS_MIN_U64,"DS_MIN_U64",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_DS_MAX_U64,"DS_MAX_U64",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_DS_AND_B64,"DS_AND_B64",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_DS_OR_B64,"DS_OR_B64",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_DS_XOR_B64,"DS_XOR_B64",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_DS_MSKOR_B64,"DS_MSKOR_B64",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_DS_WRITE_B64,"DS_WRITE_B64",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_DS_WRITE2_B64,"DS_WRITE2_B64",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_DS_CMPST_B64,"DS_CMPST_B64",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_DS_CMPST_F64,"DS_CMPST_F64",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_DS_MIN_F64,"DS_MIN_F64",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_DS_MAX_F64,"DS_MAX_F64",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_DS_READ_U8_D16,"DS_READ_U8_D16",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_DS_READ_I8_D16,"DS_READ_I8_D16",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_DS_READ_U16_D16,"DS_READ_U16_D16",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_DS_ADD_F64,"DS_ADD_F64",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_DS_INC_RTN_U64,"DS_INC_RTN_U64",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_DS_AND_RTN_B64,"DS_AND_RTN_B64",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_DS_OR_RTN_B64,"DS_OR_RTN_B64",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64",0,&operandTable[0]} ,//108
{amdgpu_cdna2_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64",0,&operandTable[0]} ,//109
{amdgpu_cdna2_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64",0,&operandTable[0]} ,//110
{amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64",0,&operandTable[0]} ,//111
{amdgpu_cdna2_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64",0,&operandTable[0]} ,//112
{amdgpu_cdna2_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64",0,&operandTable[0]} ,//113
{amdgpu_cdna2_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64",0,&operandTable[0]} ,//114
{amdgpu_cdna2_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64",0,&operandTable[0]} ,//115
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117
{amdgpu_cdna2_op_DS_READ_B64,"DS_READ_B64",0,&operandTable[0]} ,//118
{amdgpu_cdna2_op_DS_READ2_B64,"DS_READ2_B64",0,&operandTable[0]} ,//119
{amdgpu_cdna2_op_DS_READ2ST64_B64,"DS_READ2ST64_B64",0,&operandTable[0]} ,//120
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123
{amdgpu_cdna2_op_DS_ADD_RTN_F64,"DS_ADD_RTN_F64",0,&operandTable[0]} ,//124
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125
{amdgpu_cdna2_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64",0,&operandTable[0]} ,//126
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151
{amdgpu_cdna2_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL",0,&operandTable[0]} ,//152
{amdgpu_cdna2_op_DS_GWS_INIT,"DS_GWS_INIT",0,&operandTable[0]} ,//153
{amdgpu_cdna2_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V",0,&operandTable[0]} ,//154
{amdgpu_cdna2_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR",0,&operandTable[0]} ,//155
{amdgpu_cdna2_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P",0,&operandTable[0]} ,//156
{amdgpu_cdna2_op_DS_GWS_BARRIER,"DS_GWS_BARRIER",0,&operandTable[0]} ,//157
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//160
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//161
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//162
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//163
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//164
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//165
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//166
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//167
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//168
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//169
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//170
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//171
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//172
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//173
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//174
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//175
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//176
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//177
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//178
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//179
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//180
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//181
{amdgpu_cdna2_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32",0,&operandTable[0]} ,//182
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//183
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//184
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//185
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//186
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//187
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//188
{amdgpu_cdna2_op_DS_CONSUME,"DS_CONSUME",0,&operandTable[0]} ,//189
{amdgpu_cdna2_op_DS_APPEND,"DS_APPEND",0,&operandTable[0]} ,//190
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//191
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//192
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//193
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//194
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//195
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//196
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//197
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//198
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//199
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//200
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//201
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//202
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//203
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//204
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//205
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//206
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//207
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//208
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//209
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//210
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//211
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//212
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//213
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//214
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//215
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//216
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//217
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//218
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//219
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//220
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//221
{amdgpu_cdna2_op_DS_WRITE_B96,"DS_WRITE_B96",0,&operandTable[0]} ,//222
{amdgpu_cdna2_op_DS_WRITE_B128,"DS_WRITE_B128",0,&operandTable[0]} ,//223
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//224
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//225
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//226
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//227
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//228
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//229
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//230
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//231
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//232
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//233
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//234
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//235
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//236
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//237
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//238
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//239
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//240
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//241
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//242
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//243
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//244
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//245
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//246
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//247
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//248
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//249
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//250
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//251
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//252
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//253
{amdgpu_cdna2_op_DS_READ_B96,"DS_READ_B96",0,&operandTable[0]} ,//254
{amdgpu_cdna2_op_DS_READ_B128,"DS_READ_B128",0,&operandTable[0]} ,//255
}; // end ENC_DS_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_FLAT_ATOMIC_ADD_F64,"FLAT_ATOMIC_ADD_F64",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_FLAT_ATOMIC_MIN_F64,"FLAT_ATOMIC_MIN_F64",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_FLAT_ATOMIC_MAX_F64,"FLAT_ATOMIC_MAX_F64",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108
}; // end ENC_FLAT_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F64,"GLOBAL_ATOMIC_ADD_F64",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_GLOBAL_ATOMIC_MIN_F64,"GLOBAL_ATOMIC_MIN_F64",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_GLOBAL_ATOMIC_MAX_F64,"GLOBAL_ATOMIC_MAX_F64",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108
}; // end ENC_FLAT_GLBL_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37
}; // end ENC_FLAT_SCRATCH_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table = {
{amdgpu_cdna2_op_IMAGE_LOAD,"IMAGE_LOAD",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_IMAGE_LOAD_MIP,"IMAGE_LOAD_MIP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_IMAGE_LOAD_PCK,"IMAGE_LOAD_PCK",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_IMAGE_LOAD_PCK_SGN,"IMAGE_LOAD_PCK_SGN",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK,"IMAGE_LOAD_MIP_PCK",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK_SGN,"IMAGE_LOAD_MIP_PCK_SGN",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_IMAGE_STORE,"IMAGE_STORE",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_IMAGE_STORE_MIP,"IMAGE_STORE_MIP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_IMAGE_STORE_PCK,"IMAGE_STORE_PCK",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_IMAGE_STORE_MIP_PCK,"IMAGE_STORE_MIP_PCK",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_IMAGE_GET_RESINFO,"IMAGE_GET_RESINFO",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_IMAGE_ATOMIC_SWAP,"IMAGE_ATOMIC_SWAP",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_IMAGE_ATOMIC_CMPSWAP,"IMAGE_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_IMAGE_ATOMIC_ADD,"IMAGE_ATOMIC_ADD",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_IMAGE_ATOMIC_SUB,"IMAGE_ATOMIC_SUB",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_IMAGE_ATOMIC_SMIN,"IMAGE_ATOMIC_SMIN",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_IMAGE_ATOMIC_UMIN,"IMAGE_ATOMIC_UMIN",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_IMAGE_ATOMIC_SMAX,"IMAGE_ATOMIC_SMAX",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_IMAGE_ATOMIC_UMAX,"IMAGE_ATOMIC_UMAX",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_IMAGE_ATOMIC_AND,"IMAGE_ATOMIC_AND",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_IMAGE_ATOMIC_OR,"IMAGE_ATOMIC_OR",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_IMAGE_ATOMIC_XOR,"IMAGE_ATOMIC_XOR",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_IMAGE_ATOMIC_INC,"IMAGE_ATOMIC_INC",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_IMAGE_ATOMIC_DEC,"IMAGE_ATOMIC_DEC",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_IMAGE_SAMPLE,"IMAGE_SAMPLE",0,&operandTable[0]} ,//32
}; // end ENC_MIMG_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table = {
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW",0,&operandTable[0]} ,//15
}; // end ENC_MTBUF_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table = {
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_BUFFER_WBL2,"BUFFER_WBL2",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_BUFFER_INVL2,"BUFFER_INVL2",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_BUFFER_STORE_LDS_DWORD,"BUFFER_STORE_LDS_DWORD",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_BUFFER_WBINVL1,"BUFFER_WBINVL1",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_BUFFER_WBINVL1_VOL,"BUFFER_WBINVL1_VOL",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F64,"BUFFER_ATOMIC_ADD_F64",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_BUFFER_ATOMIC_MIN_F64,"BUFFER_ATOMIC_MIN_F64",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_BUFFER_ATOMIC_MAX_F64,"BUFFER_ATOMIC_MAX_F64",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108
}; // end ENC_MUBUF_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table = {
{amdgpu_cdna2_op_S_LOAD_DWORD,"S_LOAD_DWORD",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_STORE_DWORD,"S_STORE_DWORD",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_STORE_DWORDX2,"S_STORE_DWORDX2",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_STORE_DWORDX4,"S_STORE_DWORDX4",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_S_DCACHE_INV,"S_DCACHE_INV",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_S_DCACHE_WB,"S_DCACHE_WB",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_MEMTIME,"S_MEMTIME",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_MEMREALTIME,"S_MEMREALTIME",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_ATC_PROBE,"S_ATC_PROBE",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//109
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//110
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//111
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//112
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//113
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//114
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//115
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//118
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//119
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//120
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//126
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127
{amdgpu_cdna2_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP",0,&operandTable[0]} ,//128
{amdgpu_cdna2_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//129
{amdgpu_cdna2_op_S_ATOMIC_ADD,"S_ATOMIC_ADD",0,&operandTable[0]} ,//130
{amdgpu_cdna2_op_S_ATOMIC_SUB,"S_ATOMIC_SUB",0,&operandTable[0]} ,//131
{amdgpu_cdna2_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN",0,&operandTable[0]} ,//132
{amdgpu_cdna2_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN",0,&operandTable[0]} ,//133
{amdgpu_cdna2_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX",0,&operandTable[0]} ,//134
{amdgpu_cdna2_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX",0,&operandTable[0]} ,//135
{amdgpu_cdna2_op_S_ATOMIC_AND,"S_ATOMIC_AND",0,&operandTable[0]} ,//136
{amdgpu_cdna2_op_S_ATOMIC_OR,"S_ATOMIC_OR",0,&operandTable[0]} ,//137
{amdgpu_cdna2_op_S_ATOMIC_XOR,"S_ATOMIC_XOR",0,&operandTable[0]} ,//138
{amdgpu_cdna2_op_S_ATOMIC_INC,"S_ATOMIC_INC",0,&operandTable[0]} ,//139
{amdgpu_cdna2_op_S_ATOMIC_DEC,"S_ATOMIC_DEC",0,&operandTable[0]} ,//140
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159
{amdgpu_cdna2_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//160
{amdgpu_cdna2_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//161
{amdgpu_cdna2_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2",0,&operandTable[0]} ,//162
{amdgpu_cdna2_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2",0,&operandTable[0]} ,//163
{amdgpu_cdna2_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//164
{amdgpu_cdna2_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//165
{amdgpu_cdna2_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//166
{amdgpu_cdna2_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//167
{amdgpu_cdna2_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2",0,&operandTable[0]} ,//168
{amdgpu_cdna2_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2",0,&operandTable[0]} ,//169
{amdgpu_cdna2_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2",0,&operandTable[0]} ,//170
{amdgpu_cdna2_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2",0,&operandTable[0]} ,//171
{amdgpu_cdna2_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2",0,&operandTable[0]} ,//172
}; // end ENC_SMEM_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table = {
{amdgpu_cdna2_op_S_MOV_B32,"S_MOV_B32",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_MOV_B64,"S_MOV_B64",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_CMOV_B32,"S_CMOV_B32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_CMOV_B64,"S_CMOV_B64",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOT_B32,"S_NOT_B32",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOT_B64,"S_NOT_B64",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_WQM_B32,"S_WQM_B32",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_WQM_B64,"S_WQM_B64",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_BREV_B32,"S_BREV_B32",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_BREV_B64,"S_BREV_B64",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_FF0_I32_B32,"S_FF0_I32_B32",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_FF0_I32_B64,"S_FF0_I32_B64",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_FF1_I32_B32,"S_FF1_I32_B32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_FF1_I32_B64,"S_FF1_I32_B64",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_FLBIT_I32,"S_FLBIT_I32",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_SEXT_I32_I8,"S_SEXT_I32_I8",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_SEXT_I32_I16,"S_SEXT_I32_I16",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_BITSET0_B32,"S_BITSET0_B32",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_BITSET0_B64,"S_BITSET0_B64",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_BITSET1_B32,"S_BITSET1_B32",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_BITSET1_B64,"S_BITSET1_B64",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_GETPC_B64,"S_GETPC_B64",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_SETPC_B64,"S_SETPC_B64",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_SWAPPC_B64,"S_SWAPPC_B64",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_RFE_B64,"S_RFE_B64",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_QUADMASK_B32,"S_QUADMASK_B32",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_QUADMASK_B64,"S_QUADMASK_B64",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_MOVRELS_B32,"S_MOVRELS_B32",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_MOVRELS_B64,"S_MOVRELS_B64",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_MOVRELD_B32,"S_MOVRELD_B32",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_MOVRELD_B64,"S_MOVRELD_B64",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_ABS_I32,"S_ABS_I32",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32",0,&operandTable[0]} ,//55
}; // end ENC_SOP1_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table = {
{amdgpu_cdna2_op_S_ADD_U32,"S_ADD_U32",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_SUB_U32,"S_SUB_U32",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_ADD_I32,"S_ADD_I32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_SUB_I32,"S_SUB_I32",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_ADDC_U32,"S_ADDC_U32",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_SUBB_U32,"S_SUBB_U32",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_MIN_I32,"S_MIN_I32",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_MIN_U32,"S_MIN_U32",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_MAX_I32,"S_MAX_I32",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_MAX_U32,"S_MAX_U32",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_CSELECT_B32,"S_CSELECT_B32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_CSELECT_B64,"S_CSELECT_B64",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_AND_B32,"S_AND_B32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_AND_B64,"S_AND_B64",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_OR_B32,"S_OR_B32",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_OR_B64,"S_OR_B64",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_XOR_B32,"S_XOR_B32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_XOR_B64,"S_XOR_B64",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_ANDN2_B32,"S_ANDN2_B32",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_ANDN2_B64,"S_ANDN2_B64",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_ORN2_B32,"S_ORN2_B32",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_ORN2_B64,"S_ORN2_B64",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NAND_B32,"S_NAND_B32",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NAND_B64,"S_NAND_B64",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOR_B32,"S_NOR_B32",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOR_B64,"S_NOR_B64",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_XNOR_B32,"S_XNOR_B32",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_XNOR_B64,"S_XNOR_B64",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_LSHL_B32,"S_LSHL_B32",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_LSHL_B64,"S_LSHL_B64",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_LSHR_B32,"S_LSHR_B32",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_LSHR_B64,"S_LSHR_B64",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_S_ASHR_I32,"S_ASHR_I32",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_S_ASHR_I64,"S_ASHR_I64",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_S_BFM_B32,"S_BFM_B32",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_S_BFM_B64,"S_BFM_B64",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_MUL_I32,"S_MUL_I32",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_BFE_U32,"S_BFE_U32",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_BFE_I32,"S_BFE_I32",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_BFE_U64,"S_BFE_U64",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_BFE_I64,"S_BFE_I64",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_ABSDIFF_I32,"S_ABSDIFF_I32",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_MUL_HI_U32,"S_MUL_HI_U32",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_MUL_HI_I32,"S_MUL_HI_I32",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16",0,&operandTable[0]} ,//52
}; // end ENC_SOP2_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table = {
{amdgpu_cdna2_op_S_CMP_EQ_I32,"S_CMP_EQ_I32",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_CMP_LG_I32,"S_CMP_LG_I32",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_CMP_GT_I32,"S_CMP_GT_I32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_CMP_GE_I32,"S_CMP_GE_I32",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_CMP_LT_I32,"S_CMP_LT_I32",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_CMP_LE_I32,"S_CMP_LE_I32",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_CMP_EQ_U32,"S_CMP_EQ_U32",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_CMP_LG_U32,"S_CMP_LG_U32",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_CMP_GT_U32,"S_CMP_GT_U32",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_CMP_GE_U32,"S_CMP_GE_U32",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_CMP_LT_U32,"S_CMP_LT_U32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_CMP_LE_U32,"S_CMP_LE_U32",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_BITCMP0_B32,"S_BITCMP0_B32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_BITCMP1_B32,"S_BITCMP1_B32",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_BITCMP0_B64,"S_BITCMP0_B64",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_BITCMP1_B64,"S_BITCMP1_B64",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_SETVSKIP,"S_SETVSKIP",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_CMP_EQ_U64,"S_CMP_EQ_U64",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_CMP_LG_U64,"S_CMP_LG_U64",0,&operandTable[0]} ,//19
}; // end ENC_SOPC_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table = {
{amdgpu_cdna2_op_S_MOVK_I32,"S_MOVK_I32",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_CMOVK_I32,"S_CMOVK_I32",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_CMPK_LG_I32,"S_CMPK_LG_I32",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_CMPK_GT_I32,"S_CMPK_GT_I32",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_CMPK_GE_I32,"S_CMPK_GE_I32",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_CMPK_LT_I32,"S_CMPK_LT_I32",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_CMPK_LE_I32,"S_CMPK_LE_I32",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_CMPK_LG_U32,"S_CMPK_LG_U32",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_CMPK_GT_U32,"S_CMPK_GT_U32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_CMPK_GE_U32,"S_CMPK_GE_U32",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_CMPK_LT_U32,"S_CMPK_LT_U32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_CMPK_LE_U32,"S_CMPK_LE_U32",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_ADDK_I32,"S_ADDK_I32",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_MULK_I32,"S_MULK_I32",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_GETREG_B32,"S_GETREG_B32",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_SETREG_B32,"S_SETREG_B32",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_SETREG_IMM32_B32,"S_SETREG_IMM32_B32",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_CALL_B64,"S_CALL_B64",0,&operandTable[0]} ,//21
}; // end ENC_SOPK_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_ENDPGM,"S_ENDPGM",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_BRANCH,"S_BRANCH",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_WAKEUP,"S_WAKEUP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_BARRIER,"S_BARRIER",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_SETKILL,"S_SETKILL",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_WAITCNT,"S_WAITCNT",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_SETHALT,"S_SETHALT",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_SLEEP,"S_SLEEP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_SETPRIO,"S_SETPRIO",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_SENDMSG,"S_SENDMSG",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_SENDMSGHALT,"S_SENDMSGHALT",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_TRAP,"S_TRAP",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_ICACHE_INV,"S_ICACHE_INV",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_INCPERFLEVEL,"S_INCPERFLEVEL",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_DECPERFLEVEL,"S_DECPERFLEVEL",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_TTRACEDATA,"S_TTRACEDATA",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE",0,&operandTable[0]} ,//30
}; // end ENC_SOPP_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table = {
{amdgpu_cdna2_op_V_NOP,"V_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_V_MOV_B32,"V_MOV_B32",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_V_CVT_I32_F64,"V_CVT_I32_F64",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_V_CVT_F64_I32,"V_CVT_F64_I32",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_V_CVT_F32_I32,"V_CVT_F32_I32",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_V_CVT_F32_U32,"V_CVT_F32_U32",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_V_CVT_U32_F32,"V_CVT_U32_F32",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_V_CVT_I32_F32,"V_CVT_I32_F32",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_V_CVT_F16_F32,"V_CVT_F16_F32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_V_CVT_F32_F16,"V_CVT_F32_F16",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_V_CVT_F32_F64,"V_CVT_F32_F64",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_V_CVT_F64_F32,"V_CVT_F64_F32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_V_CVT_U32_F64,"V_CVT_U32_F64",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_V_CVT_F64_U32,"V_CVT_F64_U32",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_V_TRUNC_F64,"V_TRUNC_F64",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_V_CEIL_F64,"V_CEIL_F64",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_V_RNDNE_F64,"V_RNDNE_F64",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_V_FLOOR_F64,"V_FLOOR_F64",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_V_FRACT_F32,"V_FRACT_F32",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_V_TRUNC_F32,"V_TRUNC_F32",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_V_CEIL_F32,"V_CEIL_F32",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_V_RNDNE_F32,"V_RNDNE_F32",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_V_FLOOR_F32,"V_FLOOR_F32",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_V_EXP_F32,"V_EXP_F32",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_V_LOG_F32,"V_LOG_F32",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_V_RCP_F32,"V_RCP_F32",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_V_RSQ_F32,"V_RSQ_F32",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_V_RCP_F64,"V_RCP_F64",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_V_RSQ_F64,"V_RSQ_F64",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_V_SQRT_F32,"V_SQRT_F32",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_V_SQRT_F64,"V_SQRT_F64",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_V_SIN_F32,"V_SIN_F32",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_V_COS_F32,"V_COS_F32",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_V_NOT_B32,"V_NOT_B32",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_V_BFREV_B32,"V_BFREV_B32",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_V_FFBH_U32,"V_FFBH_U32",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_V_FFBL_B32,"V_FFBL_B32",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_V_FFBH_I32,"V_FFBH_I32",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_V_FRACT_F64,"V_FRACT_F64",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_V_CLREXCP,"V_CLREXCP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_V_CVT_F16_U16,"V_CVT_F16_U16",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_V_CVT_F16_I16,"V_CVT_F16_I16",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_V_CVT_U16_F16,"V_CVT_U16_F16",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_V_CVT_I16_F16,"V_CVT_I16_F16",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_V_RCP_F16,"V_RCP_F16",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_V_SQRT_F16,"V_SQRT_F16",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_V_RSQ_F16,"V_RSQ_F16",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_V_LOG_F16,"V_LOG_F16",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_V_EXP_F16,"V_EXP_F16",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_V_FLOOR_F16,"V_FLOOR_F16",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_V_CEIL_F16,"V_CEIL_F16",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_V_TRUNC_F16,"V_TRUNC_F16",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_V_RNDNE_F16,"V_RNDNE_F16",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_V_FRACT_F16,"V_FRACT_F16",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_V_SIN_F16,"V_SIN_F16",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_V_COS_F16,"V_COS_F16",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_V_SWAP_B32,"V_SWAP_B32",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32",0,&operandTable[0]} ,//82
}; // end ENC_VOP1_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_V_CMP_F_F16,"V_CMP_F_F16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_V_CMP_LT_F16,"V_CMP_LT_F16",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_V_CMP_EQ_F16,"V_CMP_EQ_F16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_V_CMP_LE_F16,"V_CMP_LE_F16",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_V_CMP_GT_F16,"V_CMP_GT_F16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_V_CMP_LG_F16,"V_CMP_LG_F16",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_V_CMP_GE_F16,"V_CMP_GE_F16",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_V_CMP_O_F16,"V_CMP_O_F16",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_V_CMP_U_F16,"V_CMP_U_F16",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_V_CMP_NGE_F16,"V_CMP_NGE_F16",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_V_CMP_NLG_F16,"V_CMP_NLG_F16",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_V_CMP_NGT_F16,"V_CMP_NGT_F16",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_V_CMP_NLE_F16,"V_CMP_NLE_F16",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_V_CMP_NLT_F16,"V_CMP_NLT_F16",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_V_CMP_TRU_F16,"V_CMP_TRU_F16",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_V_CMPX_F_F16,"V_CMPX_F_F16",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_V_CMPX_LT_F16,"V_CMPX_LT_F16",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_V_CMPX_LE_F16,"V_CMPX_LE_F16",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_V_CMPX_GT_F16,"V_CMPX_GT_F16",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_V_CMPX_LG_F16,"V_CMPX_LG_F16",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_V_CMPX_GE_F16,"V_CMPX_GE_F16",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_V_CMPX_O_F16,"V_CMPX_O_F16",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_V_CMPX_U_F16,"V_CMPX_U_F16",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_V_CMP_F_F32,"V_CMP_F_F32",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_V_CMP_LT_F32,"V_CMP_LT_F32",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_V_CMP_EQ_F32,"V_CMP_EQ_F32",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_V_CMP_LE_F32,"V_CMP_LE_F32",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_V_CMP_GT_F32,"V_CMP_GT_F32",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_V_CMP_LG_F32,"V_CMP_LG_F32",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_V_CMP_GE_F32,"V_CMP_GE_F32",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_V_CMP_O_F32,"V_CMP_O_F32",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_V_CMP_U_F32,"V_CMP_U_F32",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_V_CMP_NGE_F32,"V_CMP_NGE_F32",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_V_CMP_NLG_F32,"V_CMP_NLG_F32",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_V_CMP_NGT_F32,"V_CMP_NGT_F32",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_V_CMP_NLE_F32,"V_CMP_NLE_F32",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_V_CMP_NLT_F32,"V_CMP_NLT_F32",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_V_CMP_TRU_F32,"V_CMP_TRU_F32",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_V_CMPX_F_F32,"V_CMPX_F_F32",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_V_CMPX_LT_F32,"V_CMPX_LT_F32",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_V_CMPX_LE_F32,"V_CMPX_LE_F32",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_V_CMPX_GT_F32,"V_CMPX_GT_F32",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_V_CMPX_LG_F32,"V_CMPX_LG_F32",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_V_CMPX_GE_F32,"V_CMPX_GE_F32",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_V_CMPX_O_F32,"V_CMPX_O_F32",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_V_CMPX_U_F32,"V_CMPX_U_F32",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_V_CMP_F_F64,"V_CMP_F_F64",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_V_CMP_LT_F64,"V_CMP_LT_F64",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_V_CMP_EQ_F64,"V_CMP_EQ_F64",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_V_CMP_LE_F64,"V_CMP_LE_F64",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_V_CMP_GT_F64,"V_CMP_GT_F64",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_V_CMP_LG_F64,"V_CMP_LG_F64",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_V_CMP_GE_F64,"V_CMP_GE_F64",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_V_CMP_O_F64,"V_CMP_O_F64",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_V_CMP_U_F64,"V_CMP_U_F64",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_V_CMP_NGE_F64,"V_CMP_NGE_F64",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_V_CMP_NLG_F64,"V_CMP_NLG_F64",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_V_CMP_NGT_F64,"V_CMP_NGT_F64",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_V_CMP_NLE_F64,"V_CMP_NLE_F64",0,&operandTable[0]} ,//108
{amdgpu_cdna2_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64",0,&operandTable[0]} ,//109
{amdgpu_cdna2_op_V_CMP_NLT_F64,"V_CMP_NLT_F64",0,&operandTable[0]} ,//110
{amdgpu_cdna2_op_V_CMP_TRU_F64,"V_CMP_TRU_F64",0,&operandTable[0]} ,//111
{amdgpu_cdna2_op_V_CMPX_F_F64,"V_CMPX_F_F64",0,&operandTable[0]} ,//112
{amdgpu_cdna2_op_V_CMPX_LT_F64,"V_CMPX_LT_F64",0,&operandTable[0]} ,//113
{amdgpu_cdna2_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64",0,&operandTable[0]} ,//114
{amdgpu_cdna2_op_V_CMPX_LE_F64,"V_CMPX_LE_F64",0,&operandTable[0]} ,//115
{amdgpu_cdna2_op_V_CMPX_GT_F64,"V_CMPX_GT_F64",0,&operandTable[0]} ,//116
{amdgpu_cdna2_op_V_CMPX_LG_F64,"V_CMPX_LG_F64",0,&operandTable[0]} ,//117
{amdgpu_cdna2_op_V_CMPX_GE_F64,"V_CMPX_GE_F64",0,&operandTable[0]} ,//118
{amdgpu_cdna2_op_V_CMPX_O_F64,"V_CMPX_O_F64",0,&operandTable[0]} ,//119
{amdgpu_cdna2_op_V_CMPX_U_F64,"V_CMPX_U_F64",0,&operandTable[0]} ,//120
{amdgpu_cdna2_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64",0,&operandTable[0]} ,//121
{amdgpu_cdna2_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64",0,&operandTable[0]} ,//122
{amdgpu_cdna2_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64",0,&operandTable[0]} ,//123
{amdgpu_cdna2_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64",0,&operandTable[0]} ,//124
{amdgpu_cdna2_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64",0,&operandTable[0]} ,//125
{amdgpu_cdna2_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64",0,&operandTable[0]} ,//126
{amdgpu_cdna2_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64",0,&operandTable[0]} ,//127
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159
{amdgpu_cdna2_op_V_CMP_F_I16,"V_CMP_F_I16",0,&operandTable[0]} ,//160
{amdgpu_cdna2_op_V_CMP_LT_I16,"V_CMP_LT_I16",0,&operandTable[0]} ,//161
{amdgpu_cdna2_op_V_CMP_EQ_I16,"V_CMP_EQ_I16",0,&operandTable[0]} ,//162
{amdgpu_cdna2_op_V_CMP_LE_I16,"V_CMP_LE_I16",0,&operandTable[0]} ,//163
{amdgpu_cdna2_op_V_CMP_GT_I16,"V_CMP_GT_I16",0,&operandTable[0]} ,//164
{amdgpu_cdna2_op_V_CMP_NE_I16,"V_CMP_NE_I16",0,&operandTable[0]} ,//165
{amdgpu_cdna2_op_V_CMP_GE_I16,"V_CMP_GE_I16",0,&operandTable[0]} ,//166
{amdgpu_cdna2_op_V_CMP_T_I16,"V_CMP_T_I16",0,&operandTable[0]} ,//167
{amdgpu_cdna2_op_V_CMP_F_U16,"V_CMP_F_U16",0,&operandTable[0]} ,//168
{amdgpu_cdna2_op_V_CMP_LT_U16,"V_CMP_LT_U16",0,&operandTable[0]} ,//169
{amdgpu_cdna2_op_V_CMP_EQ_U16,"V_CMP_EQ_U16",0,&operandTable[0]} ,//170
{amdgpu_cdna2_op_V_CMP_LE_U16,"V_CMP_LE_U16",0,&operandTable[0]} ,//171
{amdgpu_cdna2_op_V_CMP_GT_U16,"V_CMP_GT_U16",0,&operandTable[0]} ,//172
{amdgpu_cdna2_op_V_CMP_NE_U16,"V_CMP_NE_U16",0,&operandTable[0]} ,//173
{amdgpu_cdna2_op_V_CMP_GE_U16,"V_CMP_GE_U16",0,&operandTable[0]} ,//174
{amdgpu_cdna2_op_V_CMP_T_U16,"V_CMP_T_U16",0,&operandTable[0]} ,//175
{amdgpu_cdna2_op_V_CMPX_F_I16,"V_CMPX_F_I16",0,&operandTable[0]} ,//176
{amdgpu_cdna2_op_V_CMPX_LT_I16,"V_CMPX_LT_I16",0,&operandTable[0]} ,//177
{amdgpu_cdna2_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16",0,&operandTable[0]} ,//178
{amdgpu_cdna2_op_V_CMPX_LE_I16,"V_CMPX_LE_I16",0,&operandTable[0]} ,//179
{amdgpu_cdna2_op_V_CMPX_GT_I16,"V_CMPX_GT_I16",0,&operandTable[0]} ,//180
{amdgpu_cdna2_op_V_CMPX_NE_I16,"V_CMPX_NE_I16",0,&operandTable[0]} ,//181
{amdgpu_cdna2_op_V_CMPX_GE_I16,"V_CMPX_GE_I16",0,&operandTable[0]} ,//182
{amdgpu_cdna2_op_V_CMPX_T_I16,"V_CMPX_T_I16",0,&operandTable[0]} ,//183
{amdgpu_cdna2_op_V_CMPX_F_U16,"V_CMPX_F_U16",0,&operandTable[0]} ,//184
{amdgpu_cdna2_op_V_CMPX_LT_U16,"V_CMPX_LT_U16",0,&operandTable[0]} ,//185
{amdgpu_cdna2_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16",0,&operandTable[0]} ,//186
{amdgpu_cdna2_op_V_CMPX_LE_U16,"V_CMPX_LE_U16",0,&operandTable[0]} ,//187
{amdgpu_cdna2_op_V_CMPX_GT_U16,"V_CMPX_GT_U16",0,&operandTable[0]} ,//188
{amdgpu_cdna2_op_V_CMPX_NE_U16,"V_CMPX_NE_U16",0,&operandTable[0]} ,//189
{amdgpu_cdna2_op_V_CMPX_GE_U16,"V_CMPX_GE_U16",0,&operandTable[0]} ,//190
{amdgpu_cdna2_op_V_CMPX_T_U16,"V_CMPX_T_U16",0,&operandTable[0]} ,//191
{amdgpu_cdna2_op_V_CMP_F_I32,"V_CMP_F_I32",0,&operandTable[0]} ,//192
{amdgpu_cdna2_op_V_CMP_LT_I32,"V_CMP_LT_I32",0,&operandTable[0]} ,//193
{amdgpu_cdna2_op_V_CMP_EQ_I32,"V_CMP_EQ_I32",0,&operandTable[0]} ,//194
{amdgpu_cdna2_op_V_CMP_LE_I32,"V_CMP_LE_I32",0,&operandTable[0]} ,//195
{amdgpu_cdna2_op_V_CMP_GT_I32,"V_CMP_GT_I32",0,&operandTable[0]} ,//196
{amdgpu_cdna2_op_V_CMP_NE_I32,"V_CMP_NE_I32",0,&operandTable[0]} ,//197
{amdgpu_cdna2_op_V_CMP_GE_I32,"V_CMP_GE_I32",0,&operandTable[0]} ,//198
{amdgpu_cdna2_op_V_CMP_T_I32,"V_CMP_T_I32",0,&operandTable[0]} ,//199
{amdgpu_cdna2_op_V_CMP_F_U32,"V_CMP_F_U32",0,&operandTable[0]} ,//200
{amdgpu_cdna2_op_V_CMP_LT_U32,"V_CMP_LT_U32",0,&operandTable[0]} ,//201
{amdgpu_cdna2_op_V_CMP_EQ_U32,"V_CMP_EQ_U32",0,&operandTable[0]} ,//202
{amdgpu_cdna2_op_V_CMP_LE_U32,"V_CMP_LE_U32",0,&operandTable[0]} ,//203
{amdgpu_cdna2_op_V_CMP_GT_U32,"V_CMP_GT_U32",0,&operandTable[0]} ,//204
{amdgpu_cdna2_op_V_CMP_NE_U32,"V_CMP_NE_U32",0,&operandTable[0]} ,//205
{amdgpu_cdna2_op_V_CMP_GE_U32,"V_CMP_GE_U32",0,&operandTable[0]} ,//206
{amdgpu_cdna2_op_V_CMP_T_U32,"V_CMP_T_U32",0,&operandTable[0]} ,//207
{amdgpu_cdna2_op_V_CMPX_F_I32,"V_CMPX_F_I32",0,&operandTable[0]} ,//208
{amdgpu_cdna2_op_V_CMPX_LT_I32,"V_CMPX_LT_I32",0,&operandTable[0]} ,//209
{amdgpu_cdna2_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32",0,&operandTable[0]} ,//210
{amdgpu_cdna2_op_V_CMPX_LE_I32,"V_CMPX_LE_I32",0,&operandTable[0]} ,//211
{amdgpu_cdna2_op_V_CMPX_GT_I32,"V_CMPX_GT_I32",0,&operandTable[0]} ,//212
{amdgpu_cdna2_op_V_CMPX_NE_I32,"V_CMPX_NE_I32",0,&operandTable[0]} ,//213
{amdgpu_cdna2_op_V_CMPX_GE_I32,"V_CMPX_GE_I32",0,&operandTable[0]} ,//214
{amdgpu_cdna2_op_V_CMPX_T_I32,"V_CMPX_T_I32",0,&operandTable[0]} ,//215
{amdgpu_cdna2_op_V_CMPX_F_U32,"V_CMPX_F_U32",0,&operandTable[0]} ,//216
{amdgpu_cdna2_op_V_CMPX_LT_U32,"V_CMPX_LT_U32",0,&operandTable[0]} ,//217
{amdgpu_cdna2_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32",0,&operandTable[0]} ,//218
{amdgpu_cdna2_op_V_CMPX_LE_U32,"V_CMPX_LE_U32",0,&operandTable[0]} ,//219
{amdgpu_cdna2_op_V_CMPX_GT_U32,"V_CMPX_GT_U32",0,&operandTable[0]} ,//220
{amdgpu_cdna2_op_V_CMPX_NE_U32,"V_CMPX_NE_U32",0,&operandTable[0]} ,//221
{amdgpu_cdna2_op_V_CMPX_GE_U32,"V_CMPX_GE_U32",0,&operandTable[0]} ,//222
{amdgpu_cdna2_op_V_CMPX_T_U32,"V_CMPX_T_U32",0,&operandTable[0]} ,//223
{amdgpu_cdna2_op_V_CMP_F_I64,"V_CMP_F_I64",0,&operandTable[0]} ,//224
{amdgpu_cdna2_op_V_CMP_LT_I64,"V_CMP_LT_I64",0,&operandTable[0]} ,//225
{amdgpu_cdna2_op_V_CMP_EQ_I64,"V_CMP_EQ_I64",0,&operandTable[0]} ,//226
{amdgpu_cdna2_op_V_CMP_LE_I64,"V_CMP_LE_I64",0,&operandTable[0]} ,//227
{amdgpu_cdna2_op_V_CMP_GT_I64,"V_CMP_GT_I64",0,&operandTable[0]} ,//228
{amdgpu_cdna2_op_V_CMP_NE_I64,"V_CMP_NE_I64",0,&operandTable[0]} ,//229
{amdgpu_cdna2_op_V_CMP_GE_I64,"V_CMP_GE_I64",0,&operandTable[0]} ,//230
{amdgpu_cdna2_op_V_CMP_T_I64,"V_CMP_T_I64",0,&operandTable[0]} ,//231
{amdgpu_cdna2_op_V_CMP_F_U64,"V_CMP_F_U64",0,&operandTable[0]} ,//232
{amdgpu_cdna2_op_V_CMP_LT_U64,"V_CMP_LT_U64",0,&operandTable[0]} ,//233
{amdgpu_cdna2_op_V_CMP_EQ_U64,"V_CMP_EQ_U64",0,&operandTable[0]} ,//234
{amdgpu_cdna2_op_V_CMP_LE_U64,"V_CMP_LE_U64",0,&operandTable[0]} ,//235
{amdgpu_cdna2_op_V_CMP_GT_U64,"V_CMP_GT_U64",0,&operandTable[0]} ,//236
{amdgpu_cdna2_op_V_CMP_NE_U64,"V_CMP_NE_U64",0,&operandTable[0]} ,//237
{amdgpu_cdna2_op_V_CMP_GE_U64,"V_CMP_GE_U64",0,&operandTable[0]} ,//238
{amdgpu_cdna2_op_V_CMP_T_U64,"V_CMP_T_U64",0,&operandTable[0]} ,//239
{amdgpu_cdna2_op_V_CMPX_F_I64,"V_CMPX_F_I64",0,&operandTable[0]} ,//240
{amdgpu_cdna2_op_V_CMPX_LT_I64,"V_CMPX_LT_I64",0,&operandTable[0]} ,//241
{amdgpu_cdna2_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64",0,&operandTable[0]} ,//242
{amdgpu_cdna2_op_V_CMPX_LE_I64,"V_CMPX_LE_I64",0,&operandTable[0]} ,//243
{amdgpu_cdna2_op_V_CMPX_GT_I64,"V_CMPX_GT_I64",0,&operandTable[0]} ,//244
{amdgpu_cdna2_op_V_CMPX_NE_I64,"V_CMPX_NE_I64",0,&operandTable[0]} ,//245
{amdgpu_cdna2_op_V_CMPX_GE_I64,"V_CMPX_GE_I64",0,&operandTable[0]} ,//246
{amdgpu_cdna2_op_V_CMPX_T_I64,"V_CMPX_T_I64",0,&operandTable[0]} ,//247
{amdgpu_cdna2_op_V_CMPX_F_U64,"V_CMPX_F_U64",0,&operandTable[0]} ,//248
{amdgpu_cdna2_op_V_CMPX_LT_U64,"V_CMPX_LT_U64",0,&operandTable[0]} ,//249
{amdgpu_cdna2_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64",0,&operandTable[0]} ,//250
{amdgpu_cdna2_op_V_CMPX_LE_U64,"V_CMPX_LE_U64",0,&operandTable[0]} ,//251
{amdgpu_cdna2_op_V_CMPX_GT_U64,"V_CMPX_GT_U64",0,&operandTable[0]} ,//252
{amdgpu_cdna2_op_V_CMPX_NE_U64,"V_CMPX_NE_U64",0,&operandTable[0]} ,//253
{amdgpu_cdna2_op_V_CMPX_GE_U64,"V_CMPX_GE_U64",0,&operandTable[0]} ,//254
{amdgpu_cdna2_op_V_CMPX_T_U64,"V_CMPX_T_U64",0,&operandTable[0]} ,//255
{amdgpu_cdna2_op_V_CNDMASK_B32,"V_CNDMASK_B32",0,&operandTable[0]} ,//256
{amdgpu_cdna2_op_V_ADD_F32,"V_ADD_F32",0,&operandTable[0]} ,//257
{amdgpu_cdna2_op_V_SUB_F32,"V_SUB_F32",0,&operandTable[0]} ,//258
{amdgpu_cdna2_op_V_SUBREV_F32,"V_SUBREV_F32",0,&operandTable[0]} ,//259
{amdgpu_cdna2_op_V_FMAC_F64,"V_FMAC_F64",0,&operandTable[0]} ,//260
{amdgpu_cdna2_op_V_MUL_F32,"V_MUL_F32",0,&operandTable[0]} ,//261
{amdgpu_cdna2_op_V_MUL_I32_I24,"V_MUL_I32_I24",0,&operandTable[0]} ,//262
{amdgpu_cdna2_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24",0,&operandTable[0]} ,//263
{amdgpu_cdna2_op_V_MUL_U32_U24,"V_MUL_U32_U24",0,&operandTable[0]} ,//264
{amdgpu_cdna2_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24",0,&operandTable[0]} ,//265
{amdgpu_cdna2_op_V_MIN_F32,"V_MIN_F32",0,&operandTable[0]} ,//266
{amdgpu_cdna2_op_V_MAX_F32,"V_MAX_F32",0,&operandTable[0]} ,//267
{amdgpu_cdna2_op_V_MIN_I32,"V_MIN_I32",0,&operandTable[0]} ,//268
{amdgpu_cdna2_op_V_MAX_I32,"V_MAX_I32",0,&operandTable[0]} ,//269
{amdgpu_cdna2_op_V_MIN_U32,"V_MIN_U32",0,&operandTable[0]} ,//270
{amdgpu_cdna2_op_V_MAX_U32,"V_MAX_U32",0,&operandTable[0]} ,//271
{amdgpu_cdna2_op_V_LSHRREV_B32,"V_LSHRREV_B32",0,&operandTable[0]} ,//272
{amdgpu_cdna2_op_V_ASHRREV_I32,"V_ASHRREV_I32",0,&operandTable[0]} ,//273
{amdgpu_cdna2_op_V_LSHLREV_B32,"V_LSHLREV_B32",0,&operandTable[0]} ,//274
{amdgpu_cdna2_op_V_AND_B32,"V_AND_B32",0,&operandTable[0]} ,//275
{amdgpu_cdna2_op_V_OR_B32,"V_OR_B32",0,&operandTable[0]} ,//276
{amdgpu_cdna2_op_V_XOR_B32,"V_XOR_B32",0,&operandTable[0]} ,//277
{amdgpu_cdna2_op_V_MAC_F32,"V_MAC_F32",0,&operandTable[0]} ,//278
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//279
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//280
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//281
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//282
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//283
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//284
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//285
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//286
{amdgpu_cdna2_op_V_ADD_F16,"V_ADD_F16",0,&operandTable[0]} ,//287
{amdgpu_cdna2_op_V_SUB_F16,"V_SUB_F16",0,&operandTable[0]} ,//288
{amdgpu_cdna2_op_V_SUBREV_F16,"V_SUBREV_F16",0,&operandTable[0]} ,//289
{amdgpu_cdna2_op_V_MUL_F16,"V_MUL_F16",0,&operandTable[0]} ,//290
{amdgpu_cdna2_op_V_MAC_F16,"V_MAC_F16",0,&operandTable[0]} ,//291
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//292
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//293
{amdgpu_cdna2_op_V_ADD_U16,"V_ADD_U16",0,&operandTable[0]} ,//294
{amdgpu_cdna2_op_V_SUB_U16,"V_SUB_U16",0,&operandTable[0]} ,//295
{amdgpu_cdna2_op_V_SUBREV_U16,"V_SUBREV_U16",0,&operandTable[0]} ,//296
{amdgpu_cdna2_op_V_MUL_LO_U16,"V_MUL_LO_U16",0,&operandTable[0]} ,//297
{amdgpu_cdna2_op_V_LSHLREV_B16,"V_LSHLREV_B16",0,&operandTable[0]} ,//298
{amdgpu_cdna2_op_V_LSHRREV_B16,"V_LSHRREV_B16",0,&operandTable[0]} ,//299
{amdgpu_cdna2_op_V_ASHRREV_I16,"V_ASHRREV_I16",0,&operandTable[0]} ,//300
{amdgpu_cdna2_op_V_MAX_F16,"V_MAX_F16",0,&operandTable[0]} ,//301
{amdgpu_cdna2_op_V_MIN_F16,"V_MIN_F16",0,&operandTable[0]} ,//302
{amdgpu_cdna2_op_V_MAX_U16,"V_MAX_U16",0,&operandTable[0]} ,//303
{amdgpu_cdna2_op_V_MAX_I16,"V_MAX_I16",0,&operandTable[0]} ,//304
{amdgpu_cdna2_op_V_MIN_U16,"V_MIN_U16",0,&operandTable[0]} ,//305
{amdgpu_cdna2_op_V_MIN_I16,"V_MIN_I16",0,&operandTable[0]} ,//306
{amdgpu_cdna2_op_V_LDEXP_F16,"V_LDEXP_F16",0,&operandTable[0]} ,//307
{amdgpu_cdna2_op_V_ADD_U32,"V_ADD_U32",0,&operandTable[0]} ,//308
{amdgpu_cdna2_op_V_SUB_U32,"V_SUB_U32",0,&operandTable[0]} ,//309
{amdgpu_cdna2_op_V_SUBREV_U32,"V_SUBREV_U32",0,&operandTable[0]} ,//310
{amdgpu_cdna2_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16",0,&operandTable[0]} ,//311
{amdgpu_cdna2_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16",0,&operandTable[0]} ,//312
{amdgpu_cdna2_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8",0,&operandTable[0]} ,//313
{amdgpu_cdna2_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4",0,&operandTable[0]} ,//314
{amdgpu_cdna2_op_V_FMAC_F32,"V_FMAC_F32",0,&operandTable[0]} ,//315
{amdgpu_cdna2_op_V_PK_FMAC_F16,"V_PK_FMAC_F16",0,&operandTable[0]} ,//316
{amdgpu_cdna2_op_V_XNOR_B32,"V_XNOR_B32",0,&operandTable[0]} ,//317
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//318
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//319
{amdgpu_cdna2_op_V_NOP,"V_NOP",0,&operandTable[0]} ,//320
{amdgpu_cdna2_op_V_MOV_B32,"V_MOV_B32",0,&operandTable[0]} ,//321
{amdgpu_cdna2_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32",0,&operandTable[0]} ,//322
{amdgpu_cdna2_op_V_CVT_I32_F64,"V_CVT_I32_F64",0,&operandTable[0]} ,//323
{amdgpu_cdna2_op_V_CVT_F64_I32,"V_CVT_F64_I32",0,&operandTable[0]} ,//324
{amdgpu_cdna2_op_V_CVT_F32_I32,"V_CVT_F32_I32",0,&operandTable[0]} ,//325
{amdgpu_cdna2_op_V_CVT_F32_U32,"V_CVT_F32_U32",0,&operandTable[0]} ,//326
{amdgpu_cdna2_op_V_CVT_U32_F32,"V_CVT_U32_F32",0,&operandTable[0]} ,//327
{amdgpu_cdna2_op_V_CVT_I32_F32,"V_CVT_I32_F32",0,&operandTable[0]} ,//328
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//329
{amdgpu_cdna2_op_V_CVT_F16_F32,"V_CVT_F16_F32",0,&operandTable[0]} ,//330
{amdgpu_cdna2_op_V_CVT_F32_F16,"V_CVT_F32_F16",0,&operandTable[0]} ,//331
{amdgpu_cdna2_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32",0,&operandTable[0]} ,//332
{amdgpu_cdna2_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32",0,&operandTable[0]} ,//333
{amdgpu_cdna2_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4",0,&operandTable[0]} ,//334
{amdgpu_cdna2_op_V_CVT_F32_F64,"V_CVT_F32_F64",0,&operandTable[0]} ,//335
{amdgpu_cdna2_op_V_CVT_F64_F32,"V_CVT_F64_F32",0,&operandTable[0]} ,//336
{amdgpu_cdna2_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0",0,&operandTable[0]} ,//337
{amdgpu_cdna2_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1",0,&operandTable[0]} ,//338
{amdgpu_cdna2_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2",0,&operandTable[0]} ,//339
{amdgpu_cdna2_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3",0,&operandTable[0]} ,//340
{amdgpu_cdna2_op_V_CVT_U32_F64,"V_CVT_U32_F64",0,&operandTable[0]} ,//341
{amdgpu_cdna2_op_V_CVT_F64_U32,"V_CVT_F64_U32",0,&operandTable[0]} ,//342
{amdgpu_cdna2_op_V_TRUNC_F64,"V_TRUNC_F64",0,&operandTable[0]} ,//343
{amdgpu_cdna2_op_V_CEIL_F64,"V_CEIL_F64",0,&operandTable[0]} ,//344
{amdgpu_cdna2_op_V_RNDNE_F64,"V_RNDNE_F64",0,&operandTable[0]} ,//345
{amdgpu_cdna2_op_V_FLOOR_F64,"V_FLOOR_F64",0,&operandTable[0]} ,//346
{amdgpu_cdna2_op_V_FRACT_F32,"V_FRACT_F32",0,&operandTable[0]} ,//347
{amdgpu_cdna2_op_V_TRUNC_F32,"V_TRUNC_F32",0,&operandTable[0]} ,//348
{amdgpu_cdna2_op_V_CEIL_F32,"V_CEIL_F32",0,&operandTable[0]} ,//349
{amdgpu_cdna2_op_V_RNDNE_F32,"V_RNDNE_F32",0,&operandTable[0]} ,//350
{amdgpu_cdna2_op_V_FLOOR_F32,"V_FLOOR_F32",0,&operandTable[0]} ,//351
{amdgpu_cdna2_op_V_EXP_F32,"V_EXP_F32",0,&operandTable[0]} ,//352
{amdgpu_cdna2_op_V_LOG_F32,"V_LOG_F32",0,&operandTable[0]} ,//353
{amdgpu_cdna2_op_V_RCP_F32,"V_RCP_F32",0,&operandTable[0]} ,//354
{amdgpu_cdna2_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32",0,&operandTable[0]} ,//355
{amdgpu_cdna2_op_V_RSQ_F32,"V_RSQ_F32",0,&operandTable[0]} ,//356
{amdgpu_cdna2_op_V_RCP_F64,"V_RCP_F64",0,&operandTable[0]} ,//357
{amdgpu_cdna2_op_V_RSQ_F64,"V_RSQ_F64",0,&operandTable[0]} ,//358
{amdgpu_cdna2_op_V_SQRT_F32,"V_SQRT_F32",0,&operandTable[0]} ,//359
{amdgpu_cdna2_op_V_SQRT_F64,"V_SQRT_F64",0,&operandTable[0]} ,//360
{amdgpu_cdna2_op_V_SIN_F32,"V_SIN_F32",0,&operandTable[0]} ,//361
{amdgpu_cdna2_op_V_COS_F32,"V_COS_F32",0,&operandTable[0]} ,//362
{amdgpu_cdna2_op_V_NOT_B32,"V_NOT_B32",0,&operandTable[0]} ,//363
{amdgpu_cdna2_op_V_BFREV_B32,"V_BFREV_B32",0,&operandTable[0]} ,//364
{amdgpu_cdna2_op_V_FFBH_U32,"V_FFBH_U32",0,&operandTable[0]} ,//365
{amdgpu_cdna2_op_V_FFBL_B32,"V_FFBL_B32",0,&operandTable[0]} ,//366
{amdgpu_cdna2_op_V_FFBH_I32,"V_FFBH_I32",0,&operandTable[0]} ,//367
{amdgpu_cdna2_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64",0,&operandTable[0]} ,//368
{amdgpu_cdna2_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64",0,&operandTable[0]} ,//369
{amdgpu_cdna2_op_V_FRACT_F64,"V_FRACT_F64",0,&operandTable[0]} ,//370
{amdgpu_cdna2_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32",0,&operandTable[0]} ,//371
{amdgpu_cdna2_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32",0,&operandTable[0]} ,//372
{amdgpu_cdna2_op_V_CLREXCP,"V_CLREXCP",0,&operandTable[0]} ,//373
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//374
{amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32",0,&operandTable[0]} ,//375
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//376
{amdgpu_cdna2_op_V_CVT_F16_U16,"V_CVT_F16_U16",0,&operandTable[0]} ,//377
{amdgpu_cdna2_op_V_CVT_F16_I16,"V_CVT_F16_I16",0,&operandTable[0]} ,//378
{amdgpu_cdna2_op_V_CVT_U16_F16,"V_CVT_U16_F16",0,&operandTable[0]} ,//379
{amdgpu_cdna2_op_V_CVT_I16_F16,"V_CVT_I16_F16",0,&operandTable[0]} ,//380
{amdgpu_cdna2_op_V_RCP_F16,"V_RCP_F16",0,&operandTable[0]} ,//381
{amdgpu_cdna2_op_V_SQRT_F16,"V_SQRT_F16",0,&operandTable[0]} ,//382
{amdgpu_cdna2_op_V_RSQ_F16,"V_RSQ_F16",0,&operandTable[0]} ,//383
{amdgpu_cdna2_op_V_LOG_F16,"V_LOG_F16",0,&operandTable[0]} ,//384
{amdgpu_cdna2_op_V_EXP_F16,"V_EXP_F16",0,&operandTable[0]} ,//385
{amdgpu_cdna2_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16",0,&operandTable[0]} ,//386
{amdgpu_cdna2_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16",0,&operandTable[0]} ,//387
{amdgpu_cdna2_op_V_FLOOR_F16,"V_FLOOR_F16",0,&operandTable[0]} ,//388
{amdgpu_cdna2_op_V_CEIL_F16,"V_CEIL_F16",0,&operandTable[0]} ,//389
{amdgpu_cdna2_op_V_TRUNC_F16,"V_TRUNC_F16",0,&operandTable[0]} ,//390
{amdgpu_cdna2_op_V_RNDNE_F16,"V_RNDNE_F16",0,&operandTable[0]} ,//391
{amdgpu_cdna2_op_V_FRACT_F16,"V_FRACT_F16",0,&operandTable[0]} ,//392
{amdgpu_cdna2_op_V_SIN_F16,"V_SIN_F16",0,&operandTable[0]} ,//393
{amdgpu_cdna2_op_V_COS_F16,"V_COS_F16",0,&operandTable[0]} ,//394
{amdgpu_cdna2_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32",0,&operandTable[0]} ,//395
{amdgpu_cdna2_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32",0,&operandTable[0]} ,//396
{amdgpu_cdna2_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16",0,&operandTable[0]} ,//397
{amdgpu_cdna2_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16",0,&operandTable[0]} ,//398
{amdgpu_cdna2_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16",0,&operandTable[0]} ,//399
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//400
{amdgpu_cdna2_op_V_SWAP_B32,"V_SWAP_B32",0,&operandTable[0]} ,//401
{amdgpu_cdna2_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32",0,&operandTable[0]} ,//402
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//403
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//404
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//405
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//406
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//407
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//408
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//409
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//410
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//411
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//412
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//413
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//414
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//415
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//416
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//417
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//418
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//419
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//420
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//421
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//422
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//423
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//424
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//425
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//426
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//427
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//428
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//429
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//430
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//431
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//432
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//433
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//434
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//435
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//436
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//437
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//438
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//439
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//440
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//441
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//442
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//443
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//444
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//445
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//446
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//447
{amdgpu_cdna2_op_V_MAD_LEGACY_F32,"V_MAD_LEGACY_F32",0,&operandTable[0]} ,//448
{amdgpu_cdna2_op_V_MAD_F32,"V_MAD_F32",0,&operandTable[0]} ,//449
{amdgpu_cdna2_op_V_MAD_I32_I24,"V_MAD_I32_I24",0,&operandTable[0]} ,//450
{amdgpu_cdna2_op_V_MAD_U32_U24,"V_MAD_U32_U24",0,&operandTable[0]} ,//451
{amdgpu_cdna2_op_V_CUBEID_F32,"V_CUBEID_F32",0,&operandTable[0]} ,//452
{amdgpu_cdna2_op_V_CUBESC_F32,"V_CUBESC_F32",0,&operandTable[0]} ,//453
{amdgpu_cdna2_op_V_CUBETC_F32,"V_CUBETC_F32",0,&operandTable[0]} ,//454
{amdgpu_cdna2_op_V_CUBEMA_F32,"V_CUBEMA_F32",0,&operandTable[0]} ,//455
{amdgpu_cdna2_op_V_BFE_U32,"V_BFE_U32",0,&operandTable[0]} ,//456
{amdgpu_cdna2_op_V_BFE_I32,"V_BFE_I32",0,&operandTable[0]} ,//457
{amdgpu_cdna2_op_V_BFI_B32,"V_BFI_B32",0,&operandTable[0]} ,//458
{amdgpu_cdna2_op_V_FMA_F32,"V_FMA_F32",0,&operandTable[0]} ,//459
{amdgpu_cdna2_op_V_FMA_F64,"V_FMA_F64",0,&operandTable[0]} ,//460
{amdgpu_cdna2_op_V_LERP_U8,"V_LERP_U8",0,&operandTable[0]} ,//461
{amdgpu_cdna2_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32",0,&operandTable[0]} ,//462
{amdgpu_cdna2_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32",0,&operandTable[0]} ,//463
{amdgpu_cdna2_op_V_MIN3_F32,"V_MIN3_F32",0,&operandTable[0]} ,//464
{amdgpu_cdna2_op_V_MIN3_I32,"V_MIN3_I32",0,&operandTable[0]} ,//465
{amdgpu_cdna2_op_V_MIN3_U32,"V_MIN3_U32",0,&operandTable[0]} ,//466
{amdgpu_cdna2_op_V_MAX3_F32,"V_MAX3_F32",0,&operandTable[0]} ,//467
{amdgpu_cdna2_op_V_MAX3_I32,"V_MAX3_I32",0,&operandTable[0]} ,//468
{amdgpu_cdna2_op_V_MAX3_U32,"V_MAX3_U32",0,&operandTable[0]} ,//469
{amdgpu_cdna2_op_V_MED3_F32,"V_MED3_F32",0,&operandTable[0]} ,//470
{amdgpu_cdna2_op_V_MED3_I32,"V_MED3_I32",0,&operandTable[0]} ,//471
{amdgpu_cdna2_op_V_MED3_U32,"V_MED3_U32",0,&operandTable[0]} ,//472
{amdgpu_cdna2_op_V_SAD_U8,"V_SAD_U8",0,&operandTable[0]} ,//473
{amdgpu_cdna2_op_V_SAD_HI_U8,"V_SAD_HI_U8",0,&operandTable[0]} ,//474
{amdgpu_cdna2_op_V_SAD_U16,"V_SAD_U16",0,&operandTable[0]} ,//475
{amdgpu_cdna2_op_V_SAD_U32,"V_SAD_U32",0,&operandTable[0]} ,//476
{amdgpu_cdna2_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32",0,&operandTable[0]} ,//477
{amdgpu_cdna2_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32",0,&operandTable[0]} ,//478
{amdgpu_cdna2_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64",0,&operandTable[0]} ,//479
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//480
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//481
{amdgpu_cdna2_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32",0,&operandTable[0]} ,//482
{amdgpu_cdna2_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64",0,&operandTable[0]} ,//483
{amdgpu_cdna2_op_V_MSAD_U8,"V_MSAD_U8",0,&operandTable[0]} ,//484
{amdgpu_cdna2_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8",0,&operandTable[0]} ,//485
{amdgpu_cdna2_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8",0,&operandTable[0]} ,//486
{amdgpu_cdna2_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8",0,&operandTable[0]} ,//487
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//488
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//489
{amdgpu_cdna2_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16",0,&operandTable[0]} ,//490
{amdgpu_cdna2_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16",0,&operandTable[0]} ,//491
{amdgpu_cdna2_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16",0,&operandTable[0]} ,//492
{amdgpu_cdna2_op_V_PERM_B32,"V_PERM_B32",0,&operandTable[0]} ,//493
{amdgpu_cdna2_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16",0,&operandTable[0]} ,//494
{amdgpu_cdna2_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16",0,&operandTable[0]} ,//495
{amdgpu_cdna2_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32",0,&operandTable[0]} ,//496
{amdgpu_cdna2_op_V_MAD_U32_U16,"V_MAD_U32_U16",0,&operandTable[0]} ,//497
{amdgpu_cdna2_op_V_MAD_I32_I16,"V_MAD_I32_I16",0,&operandTable[0]} ,//498
{amdgpu_cdna2_op_V_XAD_U32,"V_XAD_U32",0,&operandTable[0]} ,//499
{amdgpu_cdna2_op_V_MIN3_F16,"V_MIN3_F16",0,&operandTable[0]} ,//500
{amdgpu_cdna2_op_V_MIN3_I16,"V_MIN3_I16",0,&operandTable[0]} ,//501
{amdgpu_cdna2_op_V_MIN3_U16,"V_MIN3_U16",0,&operandTable[0]} ,//502
{amdgpu_cdna2_op_V_MAX3_F16,"V_MAX3_F16",0,&operandTable[0]} ,//503
{amdgpu_cdna2_op_V_MAX3_I16,"V_MAX3_I16",0,&operandTable[0]} ,//504
{amdgpu_cdna2_op_V_MAX3_U16,"V_MAX3_U16",0,&operandTable[0]} ,//505
{amdgpu_cdna2_op_V_MED3_F16,"V_MED3_F16",0,&operandTable[0]} ,//506
{amdgpu_cdna2_op_V_MED3_I16,"V_MED3_I16",0,&operandTable[0]} ,//507
{amdgpu_cdna2_op_V_MED3_U16,"V_MED3_U16",0,&operandTable[0]} ,//508
{amdgpu_cdna2_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32",0,&operandTable[0]} ,//509
{amdgpu_cdna2_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32",0,&operandTable[0]} ,//510
{amdgpu_cdna2_op_V_ADD3_U32,"V_ADD3_U32",0,&operandTable[0]} ,//511
{amdgpu_cdna2_op_V_LSHL_OR_B32,"V_LSHL_OR_B32",0,&operandTable[0]} ,//512
{amdgpu_cdna2_op_V_AND_OR_B32,"V_AND_OR_B32",0,&operandTable[0]} ,//513
{amdgpu_cdna2_op_V_OR3_B32,"V_OR3_B32",0,&operandTable[0]} ,//514
{amdgpu_cdna2_op_V_MAD_F16,"V_MAD_F16",0,&operandTable[0]} ,//515
{amdgpu_cdna2_op_V_MAD_U16,"V_MAD_U16",0,&operandTable[0]} ,//516
{amdgpu_cdna2_op_V_MAD_I16,"V_MAD_I16",0,&operandTable[0]} ,//517
{amdgpu_cdna2_op_V_FMA_F16,"V_FMA_F16",0,&operandTable[0]} ,//518
{amdgpu_cdna2_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16",0,&operandTable[0]} ,//519
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//520
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//521
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//522
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//523
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//524
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//525
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//526
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//527
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//528
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//529
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//530
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//531
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//532
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//533
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//534
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//535
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//536
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//537
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//538
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//539
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//540
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//541
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//542
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//543
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//544
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//545
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//546
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//547
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//548
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//549
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//550
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//551
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//552
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//553
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//554
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//555
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//556
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//557
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//558
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//559
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//560
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//561
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//562
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//563
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//564
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//565
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//566
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//567
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//568
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//569
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//570
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//571
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//572
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//573
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//574
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//575
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//576
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//577
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//578
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//579
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//580
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//581
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//582
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//583
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//584
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//585
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//586
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//587
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//588
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//589
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//590
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//591
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//592
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//593
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//594
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//595
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//596
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//597
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//598
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//599
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//600
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//601
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//602
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//603
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//604
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//605
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//606
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//607
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//608
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//609
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//610
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//611
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//612
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//613
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//614
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//615
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//616
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//617
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//618
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//619
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//620
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//621
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//622
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//623
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//624
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//625
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//626
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//627
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//628
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//629
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//630
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//631
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//632
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//633
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//634
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//635
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//636
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//637
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//638
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//639
{amdgpu_cdna2_op_V_ADD_F64,"V_ADD_F64",0,&operandTable[0]} ,//640
{amdgpu_cdna2_op_V_MUL_F64,"V_MUL_F64",0,&operandTable[0]} ,//641
{amdgpu_cdna2_op_V_MIN_F64,"V_MIN_F64",0,&operandTable[0]} ,//642
{amdgpu_cdna2_op_V_MAX_F64,"V_MAX_F64",0,&operandTable[0]} ,//643
{amdgpu_cdna2_op_V_LDEXP_F64,"V_LDEXP_F64",0,&operandTable[0]} ,//644
{amdgpu_cdna2_op_V_MUL_LO_U32,"V_MUL_LO_U32",0,&operandTable[0]} ,//645
{amdgpu_cdna2_op_V_MUL_HI_U32,"V_MUL_HI_U32",0,&operandTable[0]} ,//646
{amdgpu_cdna2_op_V_MUL_HI_I32,"V_MUL_HI_I32",0,&operandTable[0]} ,//647
{amdgpu_cdna2_op_V_LDEXP_F32,"V_LDEXP_F32",0,&operandTable[0]} ,//648
{amdgpu_cdna2_op_V_READLANE_B32,"V_READLANE_B32",0,&operandTable[0]} ,//649
{amdgpu_cdna2_op_V_WRITELANE_B32,"V_WRITELANE_B32",0,&operandTable[0]} ,//650
{amdgpu_cdna2_op_V_BCNT_U32_B32,"V_BCNT_U32_B32",0,&operandTable[0]} ,//651
{amdgpu_cdna2_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32",0,&operandTable[0]} ,//652
{amdgpu_cdna2_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32",0,&operandTable[0]} ,//653
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//654
{amdgpu_cdna2_op_V_LSHLREV_B64,"V_LSHLREV_B64",0,&operandTable[0]} ,//655
{amdgpu_cdna2_op_V_LSHRREV_B64,"V_LSHRREV_B64",0,&operandTable[0]} ,//656
{amdgpu_cdna2_op_V_ASHRREV_I64,"V_ASHRREV_I64",0,&operandTable[0]} ,//657
{amdgpu_cdna2_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64",0,&operandTable[0]} ,//658
{amdgpu_cdna2_op_V_BFM_B32,"V_BFM_B32",0,&operandTable[0]} ,//659
{amdgpu_cdna2_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32",0,&operandTable[0]} ,//660
{amdgpu_cdna2_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32",0,&operandTable[0]} ,//661
{amdgpu_cdna2_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32",0,&operandTable[0]} ,//662
{amdgpu_cdna2_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32",0,&operandTable[0]} ,//663
{amdgpu_cdna2_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32",0,&operandTable[0]} ,//664
{amdgpu_cdna2_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16",0,&operandTable[0]} ,//665
{amdgpu_cdna2_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16",0,&operandTable[0]} ,//666
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//667
{amdgpu_cdna2_op_V_ADD_I32,"V_ADD_I32",0,&operandTable[0]} ,//668
{amdgpu_cdna2_op_V_SUB_I32,"V_SUB_I32",0,&operandTable[0]} ,//669
{amdgpu_cdna2_op_V_ADD_I16,"V_ADD_I16",0,&operandTable[0]} ,//670
{amdgpu_cdna2_op_V_SUB_I16,"V_SUB_I16",0,&operandTable[0]} ,//671
{amdgpu_cdna2_op_V_PACK_B32_F16,"V_PACK_B32_F16",0,&operandTable[0]} ,//672
{amdgpu_cdna2_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32",0,&operandTable[0]} ,//673
}; // end ENC_VOP3_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table = {
{amdgpu_cdna2_op_V_CNDMASK_B32,"V_CNDMASK_B32",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_V_ADD_F32,"V_ADD_F32",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_V_SUB_F32,"V_SUB_F32",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_V_SUBREV_F32,"V_SUBREV_F32",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_V_FMAC_F64,"V_FMAC_F64",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_V_MUL_F32,"V_MUL_F32",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_V_MUL_I32_I24,"V_MUL_I32_I24",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_V_MUL_U32_U24,"V_MUL_U32_U24",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_V_MIN_F32,"V_MIN_F32",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_V_MAX_F32,"V_MAX_F32",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_V_MIN_I32,"V_MIN_I32",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_V_MAX_I32,"V_MAX_I32",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_V_MIN_U32,"V_MIN_U32",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_V_MAX_U32,"V_MAX_U32",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_V_LSHRREV_B32,"V_LSHRREV_B32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_V_ASHRREV_I32,"V_ASHRREV_I32",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_V_LSHLREV_B32,"V_LSHLREV_B32",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_V_AND_B32,"V_AND_B32",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_V_OR_B32,"V_OR_B32",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_V_XOR_B32,"V_XOR_B32",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_V_MAC_F32,"V_MAC_F32",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_V_ADD_CO_U32,"V_ADD_CO_U32",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_V_SUB_CO_U32,"V_SUB_CO_U32",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_V_ADDC_CO_U32,"V_ADDC_CO_U32",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_V_SUBB_CO_U32,"V_SUBB_CO_U32",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_V_ADD_F16,"V_ADD_F16",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_V_SUB_F16,"V_SUB_F16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_V_SUBREV_F16,"V_SUBREV_F16",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_V_MUL_F16,"V_MUL_F16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_V_MAC_F16,"V_MAC_F16",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_V_ADD_U16,"V_ADD_U16",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_V_SUB_U16,"V_SUB_U16",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_V_SUBREV_U16,"V_SUBREV_U16",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_V_MUL_LO_U16,"V_MUL_LO_U16",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_V_LSHLREV_B16,"V_LSHLREV_B16",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_V_LSHRREV_B16,"V_LSHRREV_B16",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_V_ASHRREV_I16,"V_ASHRREV_I16",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_V_MAX_F16,"V_MAX_F16",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_V_MIN_F16,"V_MIN_F16",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_V_MAX_U16,"V_MAX_U16",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_V_MAX_I16,"V_MAX_I16",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_V_MIN_U16,"V_MIN_U16",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_V_MIN_I16,"V_MIN_I16",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_V_LDEXP_F16,"V_LDEXP_F16",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_V_ADD_U32,"V_ADD_U32",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_V_SUB_U32,"V_SUB_U32",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_V_SUBREV_U32,"V_SUBREV_U32",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_V_FMAC_F32,"V_FMAC_F32",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_V_PK_FMAC_F16,"V_PK_FMAC_F16",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_V_XNOR_B32,"V_XNOR_B32",0,&operandTable[0]} ,//61
}; // end ENC_VOP2_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_V_MADMK_F32,"V_MADMK_F32",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_V_MADAK_F32,"V_MADAK_F32",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_V_MADMK_F16,"V_MADMK_F16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_V_MADAK_F16,"V_MADAK_F16",0,&operandTable[0]} ,//37
}; // end ENC_VOP2_LITERAL_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//108
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//109
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//110
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//111
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//112
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//113
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//114
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//115
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//118
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//119
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//120
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//126
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//160
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//161
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//162
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//163
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//164
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//165
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//166
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//167
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//168
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//169
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//170
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//171
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//172
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//173
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//174
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//175
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//176
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//177
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//178
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//179
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//180
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//181
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//182
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//183
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//184
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//185
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//186
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//187
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//188
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//189
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//190
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//191
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//192
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//193
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//194
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//195
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//196
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//197
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//198
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//199
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//200
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//201
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//202
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//203
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//204
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//205
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//206
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//207
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//208
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//209
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//210
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//211
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//212
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//213
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//214
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//215
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//216
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//217
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//218
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//219
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//220
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//221
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//222
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//223
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//224
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//225
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//226
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//227
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//228
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//229
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//230
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//231
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//232
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//233
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//234
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//235
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//236
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//237
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//238
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//239
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//240
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//241
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//242
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//243
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//244
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//245
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//246
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//247
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//248
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//249
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//250
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//251
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//252
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//253
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//254
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//255
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//256
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//257
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//258
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//259
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//260
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//261
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//262
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//263
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//264
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//265
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//266
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//267
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//268
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//269
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//270
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//271
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//272
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//273
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//274
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//275
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//276
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//277
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//278
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//279
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//280
{amdgpu_cdna2_op_V_ADD_CO_U32,"V_ADD_CO_U32",0,&operandTable[0]} ,//281
{amdgpu_cdna2_op_V_SUB_CO_U32,"V_SUB_CO_U32",0,&operandTable[0]} ,//282
{amdgpu_cdna2_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32",0,&operandTable[0]} ,//283
{amdgpu_cdna2_op_V_ADDC_CO_U32,"V_ADDC_CO_U32",0,&operandTable[0]} ,//284
{amdgpu_cdna2_op_V_SUBB_CO_U32,"V_SUBB_CO_U32",0,&operandTable[0]} ,//285
{amdgpu_cdna2_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32",0,&operandTable[0]} ,//286
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//287
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//288
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//289
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//290
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//291
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//292
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//293
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//294
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//295
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//296
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//297
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//298
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//299
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//300
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//301
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//302
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//303
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//304
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//305
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//306
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//307
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//308
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//309
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//310
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//311
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//312
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//313
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//314
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//315
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//316
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//317
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//318
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//319
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//320
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//321
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//322
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//323
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//324
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//325
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//326
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//327
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//328
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//329
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//330
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//331
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//332
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//333
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//334
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//335
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//336
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//337
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//338
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//339
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//340
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//341
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//342
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//343
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//344
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//345
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//346
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//347
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//348
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//349
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//350
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//351
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//352
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//353
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//354
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//355
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//356
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//357
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//358
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//359
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//360
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//361
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//362
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//363
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//364
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//365
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//366
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//367
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//368
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//369
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//370
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//371
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//372
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//373
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//374
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//375
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//376
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//377
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//378
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//379
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//380
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//381
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//382
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//383
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//384
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//385
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//386
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//387
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//388
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//389
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//390
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//391
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//392
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//393
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//394
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//395
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//396
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//397
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//398
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//399
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//400
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//401
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//402
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//403
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//404
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//405
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//406
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//407
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//408
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//409
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//410
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//411
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//412
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//413
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//414
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//415
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//416
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//417
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//418
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//419
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//420
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//421
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//422
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//423
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//424
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//425
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//426
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//427
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//428
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//429
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//430
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//431
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//432
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//433
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//434
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//435
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//436
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//437
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//438
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//439
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//440
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//441
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//442
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//443
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//444
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//445
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//446
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//447
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//448
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//449
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//450
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//451
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//452
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//453
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//454
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//455
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//456
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//457
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//458
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//459
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//460
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//461
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//462
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//463
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//464
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//465
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//466
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//467
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//468
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//469
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//470
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//471
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//472
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//473
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//474
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//475
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//476
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//477
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//478
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//479
{amdgpu_cdna2_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32",0,&operandTable[0]} ,//480
{amdgpu_cdna2_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64",0,&operandTable[0]} ,//481
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//482
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//483
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//484
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//485
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//486
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//487
{amdgpu_cdna2_op_V_MAD_U64_U32,"V_MAD_U64_U32",0,&operandTable[0]} ,//488
{amdgpu_cdna2_op_V_MAD_I64_I32,"V_MAD_I64_I32",0,&operandTable[0]} ,//489
}; // end ENC_VOP3B_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table = {
{amdgpu_cdna2_op_V_PK_MAD_I16,"V_PK_MAD_I16",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_V_PK_ADD_I16,"V_PK_ADD_I16",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_V_PK_SUB_I16,"V_PK_SUB_I16",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_V_PK_MAX_I16,"V_PK_MAX_I16",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_V_PK_MIN_I16,"V_PK_MIN_I16",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_V_PK_MAD_U16,"V_PK_MAD_U16",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_V_PK_ADD_U16,"V_PK_ADD_U16",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_V_PK_SUB_U16,"V_PK_SUB_U16",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_V_PK_MAX_U16,"V_PK_MAX_U16",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_V_PK_MIN_U16,"V_PK_MIN_U16",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_V_PK_FMA_F16,"V_PK_FMA_F16",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_V_PK_ADD_F16,"V_PK_ADD_F16",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_V_PK_MUL_F16,"V_PK_MUL_F16",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_V_PK_MIN_F16,"V_PK_MIN_F16",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_V_PK_MAX_F16,"V_PK_MAX_F16",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_V_MAD_MIX_F32,"V_MAD_MIX_F32",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_V_DOT2_F32_F16,"V_DOT2_F32_F16",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_V_DOT2_I32_I16,"V_DOT2_I32_I16",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_V_DOT2_U32_U16,"V_DOT2_U32_U16",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_V_DOT4_I32_I8,"V_DOT4_I32_I8",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_V_DOT4_U32_U8,"V_DOT4_U32_U8",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_V_DOT8_I32_I4,"V_DOT8_I32_I4",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_V_DOT8_U32_U4,"V_DOT8_U32_U4",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_V_PK_FMA_F32,"V_PK_FMA_F32",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_V_PK_MUL_F32,"V_PK_MUL_F32",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_V_PK_ADD_F32,"V_PK_ADD_F32",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_V_PK_MOV_B32,"V_PK_MOV_B32",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_V_ACCVGPR_READ,"V_ACCVGPR_READ",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE",0,&operandTable[0]} ,//89
}; // end ENC_VOP3P_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_V_MFMA_F32_32X32X1F32,"V_MFMA_F32_32X32X1F32",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_V_MFMA_F32_16X16X1F32,"V_MFMA_F32_16X16X1F32",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_V_MFMA_F32_4X4X1F32,"V_MFMA_F32_4X4X1F32",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_V_MFMA_F32_32X32X2F32,"V_MFMA_F32_32X32X2F32",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_V_MFMA_F32_16X16X4F32,"V_MFMA_F32_16X16X4F32",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_V_MFMA_F32_32X32X4F16,"V_MFMA_F32_32X32X4F16",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_V_MFMA_F32_16X16X4F16,"V_MFMA_F32_16X16X4F16",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_V_MFMA_F32_4X4X4F16,"V_MFMA_F32_4X4X4F16",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_V_MFMA_F32_32X32X8F16,"V_MFMA_F32_32X32X8F16",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_V_MFMA_F32_16X16X16F16,"V_MFMA_F32_16X16X16F16",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_V_MFMA_I32_32X32X4I8,"V_MFMA_I32_32X32X4I8",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_V_MFMA_I32_16X16X4I8,"V_MFMA_I32_16X16X4I8",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_V_MFMA_I32_4X4X4I8,"V_MFMA_I32_4X4X4I8",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_V_MFMA_I32_32X32X8I8,"V_MFMA_I32_32X32X8I8",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_V_MFMA_I32_16X16X16I8,"V_MFMA_I32_16X16X16I8",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16_1K,"V_MFMA_F32_32X32X4BF16_1K",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_V_MFMA_F32_16X16X4BF16_1K,"V_MFMA_F32_16X16X4BF16_1K",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_V_MFMA_F32_4X4X4BF16_1K,"V_MFMA_F32_4X4X4BF16_1K",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_V_MFMA_F32_32X32X8BF16_1K,"V_MFMA_F32_32X32X8BF16_1K",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_V_MFMA_F32_16X16X16BF16_1K,"V_MFMA_F32_16X16X16BF16_1K",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_V_MFMA_F32_32X32X2BF16,"V_MFMA_F32_32X32X2BF16",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_V_MFMA_F32_16X16X2BF16,"V_MFMA_F32_16X16X2BF16",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_V_MFMA_F32_4X4X2BF16,"V_MFMA_F32_4X4X2BF16",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16,"V_MFMA_F32_32X32X4BF16",0,&operandTable[0]} ,//108
{amdgpu_cdna2_op_V_MFMA_F32_16X16X8BF16,"V_MFMA_F32_16X16X8BF16",0,&operandTable[0]} ,//109
{amdgpu_cdna2_op_V_MFMA_F64_16X16X4F64,"V_MFMA_F64_16X16X4F64",0,&operandTable[0]} ,//110
{amdgpu_cdna2_op_V_MFMA_F64_4X4X4F64,"V_MFMA_F64_4X4X4F64",0,&operandTable[0]} ,//111
}; // end ENC_VOP3P_MFMA_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15
{amdgpu_cdna2_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32",0,&operandTable[0]} ,//16
{amdgpu_cdna2_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32",0,&operandTable[0]} ,//17
{amdgpu_cdna2_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64",0,&operandTable[0]} ,//18
{amdgpu_cdna2_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64",0,&operandTable[0]} ,//19
{amdgpu_cdna2_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16",0,&operandTable[0]} ,//20
{amdgpu_cdna2_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16",0,&operandTable[0]} ,//21
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31
{amdgpu_cdna2_op_V_CMP_F_F16,"V_CMP_F_F16",0,&operandTable[0]} ,//32
{amdgpu_cdna2_op_V_CMP_LT_F16,"V_CMP_LT_F16",0,&operandTable[0]} ,//33
{amdgpu_cdna2_op_V_CMP_EQ_F16,"V_CMP_EQ_F16",0,&operandTable[0]} ,//34
{amdgpu_cdna2_op_V_CMP_LE_F16,"V_CMP_LE_F16",0,&operandTable[0]} ,//35
{amdgpu_cdna2_op_V_CMP_GT_F16,"V_CMP_GT_F16",0,&operandTable[0]} ,//36
{amdgpu_cdna2_op_V_CMP_LG_F16,"V_CMP_LG_F16",0,&operandTable[0]} ,//37
{amdgpu_cdna2_op_V_CMP_GE_F16,"V_CMP_GE_F16",0,&operandTable[0]} ,//38
{amdgpu_cdna2_op_V_CMP_O_F16,"V_CMP_O_F16",0,&operandTable[0]} ,//39
{amdgpu_cdna2_op_V_CMP_U_F16,"V_CMP_U_F16",0,&operandTable[0]} ,//40
{amdgpu_cdna2_op_V_CMP_NGE_F16,"V_CMP_NGE_F16",0,&operandTable[0]} ,//41
{amdgpu_cdna2_op_V_CMP_NLG_F16,"V_CMP_NLG_F16",0,&operandTable[0]} ,//42
{amdgpu_cdna2_op_V_CMP_NGT_F16,"V_CMP_NGT_F16",0,&operandTable[0]} ,//43
{amdgpu_cdna2_op_V_CMP_NLE_F16,"V_CMP_NLE_F16",0,&operandTable[0]} ,//44
{amdgpu_cdna2_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16",0,&operandTable[0]} ,//45
{amdgpu_cdna2_op_V_CMP_NLT_F16,"V_CMP_NLT_F16",0,&operandTable[0]} ,//46
{amdgpu_cdna2_op_V_CMP_TRU_F16,"V_CMP_TRU_F16",0,&operandTable[0]} ,//47
{amdgpu_cdna2_op_V_CMPX_F_F16,"V_CMPX_F_F16",0,&operandTable[0]} ,//48
{amdgpu_cdna2_op_V_CMPX_LT_F16,"V_CMPX_LT_F16",0,&operandTable[0]} ,//49
{amdgpu_cdna2_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16",0,&operandTable[0]} ,//50
{amdgpu_cdna2_op_V_CMPX_LE_F16,"V_CMPX_LE_F16",0,&operandTable[0]} ,//51
{amdgpu_cdna2_op_V_CMPX_GT_F16,"V_CMPX_GT_F16",0,&operandTable[0]} ,//52
{amdgpu_cdna2_op_V_CMPX_LG_F16,"V_CMPX_LG_F16",0,&operandTable[0]} ,//53
{amdgpu_cdna2_op_V_CMPX_GE_F16,"V_CMPX_GE_F16",0,&operandTable[0]} ,//54
{amdgpu_cdna2_op_V_CMPX_O_F16,"V_CMPX_O_F16",0,&operandTable[0]} ,//55
{amdgpu_cdna2_op_V_CMPX_U_F16,"V_CMPX_U_F16",0,&operandTable[0]} ,//56
{amdgpu_cdna2_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16",0,&operandTable[0]} ,//57
{amdgpu_cdna2_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16",0,&operandTable[0]} ,//58
{amdgpu_cdna2_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16",0,&operandTable[0]} ,//59
{amdgpu_cdna2_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16",0,&operandTable[0]} ,//60
{amdgpu_cdna2_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16",0,&operandTable[0]} ,//61
{amdgpu_cdna2_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16",0,&operandTable[0]} ,//62
{amdgpu_cdna2_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16",0,&operandTable[0]} ,//63
{amdgpu_cdna2_op_V_CMP_F_F32,"V_CMP_F_F32",0,&operandTable[0]} ,//64
{amdgpu_cdna2_op_V_CMP_LT_F32,"V_CMP_LT_F32",0,&operandTable[0]} ,//65
{amdgpu_cdna2_op_V_CMP_EQ_F32,"V_CMP_EQ_F32",0,&operandTable[0]} ,//66
{amdgpu_cdna2_op_V_CMP_LE_F32,"V_CMP_LE_F32",0,&operandTable[0]} ,//67
{amdgpu_cdna2_op_V_CMP_GT_F32,"V_CMP_GT_F32",0,&operandTable[0]} ,//68
{amdgpu_cdna2_op_V_CMP_LG_F32,"V_CMP_LG_F32",0,&operandTable[0]} ,//69
{amdgpu_cdna2_op_V_CMP_GE_F32,"V_CMP_GE_F32",0,&operandTable[0]} ,//70
{amdgpu_cdna2_op_V_CMP_O_F32,"V_CMP_O_F32",0,&operandTable[0]} ,//71
{amdgpu_cdna2_op_V_CMP_U_F32,"V_CMP_U_F32",0,&operandTable[0]} ,//72
{amdgpu_cdna2_op_V_CMP_NGE_F32,"V_CMP_NGE_F32",0,&operandTable[0]} ,//73
{amdgpu_cdna2_op_V_CMP_NLG_F32,"V_CMP_NLG_F32",0,&operandTable[0]} ,//74
{amdgpu_cdna2_op_V_CMP_NGT_F32,"V_CMP_NGT_F32",0,&operandTable[0]} ,//75
{amdgpu_cdna2_op_V_CMP_NLE_F32,"V_CMP_NLE_F32",0,&operandTable[0]} ,//76
{amdgpu_cdna2_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32",0,&operandTable[0]} ,//77
{amdgpu_cdna2_op_V_CMP_NLT_F32,"V_CMP_NLT_F32",0,&operandTable[0]} ,//78
{amdgpu_cdna2_op_V_CMP_TRU_F32,"V_CMP_TRU_F32",0,&operandTable[0]} ,//79
{amdgpu_cdna2_op_V_CMPX_F_F32,"V_CMPX_F_F32",0,&operandTable[0]} ,//80
{amdgpu_cdna2_op_V_CMPX_LT_F32,"V_CMPX_LT_F32",0,&operandTable[0]} ,//81
{amdgpu_cdna2_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32",0,&operandTable[0]} ,//82
{amdgpu_cdna2_op_V_CMPX_LE_F32,"V_CMPX_LE_F32",0,&operandTable[0]} ,//83
{amdgpu_cdna2_op_V_CMPX_GT_F32,"V_CMPX_GT_F32",0,&operandTable[0]} ,//84
{amdgpu_cdna2_op_V_CMPX_LG_F32,"V_CMPX_LG_F32",0,&operandTable[0]} ,//85
{amdgpu_cdna2_op_V_CMPX_GE_F32,"V_CMPX_GE_F32",0,&operandTable[0]} ,//86
{amdgpu_cdna2_op_V_CMPX_O_F32,"V_CMPX_O_F32",0,&operandTable[0]} ,//87
{amdgpu_cdna2_op_V_CMPX_U_F32,"V_CMPX_U_F32",0,&operandTable[0]} ,//88
{amdgpu_cdna2_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32",0,&operandTable[0]} ,//89
{amdgpu_cdna2_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32",0,&operandTable[0]} ,//90
{amdgpu_cdna2_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32",0,&operandTable[0]} ,//91
{amdgpu_cdna2_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32",0,&operandTable[0]} ,//92
{amdgpu_cdna2_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32",0,&operandTable[0]} ,//93
{amdgpu_cdna2_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32",0,&operandTable[0]} ,//94
{amdgpu_cdna2_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32",0,&operandTable[0]} ,//95
{amdgpu_cdna2_op_V_CMP_F_F64,"V_CMP_F_F64",0,&operandTable[0]} ,//96
{amdgpu_cdna2_op_V_CMP_LT_F64,"V_CMP_LT_F64",0,&operandTable[0]} ,//97
{amdgpu_cdna2_op_V_CMP_EQ_F64,"V_CMP_EQ_F64",0,&operandTable[0]} ,//98
{amdgpu_cdna2_op_V_CMP_LE_F64,"V_CMP_LE_F64",0,&operandTable[0]} ,//99
{amdgpu_cdna2_op_V_CMP_GT_F64,"V_CMP_GT_F64",0,&operandTable[0]} ,//100
{amdgpu_cdna2_op_V_CMP_LG_F64,"V_CMP_LG_F64",0,&operandTable[0]} ,//101
{amdgpu_cdna2_op_V_CMP_GE_F64,"V_CMP_GE_F64",0,&operandTable[0]} ,//102
{amdgpu_cdna2_op_V_CMP_O_F64,"V_CMP_O_F64",0,&operandTable[0]} ,//103
{amdgpu_cdna2_op_V_CMP_U_F64,"V_CMP_U_F64",0,&operandTable[0]} ,//104
{amdgpu_cdna2_op_V_CMP_NGE_F64,"V_CMP_NGE_F64",0,&operandTable[0]} ,//105
{amdgpu_cdna2_op_V_CMP_NLG_F64,"V_CMP_NLG_F64",0,&operandTable[0]} ,//106
{amdgpu_cdna2_op_V_CMP_NGT_F64,"V_CMP_NGT_F64",0,&operandTable[0]} ,//107
{amdgpu_cdna2_op_V_CMP_NLE_F64,"V_CMP_NLE_F64",0,&operandTable[0]} ,//108
{amdgpu_cdna2_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64",0,&operandTable[0]} ,//109
{amdgpu_cdna2_op_V_CMP_NLT_F64,"V_CMP_NLT_F64",0,&operandTable[0]} ,//110
{amdgpu_cdna2_op_V_CMP_TRU_F64,"V_CMP_TRU_F64",0,&operandTable[0]} ,//111
{amdgpu_cdna2_op_V_CMPX_F_F64,"V_CMPX_F_F64",0,&operandTable[0]} ,//112
{amdgpu_cdna2_op_V_CMPX_LT_F64,"V_CMPX_LT_F64",0,&operandTable[0]} ,//113
{amdgpu_cdna2_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64",0,&operandTable[0]} ,//114
{amdgpu_cdna2_op_V_CMPX_LE_F64,"V_CMPX_LE_F64",0,&operandTable[0]} ,//115
{amdgpu_cdna2_op_V_CMPX_GT_F64,"V_CMPX_GT_F64",0,&operandTable[0]} ,//116
{amdgpu_cdna2_op_V_CMPX_LG_F64,"V_CMPX_LG_F64",0,&operandTable[0]} ,//117
{amdgpu_cdna2_op_V_CMPX_GE_F64,"V_CMPX_GE_F64",0,&operandTable[0]} ,//118
{amdgpu_cdna2_op_V_CMPX_O_F64,"V_CMPX_O_F64",0,&operandTable[0]} ,//119
{amdgpu_cdna2_op_V_CMPX_U_F64,"V_CMPX_U_F64",0,&operandTable[0]} ,//120
{amdgpu_cdna2_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64",0,&operandTable[0]} ,//121
{amdgpu_cdna2_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64",0,&operandTable[0]} ,//122
{amdgpu_cdna2_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64",0,&operandTable[0]} ,//123
{amdgpu_cdna2_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64",0,&operandTable[0]} ,//124
{amdgpu_cdna2_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64",0,&operandTable[0]} ,//125
{amdgpu_cdna2_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64",0,&operandTable[0]} ,//126
{amdgpu_cdna2_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64",0,&operandTable[0]} ,//127
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159
{amdgpu_cdna2_op_V_CMP_F_I16,"V_CMP_F_I16",0,&operandTable[0]} ,//160
{amdgpu_cdna2_op_V_CMP_LT_I16,"V_CMP_LT_I16",0,&operandTable[0]} ,//161
{amdgpu_cdna2_op_V_CMP_EQ_I16,"V_CMP_EQ_I16",0,&operandTable[0]} ,//162
{amdgpu_cdna2_op_V_CMP_LE_I16,"V_CMP_LE_I16",0,&operandTable[0]} ,//163
{amdgpu_cdna2_op_V_CMP_GT_I16,"V_CMP_GT_I16",0,&operandTable[0]} ,//164
{amdgpu_cdna2_op_V_CMP_NE_I16,"V_CMP_NE_I16",0,&operandTable[0]} ,//165
{amdgpu_cdna2_op_V_CMP_GE_I16,"V_CMP_GE_I16",0,&operandTable[0]} ,//166
{amdgpu_cdna2_op_V_CMP_T_I16,"V_CMP_T_I16",0,&operandTable[0]} ,//167
{amdgpu_cdna2_op_V_CMP_F_U16,"V_CMP_F_U16",0,&operandTable[0]} ,//168
{amdgpu_cdna2_op_V_CMP_LT_U16,"V_CMP_LT_U16",0,&operandTable[0]} ,//169
{amdgpu_cdna2_op_V_CMP_EQ_U16,"V_CMP_EQ_U16",0,&operandTable[0]} ,//170
{amdgpu_cdna2_op_V_CMP_LE_U16,"V_CMP_LE_U16",0,&operandTable[0]} ,//171
{amdgpu_cdna2_op_V_CMP_GT_U16,"V_CMP_GT_U16",0,&operandTable[0]} ,//172
{amdgpu_cdna2_op_V_CMP_NE_U16,"V_CMP_NE_U16",0,&operandTable[0]} ,//173
{amdgpu_cdna2_op_V_CMP_GE_U16,"V_CMP_GE_U16",0,&operandTable[0]} ,//174
{amdgpu_cdna2_op_V_CMP_T_U16,"V_CMP_T_U16",0,&operandTable[0]} ,//175
{amdgpu_cdna2_op_V_CMPX_F_I16,"V_CMPX_F_I16",0,&operandTable[0]} ,//176
{amdgpu_cdna2_op_V_CMPX_LT_I16,"V_CMPX_LT_I16",0,&operandTable[0]} ,//177
{amdgpu_cdna2_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16",0,&operandTable[0]} ,//178
{amdgpu_cdna2_op_V_CMPX_LE_I16,"V_CMPX_LE_I16",0,&operandTable[0]} ,//179
{amdgpu_cdna2_op_V_CMPX_GT_I16,"V_CMPX_GT_I16",0,&operandTable[0]} ,//180
{amdgpu_cdna2_op_V_CMPX_NE_I16,"V_CMPX_NE_I16",0,&operandTable[0]} ,//181
{amdgpu_cdna2_op_V_CMPX_GE_I16,"V_CMPX_GE_I16",0,&operandTable[0]} ,//182
{amdgpu_cdna2_op_V_CMPX_T_I16,"V_CMPX_T_I16",0,&operandTable[0]} ,//183
{amdgpu_cdna2_op_V_CMPX_F_U16,"V_CMPX_F_U16",0,&operandTable[0]} ,//184
{amdgpu_cdna2_op_V_CMPX_LT_U16,"V_CMPX_LT_U16",0,&operandTable[0]} ,//185
{amdgpu_cdna2_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16",0,&operandTable[0]} ,//186
{amdgpu_cdna2_op_V_CMPX_LE_U16,"V_CMPX_LE_U16",0,&operandTable[0]} ,//187
{amdgpu_cdna2_op_V_CMPX_GT_U16,"V_CMPX_GT_U16",0,&operandTable[0]} ,//188
{amdgpu_cdna2_op_V_CMPX_NE_U16,"V_CMPX_NE_U16",0,&operandTable[0]} ,//189
{amdgpu_cdna2_op_V_CMPX_GE_U16,"V_CMPX_GE_U16",0,&operandTable[0]} ,//190
{amdgpu_cdna2_op_V_CMPX_T_U16,"V_CMPX_T_U16",0,&operandTable[0]} ,//191
{amdgpu_cdna2_op_V_CMP_F_I32,"V_CMP_F_I32",0,&operandTable[0]} ,//192
{amdgpu_cdna2_op_V_CMP_LT_I32,"V_CMP_LT_I32",0,&operandTable[0]} ,//193
{amdgpu_cdna2_op_V_CMP_EQ_I32,"V_CMP_EQ_I32",0,&operandTable[0]} ,//194
{amdgpu_cdna2_op_V_CMP_LE_I32,"V_CMP_LE_I32",0,&operandTable[0]} ,//195
{amdgpu_cdna2_op_V_CMP_GT_I32,"V_CMP_GT_I32",0,&operandTable[0]} ,//196
{amdgpu_cdna2_op_V_CMP_NE_I32,"V_CMP_NE_I32",0,&operandTable[0]} ,//197
{amdgpu_cdna2_op_V_CMP_GE_I32,"V_CMP_GE_I32",0,&operandTable[0]} ,//198
{amdgpu_cdna2_op_V_CMP_T_I32,"V_CMP_T_I32",0,&operandTable[0]} ,//199
{amdgpu_cdna2_op_V_CMP_F_U32,"V_CMP_F_U32",0,&operandTable[0]} ,//200
{amdgpu_cdna2_op_V_CMP_LT_U32,"V_CMP_LT_U32",0,&operandTable[0]} ,//201
{amdgpu_cdna2_op_V_CMP_EQ_U32,"V_CMP_EQ_U32",0,&operandTable[0]} ,//202
{amdgpu_cdna2_op_V_CMP_LE_U32,"V_CMP_LE_U32",0,&operandTable[0]} ,//203
{amdgpu_cdna2_op_V_CMP_GT_U32,"V_CMP_GT_U32",0,&operandTable[0]} ,//204
{amdgpu_cdna2_op_V_CMP_NE_U32,"V_CMP_NE_U32",0,&operandTable[0]} ,//205
{amdgpu_cdna2_op_V_CMP_GE_U32,"V_CMP_GE_U32",0,&operandTable[0]} ,//206
{amdgpu_cdna2_op_V_CMP_T_U32,"V_CMP_T_U32",0,&operandTable[0]} ,//207
{amdgpu_cdna2_op_V_CMPX_F_I32,"V_CMPX_F_I32",0,&operandTable[0]} ,//208
{amdgpu_cdna2_op_V_CMPX_LT_I32,"V_CMPX_LT_I32",0,&operandTable[0]} ,//209
{amdgpu_cdna2_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32",0,&operandTable[0]} ,//210
{amdgpu_cdna2_op_V_CMPX_LE_I32,"V_CMPX_LE_I32",0,&operandTable[0]} ,//211
{amdgpu_cdna2_op_V_CMPX_GT_I32,"V_CMPX_GT_I32",0,&operandTable[0]} ,//212
{amdgpu_cdna2_op_V_CMPX_NE_I32,"V_CMPX_NE_I32",0,&operandTable[0]} ,//213
{amdgpu_cdna2_op_V_CMPX_GE_I32,"V_CMPX_GE_I32",0,&operandTable[0]} ,//214
{amdgpu_cdna2_op_V_CMPX_T_I32,"V_CMPX_T_I32",0,&operandTable[0]} ,//215
{amdgpu_cdna2_op_V_CMPX_F_U32,"V_CMPX_F_U32",0,&operandTable[0]} ,//216
{amdgpu_cdna2_op_V_CMPX_LT_U32,"V_CMPX_LT_U32",0,&operandTable[0]} ,//217
{amdgpu_cdna2_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32",0,&operandTable[0]} ,//218
{amdgpu_cdna2_op_V_CMPX_LE_U32,"V_CMPX_LE_U32",0,&operandTable[0]} ,//219
{amdgpu_cdna2_op_V_CMPX_GT_U32,"V_CMPX_GT_U32",0,&operandTable[0]} ,//220
{amdgpu_cdna2_op_V_CMPX_NE_U32,"V_CMPX_NE_U32",0,&operandTable[0]} ,//221
{amdgpu_cdna2_op_V_CMPX_GE_U32,"V_CMPX_GE_U32",0,&operandTable[0]} ,//222
{amdgpu_cdna2_op_V_CMPX_T_U32,"V_CMPX_T_U32",0,&operandTable[0]} ,//223
{amdgpu_cdna2_op_V_CMP_F_I64,"V_CMP_F_I64",0,&operandTable[0]} ,//224
{amdgpu_cdna2_op_V_CMP_LT_I64,"V_CMP_LT_I64",0,&operandTable[0]} ,//225
{amdgpu_cdna2_op_V_CMP_EQ_I64,"V_CMP_EQ_I64",0,&operandTable[0]} ,//226
{amdgpu_cdna2_op_V_CMP_LE_I64,"V_CMP_LE_I64",0,&operandTable[0]} ,//227
{amdgpu_cdna2_op_V_CMP_GT_I64,"V_CMP_GT_I64",0,&operandTable[0]} ,//228
{amdgpu_cdna2_op_V_CMP_NE_I64,"V_CMP_NE_I64",0,&operandTable[0]} ,//229
{amdgpu_cdna2_op_V_CMP_GE_I64,"V_CMP_GE_I64",0,&operandTable[0]} ,//230
{amdgpu_cdna2_op_V_CMP_T_I64,"V_CMP_T_I64",0,&operandTable[0]} ,//231
{amdgpu_cdna2_op_V_CMP_F_U64,"V_CMP_F_U64",0,&operandTable[0]} ,//232
{amdgpu_cdna2_op_V_CMP_LT_U64,"V_CMP_LT_U64",0,&operandTable[0]} ,//233
{amdgpu_cdna2_op_V_CMP_EQ_U64,"V_CMP_EQ_U64",0,&operandTable[0]} ,//234
{amdgpu_cdna2_op_V_CMP_LE_U64,"V_CMP_LE_U64",0,&operandTable[0]} ,//235
{amdgpu_cdna2_op_V_CMP_GT_U64,"V_CMP_GT_U64",0,&operandTable[0]} ,//236
{amdgpu_cdna2_op_V_CMP_NE_U64,"V_CMP_NE_U64",0,&operandTable[0]} ,//237
{amdgpu_cdna2_op_V_CMP_GE_U64,"V_CMP_GE_U64",0,&operandTable[0]} ,//238
{amdgpu_cdna2_op_V_CMP_T_U64,"V_CMP_T_U64",0,&operandTable[0]} ,//239
{amdgpu_cdna2_op_V_CMPX_F_I64,"V_CMPX_F_I64",0,&operandTable[0]} ,//240
{amdgpu_cdna2_op_V_CMPX_LT_I64,"V_CMPX_LT_I64",0,&operandTable[0]} ,//241
{amdgpu_cdna2_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64",0,&operandTable[0]} ,//242
{amdgpu_cdna2_op_V_CMPX_LE_I64,"V_CMPX_LE_I64",0,&operandTable[0]} ,//243
{amdgpu_cdna2_op_V_CMPX_GT_I64,"V_CMPX_GT_I64",0,&operandTable[0]} ,//244
{amdgpu_cdna2_op_V_CMPX_NE_I64,"V_CMPX_NE_I64",0,&operandTable[0]} ,//245
{amdgpu_cdna2_op_V_CMPX_GE_I64,"V_CMPX_GE_I64",0,&operandTable[0]} ,//246
{amdgpu_cdna2_op_V_CMPX_T_I64,"V_CMPX_T_I64",0,&operandTable[0]} ,//247
{amdgpu_cdna2_op_V_CMPX_F_U64,"V_CMPX_F_U64",0,&operandTable[0]} ,//248
{amdgpu_cdna2_op_V_CMPX_LT_U64,"V_CMPX_LT_U64",0,&operandTable[0]} ,//249
{amdgpu_cdna2_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64",0,&operandTable[0]} ,//250
{amdgpu_cdna2_op_V_CMPX_LE_U64,"V_CMPX_LE_U64",0,&operandTable[0]} ,//251
{amdgpu_cdna2_op_V_CMPX_GT_U64,"V_CMPX_GT_U64",0,&operandTable[0]} ,//252
{amdgpu_cdna2_op_V_CMPX_NE_U64,"V_CMPX_NE_U64",0,&operandTable[0]} ,//253
{amdgpu_cdna2_op_V_CMPX_GE_U64,"V_CMPX_GE_U64",0,&operandTable[0]} ,//254
{amdgpu_cdna2_op_V_CMPX_T_U64,"V_CMPX_T_U64",0,&operandTable[0]} ,//255
}; // end ENC_VOPC_insn_table
const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table = {
{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0
}; // end ENC_VINTRP_insn_table
