diff --git a/.gitignore b/.gitignore index 4177c02..8c09a8a 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1 @@ -SOURCES/valgrind-3.12.0.tar.bz2 +SOURCES/valgrind-3.13.0.tar.bz2 diff --git a/.valgrind.metadata b/.valgrind.metadata index 6b371bb..03d59c3 100644 --- a/.valgrind.metadata +++ b/.valgrind.metadata @@ -1 +1 @@ -7a6878bf998c60d1e377a4f22ebece8d9305bda4 SOURCES/valgrind-3.12.0.tar.bz2 +ddf13e22dd0ee688bd533fc66b94cf88f75fad86 SOURCES/valgrind-3.13.0.tar.bz2 diff --git a/SOURCES/valgrind-3.12.0-aarch64-syscalls.patch b/SOURCES/valgrind-3.12.0-aarch64-syscalls.patch deleted file mode 100644 index cc67009..0000000 --- a/SOURCES/valgrind-3.12.0-aarch64-syscalls.patch +++ /dev/null @@ -1,444 +0,0 @@ -diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c -index f8b5b7c..60482d7 100644 ---- a/coregrind/m_syswrap/syswrap-arm64-linux.c -+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c -@@ -666,10 +666,11 @@ static SyscallTableEntry syscall_main_table[] = { - LINX_(__NR_unlinkat, sys_unlinkat), // 35 - LINX_(__NR_symlinkat, sys_symlinkat), // 36 - LINX_(__NR_linkat, sys_linkat), // 37 -- LINX_(__NR_renameat, sys_renameat), // 38 -+ LINX_(__NR_renameat, sys_renameat), // 38 - LINX_(__NR_umount2, sys_umount), // 39 - LINX_(__NR_mount, sys_mount), // 40 -- -+ LINX_(__NR_pivot_root, sys_pivot_root), // 41 -+ // (__NR_nfsservctl, sys_ni_syscall), // 42 - GENXY(__NR_statfs, sys_statfs), // 43 - GENXY(__NR_fstatfs, sys_fstatfs), // 44 - GENX_(__NR_truncate, sys_truncate), // 45 -@@ -711,7 +712,7 @@ static SyscallTableEntry syscall_main_table[] = { - GENX_(__NR_sync, sys_sync), // 81 - GENX_(__NR_fsync, sys_fsync), // 82 - GENX_(__NR_fdatasync, sys_fdatasync), // 83 -- -+ LINX_(__NR_sync_file_range, sys_sync_file_range), // 84 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 85 - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 86 - LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 87 -@@ -724,27 +725,27 @@ static SyscallTableEntry syscall_main_table[] = { - LINX_(__NR_exit_group, sys_exit_group), // 94 - LINXY(__NR_waitid, sys_waitid), // 95 - LINX_(__NR_set_tid_address, sys_set_tid_address), // 96 -- -+ LINX_(__NR_unshare, sys_unshare), // 97 - LINXY(__NR_futex, sys_futex), // 98 - LINX_(__NR_set_robust_list, sys_set_robust_list), // 99 -- -+ LINXY(__NR_get_robust_list, sys_get_robust_list), // 100 - GENXY(__NR_nanosleep, sys_nanosleep), // 101 - GENXY(__NR_getitimer, sys_getitimer), // 102 - GENXY(__NR_setitimer, sys_setitimer), // 103 - GENX_(__NR_kexec_load, sys_ni_syscall), // 104 - LINX_(__NR_init_module, sys_init_module), // 105 -- -+ LINX_(__NR_delete_module, sys_delete_module), // 106 - LINXY(__NR_timer_create, sys_timer_create), // 107 -- LINXY(__NR_timer_settime, sys_timer_settime), // 108 -- LINXY(__NR_timer_gettime, sys_timer_gettime), // 109 -- LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 110 -+ LINXY(__NR_timer_gettime, sys_timer_gettime), // 108 -+ LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 109 -+ LINXY(__NR_timer_settime, sys_timer_settime), // 110 - LINX_(__NR_timer_delete, sys_timer_delete), // 111 - LINX_(__NR_clock_settime, sys_clock_settime), // 112 - LINXY(__NR_clock_gettime, sys_clock_gettime), // 113 - LINXY(__NR_clock_getres, sys_clock_getres), // 114 - LINXY(__NR_clock_nanosleep, sys_clock_nanosleep), // 115 - LINXY(__NR_syslog, sys_syslog), // 116 -- -+ // (__NR_ptrace, sys_ptrace), // 117 - LINXY(__NR_sched_setparam, sys_sched_setparam), // 118 - LINX_(__NR_sched_setscheduler,sys_sched_setscheduler),// 119 - LINX_(__NR_sched_getscheduler,sys_sched_getscheduler),// 120 -@@ -754,9 +755,10 @@ static SyscallTableEntry syscall_main_table[] = { - LINX_(__NR_sched_yield, sys_sched_yield), // 124 - LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 125 - LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 126 -- -+ LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval),// 127 -+ // (__NR_restart_syscall, sys_ni_syscall), // 128 - GENX_(__NR_kill, sys_kill), // 129 -- -+ LINXY(__NR_tkill, sys_tkill), // 130 - LINX_(__NR_tgkill, sys_tgkill), // 131 - GENXY(__NR_sigaltstack, sys_sigaltstack), // 132 - LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 133 -@@ -768,7 +770,7 @@ static SyscallTableEntry syscall_main_table[] = { - PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139 - GENX_(__NR_setpriority, sys_setpriority), // 140 - GENX_(__NR_getpriority, sys_getpriority), // 141 -- -+ // (__NR_reboot, sys_ni_syscall), // 142 - GENX_(__NR_setregid, sys_setregid), // 143 - GENX_(__NR_setgid, sys_setgid), // 144 - GENX_(__NR_setreuid, sys_setreuid), // 145 -@@ -787,13 +789,14 @@ static SyscallTableEntry syscall_main_table[] = { - GENXY(__NR_getgroups, sys_getgroups), // 158 - GENX_(__NR_setgroups, sys_setgroups), // 159 - GENXY(__NR_uname, sys_newuname), // 160 -- -+ GENX_(__NR_sethostname, sys_sethostname), // 161 -+ // (__NR_setdomainname, sys_ni_syscall), // 162 - GENXY(__NR_getrlimit, sys_old_getrlimit), // 163 - GENX_(__NR_setrlimit, sys_setrlimit), // 164 - GENXY(__NR_getrusage, sys_getrusage), // 165 - GENX_(__NR_umask, sys_umask), // 166 - LINXY(__NR_prctl, sys_prctl), // 167 -- -+ LINXY(__NR_getcpu, sys_getcpu), // 168 - GENXY(__NR_gettimeofday, sys_gettimeofday), // 169 - GENX_(__NR_settimeofday, sys_settimeofday), // 170 - LINXY(__NR_adjtimex, sys_adjtimex), // 171 -@@ -843,13 +846,14 @@ static SyscallTableEntry syscall_main_table[] = { - GENXY(__NR_munmap, sys_munmap), // 215 - GENX_(__NR_mremap, sys_mremap), // 216 - LINX_(__NR_add_key, sys_add_key), // 217 -- -+ LINX_(__NR_request_key, sys_request_key), // 218 - LINXY(__NR_keyctl, sys_keyctl), // 219 - LINX_(__NR_clone, sys_clone), // 220 - GENX_(__NR_execve, sys_execve), // 221 - PLAX_(__NR_mmap, sys_mmap), // 222 - PLAX_(__NR_fadvise64, sys_fadvise64), // 223 -- -+ // (__NR_swapon, sys_swapon), // 224 -+ // (__NR_swapoff, sys_swapoff), // 225 - GENXY(__NR_mprotect, sys_mprotect), // 226 - GENX_(__NR_msync, sys_msync), // 227 - GENX_(__NR_mlock, sys_mlock), // 228 -@@ -858,301 +862,47 @@ static SyscallTableEntry syscall_main_table[] = { - LINX_(__NR_munlockall, sys_munlockall), // 231 - GENXY(__NR_mincore, sys_mincore), // 232 - GENX_(__NR_madvise, sys_madvise), // 233 -- -+ // (__NR_remap_file_pages, sys_ni_syscall) // 234 - LINX_(__NR_mbind, sys_mbind), // 235 - LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 236 - LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 237 -- -+ // (__NR_migrate_pages, sys_ni_syscall), // 238 -+ LINXY(__NR_move_pages, sys_move_pages), // 239 -+ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo), // 240 - LINXY(__NR_perf_event_open, sys_perf_event_open), // 241 - LINXY(__NR_accept4, sys_accept4), // 242 - LINXY(__NR_recvmmsg, sys_recvmmsg), // 243 -- - GENXY(__NR_wait4, sys_wait4), // 260 - LINXY(__NR_prlimit64, sys_prlimit64), // 261 -- -+ LINXY(__NR_fanotify_init, sys_fanotify_init), // 262 -+ LINX_(__NR_fanotify_mark, sys_fanotify_mark), // 263 - LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 264 - LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 265 -- -+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 266 - LINX_(__NR_syncfs, sys_syncfs), // 267 -- -+ // (__NR_setns, sys_ni_syscall), // 268 - LINXY(__NR_sendmmsg, sys_sendmmsg), // 269 - LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 270 - LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 271 -- -+ LINX_(__NR_kcmp, sys_kcmp), // 272 -+ // (__NR_finit_module, sys_ni_syscall), // 273 -+ // (__NR_sched_setattr, sys_ni_syscall), // 274 -+ // (__NR_sched_getattr, sys_ni_syscall), // 275 - LINX_(__NR_renameat2, sys_renameat2), // 276 -- -+ // (__NR_seccomp, sys_ni_syscall), // 277 - LINXY(__NR_getrandom, sys_getrandom), // 278 - LINXY(__NR_memfd_create, sys_memfd_create), // 279 -- --// The numbers below are bogus. (See comment further down.) --// When pulling entries above this line, change the numbers --// to be correct. -- --//ZZ //zz // (restart_syscall) // 0 --//ZZ GENX_(__NR_fork, sys_fork), // 2 --//ZZ --//ZZ GENXY(__NR_open, sys_open), // 5 --//ZZ // GENXY(__NR_waitpid, sys_waitpid), // 7 --//ZZ GENXY(__NR_creat, sys_creat), // 8 --//ZZ GENX_(__NR_link, sys_link), // 9 --//ZZ --//ZZ GENX_(__NR_unlink, sys_unlink), // 10 --//ZZ GENXY(__NR_time, sys_time), // 13 --//ZZ GENX_(__NR_mknod, sys_mknod), // 14 --//ZZ --//ZZ GENX_(__NR_chmod, sys_chmod), // 15 --//ZZ //zz LINX_(__NR_lchown, sys_lchown16), // 16 --//ZZ // GENX_(__NR_break, sys_ni_syscall), // 17 --//ZZ //zz // (__NR_oldstat, sys_stat), // 18 (obsolete) --//ZZ LINX_(__NR_lseek, sys_lseek), // 19 --//ZZ --//ZZ GENX_(__NR_getpid, sys_getpid), // 20 --//ZZ LINX_(__NR_umount, sys_oldumount), // 22 --//ZZ LINX_(__NR_setuid, sys_setuid16), // 23 ## P --//ZZ LINX_(__NR_getuid, sys_getuid16), // 24 ## P --//ZZ //zz --//ZZ //zz // (__NR_stime, sys_stime), // 25 * (SVr4,SVID,X/OPEN) --//ZZ PLAXY(__NR_ptrace, sys_ptrace), // 26 --//ZZ GENX_(__NR_alarm, sys_alarm), // 27 --//ZZ //zz // (__NR_oldfstat, sys_fstat), // 28 * L -- obsolete --//ZZ GENX_(__NR_pause, sys_pause), // 29 --//ZZ --//ZZ LINX_(__NR_utime, sys_utime), // 30 --//ZZ // GENX_(__NR_stty, sys_ni_syscall), // 31 --//ZZ // GENX_(__NR_gtty, sys_ni_syscall), // 32 --//ZZ GENX_(__NR_access, sys_access), // 33 --//ZZ GENX_(__NR_nice, sys_nice), // 34 --//ZZ --//ZZ // GENX_(__NR_ftime, sys_ni_syscall), // 35 --//ZZ GENX_(__NR_rename, sys_rename), // 38 --//ZZ GENX_(__NR_mkdir, sys_mkdir), // 39 --//ZZ --//ZZ GENX_(__NR_rmdir, sys_rmdir), // 40 --//ZZ LINXY(__NR_pipe, sys_pipe), // 42 --//ZZ // GENX_(__NR_prof, sys_ni_syscall), // 44 -- --//ZZ LINX_(__NR_getgid, sys_getgid16), // 47 --//ZZ //zz // (__NR_signal, sys_signal), // 48 */* (ANSI C) --//ZZ LINX_(__NR_geteuid, sys_geteuid16), // 49 --//ZZ --//ZZ LINX_(__NR_getegid, sys_getegid16), // 50 --//ZZ // GENX_(__NR_lock, sys_ni_syscall), // 53 --//ZZ --//ZZ LINXY(__NR_fcntl, sys_fcntl), // 55 --//ZZ // GENX_(__NR_mpx, sys_ni_syscall), // 56 --//ZZ // GENX_(__NR_ulimit, sys_ni_syscall), // 58 --//ZZ //zz // (__NR_oldolduname, sys_olduname), // 59 Linux -- obsolete --//ZZ //zz --//ZZ //zz // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated --//ZZ GENXY(__NR_dup2, sys_dup2), // 63 --//ZZ GENX_(__NR_getppid, sys_getppid), // 64 --//ZZ --//ZZ GENX_(__NR_getpgrp, sys_getpgrp), // 65 --//ZZ LINXY(__NR_sigaction, sys_sigaction), // 67 --//ZZ //zz // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C) --//ZZ //zz // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C) --//ZZ //zz --//ZZ PLAX_(__NR_sigsuspend, sys_sigsuspend), // 72 --//ZZ LINXY(__NR_sigpending, sys_sigpending), // 73 --//ZZ //zz // (__NR_sethostname, sys_sethostname), // 74 */* --//ZZ //zz --//ZZ GENXY(__NR_getrlimit, sys_old_getrlimit), // 76 --//ZZ --//ZZ LINXY(__NR_getgroups, sys_getgroups16), // 80 --//ZZ LINX_(__NR_setgroups, sys_setgroups16), // 81 --//ZZ // PLAX_(__NR_select, old_select), // 82 --//ZZ GENX_(__NR_symlink, sys_symlink), // 83 --//ZZ //zz // (__NR_oldlstat, sys_lstat), // 84 -- obsolete --//ZZ //zz --//ZZ GENX_(__NR_readlink, sys_readlink), // 85 --//ZZ //zz // (__NR_uselib, sys_uselib), // 86 */Linux --//ZZ //zz // (__NR_swapon, sys_swapon), // 87 */Linux --//ZZ //zz // (__NR_reboot, sys_reboot), // 88 */Linux --//ZZ //zz // (__NR_readdir, old_readdir), // 89 -- superseded --//ZZ //zz --//ZZ // _____(__NR_mmap, old_mmap), // 90 --//ZZ GENXY(__NR_munmap, sys_munmap), // 91 --//ZZ GENX_(__NR_truncate, sys_truncate), // 92 --//ZZ GENX_(__NR_ftruncate, sys_ftruncate), // 93 --//ZZ --//ZZ LINX_(__NR_fchown, sys_fchown16), // 95 --//ZZ // GENX_(__NR_profil, sys_ni_syscall), // 98 --//ZZ GENXY(__NR_statfs, sys_statfs), // 99 --//ZZ --//ZZ GENXY(__NR_fstatfs, sys_fstatfs), // 100 --//ZZ // LINX_(__NR_ioperm, sys_ioperm), // 101 --//ZZ LINXY(__NR_socketcall, sys_socketcall), // 102 --//ZZ --//ZZ GENXY(__NR_stat, sys_newstat), // 106 --//ZZ GENXY(__NR_lstat, sys_newlstat), // 107 --//ZZ GENXY(__NR_fstat, sys_newfstat), // 108 --//ZZ //zz // (__NR_olduname, sys_uname), // 109 -- obsolete --//ZZ //zz --//ZZ // GENX_(__NR_iopl, sys_iopl), // 110 --//ZZ // GENX_(__NR_idle, sys_ni_syscall), // 112 --//ZZ // PLAXY(__NR_vm86old, sys_vm86old), // 113 __NR_syscall... weird --//ZZ //zz --//ZZ //zz // (__NR_swapoff, sys_swapoff), // 115 */Linux --//ZZ // _____(__NR_ipc, sys_ipc), // 117 --//ZZ GENX_(__NR_fsync, sys_fsync), // 118 --//ZZ PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux --//ZZ --//ZZ //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) --//ZZ // PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 --//ZZ //zz --//ZZ LINXY(__NR_sigprocmask, sys_sigprocmask), // 126 --//ZZ //zz // Nb: create_module() was removed 2.4-->2.6 --//ZZ // GENX_(__NR_create_module, sys_ni_syscall), // 127 --//ZZ LINX_(__NR_delete_module, sys_delete_module), // 129 --//ZZ //zz --//ZZ //zz // Nb: get_kernel_syms() was removed 2.4-->2.6 --//ZZ // GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130 --//ZZ GENX_(__NR_getpgid, sys_getpgid), // 132 --//ZZ //zz // (__NR_bdflush, sys_bdflush), // 134 */Linux --//ZZ //zz --//ZZ //zz // (__NR_sysfs, sys_sysfs), // 135 SVr4 --//ZZ // GENX_(__NR_afs_syscall, sys_ni_syscall), // 137 --//ZZ --//ZZ LINXY(__NR__llseek, sys_llseek), // 140 --//ZZ GENXY(__NR_getdents, sys_getdents), // 141 --//ZZ GENX_(__NR__newselect, sys_select), // 142 --//ZZ --//ZZ LINXY(__NR__sysctl, sys_sysctl), // 149 --//ZZ --//ZZ //zz //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */* --//ZZ LINX_(__NR_setresuid, sys_setresuid16), // 164 --//ZZ --//ZZ LINXY(__NR_getresuid, sys_getresuid16), // 165 --//ZZ // PLAXY(__NR_vm86, sys_vm86), // 166 x86/Linux-only --//ZZ // GENX_(__NR_query_module, sys_ni_syscall), // 167 --//ZZ GENXY(__NR_poll, sys_poll), // 168 --//ZZ //zz // (__NR_nfsservctl, sys_nfsservctl), // 169 */Linux --//ZZ //zz --//ZZ LINX_(__NR_setresgid, sys_setresgid16), // 170 --//ZZ LINXY(__NR_getresgid, sys_getresgid16), // 171 --//ZZ LINXY(__NR_prctl, sys_prctl), // 172 --//ZZ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 174 --//ZZ --//ZZ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177 --//ZZ --//ZZ LINX_(__NR_chown, sys_chown16), // 182 --//ZZ --//ZZ LINXY(__NR_sendfile, sys_sendfile), // 187 --//ZZ // GENXY(__NR_getpmsg, sys_getpmsg), // 188 --//ZZ // GENX_(__NR_putpmsg, sys_putpmsg), // 189 --//ZZ --//ZZ // Nb: we treat vfork as fork --//ZZ GENX_(__NR_vfork, sys_fork), // 190 --//ZZ GENXY(__NR_ugetrlimit, sys_getrlimit), // 191 --//ZZ GENX_(__NR_truncate64, sys_truncate64), // 193 --//ZZ GENX_(__NR_ftruncate64, sys_ftruncate64), // 194 --//ZZ --//ZZ PLAXY(__NR_stat64, sys_stat64), // 195 --//ZZ PLAXY(__NR_lstat64, sys_lstat64), // 196 --//ZZ PLAXY(__NR_fstat64, sys_fstat64), // 197 --//ZZ GENX_(__NR_lchown32, sys_lchown), // 198 --//ZZ GENX_(__NR_getuid32, sys_getuid), // 199 --//ZZ --//ZZ GENX_(__NR_getgid32, sys_getgid), // 200 --//ZZ GENX_(__NR_geteuid32, sys_geteuid), // 201 --//ZZ GENX_(__NR_getegid32, sys_getegid), // 202 --//ZZ GENX_(__NR_setreuid32, sys_setreuid), // 203 --//ZZ GENX_(__NR_setregid32, sys_setregid), // 204 --//ZZ --//ZZ LINX_(__NR_setresuid32, sys_setresuid), // 208 --//ZZ LINXY(__NR_getresuid32, sys_getresuid), // 209 --//ZZ --//ZZ LINX_(__NR_setresgid32, sys_setresgid), // 210 --//ZZ LINXY(__NR_getresgid32, sys_getresgid), // 211 --//ZZ GENX_(__NR_chown32, sys_chown), // 212 --//ZZ GENX_(__NR_setuid32, sys_setuid), // 213 --//ZZ GENX_(__NR_setgid32, sys_setgid), // 214 --//ZZ --//ZZ LINX_(__NR_setfsuid32, sys_setfsuid), // 215 --//ZZ LINX_(__NR_setfsgid32, sys_setfsgid), // 216 --//ZZ //zz // (__NR_pivot_root, sys_pivot_root), // 217 */Linux --//ZZ --//ZZ LINXY(__NR_fcntl64, sys_fcntl64), // 221 --//ZZ // GENX_(222, sys_ni_syscall), // 222 --//ZZ // PLAXY(223, sys_syscall223), // 223 // sys_bproc? --//ZZ --//ZZ LINXY(__NR_tkill, sys_tkill), // 238 */Linux --//ZZ --//ZZ LINXY(__NR_futex, sys_futex), // 240 --//ZZ LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 242 --//ZZ // PLAX_(__NR_set_thread_area, sys_set_thread_area), // 243 --//ZZ // PLAX_(__NR_get_thread_area, sys_get_thread_area), // 244 --//ZZ --//ZZ // LINX_(__NR_fadvise64, sys_fadvise64), // 250 */(Linux?) --//ZZ GENX_(251, sys_ni_syscall), // 251 --//ZZ LINXY(__NR_epoll_create, sys_epoll_create), // 254 --//ZZ --//ZZ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 255 --//ZZ LINXY(__NR_epoll_wait, sys_epoll_wait), // 256 --//ZZ //zz // (__NR_remap_file_pages, sys_remap_file_pages), // 257 */Linux --//ZZ LINX_(__NR_set_tid_address, sys_set_tid_address), // 258 --//ZZ --//ZZ LINXY(__NR_clock_getres, sys_clock_getres), // (timer_create+7) --//ZZ GENXY(__NR_statfs64, sys_statfs64), // 268 --//ZZ GENXY(__NR_fstatfs64, sys_fstatfs64), // 269 --//ZZ --//ZZ GENX_(__NR_utimes, sys_utimes), // 271 --//ZZ // LINX_(__NR_fadvise64_64, sys_fadvise64_64), // 272 */(Linux?) --//ZZ GENX_(__NR_vserver, sys_ni_syscall), // 273 --//ZZ LINX_(__NR_mbind, sys_mbind), // 274 ?/? --//ZZ --//ZZ LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 275 ?/? --//ZZ LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 276 ?/? --//ZZ --//ZZ LINX_(__NR_send, sys_send), --//ZZ LINXY(__NR_recv, sys_recv), --//ZZ LINXY(__NR_recvfrom, sys_recvfrom), // 292 --//ZZ LINX_(__NR_semget, sys_semget), // 299 --//ZZ LINXY(__NR_semctl, sys_semctl), // 300 --//ZZ --//ZZ LINX_(__NR_request_key, sys_request_key), // 287 --//ZZ LINX_(__NR_inotify_init, sys_inotify_init), // 291 --//ZZ // LINX_(__NR_migrate_pages, sys_migrate_pages), // 294 --//ZZ --//ZZ LINX_(__NR_futimesat, sys_futimesat), // 326 on arm --//ZZ --//ZZ PLAXY(__NR_fstatat64, sys_fstatat64), // 300 --//ZZ LINX_(__NR_renameat, sys_renameat), // 302 --//ZZ LINX_(__NR_symlinkat, sys_symlinkat), // 304 --//ZZ --//ZZ LINX_(__NR_shmget, sys_shmget), //307 --//ZZ // LINX_(__NR_pselect6, sys_pselect6), // --//ZZ --//ZZ // LINX_(__NR_unshare, sys_unshare), // 310 --//ZZ LINX_(__NR_set_robust_list, sys_set_robust_list), // 311 --//ZZ LINXY(__NR_get_robust_list, sys_get_robust_list), // 312 --//ZZ // LINX_(__NR_sync_file_range, sys_sync_file_range), // 314 --//ZZ --//ZZ LINXY(__NR_move_pages, sys_move_pages), // 317 --//ZZ // LINX_(__NR_getcpu, sys_ni_syscall), // 318 --//ZZ --//ZZ LINXY(__NR_signalfd, sys_signalfd), // 321 --//ZZ LINXY(__NR_eventfd, sys_eventfd), // 323 --//ZZ --//ZZ --//ZZ /////////////// --//ZZ --//ZZ // JRS 2010-Jan-03: I believe that all the numbers listed --//ZZ // in comments in the table prior to this point (eg "// 326", --//ZZ // etc) are bogus since it looks to me like they are copied --//ZZ // verbatim from syswrap-x86-linux.c and they certainly do not --//ZZ // correspond to what's in include/vki/vki-scnums-arm-linux.h. --//ZZ // From here onwards, please ensure the numbers are correct. --//ZZ --//ZZ --//ZZ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 346 --//ZZ --//ZZ --//ZZ LINXY(__NR_eventfd2, sys_eventfd2), // 356 --//ZZ LINXY(__NR_epoll_create1, sys_epoll_create1), // 357 --//ZZ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 363 --//ZZ --//ZZ LINXY(__NR_clock_adjtime, sys_clock_adjtime) // 372 -+ // (__NR_bpf, sys_ni_syscall) // 280 -+ // (__NR_execveat, sys_ni_syscall), // 281 -+ // (__NR_userfaultfd, sys_ni_syscall), // 282 -+ // (__NR_membarrier, sys_ni_syscall), // 283 -+ // (__NR_mlock2, sys_ni_syscall), // 284 -+ // (__NR_copy_file_range, sys_ni_syscall), // 285 -+ // (__NR_preadv2, sys_ni_syscall), // 286 -+ // (__NR_pwritev2, sys_ni_syscall), // 287 -+ // (__NR_pkey_mprotect, sys_ni_syscall), // 288 -+ // (__NR_pkey_alloc, sys_ni_syscall), // 289 -+ // (__NR_pkey_free, sys_ni_syscall), // 290 - }; - - diff --git a/SOURCES/valgrind-3.12.0-arm64-hint.patch b/SOURCES/valgrind-3.12.0-arm64-hint.patch deleted file mode 100644 index 561444f..0000000 --- a/SOURCES/valgrind-3.12.0-arm64-hint.patch +++ /dev/null @@ -1,33 +0,0 @@ -commit cd685e0ff55060e9ec341c86b23c6dbb2d3127f4 -Author: tom -Date: Sat Feb 11 10:44:29 2017 +0000 - - Handle unknown HINT instructions on aarch64 by ignoring them. BZ#376279. - - - git-svn-id: svn://svn.valgrind.org/vex/trunk@3302 8f6e269a-dfd6-0310-a8e1-e2731360e62c - -diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c -index e527447..484a26e 100644 ---- a/VEX/priv/guest_arm64_toIR.c -+++ b/VEX/priv/guest_arm64_toIR.c -@@ -7022,6 +7022,19 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn, - return True; - } - -+ /* -------------------- HINT ------------------- */ -+ /* 31 23 15 11 4 3 -+ 1101 0101 0000 0011 0010 imm7 1 1111 -+ */ -+ if (INSN(31,24) == BITS8(1,1,0,1,0,1,0,1) -+ && INSN(23,16) == BITS8(0,0,0,0,0,0,1,1) -+ && INSN(15,12) == BITS4(0,0,1,0) -+ && INSN(4,0) == BITS5(1,1,1,1,1)) { -+ UInt imm7 = INSN(11,5); -+ DIP("hint #%u\n", imm7); -+ return True; -+ } -+ - /* ------------------- CLREX ------------------ */ - /* 31 23 15 11 7 - 1101 0101 0000 0011 0011 m 0101 1111 CLREX CRm diff --git a/SOURCES/valgrind-3.12.0-arm64-ppc64-prlimit64.patch b/SOURCES/valgrind-3.12.0-arm64-ppc64-prlimit64.patch deleted file mode 100644 index 4b4e9ac..0000000 --- a/SOURCES/valgrind-3.12.0-arm64-ppc64-prlimit64.patch +++ /dev/null @@ -1,24 +0,0 @@ -diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c -index 1be6629..f8b5b7c 100644 ---- a/coregrind/m_syswrap/syswrap-arm64-linux.c -+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c -@@ -868,6 +868,7 @@ static SyscallTableEntry syscall_main_table[] = { - LINXY(__NR_recvmmsg, sys_recvmmsg), // 243 - - GENXY(__NR_wait4, sys_wait4), // 260 -+ LINXY(__NR_prlimit64, sys_prlimit64), // 261 - - LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 264 - LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 265 -diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c -index f90140d..ce5cbbb 100644 ---- a/coregrind/m_syswrap/syswrap-ppc64-linux.c -+++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c -@@ -905,6 +905,7 @@ static SyscallTableEntry syscall_table[] = { - LINX_(__NR_pwritev, sys_pwritev), // 321 - LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322 - -+ LINXY(__NR_prlimit64, sys_prlimit64), // 325 - LINXY(__NR_socket, sys_socket), // 326 - LINX_(__NR_bind, sys_bind), // 327 - LINX_(__NR_connect, sys_connect), // 328 diff --git a/SOURCES/valgrind-3.12.0-cd-dvd-ioctl.patch b/SOURCES/valgrind-3.12.0-cd-dvd-ioctl.patch deleted file mode 100644 index 54edf91..0000000 --- a/SOURCES/valgrind-3.12.0-cd-dvd-ioctl.patch +++ /dev/null @@ -1,97 +0,0 @@ -commit 9e00f6ed1e84a3b251aded21ef98ed9e4adc6936 -Author: sewardj -Date: Wed Nov 23 13:15:22 2016 +0000 - - Bug 352767 - Wine/valgrind: Warning: noted but unhandled ioctl 0x5307 - with no size/direction hints. (CDROMSTOP). - - Patch from Austin English (austinenglish@gmail.com). - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16152 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c -index fda8dd1..5e540e8 100644 ---- a/coregrind/m_syswrap/syswrap-linux.c -+++ b/coregrind/m_syswrap/syswrap-linux.c -@@ -5672,6 +5672,7 @@ PRE(sys_ioctl) - - /* CDROM stuff. */ - case VKI_CDROM_DISC_STATUS: -+ case VKI_CDROMSTOP: - - /* KVM ioctls that dont check for a numeric value as parameter */ - case VKI_KVM_S390_ENABLE_SIE: -@@ -9188,6 +9189,7 @@ POST(sys_ioctl) - - /* CD ROM stuff (??) */ - case VKI_CDROM_DISC_STATUS: -+ case VKI_CDROMSTOP: - break; - case VKI_CDROMSUBCHNL: - POST_MEM_WRITE(ARG3, sizeof(struct vki_cdrom_subchnl)); -diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h -index bdb8f33..7f6a117 100644 ---- a/include/vki/vki-linux.h -+++ b/include/vki/vki-linux.h -@@ -1865,6 +1865,7 @@ struct vki_scsi_idlun { - (struct cdrom_tochdr) */ - #define VKI_CDROMREADTOCENTRY 0x5306 /* Read TOC entry - (struct cdrom_tocentry) */ -+#define VKI_CDROMSTOP 0x5307 /* Stop the cdrom drive */ - #define VKI_CDROMSUBCHNL 0x530b /* Read subchannel data - (struct cdrom_subchnl) */ - #define VKI_CDROMREADMODE2 0x530c /* Read CDROM mode 2 data (2336 Bytes) - -commit 88c8d843f64fcb56a0ddd492fb560e6594c3f2e6 -Author: sewardj -Date: Wed Nov 23 13:26:23 2016 +0000 - - Bug 348616 - Wine/valgrind: Warning: noted but unhandled ioctl 0x5390 - with no size/direction hints. (DVD_READ_STRUCT) - - Patch from Austin English (austinenglish@gmail.com). - - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16153 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c -index 5e540e8..af10b92 100644 ---- a/coregrind/m_syswrap/syswrap-linux.c -+++ b/coregrind/m_syswrap/syswrap-linux.c -@@ -5674,7 +5674,10 @@ PRE(sys_ioctl) - case VKI_CDROM_DISC_STATUS: - case VKI_CDROMSTOP: - -- /* KVM ioctls that dont check for a numeric value as parameter */ -+ /* DVD stuff */ -+ case VKI_DVD_READ_STRUCT: -+ -+ /* KVM ioctls that don't check for a numeric value as parameter */ - case VKI_KVM_S390_ENABLE_SIE: - case VKI_KVM_CREATE_IRQCHIP: - case VKI_KVM_S390_INITIAL_RESET: -@@ -9226,6 +9229,10 @@ POST(sys_ioctl) - case VKI_CDROM_GET_CAPABILITY: /* 0x5331 */ - break; - -+ /* DVD stuff */ -+ case VKI_DVD_READ_STRUCT: -+ break; -+ - case VKI_FIGETBSZ: - POST_MEM_WRITE(ARG3, sizeof(unsigned long)); - break; -diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h -index 7f6a117..b64b521 100644 ---- a/include/vki/vki-linux.h -+++ b/include/vki/vki-linux.h -@@ -1885,6 +1885,7 @@ struct vki_scsi_idlun { - #define VKI_CDROM_DISC_STATUS 0x5327 /* get CD type information */ - #define VKI_CDROM_GET_CAPABILITY 0x5331 /* get capabilities */ - -+#define VKI_DVD_READ_STRUCT 0x5390 /* read structure */ - #define VKI_CDROM_SEND_PACKET 0x5393 /* send a packet to the drive */ - - struct vki_cdrom_msf0 diff --git a/SOURCES/valgrind-3.12.0-clone-spawn.patch b/SOURCES/valgrind-3.12.0-clone-spawn.patch deleted file mode 100644 index f30e7aa..0000000 --- a/SOURCES/valgrind-3.12.0-clone-spawn.patch +++ /dev/null @@ -1,3325 +0,0 @@ -commit e31d72da6cb415d0856ad53dac78e307548cd831 -Author: philippe -Date: Sun Dec 11 21:39:23 2016 +0000 - - Fix 342040 Valgrind mishandles clone with CLONE_VFORK | CLONE_VM that clones to a different stack - Fix 373192 Calling posix_spawn in glibc 2.24 completely broken - - Functionally, this patch just does the following 2 changes to the - fork clone handling: - * It does not mask anymore CLONE_VFORK : - The only effect of this flag is to suspend the parent, waiting for - the child to either exit or execve. - If some applications depends on this synchronisation, better keep it, - as it will not harm to suspend the parent valgrind waiting for the - child valgrind to exit or execve. - * In case the guest calls the clone syscall providing a non zero client stack, - set the child guest SP after the syscall, before executing guest instructions. - Not setting the guest stack ptr was the source of the problem reported - in the bugs. - - This also adds a test case none/tests/linux/clonev. - Before this patch, test gives a SEGV, which is fixed by the patch. - - The patch is however a lot bigger : this fix was touching some (mostly - identical/duplicated) code in all the linux platforms. - So, the clone/fork code has been factorised as much as possible. - This removes about 1700 lines of code. - - This has been tested on: - * amd64 - * x86 - * ppc64 be and le - * ppc32 - * arm64 - - This has been compiled on but *not really tested* on: - * mips64 (not too clear how to properly build and run valgrind on gcc22) - - It has *not* been compiled and *not* tested on: - * arm - * mips32 - * tilegx - * darwin (normally, no impact) - * solaris (normally, no impact) - - The changes are relatively mechanical, so it is not impossible that - it will compile and work out of the box on these platforms. - Otherwise, questions welcome. - - A few points of interest: - * Some platforms did have a typedef void vki_modify_ldt_t, - and some platforms had no definition for this type at all. - To make it easier to factorise, for such platforms, the following has - been used: - typedef char vki_modify_ldt_t; - When the sizeof vki_modify_ldt_t is > 1, then the arg syscall is checked. - This is somewhat a hack, but was simplifying the factorisation. - - * for mips32/mips64 and tilegx, there is a strange unconditional assignment - of 0 to a register (guest_r2 on mips, guest_r0 on tilegx). - Unclear what this is, in particular because this is assigned whatever - the result of the syscall (success or not). - - - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16186 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_syswrap/priv_syswrap-linux.h b/coregrind/m_syswrap/priv_syswrap-linux.h -index 38fcd7b..06ea7cd 100644 ---- a/coregrind/m_syswrap/priv_syswrap-linux.h -+++ b/coregrind/m_syswrap/priv_syswrap-linux.h -@@ -39,12 +39,10 @@ extern Word ML_(start_thread_NORETURN) ( void* arg ); - extern Addr ML_(allocstack) ( ThreadId tid ); - extern void ML_(call_on_new_stack_0_1) ( Addr stack, Addr retaddr, - void (*f)(Word), Word arg1 ); --extern SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, -- Int* parent_tidptr, Int* child_tidptr ); -- - - // Linux-specific (but non-arch-specific) syscalls - -+DECL_TEMPLATE(linux, sys_clone) - DECL_TEMPLATE(linux, sys_mount); - DECL_TEMPLATE(linux, sys_oldumount); - DECL_TEMPLATE(linux, sys_umount); -@@ -61,6 +59,10 @@ DECL_TEMPLATE(linux, sys_vmsplice); - DECL_TEMPLATE(linux, sys_readahead); - DECL_TEMPLATE(linux, sys_move_pages); - -+// clone is similar enough between linux variants to have a generic -+// version, but which will call an extern defined in syswrap--linux.c -+DECL_TEMPLATE(linux, sys_clone); -+ - // POSIX, but various sub-cases differ between Linux and Darwin. - DECL_TEMPLATE(linux, sys_fcntl); - DECL_TEMPLATE(linux, sys_fcntl64); -@@ -368,7 +370,83 @@ DECL_TEMPLATE(linux, sys_getpeername); - DECL_TEMPLATE(linux, sys_socketpair); - DECL_TEMPLATE(linux, sys_kcmp); - --#endif // __PRIV_SYSWRAP_LINUX_H -+// Some arch specific functions called from syswrap-linux.c -+extern Int do_syscall_clone_x86_linux ( Word (*fn)(void *), -+ void* stack, -+ Int flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls_ptr); -+extern SysRes ML_(x86_sys_set_thread_area) ( ThreadId tid, -+ vki_modify_ldt_t* info ); -+extern void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child, -+ /*IN*/ ThreadArchState *parent ); -+ -+extern Long do_syscall_clone_amd64_linux ( Word (*fn)(void *), -+ void* stack, -+ Long flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls_ptr); -+extern ULong do_syscall_clone_ppc32_linux ( Word (*fn)(void *), -+ void* stack, -+ Int flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls_ptr); -+extern ULong do_syscall_clone_ppc64_linux ( Word (*fn)(void *), -+ void* stack, -+ Int flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls_ptr ); -+extern ULong do_syscall_clone_s390x_linux ( void *stack, -+ ULong flags, -+ Int *parent_tid, -+ Int *child_tid, -+ void* tls_ptr, -+ Word (*fn)(void *), -+ void *arg); -+extern Long do_syscall_clone_arm64_linux ( Word (*fn)(void *), -+ void* stack, -+ Long flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls_ptr ); -+extern ULong do_syscall_clone_arm_linux ( Word (*fn)(void *), -+ void* stack, -+ Int flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls_ptr ); -+extern ULong do_syscall_clone_mips64_linux ( Word (*fn) (void *), /* a0 - 4 */ -+ void* stack, /* a1 - 5 */ -+ Int flags, /* a2 - 6 */ -+ void* arg, /* a3 - 7 */ -+ Int* parent_tid, /* a4 - 8 */ -+ void* tls_ptr, /* a5 - 9 */ -+ Int* child_tid ); /* a6 - 10 */ -+extern UInt do_syscall_clone_mips_linux ( Word (*fn) (void *), //a0 0 32 -+ void* stack, //a1 4 36 -+ Int flags, //a2 8 40 -+ void* arg, //a3 12 44 -+ Int* child_tid, //stack 16 48 -+ Int* parent_tid, //stack 20 52 -+ void* tls_ptr); //stack 24 56 -+extern Long do_syscall_clone_tilegx_linux ( Word (*fn) (void *), //r0 -+ void* stack, //r1 -+ Long flags, //r2 -+ void* arg, //r3 -+ Long* child_tid, //r4 -+ Long* parent_tid, //r5 -+ void* tls_ptr ); //r6 -+ #endif // __PRIV_SYSWRAP_LINUX_H - - /*--------------------------------------------------------------------*/ - /*--- end ---*/ -diff --git a/coregrind/m_syswrap/syswrap-amd64-linux.c b/coregrind/m_syswrap/syswrap-amd64-linux.c -index 08e9a93..3fe9938 100644 ---- a/coregrind/m_syswrap/syswrap-amd64-linux.c -+++ b/coregrind/m_syswrap/syswrap-amd64-linux.c -@@ -130,14 +130,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --Long do_syscall_clone_amd64_linux ( Word (*fn)(void *), -- void* stack, -- Long flags, -- void* arg, -- Long* child_tid, -- Long* parent_tid, -- vki_modify_ldt_t * ); -+// See priv_syswrap-linux.h for arg profile. - asm( - ".text\n" - ".globl do_syscall_clone_amd64_linux\n" -@@ -183,126 +176,6 @@ asm( - #undef __NR_EXIT - - --// forward declaration --static void setup_child ( ThreadArchState*, ThreadArchState* ); -- --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for EIP, and a separate stack -- for ESP. -- */ --static SysRes do_clone ( ThreadId ptid, -- ULong flags, Addr rsp, -- Long* parent_tidptr, -- Long* child_tidptr, -- Addr tlsaddr ) --{ -- static const Bool debug = False; -- -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- UWord* stack; -- SysRes res; -- Long rax; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- -- /* Copy register state -- -- Both parent and child return to the same place, and the code -- following the clone syscall works out which is which, so we -- don't need to worry about it. -- -- The parent gets the child's new tid returned from clone, but the -- child gets 0. -- -- If the clone call specifies a NULL rsp for the new thread, then -- it actually gets a copy of the parent's rsp. -- */ -- setup_child( &ctst->arch, &ptst->arch ); -- -- /* Make sys_clone appear to have returned Success(0) in the -- child. */ -- ctst->arch.vex.guest_RAX = 0; -- -- if (rsp != 0) -- ctst->arch.vex.guest_RSP = rsp; -- -- ctst->os_state.parent = ptid; -- -- /* inherit signal mask */ -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (rsp, ctst); -- -- /* Assume the clone will succeed, and tell any tool that wants to -- know that this thread has come into existence. If the clone -- fails, we'll send out a ll_exit notification for it at the out: -- label below, to clean up. */ -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls at %#lx\n", tlsaddr); -- ctst->arch.vex.guest_FS_CONST = tlsaddr; -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- -- /* start the thread with everything blocked */ -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- /* Create the new thread */ -- rax = do_syscall_clone_amd64_linux( -- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -- child_tidptr, parent_tidptr, NULL -- ); -- res = VG_(mk_SysRes_amd64_linux)( rax ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError(res)) { -- /* clone failed */ -- VG_(cleanup_thread)(&ctst->arch); -- ctst->status = VgTs_Empty; -- /* oops. Better tell the tool the thread exited in a hurry :-) */ -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; --} -- -- - /* --------------------------------------------------------------------- - More thread stuff - ------------------------------------------------------------------ */ -@@ -311,16 +184,6 @@ void VG_(cleanup_thread) ( ThreadArchState *arch ) - { - } - --void setup_child ( /*OUT*/ ThreadArchState *child, -- /*IN*/ ThreadArchState *parent ) --{ -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- -- - /* --------------------------------------------------------------------- - PRE/POST wrappers for AMD64/Linux-specific syscalls - ------------------------------------------------------------------ */ -@@ -333,7 +196,6 @@ void setup_child ( /*OUT*/ ThreadArchState *child, - the right thing to do is to make these wrappers 'static' since they - aren't visible outside this file, but that requires even more macro - magic. */ --DECL_TEMPLATE(amd64_linux, sys_clone); - DECL_TEMPLATE(amd64_linux, sys_rt_sigreturn); - DECL_TEMPLATE(amd64_linux, sys_arch_prctl); - DECL_TEMPLATE(amd64_linux, sys_ptrace); -@@ -342,108 +204,6 @@ DECL_TEMPLATE(amd64_linux, sys_mmap); - DECL_TEMPLATE(amd64_linux, sys_syscall184); - - --PRE(sys_clone) --{ -- ULong cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ2(int, "clone", -- unsigned long, flags, -- void *, child_stack); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA3("clone", int *, parent_tidptr); -- } -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & VKI_CLONE_SETTLS) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA4("clone", vki_modify_ldt_t *, tlsinfo); -- } -- PRE_MEM_READ("clone(tlsinfo)", ARG4, sizeof(vki_modify_ldt_t)); -- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), -- VKI_PROT_READ)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA5("clone", int *, child_tidptr); -- } -- PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int), VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child ESP */ -- (Long *)ARG3, /* parent_tidptr */ -- (Long *)ARG4, /* child_tidptr */ -- (Addr)ARG5)); /* set_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG4)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, -- "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, -- "\n"); -- VG_(message)(Vg_UserMsg, -- "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, -- " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, -- " - via the implementation of fork or vfork\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG4, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_rt_sigreturn) - { - /* This isn't really a syscall at all - it's a misuse of the -@@ -761,7 +521,7 @@ static SyscallTableEntry syscall_table[] = { - LINX_(__NR_setsockopt, sys_setsockopt), // 54 - - LINXY(__NR_getsockopt, sys_getsockopt), // 55 -- PLAX_(__NR_clone, sys_clone), // 56 -+ LINX_(__NR_clone, sys_clone), // 56 - GENX_(__NR_fork, sys_fork), // 57 - GENX_(__NR_vfork, sys_fork), // 58 treat as fork - GENX_(__NR_execve, sys_execve), // 59 -diff --git a/coregrind/m_syswrap/syswrap-arm-linux.c b/coregrind/m_syswrap/syswrap-arm-linux.c -index 3bbd109..b417428 100644 ---- a/coregrind/m_syswrap/syswrap-arm-linux.c -+++ b/coregrind/m_syswrap/syswrap-arm-linux.c -@@ -102,14 +102,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --ULong do_syscall_clone_arm_linux ( Word (*fn)(void *), -- void* stack, -- Int flags, -- void* arg, -- Int* child_tid, -- Int* parent_tid, -- void* tls ); -+// See priv_syswrap-linux.h for arg profile. - asm( - ".text\n" - ".globl do_syscall_clone_arm_linux\n" -@@ -148,104 +141,8 @@ asm( - #undef __NR_EXIT - - // forward declarations --static void setup_child ( ThreadArchState*, ThreadArchState* ); --static void assign_guest_tls(ThreadId ctid, Addr tlsptr); - static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ); - --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for IP, and a separate stack -- for SP. -- */ --static SysRes do_clone ( ThreadId ptid, -- UInt flags, Addr sp, -- Int *parent_tidptr, -- Int *child_tidptr, -- Addr child_tls) --{ -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- UInt r0; -- UWord *stack; -- SysRes res; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- -- if(stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- -- setup_child( &ctst->arch, &ptst->arch ); -- -- ctst->arch.vex.guest_R0 = 0; -- if(sp != 0) -- ctst->arch.vex.guest_R13 = sp; -- -- ctst->os_state.parent = ptid; -- -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (sp, ctst); -- -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- /* Just assign the tls pointer in the guest TPIDRURO. */ -- assign_guest_tls(ctid, child_tls); -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- r0 = do_syscall_clone_arm_linux( -- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -- child_tidptr, parent_tidptr, NULL -- ); -- //VG_(printf)("AFTER SYSCALL, %x and %x CHILD: %d PARENT: %d\n",child_tidptr, parent_tidptr,*child_tidptr,*parent_tidptr); -- -- res = VG_(mk_SysRes_arm_linux)( r0 ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- --out: -- if (sr_isError(res)) { -- VG_(cleanup_thread)(&ctst->arch); -- ctst->status = VgTs_Empty; -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; --} -- -- -- - /* --------------------------------------------------------------------- - More thread stuff - ------------------------------------------------------------------ */ -@@ -256,26 +153,13 @@ void VG_(cleanup_thread) ( ThreadArchState* arch ) - { - } - --void setup_child ( /*OUT*/ ThreadArchState *child, -- /*IN*/ ThreadArchState *parent ) --{ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- --static void assign_guest_tls(ThreadId tid, Addr tlsptr) --{ -- VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr; --} -- - /* Assigns tlsptr to the guest TPIDRURO. - If needed for the specific hardware, really executes - the set_tls syscall. - */ - static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) - { -- assign_guest_tls(tid, tlsptr); -+ VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr; - - if (KernelVariantiS(KernelVariant_android_no_hw_tls, - VG_(clo_kernel_variant))) { -@@ -333,7 +217,6 @@ DECL_TEMPLATE(arm_linux, sys_stat64); - DECL_TEMPLATE(arm_linux, sys_lstat64); - DECL_TEMPLATE(arm_linux, sys_fstatat64); - DECL_TEMPLATE(arm_linux, sys_fstat64); --DECL_TEMPLATE(arm_linux, sys_clone); - DECL_TEMPLATE(arm_linux, sys_sigreturn); - DECL_TEMPLATE(arm_linux, sys_rt_sigreturn); - DECL_TEMPLATE(arm_linux, sys_sigsuspend); -@@ -424,100 +307,6 @@ POST(sys_fstat64) - POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); - } - --PRE(sys_clone) --{ -- UInt cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ5(int, "clone", -- unsigned long, flags, -- void *, child_stack, -- int *, parent_tidptr, -- void *, child_tls, -- int *, child_tidptr); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & VKI_CLONE_SETTLS) { -- PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t)); -- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), -- VKI_PROT_READ)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child ESP */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5, /* child_tidptr */ -- (Addr)ARG4)); /* set_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -- VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG5, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_sigreturn) - { - /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -@@ -901,7 +690,7 @@ static SyscallTableEntry syscall_main_table[] = { - GENX_(__NR_fsync, sys_fsync), // 118 - PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux - -- PLAX_(__NR_clone, sys_clone), // 120 -+ LINX_(__NR_clone, sys_clone), // 120 - //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) - GENXY(__NR_uname, sys_newuname), // 122 - // PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c -index 6b579e8..1be6629 100644 ---- a/coregrind/m_syswrap/syswrap-arm64-linux.c -+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c -@@ -138,14 +138,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --Long do_syscall_clone_arm64_linux ( Word (*fn)(void *), -- void* child_stack, -- Long flags, -- void* arg, -- Int* child_tid, -- Int* parent_tid, -- void* tls ); -+// See priv_syswrap-linux.h for arg profile. - asm( - ".text\n" - ".globl do_syscall_clone_arm64_linux\n" -@@ -196,121 +189,6 @@ static void setup_child ( ThreadArchState*, ThreadArchState* ); - static void assign_guest_tls(ThreadId ctid, Addr tlsptr); - //ZZ static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ); - --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for IP, and a separate stack -- for SP. -- */ --static SysRes do_clone ( ThreadId ptid, -- ULong flags, -- Addr child_xsp, -- Int* parent_tidptr, -- Int* child_tidptr, -- Addr child_tls ) --{ -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- UWord* stack; -- SysRes res; -- ULong x0; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- -- /* Copy register state -- -- Both parent and child return to the same place, and the code -- following the clone syscall works out which is which, so we -- don't need to worry about it. -- -- The parent gets the child's new tid returned from clone, but the -- child gets 0. -- -- If the clone call specifies a NULL xsp for the new thread, then -- it actually gets a copy of the parent's xsp. -- */ -- setup_child( &ctst->arch, &ptst->arch ); -- -- /* Make sys_clone appear to have returned Success(0) in the -- child. */ -- ctst->arch.vex.guest_X0 = 0; -- -- if (child_xsp != 0) -- ctst->arch.vex.guest_XSP = child_xsp; -- -- ctst->os_state.parent = ptid; -- -- /* inherit signal mask */ -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack)(child_xsp, ctst); -- -- /* Assume the clone will succeed, and tell any tool that wants to -- know that this thread has come into existence. If the clone -- fails, we'll send out a ll_exit notification for it at the out: -- label below, to clean up. */ -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- /* Just assign the tls pointer in the guest TPIDR_EL0. */ -- assign_guest_tls(ctid, child_tls); -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- -- /* start the thread with everything blocked */ -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- x0 = do_syscall_clone_arm64_linux( -- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -- child_tidptr, parent_tidptr, NULL -- ); -- -- res = VG_(mk_SysRes_arm64_linux)( x0 ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError(res)) { -- /* clone failed */ -- VG_(cleanup_thread)(&ctst->arch); -- ctst->status = VgTs_Empty; -- /* oops. Better tell the tool the thread exited in a hurry :-) */ -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; --} -- -- - /* --------------------------------------------------------------------- - More thread stuff - ------------------------------------------------------------------ */ -@@ -397,7 +275,6 @@ DECL_TEMPLATE(arm64_linux, sys_mmap); - //ZZ DECL_TEMPLATE(arm_linux, sys_lstat64); - //ZZ DECL_TEMPLATE(arm_linux, sys_fstatat64); - //ZZ DECL_TEMPLATE(arm_linux, sys_fstat64); --DECL_TEMPLATE(arm64_linux, sys_clone); - //ZZ DECL_TEMPLATE(arm_linux, sys_sigreturn); - DECL_TEMPLATE(arm64_linux, sys_rt_sigreturn); - //ZZ DECL_TEMPLATE(arm_linux, sys_sigsuspend); -@@ -512,110 +389,6 @@ PRE(sys_mmap) - //ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); - //ZZ } - --/* Aarch64 seems to use CONFIG_CLONE_BACKWARDS in the kernel. See: -- http://dev.gentoo.org/~vapier/aarch64/linux-3.12.6.config -- http://people.redhat.com/wcohen/aarch64/aarch64_config -- from linux-3.10.5/kernel/fork.c -- #ifdef CONFIG_CLONE_BACKWARDS -- SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp, -- int __user *, parent_tidptr, -- int, tls_val, -- int __user *, child_tidptr) --*/ --PRE(sys_clone) --{ -- UInt cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ5(int, "clone", -- unsigned long, flags, -- void *, child_stack, -- int *, parent_tidptr, -- void *, child_tls, -- int *, child_tidptr); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } --//ZZ if (ARG1 & VKI_CLONE_SETTLS) { --//ZZ PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t)); --//ZZ if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), --//ZZ VKI_PROT_READ)) { --//ZZ SET_STATUS_Failure( VKI_EFAULT ); --//ZZ return; --//ZZ } --//ZZ } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child SP */ -- (Int*)ARG3, /* parent_tidptr */ -- (Int*)ARG5, /* child_tidptr */ -- (Addr)ARG4)); /* tls_val */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int*)ARG3, /* parent_tidptr */ -- (Int*)ARG5)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -- VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG5, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - //ZZ PRE(sys_sigreturn) - //ZZ { - //ZZ /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -@@ -1072,7 +845,7 @@ static SyscallTableEntry syscall_main_table[] = { - LINX_(__NR_add_key, sys_add_key), // 217 - - LINXY(__NR_keyctl, sys_keyctl), // 219 -- PLAX_(__NR_clone, sys_clone), // 220 -+ LINX_(__NR_clone, sys_clone), // 220 - GENX_(__NR_execve, sys_execve), // 221 - PLAX_(__NR_mmap, sys_mmap), // 222 - PLAX_(__NR_fadvise64, sys_fadvise64), // 223 -diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c -index b3ffdb1..aa00a5f 100644 ---- a/coregrind/m_syswrap/syswrap-linux.c -+++ b/coregrind/m_syswrap/syswrap-linux.c -@@ -93,9 +93,8 @@ static VgSchedReturnCode thread_wrapper(Word /*ThreadId*/ tidW) - VG_TRACK(pre_thread_first_insn, tid); - - tst->os_state.lwpid = VG_(gettid)(); -- /* Set the threadgroup for real. This overwrites the provisional -- value set in do_clone() syswrap-*-linux.c. See comments in -- do_clone for background, also #226116. */ -+ /* Set the threadgroup for real. This overwrites the provisional value set -+ in do_clone(). See comments in do_clone for background, also #226116. */ - tst->os_state.threadgroup = VG_(getpid)(); - - /* Thread created with all signals blocked; scheduler will set the -@@ -430,17 +429,327 @@ void VG_(main_thread_wrapper_NORETURN)(ThreadId tid) - vg_assert(0); - } - -+/* Clone a new thread. Note that in the clone syscalls, we hard-code -+ tlsaddr argument as NULL : the guest TLS is emulated via guest -+ registers, and Valgrind itself has no thread local storage. */ -+static SysRes clone_new_thread ( Word (*fn)(void *), -+ void* stack, -+ Word flags, -+ ThreadState* ctst, -+ Int* child_tidptr, -+ Int* parent_tidptr) -+{ -+ SysRes res; -+ /* Note that in all the below, we make sys_clone appear to have returned -+ Success(0) in the child, by assigning the relevant child guest -+ register(s) just before the clone syscall. */ -+#if defined(VGP_x86_linux) -+ Int eax; -+ ctst->arch.vex.guest_EAX = 0; -+ eax = do_syscall_clone_x86_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ res = VG_(mk_SysRes_x86_linux)( eax ); -+#elif defined(VGP_amd64_linux) -+ Long rax; -+ ctst->arch.vex.guest_RAX = 0; -+ rax = do_syscall_clone_amd64_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ res = VG_(mk_SysRes_amd64_linux)( rax ); -+#elif defined(VGP_ppc32_linux) -+ ULong word64; -+ UInt old_cr = LibVEX_GuestPPC32_get_CR( &ctst->arch.vex ); -+ /* %r3 = 0 */ -+ ctst->arch.vex.guest_GPR3 = 0; -+ /* %cr0.so = 0 */ -+ LibVEX_GuestPPC32_put_CR( old_cr & ~(1<<28), &ctst->arch.vex ); -+ word64 = do_syscall_clone_ppc32_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ /* High half word64 is syscall return value. Low half is -+ the entire CR, from which we need to extract CR0.SO. */ -+ /* VG_(printf)("word64 = 0x%llx\n", word64); */ -+ res = VG_(mk_SysRes_ppc32_linux)(/*val*/(UInt)(word64 >> 32), -+ /*errflag*/ (((UInt)word64) >> 28) & 1); -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -+ ULong word64; -+ UInt old_cr = LibVEX_GuestPPC64_get_CR( &ctst->arch.vex ); -+ /* %r3 = 0 */ -+ ctst->arch.vex.guest_GPR3 = 0; -+ /* %cr0.so = 0 */ -+ LibVEX_GuestPPC64_put_CR( old_cr & ~(1<<28), &ctst->arch.vex ); -+ word64 = do_syscall_clone_ppc64_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ /* Low half word64 is syscall return value. Hi half is -+ the entire CR, from which we need to extract CR0.SO. */ -+ /* VG_(printf)("word64 = 0x%llx\n", word64); */ -+ res = VG_(mk_SysRes_ppc64_linux) -+ (/*val*/(UInt)(word64 & 0xFFFFFFFFULL), -+ /*errflag*/ (UInt)((word64 >> (32+28)) & 1)); -+#elif defined(VGP_s390x_linux) -+ ULong r2; -+ ctst->arch.vex.guest_r2 = 0; -+ r2 = do_syscall_clone_s390x_linux -+ (stack, flags, parent_tidptr, child_tidptr, NULL, -+ ML_(start_thread_NORETURN), ctst); -+ res = VG_(mk_SysRes_s390x_linux)( r2 ); -+#elif defined(VGP_arm64_linux) -+ ULong x0; -+ ctst->arch.vex.guest_X0 = 0; -+ x0 = do_syscall_clone_arm64_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ res = VG_(mk_SysRes_arm64_linux)( x0 ); -+#elif defined(VGP_arm_linux) -+ UInt r0; -+ ctst->arch.vex.guest_R0 = 0; -+ r0 = do_syscall_clone_arm_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ res = VG_(mk_SysRes_arm_linux)( r0 ); -+#elif defined(VGP_mips64_linux) -+ UInt ret = 0; -+ ctst->arch.vex.guest_r2 = 0; -+ ctst->arch.vex.guest_r7 = 0; -+ ret = do_syscall_clone_mips64_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ parent_tidptr, NULL, child_tidptr); -+ res = VG_(mk_SysRes_mips64_linux)( /* val */ ret, 0, /* errflag */ 0); -+#elif defined(VGP_mips32_linux) -+ UInt ret = 0; -+ ctst->arch.vex.guest_r2 = 0; -+ ctst->arch.vex.guest_r7 = 0; -+ ret = do_syscall_clone_mips_linux -+ (ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ /* High half word64 is syscall return value. Low half is -+ the entire CR, from which we need to extract CR0.SO. */ -+ res = VG_ (mk_SysRes_mips32_linux) (/*val */ ret, 0, /*errflag */ 0); -+#elif defined(VGP_tilegx_linux) -+ Long ret = 0; -+ ctst->arch.vex.guest_r0 = 0; -+ ctst->arch.vex.guest_r3 = 0; -+ ret = do_syscall_clone_tilegx_linux -+ (ML_ (start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr, NULL); -+ /* High half word64 is syscall return value. */ -+ res = VG_(mk_SysRes_tilegx_linux) (/*val */ ret); -+#else -+# error Unknown platform -+#endif -+ return res; -+} -+ -+static void setup_child ( /*OUT*/ ThreadArchState *child, -+ /*IN*/ ThreadArchState *parent ) -+{ -+ /* We inherit our parent's guest state. */ -+ child->vex = parent->vex; -+ child->vex_shadow1 = parent->vex_shadow1; -+ child->vex_shadow2 = parent->vex_shadow2; - --/* Do a clone which is really a fork() */ --SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, -- Int* parent_tidptr, Int* child_tidptr ) -+#if defined(VGP_x86_linux) -+ extern void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child, -+ /*IN*/ ThreadArchState *parent ); -+ ML_(x86_setup_LDT_GDT)(child, parent); -+#endif -+} -+ -+static SysRes setup_child_tls (ThreadId ctid, Addr tlsaddr) -+{ -+ static const Bool debug = False; -+ ThreadState* ctst = VG_(get_ThreadState)(ctid); -+ // res is succesful by default, overriden if a real syscall is needed/done. -+ SysRes res = VG_(mk_SysRes_Success)(0); -+ -+ if (debug) -+ VG_(printf)("clone child has SETTLS: tls at %#lx\n", tlsaddr); -+ -+#if defined(VGP_x86_linux) -+ vki_modify_ldt_t* tlsinfo = (vki_modify_ldt_t*)tlsaddr; -+ if (debug) -+ VG_(printf)("clone child has SETTLS: tls info at %p: idx=%u " -+ "base=%#lx limit=%x; esp=%#x fs=%x gs=%x\n", -+ tlsinfo, tlsinfo->entry_number, -+ tlsinfo->base_addr, tlsinfo->limit, -+ ctst->arch.vex.guest_ESP, -+ ctst->arch.vex.guest_FS, ctst->arch.vex.guest_GS); -+ res = ML_(x86_sys_set_thread_area)(ctid, tlsinfo); -+#elif defined(VGP_amd64_linux) -+ ctst->arch.vex.guest_FS_CONST = tlsaddr; -+#elif defined(VGP_ppc32_linux) -+ ctst->arch.vex.guest_GPR2 = tlsaddr; -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -+ ctst->arch.vex.guest_GPR13 = tlsaddr; -+#elif defined(VGP_s390x_linux) -+ ctst->arch.vex.guest_a0 = (UInt) (tlsaddr >> 32); -+ ctst->arch.vex.guest_a1 = (UInt) tlsaddr; -+#elif defined(VGP_arm64_linux) -+ /* Just assign the tls pointer in the guest TPIDR_EL0. */ -+ ctst->arch.vex.guest_TPIDR_EL0 = tlsaddr; -+#elif defined(VGP_arm_linux) -+ /* Just assign the tls pointer in the guest TPIDRURO. */ -+ ctst->arch.vex.guest_TPIDRURO = tlsaddr; -+#elif defined(VGP_mips64_linux) -+ ctst->arch.vex.guest_ULR = tlsaddr; -+ ctst->arch.vex.guest_r27 = tlsaddr; -+#elif defined(VGP_mips32_linux) -+ ctst->arch.vex.guest_ULR = tlsaddr; -+ ctst->arch.vex.guest_r27 = tlsaddr; -+#elif defined(VGP_tilegx_linux) -+ ctst->arch.vex.guest_r53 = tlsaddr; -+#else -+# error Unknown platform -+#endif -+ return res; -+} -+ -+/* -+ When a client clones, we need to keep track of the new thread. This means: -+ 1. allocate a ThreadId+ThreadState+stack for the thread -+ -+ 2. initialize the thread's new VCPU state -+ -+ 3. create the thread using the same args as the client requested, -+ but using the scheduler entrypoint for EIP, and a separate stack -+ for ESP. -+ */ -+static SysRes do_clone ( ThreadId ptid, -+ UWord flags, Addr sp, -+ Int* parent_tidptr, -+ Int* child_tidptr, -+ Addr tlsaddr) -+{ -+ ThreadId ctid = VG_(alloc_ThreadState)(); -+ ThreadState* ptst = VG_(get_ThreadState)(ptid); -+ ThreadState* ctst = VG_(get_ThreadState)(ctid); -+ UWord* stack; -+ SysRes res; -+ vki_sigset_t blockall, savedmask; -+ -+ VG_(sigfillset)(&blockall); -+ -+ vg_assert(VG_(is_running_thread)(ptid)); -+ vg_assert(VG_(is_valid_tid)(ctid)); -+ -+ stack = (UWord*)ML_(allocstack)(ctid); -+ if (stack == NULL) { -+ res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -+ goto out; -+ } -+ -+ /* Copy register state -+ -+ Both parent and child return to the same place, and the code -+ following the clone syscall works out which is which, so we -+ don't need to worry about it. -+ -+ The parent gets the child's new tid returned from clone, but the -+ child gets 0. -+ -+ If the clone call specifies a NULL sp for the new thread, then -+ it actually gets a copy of the parent's sp. -+ */ -+ setup_child( &ctst->arch, &ptst->arch ); -+ -+ if (sp != 0) -+ VG_(set_SP)(ctid, sp); -+ -+ ctst->os_state.parent = ptid; -+ -+ /* inherit signal mask */ -+ ctst->sig_mask = ptst->sig_mask; -+ ctst->tmp_sig_mask = ptst->sig_mask; -+ -+ /* Start the child with its threadgroup being the same as the -+ parent's. This is so that any exit_group calls that happen -+ after the child is created but before it sets its -+ os_state.threadgroup field for real (in thread_wrapper in -+ syswrap-linux.c), really kill the new thread. a.k.a this avoids -+ a race condition in which the thread is unkillable (via -+ exit_group) because its threadgroup is not set. The race window -+ is probably only a few hundred or a few thousand cycles long. -+ See #226116. */ -+ ctst->os_state.threadgroup = ptst->os_state.threadgroup; -+ -+ ML_(guess_and_register_stack) (sp, ctst); -+ -+ /* Assume the clone will succeed, and tell any tool that wants to -+ know that this thread has come into existence. We cannot defer -+ it beyond this point because setup_tls, just below, -+ causes checks to assert by making references to the new ThreadId -+ if we don't state the new thread exists prior to that point. -+ If the clone fails, we'll send out a ll_exit notification for it -+ at the out: label below, to clean up. */ -+ vg_assert(VG_(owns_BigLock_LL)(ptid)); -+ VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -+ -+ if (flags & VKI_CLONE_SETTLS) { -+ res = setup_child_tls(ctid, tlsaddr); -+ if (sr_isError(res)) -+ goto out; -+ } -+ flags &= ~VKI_CLONE_SETTLS; -+ -+ /* start the thread with everything blocked */ -+ VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -+ -+ /* Create the new thread */ -+ res = clone_new_thread ( ML_(start_thread_NORETURN), stack, flags, ctst, -+ child_tidptr, parent_tidptr); -+ -+ VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -+ -+ out: -+ if (sr_isError(res)) { -+ /* clone failed */ -+ VG_(cleanup_thread)(&ctst->arch); -+ ctst->status = VgTs_Empty; -+ /* oops. Better tell the tool the thread exited in a hurry :-) */ -+ VG_TRACK( pre_thread_ll_exit, ctid ); -+ } -+ -+#if defined(VGP_mips64_linux) || defined(VGP_mips32_linux) -+ // ??? why do we set unconditionally r2 to 0, even when error out ??? -+ ptst->arch.vex.guest_r2 = 0; -+#elif defined(VGP_tilegx_linux) -+ // ??? why do we set unconditionally r0 to 0, even when error out ??? -+ ptst->arch.vex.guest_r0 = 0; -+#endif -+ -+ return res; -+} -+ -+/* Do a clone which is really a fork(). -+ ML_(do_fork_clone) uses the clone syscall to fork a child process. -+ Note that this should not be called for a thread creation. -+ Also, some flags combinations are not supported, and such combinations -+ are handled either by masking the non supported flags or by asserting. -+ -+ The CLONE_VFORK flag is accepted, as this just tells that the parent is -+ suspended till the child exits or calls execve. We better keep this flag, -+ just in case the guests parent/client code depends on this synchronisation. -+ -+ We cannot keep the flag CLONE_VM, as Valgrind will do whatever host -+ instructions in the child process, that will mess up the parent host -+ memory. So, we hope for the best and assumes that the guest application does -+ not (really) depends on sharing the memory between parent and child in the -+ interval between clone and exits/execve. -+ -+ If child_sp != 0, the child (guest) sp will be set to child_sp just after the -+ clone syscall, before child guest instructions are executed. */ -+static SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, -+ Int* parent_tidptr, Int* child_tidptr, -+ Addr child_sp) - { - vki_sigset_t fork_saved_mask; - vki_sigset_t mask; - SysRes res; - - if (flags & (VKI_CLONE_SETTLS | VKI_CLONE_FS | VKI_CLONE_VM -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) -+ | VKI_CLONE_FILES)) - return VG_(mk_SysRes_Error)( VKI_EINVAL ); - - /* Block all signals during fork, so that we can fix things up in -@@ -476,6 +785,8 @@ SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, - - if (!sr_isError(res) && sr_Res(res) == 0) { - /* child */ -+ if (child_sp != 0) -+ VG_(set_SP)(tid, child_sp); - VG_(do_atfork_child)(tid); - - /* restore signal mask */ -@@ -508,7 +819,6 @@ SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, - return res; - } - -- - /* --------------------------------------------------------------------- - PRE/POST wrappers for arch-generic, Linux-specific syscalls - ------------------------------------------------------------------ */ -@@ -519,6 +829,157 @@ SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, - #error Unknown endianness - #endif - -+PRE(sys_clone) -+{ -+ UInt cloneflags; -+ Bool badarg = False; -+ -+ PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -+ -+// Order of arguments differs between platforms. -+#if defined(VGP_x86_linux) \ -+ || defined(VGP_ppc32_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \ -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) -+#define ARG_CHILD_TIDPTR ARG5 -+#define PRA_CHILD_TIDPTR PRA5 -+#define ARG_TLS ARG4 -+#define PRA_TLS PRA4 -+#elif defined(VGP_amd64_linux) || defined(VGP_tilegx_linux) \ -+ || defined(VGP_s390x_linux) -+#define ARG_CHILD_TIDPTR ARG4 -+#define PRA_CHILD_TIDPTR PRA4 -+#define ARG_TLS ARG5 -+#define PRA_TLS PRA5 -+#else -+# error Unknown platform -+#endif -+// And s390x is even more special, and inverts flags and child stack args -+#if defined(VGP_s390x_linux) -+#define ARG_FLAGS ARG2 -+#define PRA_FLAGS PRA2 -+#define ARG_CHILD_STACK ARG1 -+#define PRA_CHILD_STACK PRA1 -+#else -+#define ARG_FLAGS ARG1 -+#define PRA_FLAGS PRA1 -+#define ARG_CHILD_STACK ARG2 -+#define PRA_CHILD_STACK PRA2 -+#endif -+ -+ if (VG_(tdict).track_pre_reg_read) { -+ PRA_FLAGS("clone", unsigned long, flags); -+ PRA_CHILD_STACK("clone", void *, child_stack); -+ } -+ -+ if (ARG_FLAGS & VKI_CLONE_PARENT_SETTID) { -+ if (VG_(tdict).track_pre_reg_read) { -+ PRA3("clone", int *, parent_tidptr); -+ } -+ PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -+ if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -+ VKI_PROT_WRITE)) { -+ badarg = True; -+ } -+ } -+ if (ARG_FLAGS & VKI_CLONE_SETTLS) { -+ if (VG_(tdict).track_pre_reg_read) { -+ PRA_TLS("clone", vki_modify_ldt_t *, tlsinfo); -+ } -+ /* Not very clear what is vki_modify_ldt_t: for many platforms, it is a -+ dummy type (that we define as a char). We only dereference/check the -+ ARG_TLS pointer if the type looks like a real type, i.e. sizeof > 1. */ -+ if (sizeof(vki_modify_ldt_t) > 1) { -+ PRE_MEM_READ("clone(tlsinfo)", ARG_TLS, sizeof(vki_modify_ldt_t)); -+ if (!VG_(am_is_valid_for_client)(ARG_TLS, sizeof(vki_modify_ldt_t), -+ VKI_PROT_READ)) { -+ badarg = True; -+ } -+ } -+ } -+ if (ARG_FLAGS & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -+ if (VG_(tdict).track_pre_reg_read) { -+ PRA_CHILD_TIDPTR("clone", int *, child_tidptr); -+ } -+ PRE_MEM_WRITE("clone(child_tidptr)", ARG_CHILD_TIDPTR, sizeof(Int)); -+ if (!VG_(am_is_valid_for_client)(ARG_CHILD_TIDPTR, sizeof(Int), -+ VKI_PROT_WRITE)) { -+ badarg = True; -+ } -+ } -+ -+ if (badarg) { -+ SET_STATUS_Failure( VKI_EFAULT ); -+ return; -+ } -+ -+ cloneflags = ARG_FLAGS; -+ -+ if (!ML_(client_signal_OK)(ARG_FLAGS & VKI_CSIGNAL)) { -+ SET_STATUS_Failure( VKI_EINVAL ); -+ return; -+ } -+ -+ /* Only look at the flags we really care about */ -+ switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -+ | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -+ case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -+ /* thread creation */ -+ SET_STATUS_from_SysRes( -+ do_clone(tid, -+ ARG_FLAGS, /* flags */ -+ (Addr)ARG_CHILD_STACK, /* child ESP */ -+ (Int*)ARG3, /* parent_tidptr */ -+ (Int*)ARG_CHILD_TIDPTR, /* child_tidptr */ -+ (Addr)ARG_TLS)); /* set_tls */ -+ break; -+ -+ case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -+ // FALLTHROUGH - assume vfork (somewhat) == fork, see ML_(do_fork_clone). -+ cloneflags &= ~VKI_CLONE_VM; -+ -+ case 0: /* plain fork */ -+ SET_STATUS_from_SysRes( -+ ML_(do_fork_clone)(tid, -+ cloneflags, /* flags */ -+ (Int*)ARG3, /* parent_tidptr */ -+ (Int*)ARG_CHILD_TIDPTR, /* child_tidptr */ -+ (Addr)ARG_CHILD_STACK)); -+ break; -+ -+ default: -+ /* should we just ENOSYS? */ -+ VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG_FLAGS); -+ VG_(message)(Vg_UserMsg, "\n"); -+ VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -+ VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n"); -+ VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -+ VG_(unimplemented) -+ ("Valgrind does not support general clone()."); -+ } -+ -+ if (SUCCESS) { -+ if (ARG_FLAGS & VKI_CLONE_PARENT_SETTID) -+ POST_MEM_WRITE(ARG3, sizeof(Int)); -+ if (ARG_FLAGS & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -+ POST_MEM_WRITE(ARG_CHILD_TIDPTR, sizeof(Int)); -+ -+ /* Thread creation was successful; let the child have the chance -+ to run */ -+ *flags |= SfYieldAfter; -+ } -+ -+#undef ARG_CHILD_TIDPTR -+#undef PRA_CHILD_TIDPTR -+#undef ARG_TLS -+#undef PRA_TLS -+#undef ARG_FLAGS -+#undef PRA_FLAGS -+#undef ARG_CHILD_STACK -+#undef PRA_CHILD_STACK -+} -+ - /* --------------------------------------------------------------------- - *mount wrappers - ------------------------------------------------------------------ */ -diff --git a/coregrind/m_syswrap/syswrap-mips64-linux.c b/coregrind/m_syswrap/syswrap-mips64-linux.c -index 6e3db74..d3d70c5 100644 ---- a/coregrind/m_syswrap/syswrap-mips64-linux.c -+++ b/coregrind/m_syswrap/syswrap-mips64-linux.c -@@ -136,14 +136,7 @@ asm ( - #define __NR_CLONE __NR_clone - #define __NR_EXIT __NR_exit - --ULong do_syscall_clone_mips64_linux ( Word (*fn) (void *), /* a0 - 4 */ -- void* stack, /* a1 - 5 */ -- Int flags, /* a2 - 6 */ -- void* arg, /* a3 - 7 */ -- Int* parent_tid, /* a4 - 8 */ -- void* /* Int tls */, /* a5 - 9 */ -- Int* child_tid ); /* a6 - 10 */ -- -+// See priv_syswrap-linux.h for arg profile. - asm( - ".text\n" - ".set noreorder\n" -@@ -199,104 +192,13 @@ asm( - #undef __NR_EXIT - - /* forward declarations */ --static void setup_child ( ThreadArchState *, ThreadArchState *); - static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr); - --/* When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, but using -- the scheduler entrypoint for IP, and a separate stack for SP. */ --static SysRes do_clone ( ThreadId ptid, -- UInt flags, Addr sp, -- Int* parent_tidptr, -- Int* child_tidptr, -- Addr child_tls ) --{ -- const Bool debug = False; -- ThreadId ctid = VG_ (alloc_ThreadState) (); -- ThreadState * ptst = VG_ (get_ThreadState) (ptid); -- ThreadState * ctst = VG_ (get_ThreadState) (ctid); -- UInt ret = 0; -- UWord * stack; -- SysRes res; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- stack = (UWord *)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)(VKI_ENOMEM); -- goto out; -- } -- setup_child(&ctst->arch, &ptst->arch); -- -- /* on MIPS we need to set V0 and A3 to zero */ -- ctst->arch.vex.guest_r2 = 0; -- ctst->arch.vex.guest_r7 = 0; -- if (sp != 0) -- ctst->arch.vex.guest_r29 = sp; -- -- ctst->os_state.parent = ptid; -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (sp, ctst); -- -- VG_TRACK(pre_thread_ll_create, ptid, ctid); -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls); -- res = sys_set_tls(ctid, child_tls); -- if (sr_isError(res)) -- goto out; -- ctst->arch.vex.guest_r27 = child_tls; -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- VG_ (sigprocmask) (VKI_SIG_SETMASK, &blockall, &savedmask); -- /* Create the new thread */ -- ret = do_syscall_clone_mips64_linux(ML_(start_thread_NORETURN), -- stack, flags, &VG_(threads)[ctid], -- parent_tidptr, NULL /*child_tls*/, -- child_tidptr); -- if (debug) -- VG_(printf)("ret: 0x%x\n", ret); -- -- res = VG_(mk_SysRes_mips64_linux)( /* val */ ret, 0, /* errflag */ 0); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError (res)) { -- VG_ (cleanup_thread) (&ctst->arch); -- ctst->status = VgTs_Empty; -- VG_TRACK (pre_thread_ll_exit, ctid); -- } -- ptst->arch.vex.guest_r2 = 0; -- -- return res; --} -- - /* --------------------------------------------------------------------- - More thread stuff - ------------------------------------------------------------------ */ - void VG_(cleanup_thread) ( ThreadArchState * arch ) { }; - --void setup_child ( /* OUT */ ThreadArchState * child, -- /* IN */ ThreadArchState * parent ) --{ -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- - SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) - { - VG_(threads)[tid].arch.vex.guest_ULR = tlsptr; -@@ -316,7 +218,6 @@ SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) - file, but that requires even more macro magic. */ - - DECL_TEMPLATE (mips_linux, sys_set_thread_area); --DECL_TEMPLATE (mips_linux, sys_clone); - DECL_TEMPLATE (mips_linux, sys_tee); - DECL_TEMPLATE (mips_linux, sys_splice); - DECL_TEMPLATE (mips_linux, sys_vmsplice); -@@ -494,84 +395,6 @@ PRE(sys_mmap) - (Off64T) ARG6); - SET_STATUS_from_SysRes(r); - } -- --PRE(sys_clone) --{ -- Bool badarg = False; -- UInt cloneflags; -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )", ARG1, ARG2, ARG3, -- ARG4, ARG5); -- PRE_REG_READ2(int, "clone", unsigned long, flags, void *, child_stack); -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA3("clone", int *, parent_tidptr); -- } -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) { -- badarg = True; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA5("clone", int *, child_tidptr); -- } -- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof (Int)); -- if (!VG_(am_is_valid_for_client)(ARG5, sizeof (Int), VKI_PROT_WRITE)) -- badarg = True; -- } -- if (badarg) { -- SET_STATUS_Failure(VKI_EFAULT); -- return; -- } -- cloneflags = ARG1; -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure(VKI_EINVAL); -- return; -- } -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- |VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes(do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child SP */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5, /* child_tidptr */ -- (Addr)ARG4)); /* child_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes(ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, -- " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, -- " - via the implementation of fork or vfork\n"); -- VG_(unimplemented)("Valgrind does not support general clone()."); -- } -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG5, sizeof(Int)); -- /* Thread creation was successful; let the child have the chance to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_rt_sigreturn) - { - /* See comments on PRE(sys_rt_sigreturn) in syswrap-s390x-linux.c for -@@ -766,7 +589,7 @@ static SyscallTableEntry syscall_main_table[] = { - LINXY (__NR_socketpair, sys_socketpair), - LINX_ (__NR_setsockopt, sys_setsockopt), - LINXY (__NR_getsockopt, sys_getsockopt), -- PLAX_ (__NR_clone, sys_clone), -+ LINX_ (__NR_clone, sys_clone), - GENX_ (__NR_fork, sys_fork), - GENX_ (__NR_execve, sys_execve), - GENX_ (__NR_exit, sys_exit), -diff --git a/coregrind/m_syswrap/syswrap-ppc32-linux.c b/coregrind/m_syswrap/syswrap-ppc32-linux.c -index 379fcb3..a654a90 100644 ---- a/coregrind/m_syswrap/syswrap-ppc32-linux.c -+++ b/coregrind/m_syswrap/syswrap-ppc32-linux.c -@@ -146,14 +146,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --ULong do_syscall_clone_ppc32_linux ( Word (*fn)(void *), -- void* stack, -- Int flags, -- void* arg, -- Int* child_tid, -- Int* parent_tid, -- vki_modify_ldt_t * ); -+// See priv_syswrap-linux.h for arg profile. - asm( - ".text\n" - ".globl do_syscall_clone_ppc32_linux\n" -@@ -216,145 +209,6 @@ asm( - #undef __NR_CLONE - #undef __NR_EXIT - --// forward declarations --static void setup_child ( ThreadArchState*, ThreadArchState* ); -- --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for IP, and a separate stack -- for SP. -- */ --static SysRes do_clone ( ThreadId ptid, -- UInt flags, Addr sp, -- Int *parent_tidptr, -- Int *child_tidptr, -- Addr child_tls) --{ -- const Bool debug = False; -- -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- ULong word64; -- UWord* stack; -- SysRes res; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- --//? /* make a stack frame */ --//? stack -= 16; --//? *(UWord *)stack = 0; -- -- -- /* Copy register state -- -- Both parent and child return to the same place, and the code -- following the clone syscall works out which is which, so we -- don't need to worry about it. -- -- The parent gets the child's new tid returned from clone, but the -- child gets 0. -- -- If the clone call specifies a NULL SP for the new thread, then -- it actually gets a copy of the parent's SP. -- -- The child's TLS register (r2) gets set to the tlsaddr argument -- if the CLONE_SETTLS flag is set. -- */ -- setup_child( &ctst->arch, &ptst->arch ); -- -- /* Make sys_clone appear to have returned Success(0) in the -- child. */ -- { UInt old_cr = LibVEX_GuestPPC32_get_CR( &ctst->arch.vex ); -- /* %r3 = 0 */ -- ctst->arch.vex.guest_GPR3 = 0; -- /* %cr0.so = 0 */ -- LibVEX_GuestPPC32_put_CR( old_cr & ~(1<<28), &ctst->arch.vex ); -- } -- -- if (sp != 0) -- ctst->arch.vex.guest_GPR1 = sp; -- -- ctst->os_state.parent = ptid; -- -- /* inherit signal mask */ -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (sp, ctst); -- -- /* Assume the clone will succeed, and tell any tool that wants to -- know that this thread has come into existence. If the clone -- fails, we'll send out a ll_exit notification for it at the out: -- label below, to clean up. */ -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls); -- ctst->arch.vex.guest_GPR2 = child_tls; -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- -- /* start the thread with everything blocked */ -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- /* Create the new thread */ -- word64 = do_syscall_clone_ppc32_linux( -- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -- child_tidptr, parent_tidptr, NULL -- ); -- /* High half word64 is syscall return value. Low half is -- the entire CR, from which we need to extract CR0.SO. */ -- /* VG_(printf)("word64 = 0x%llx\n", word64); */ -- res = VG_(mk_SysRes_ppc32_linux)( -- /*val*/(UInt)(word64 >> 32), -- /*errflag*/ (((UInt)word64) >> 28) & 1 -- ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError(res)) { -- /* clone failed */ -- VG_(cleanup_thread)(&ctst->arch); -- ctst->status = VgTs_Empty; -- /* oops. Better tell the tool the thread exited in a hurry :-) */ -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; --} -- -- - - /* --------------------------------------------------------------------- - More thread stuff -@@ -364,16 +218,6 @@ void VG_(cleanup_thread) ( ThreadArchState* arch ) - { - } - --void setup_child ( /*OUT*/ ThreadArchState *child, -- /*IN*/ ThreadArchState *parent ) --{ -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- -- - /* --------------------------------------------------------------------- - PRE/POST wrappers for ppc32/Linux-specific syscalls - ------------------------------------------------------------------ */ -@@ -393,7 +237,6 @@ DECL_TEMPLATE(ppc32_linux, sys_stat64); - DECL_TEMPLATE(ppc32_linux, sys_lstat64); - DECL_TEMPLATE(ppc32_linux, sys_fstatat64); - DECL_TEMPLATE(ppc32_linux, sys_fstat64); --DECL_TEMPLATE(ppc32_linux, sys_clone); - DECL_TEMPLATE(ppc32_linux, sys_sigreturn); - DECL_TEMPLATE(ppc32_linux, sys_rt_sigreturn); - DECL_TEMPLATE(ppc32_linux, sys_sigsuspend); -@@ -530,91 +373,6 @@ POST(sys_fstat64) - //.. } - //.. } - --PRE(sys_clone) --{ -- UInt cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ5(int, "clone", -- unsigned long, flags, -- void *, child_stack, -- int *, parent_tidptr, -- void *, child_tls, -- int *, child_tidptr); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child SP */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5, /* child_tidptr */ -- (Addr)ARG4)); /* child_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG5, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_sigreturn) - { - /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -@@ -999,7 +757,7 @@ static SyscallTableEntry syscall_table[] = { - GENX_(__NR_fsync, sys_fsync), // 118 - PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux - //.. -- PLAX_(__NR_clone, sys_clone), // 120 -+ LINX_(__NR_clone, sys_clone), // 120 - //.. // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) - GENXY(__NR_uname, sys_newuname), // 122 - //.. PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c -index 1ae4454..f90140d 100644 ---- a/coregrind/m_syswrap/syswrap-ppc64-linux.c -+++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c -@@ -209,14 +209,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --ULong do_syscall_clone_ppc64_linux ( Word (*fn)(void *), -- void* stack, -- Int flags, -- void* arg, -- Int* child_tid, -- Int* parent_tid, -- void/*vki_modify_ldt_t*/ * ); -+// See priv_syswrap-linux.h for arg profile. - asm( - #if defined(VGP_ppc64be_linux) - " .align 2\n" -@@ -366,148 +359,6 @@ asm( - #undef __NR_CLONE - #undef __NR_EXIT - --// forward declarations --static void setup_child ( ThreadArchState*, ThreadArchState* ); -- --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for IP, and a separate stack -- for SP. -- */ --static SysRes do_clone ( ThreadId ptid, -- UInt flags, Addr sp, -- Int *parent_tidptr, -- Int *child_tidptr, -- Addr child_tls) --{ -- const Bool debug = False; -- -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- ULong word64; -- UWord* stack; -- SysRes res; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- --//? /* make a stack frame */ --//? stack -= 16; --//? *(UWord *)stack = 0; -- -- -- /* Copy register state -- -- Both parent and child return to the same place, and the code -- following the clone syscall works out which is which, so we -- don't need to worry about it. -- -- The parent gets the child's new tid returned from clone, but the -- child gets 0. -- -- If the clone call specifies a NULL SP for the new thread, then -- it actually gets a copy of the parent's SP. -- -- The child's TLS register (r2) gets set to the tlsaddr argument -- if the CLONE_SETTLS flag is set. -- */ -- setup_child( &ctst->arch, &ptst->arch ); -- -- /* Make sys_clone appear to have returned Success(0) in the -- child. */ -- { UInt old_cr = LibVEX_GuestPPC64_get_CR( &ctst->arch.vex ); -- /* %r3 = 0 */ -- ctst->arch.vex.guest_GPR3 = 0; -- /* %cr0.so = 0 */ -- LibVEX_GuestPPC64_put_CR( old_cr & ~(1<<28), &ctst->arch.vex ); -- } -- -- if (sp != 0) -- ctst->arch.vex.guest_GPR1 = sp; -- -- ctst->os_state.parent = ptid; -- -- /* inherit signal mask */ -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (sp, ctst); -- -- /* Assume the clone will succeed, and tell any tool that wants to -- know that this thread has come into existence. If the clone -- fails, we'll send out a ll_exit notification for it at the out: -- label below, to clean up. */ -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls); -- ctst->arch.vex.guest_GPR13 = child_tls; -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- -- /* start the thread with everything blocked */ -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- /* Create the new thread */ -- word64 = do_syscall_clone_ppc64_linux( -- ML_(start_thread_NORETURN), -- stack, flags, &VG_(threads)[ctid], -- child_tidptr, parent_tidptr, NULL -- ); -- -- /* Low half word64 is syscall return value. Hi half is -- the entire CR, from which we need to extract CR0.SO. */ -- /* VG_(printf)("word64 = 0x%llx\n", word64); */ -- res = VG_(mk_SysRes_ppc64_linux)( -- /*val*/(UInt)(word64 & 0xFFFFFFFFULL), -- /*errflag*/ (UInt)((word64 >> (32+28)) & 1) -- ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError(res)) { -- /* clone failed */ -- VG_(cleanup_thread)(&ctst->arch); -- ctst->status = VgTs_Empty; -- /* oops. Better tell the tool the thread exited in a hurry :-) */ -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; --} -- -- -- - /* --------------------------------------------------------------------- - More thread stuff - ------------------------------------------------------------------ */ -@@ -516,16 +367,6 @@ void VG_(cleanup_thread) ( ThreadArchState* arch ) - { - } - --void setup_child ( /*OUT*/ ThreadArchState *child, -- /*IN*/ ThreadArchState *parent ) --{ -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- -- - /* --------------------------------------------------------------------- - PRE/POST wrappers for ppc64/Linux-specific syscalls - ------------------------------------------------------------------ */ -@@ -544,7 +385,6 @@ DECL_TEMPLATE(ppc64_linux, sys_mmap); - //zz DECL_TEMPLATE(ppc64_linux, sys_stat64); - //zz DECL_TEMPLATE(ppc64_linux, sys_lstat64); - //zz DECL_TEMPLATE(ppc64_linux, sys_fstat64); --DECL_TEMPLATE(ppc64_linux, sys_clone); - //zz DECL_TEMPLATE(ppc64_linux, sys_sigreturn); - DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn); - DECL_TEMPLATE(ppc64_linux, sys_fadvise64); -@@ -629,92 +469,6 @@ PRE(sys_mmap) - //zz POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); - //zz } - -- --PRE(sys_clone) --{ -- UInt cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ5(int, "clone", -- unsigned long, flags, -- void *, child_stack, -- int *, parent_tidptr, -- void *, child_tls, -- int *, child_tidptr); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child SP */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5, /* child_tidptr */ -- (Addr)ARG4)); /* child_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG5, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_fadvise64) - { - PRINT("sys_fadvise64 ( %ld, %ld, %lu, %ld )", SARG1, SARG2, SARG3, SARG4); -@@ -922,7 +676,7 @@ static SyscallTableEntry syscall_table[] = { - GENX_(__NR_fsync, sys_fsync), // 118 - // _____(__NR_sigreturn, sys_sigreturn), // 119 - -- PLAX_(__NR_clone, sys_clone), // 120 -+ LINX_(__NR_clone, sys_clone), // 120 - // _____(__NR_setdomainname, sys_setdomainname), // 121 - GENXY(__NR_uname, sys_newuname), // 122 - // _____(__NR_modify_ldt, sys_modify_ldt), // 123 -diff --git a/coregrind/m_syswrap/syswrap-s390x-linux.c b/coregrind/m_syswrap/syswrap-s390x-linux.c -index ebb8295..f596341 100644 ---- a/coregrind/m_syswrap/syswrap-s390x-linux.c -+++ b/coregrind/m_syswrap/syswrap-s390x-linux.c -@@ -138,14 +138,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --ULong do_syscall_clone_s390x_linux ( void *stack, -- ULong flags, -- Int *parent_tid, -- Int *child_tid, -- Addr tlsaddr, -- Word (*fn)(void *), -- void *arg); -+// See priv_syswrap-linux.h for arg profile. - asm( - " .text\n" - " .align 4\n" -@@ -182,126 +175,6 @@ void VG_(cleanup_thread) ( ThreadArchState* arch ) - /* only used on x86 for descriptor tables */ - } - --static void setup_child ( /*OUT*/ ThreadArchState *child, -- /*IN*/ ThreadArchState *parent ) --{ -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- -- --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for IP, and a separate stack -- for SP. -- */ --static SysRes do_clone ( ThreadId ptid, -- Addr sp, ULong flags, -- Int *parent_tidptr, -- Int *child_tidptr, -- Addr tlsaddr) --{ -- static const Bool debug = False; -- -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- UWord* stack; -- SysRes res; -- ULong r2; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- -- /* Copy register state -- -- Both parent and child return to the same place, and the code -- following the clone syscall works out which is which, so we -- don't need to worry about it. -- -- The parent gets the child's new tid returned from clone, but the -- child gets 0. -- -- If the clone call specifies a NULL sp for the new thread, then -- it actually gets a copy of the parent's sp. -- */ -- setup_child( &ctst->arch, &ptst->arch ); -- -- /* Make sys_clone appear to have returned Success(0) in the -- child. */ -- ctst->arch.vex.guest_r2 = 0; -- -- if (sp != 0) -- ctst->arch.vex.guest_SP = sp; -- -- ctst->os_state.parent = ptid; -- -- /* inherit signal mask */ -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* have the parents thread group */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (sp, ctst); -- -- /* Assume the clone will succeed, and tell any tool that wants to -- know that this thread has come into existence. If the clone -- fails, we'll send out a ll_exit notification for it at the out: -- label below, to clean up. */ -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls at %#lx\n", tlsaddr); -- ctst->arch.vex.guest_a0 = (UInt) (tlsaddr >> 32); -- ctst->arch.vex.guest_a1 = (UInt) tlsaddr; -- } -- flags &= ~VKI_CLONE_SETTLS; -- -- /* start the thread with everything blocked */ -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- /* Create the new thread */ -- r2 = do_syscall_clone_s390x_linux( -- stack, flags, parent_tidptr, child_tidptr, tlsaddr, -- ML_(start_thread_NORETURN), &VG_(threads)[ctid]); -- -- res = VG_(mk_SysRes_s390x_linux)( r2 ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError(res)) { -- /* clone failed */ -- ctst->status = VgTs_Empty; -- /* oops. Better tell the tool the thread exited in a hurry :-) */ -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; -- --} -- -- -- - /* --------------------------------------------------------------------- - PRE/POST wrappers for s390x/Linux-specific syscalls - ------------------------------------------------------------------ */ -@@ -317,7 +190,6 @@ static SysRes do_clone ( ThreadId ptid, - - DECL_TEMPLATE(s390x_linux, sys_ptrace); - DECL_TEMPLATE(s390x_linux, sys_mmap); --DECL_TEMPLATE(s390x_linux, sys_clone); - DECL_TEMPLATE(s390x_linux, sys_sigreturn); - DECL_TEMPLATE(s390x_linux, sys_rt_sigreturn); - DECL_TEMPLATE(s390x_linux, sys_fadvise64); -@@ -452,99 +324,6 @@ PRE(sys_mmap) - SET_STATUS_from_SysRes(r); - } - --PRE(sys_clone) --{ -- UInt cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4, ARG5); -- PRE_REG_READ2(int, "clone", -- void *, child_stack, -- unsigned long, flags); -- -- if (ARG2 & VKI_CLONE_PARENT_SETTID) { -- if (VG_(tdict).track_pre_reg_read) -- PRA3("clone(parent_tidptr)", int *, parent_tidptr); -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG2 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- if (VG_(tdict).track_pre_reg_read) -- PRA4("clone(child_tidptr)", int *, child_tidptr); -- PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int), -- VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- /* The kernel simply copies reg6 (ARG5) into AR0 and AR1, no checks */ -- if (ARG2 & VKI_CLONE_SETTLS) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA5("clone", Addr, tlsinfo); -- } -- } -- -- cloneflags = ARG2; -- -- if (!ML_(client_signal_OK)(ARG2 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- (Addr)ARG1, /* child SP */ -- ARG2, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG4, /* child_tidptr */ -- (Addr)ARG5)); /* tlsaddr */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG4)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG2); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, " - via a threads library (NPTL)\n"); -- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG2 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG2 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG4, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_sigreturn) - { - ThreadState* tst; -@@ -775,7 +554,7 @@ static SyscallTableEntry syscall_table[] = { - GENX_(__NR_fsync, sys_fsync), // 118 - PLAX_(__NR_sigreturn, sys_sigreturn), // 119 - -- PLAX_(__NR_clone, sys_clone), // 120 -+ LINX_(__NR_clone, sys_clone), // 120 - // ?????(__NR_setdomainname, ), // 121 - GENXY(__NR_uname, sys_newuname), // 122 - GENX_(123, sys_ni_syscall), /* unimplemented (by the kernel) */ // 123 -diff --git a/coregrind/m_syswrap/syswrap-tilegx-linux.c b/coregrind/m_syswrap/syswrap-tilegx-linux.c -index 7501b20..05d81e8 100644 ---- a/coregrind/m_syswrap/syswrap-tilegx-linux.c -+++ b/coregrind/m_syswrap/syswrap-tilegx-linux.c -@@ -224,14 +224,7 @@ void ML_(call_on_new_stack_0_1) (Addr stack, Addr retaddr, - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --Long do_syscall_clone_tilegx_linux ( Word (*fn) (void *), //r0 -- void *stack, //r1 -- Long flags, //r2 -- void *arg, //r3 -- Long * child_tid, //r4 -- Long * parent_tid, //r5 -- Long tls ); //r6 -- /* -+ /* - stack - high -> 4 r29 - 3 -@@ -239,6 +232,7 @@ Long do_syscall_clone_tilegx_linux ( Word (*fn) (void *), //r0 - 1 r10 - low -> 0 lr <- sp - */ -+// See priv_syswrap-linux.h for arg profile. - asm ( - ".text\n" - " .globl do_syscall_clone_tilegx_linux\n" -@@ -315,101 +309,6 @@ Long do_syscall_clone_tilegx_linux ( Word (*fn) (void *), //r0 - #undef __NR_EXIT - - // forward declarations --static void setup_child ( ThreadArchState *, ThreadArchState * ); --static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ); -- /* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- 2. initialize the thread's new VCPU state -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for IP, and a separate stack -- for SP. -- */ --static SysRes do_clone ( ThreadId ptid, -- Long flags, Addr sp, -- Long * parent_tidptr, -- Long * child_tidptr, -- Addr child_tls ) --{ -- const Bool debug = False; -- ThreadId ctid = VG_ (alloc_ThreadState) (); -- ThreadState * ptst = VG_ (get_ThreadState) (ptid); -- ThreadState * ctst = VG_ (get_ThreadState) (ctid); -- Long ret = 0; -- Long * stack; -- SysRes res; -- vki_sigset_t blockall, savedmask; -- -- VG_ (sigfillset) (&blockall); -- vg_assert (VG_ (is_running_thread) (ptid)); -- vg_assert (VG_ (is_valid_tid) (ctid)); -- stack = (Long *) ML_ (allocstack) (ctid); -- if (stack == NULL) { -- res = VG_ (mk_SysRes_Error) (VKI_ENOMEM); -- goto out; -- } -- setup_child (&ctst->arch, &ptst->arch); -- -- /* On TILEGX we need to set r0 and r3 to zero */ -- ctst->arch.vex.guest_r0 = 0; -- ctst->arch.vex.guest_r3 = 0; -- if (sp != 0) -- ctst->arch.vex.guest_r54 = sp; -- -- ctst->os_state.parent = ptid; -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- ML_(guess_and_register_stack) (sp, ctst); -- -- VG_TRACK (pre_thread_ll_create, ptid, ctid); -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls); -- ctst->arch.vex.guest_r53 = child_tls; -- res = sys_set_tls(ctid, child_tls); -- if (sr_isError(res)) -- goto out; -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- VG_ (sigprocmask) (VKI_SIG_SETMASK, &blockall, &savedmask); -- /* Create the new thread */ -- ret = do_syscall_clone_tilegx_linux (ML_ (start_thread_NORETURN), -- stack, flags, &VG_ (threads)[ctid], -- child_tidptr, parent_tidptr, -- (Long)NULL /*child_tls*/); -- -- /* High half word64 is syscall return value. */ -- if (debug) -- VG_(printf)("ret: 0x%llx\n", (ULong)ret); -- -- res = VG_(mk_SysRes_tilegx_linux) (/*val */ ret); -- -- VG_ (sigprocmask) (VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError (res)) { -- VG_(cleanup_thread) (&ctst->arch); -- ctst->status = VgTs_Empty; -- VG_TRACK (pre_thread_ll_exit, ctid); -- } -- ptst->arch.vex.guest_r0 = 0; -- -- return res; --} -- - extern Addr do_brk ( Addr newbrk ); - - extern -@@ -428,23 +327,6 @@ extern Bool linux_kernel_2_6_22(void); - void - VG_ (cleanup_thread) ( ThreadArchState * arch ) { } - --void --setup_child ( /*OUT*/ ThreadArchState * child, -- /*IN*/ ThreadArchState * parent ) --{ -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; --} -- --SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) --{ -- VG_(threads)[tid].arch.vex.guest_r53 = tlsptr; -- return VG_(mk_SysRes_Success)( 0 ); --} -- -- - /* --------------------------------------------------------------------- - PRE/POST wrappers for tilegx/Linux-specific syscalls - ------------------------------------------------------------------ */ -@@ -457,7 +339,6 @@ SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) - aren't visible outside this file, but that requires even more macro - magic. */ - --DECL_TEMPLATE (tilegx_linux, sys_clone); - DECL_TEMPLATE (tilegx_linux, sys_rt_sigreturn); - DECL_TEMPLATE (tilegx_linux, sys_socket); - DECL_TEMPLATE (tilegx_linux, sys_setsockopt); -@@ -496,94 +377,6 @@ DECL_TEMPLATE (tilegx_linux, sys_syscall184); - DECL_TEMPLATE (tilegx_linux, sys_cacheflush); - DECL_TEMPLATE (tilegx_linux, sys_set_dataplane); - --PRE(sys_clone) --{ -- ULong cloneflags; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ5(int, "clone", -- unsigned long, flags, -- void *, child_stack, -- int *, parent_tidptr, -- int *, child_tidptr, -- void *, tlsaddr); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int), VKI_PROT_WRITE)) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child ESP */ -- (Long *)ARG3, /* parent_tidptr */ -- (Long *)ARG4, /* child_tidptr */ -- (Addr)ARG5)); /* set_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG4)); /* child_tidptr */ -- break; -- -- default: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, -- "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, -- "\n"); -- VG_(message)(Vg_UserMsg, -- "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, -- " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, -- " - via the implementation of fork or vfork\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG4, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_rt_sigreturn) - { - /* This isn't really a syscall at all - it's a misuse of the -@@ -1344,7 +1137,7 @@ static SyscallTableEntry syscall_table[] = { - LINX_(__NR_add_key, sys_add_key), // 217 - LINX_(__NR_request_key, sys_request_key), // 218 - LINXY(__NR_keyctl, sys_keyctl), // 219 -- PLAX_(__NR_clone, sys_clone), // 220 -+ LINX_(__NR_clone, sys_clone), // 220 - GENX_(__NR_execve, sys_execve), // 221 - PLAX_(__NR_mmap, sys_mmap), // 222 - GENXY(__NR_mprotect, sys_mprotect), // 226 -diff --git a/coregrind/m_syswrap/syswrap-x86-linux.c b/coregrind/m_syswrap/syswrap-x86-linux.c -index 0e5af98..f8c4eb4 100644 ---- a/coregrind/m_syswrap/syswrap-x86-linux.c -+++ b/coregrind/m_syswrap/syswrap-x86-linux.c -@@ -131,14 +131,7 @@ asm( - #define __NR_CLONE VG_STRINGIFY(__NR_clone) - #define __NR_EXIT VG_STRINGIFY(__NR_exit) - --extern --Int do_syscall_clone_x86_linux ( Word (*fn)(void *), -- void* stack, -- Int flags, -- void* arg, -- Int* child_tid, -- Int* parent_tid, -- vki_modify_ldt_t * ); -+// See priv_syswrap-linux.h for arg profile. - asm( - ".text\n" - ".globl do_syscall_clone_x86_linux\n" -@@ -191,141 +184,6 @@ asm( - #undef __NR_EXIT - - --// forward declarations --static void setup_child ( ThreadArchState*, ThreadArchState*, Bool ); --static SysRes sys_set_thread_area ( ThreadId, vki_modify_ldt_t* ); -- --/* -- When a client clones, we need to keep track of the new thread. This means: -- 1. allocate a ThreadId+ThreadState+stack for the thread -- -- 2. initialize the thread's new VCPU state -- -- 3. create the thread using the same args as the client requested, -- but using the scheduler entrypoint for EIP, and a separate stack -- for ESP. -- */ --static SysRes do_clone ( ThreadId ptid, -- UInt flags, Addr esp, -- Int* parent_tidptr, -- Int* child_tidptr, -- vki_modify_ldt_t *tlsinfo) --{ -- static const Bool debug = False; -- -- ThreadId ctid = VG_(alloc_ThreadState)(); -- ThreadState* ptst = VG_(get_ThreadState)(ptid); -- ThreadState* ctst = VG_(get_ThreadState)(ctid); -- UWord* stack; -- SysRes res; -- Int eax; -- vki_sigset_t blockall, savedmask; -- -- VG_(sigfillset)(&blockall); -- -- vg_assert(VG_(is_running_thread)(ptid)); -- vg_assert(VG_(is_valid_tid)(ctid)); -- -- stack = (UWord*)ML_(allocstack)(ctid); -- if (stack == NULL) { -- res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -- goto out; -- } -- -- /* Copy register state -- -- Both parent and child return to the same place, and the code -- following the clone syscall works out which is which, so we -- don't need to worry about it. -- -- The parent gets the child's new tid returned from clone, but the -- child gets 0. -- -- If the clone call specifies a NULL esp for the new thread, then -- it actually gets a copy of the parent's esp. -- */ -- /* Note: the clone call done by the Quadrics Elan3 driver specifies -- clone flags of 0xF00, and it seems to rely on the assumption -- that the child inherits a copy of the parent's GDT. -- setup_child takes care of setting that up. */ -- setup_child( &ctst->arch, &ptst->arch, True ); -- -- /* Make sys_clone appear to have returned Success(0) in the -- child. */ -- ctst->arch.vex.guest_EAX = 0; -- -- if (esp != 0) -- ctst->arch.vex.guest_ESP = esp; -- -- ctst->os_state.parent = ptid; -- -- /* inherit signal mask */ -- ctst->sig_mask = ptst->sig_mask; -- ctst->tmp_sig_mask = ptst->sig_mask; -- -- /* Start the child with its threadgroup being the same as the -- parent's. This is so that any exit_group calls that happen -- after the child is created but before it sets its -- os_state.threadgroup field for real (in thread_wrapper in -- syswrap-linux.c), really kill the new thread. a.k.a this avoids -- a race condition in which the thread is unkillable (via -- exit_group) because its threadgroup is not set. The race window -- is probably only a few hundred or a few thousand cycles long. -- See #226116. */ -- ctst->os_state.threadgroup = ptst->os_state.threadgroup; -- -- ML_(guess_and_register_stack) (esp, ctst); -- -- /* Assume the clone will succeed, and tell any tool that wants to -- know that this thread has come into existence. We cannot defer -- it beyond this point because sys_set_thread_area, just below, -- causes tCheck to assert by making references to the new ThreadId -- if we don't state the new thread exists prior to that point. -- If the clone fails, we'll send out a ll_exit notification for it -- at the out: label below, to clean up. */ -- vg_assert(VG_(owns_BigLock_LL)(ptid)); -- VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -- -- if (flags & VKI_CLONE_SETTLS) { -- if (debug) -- VG_(printf)("clone child has SETTLS: tls info at %p: idx=%u " -- "base=%#lx limit=%x; esp=%#x fs=%x gs=%x\n", -- tlsinfo, tlsinfo->entry_number, -- tlsinfo->base_addr, tlsinfo->limit, -- ptst->arch.vex.guest_ESP, -- ctst->arch.vex.guest_FS, ctst->arch.vex.guest_GS); -- res = sys_set_thread_area(ctid, tlsinfo); -- if (sr_isError(res)) -- goto out; -- } -- -- flags &= ~VKI_CLONE_SETTLS; -- -- /* start the thread with everything blocked */ -- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -- -- /* Create the new thread */ -- eax = do_syscall_clone_x86_linux( -- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -- child_tidptr, parent_tidptr, NULL -- ); -- res = VG_(mk_SysRes_x86_linux)( eax ); -- -- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -- -- out: -- if (sr_isError(res)) { -- /* clone failed */ -- VG_(cleanup_thread)(&ctst->arch); -- ctst->status = VgTs_Empty; -- /* oops. Better tell the tool the thread exited in a hurry :-) */ -- VG_TRACK( pre_thread_ll_exit, ctid ); -- } -- -- return res; --} -- -- - /* --------------------------------------------------------------------- - LDT/GDT simulation - ------------------------------------------------------------------ */ -@@ -630,7 +488,7 @@ static SysRes sys_modify_ldt ( ThreadId tid, - } - - --static SysRes sys_set_thread_area ( ThreadId tid, vki_modify_ldt_t* info ) -+SysRes ML_(x86_sys_set_thread_area) ( ThreadId tid, vki_modify_ldt_t* info ) - { - Int idx; - VexGuestX86SegDescr* gdt; -@@ -738,15 +596,9 @@ void VG_(cleanup_thread) ( ThreadArchState* arch ) - } - - --static void setup_child ( /*OUT*/ ThreadArchState *child, -- /*IN*/ ThreadArchState *parent, -- Bool inherit_parents_GDT ) -+void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child, -+ /*IN*/ ThreadArchState *parent ) - { -- /* We inherit our parent's guest state. */ -- child->vex = parent->vex; -- child->vex_shadow1 = parent->vex_shadow1; -- child->vex_shadow2 = parent->vex_shadow2; -- - /* We inherit our parent's LDT. */ - if (parent->vex.guest_LDT == (HWord)NULL) { - /* We hope this is the common case. */ -@@ -763,7 +615,7 @@ static void setup_child ( /*OUT*/ ThreadArchState *child, - only). */ - child->vex.guest_GDT = (HWord)NULL; - -- if (inherit_parents_GDT && parent->vex.guest_GDT != (HWord)NULL) { -+ if (parent->vex.guest_GDT != (HWord)NULL) { - child->vex.guest_GDT = (HWord)alloc_zeroed_x86_GDT(); - copy_GDT_from_to( (VexGuestX86SegDescr*)parent->vex.guest_GDT, - (VexGuestX86SegDescr*)child->vex.guest_GDT ); -@@ -787,7 +639,6 @@ DECL_TEMPLATE(x86_linux, sys_stat64); - DECL_TEMPLATE(x86_linux, sys_fstatat64); - DECL_TEMPLATE(x86_linux, sys_fstat64); - DECL_TEMPLATE(x86_linux, sys_lstat64); --DECL_TEMPLATE(x86_linux, sys_clone); - DECL_TEMPLATE(x86_linux, old_mmap); - DECL_TEMPLATE(x86_linux, sys_mmap2); - DECL_TEMPLATE(x86_linux, sys_sigreturn); -@@ -835,137 +686,6 @@ PRE(old_select) - } - } - --PRE(sys_clone) --{ -- UInt cloneflags; -- Bool badarg = False; -- -- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -- PRE_REG_READ2(int, "clone", -- unsigned long, flags, -- void *, child_stack); -- -- if (ARG1 & VKI_CLONE_PARENT_SETTID) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA3("clone", int *, parent_tidptr); -- } -- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -- VKI_PROT_WRITE)) { -- badarg = True; -- } -- } -- if (ARG1 & VKI_CLONE_SETTLS) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA4("clone", vki_modify_ldt_t *, tlsinfo); -- } -- PRE_MEM_READ("clone(tlsinfo)", ARG4, sizeof(vki_modify_ldt_t)); -- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), -- VKI_PROT_READ)) { -- badarg = True; -- } -- } -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -- if (VG_(tdict).track_pre_reg_read) { -- PRA5("clone", int *, child_tidptr); -- } -- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -- VKI_PROT_WRITE)) { -- badarg = True; -- } -- } -- -- if (badarg) { -- SET_STATUS_Failure( VKI_EFAULT ); -- return; -- } -- -- cloneflags = ARG1; -- -- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -- SET_STATUS_Failure( VKI_EINVAL ); -- return; -- } -- -- /* Be ultra-paranoid and filter out any clone-variants we don't understand: -- - ??? specifies clone flags of 0x100011 -- - ??? specifies clone flags of 0x1200011. -- - NPTL specifies clone flags of 0x7D0F00. -- - The Quadrics Elan3 driver specifies clone flags of 0xF00. -- - Newer Quadrics Elan3 drivers with NTPL support specify 0x410F00. -- Everything else is rejected. -- */ -- if ( -- 1 || -- /* 11 Nov 05: for the time being, disable this ultra-paranoia. -- The switch below probably does a good enough job. */ -- (cloneflags == 0x100011 || cloneflags == 0x1200011 -- || cloneflags == 0x7D0F00 -- || cloneflags == 0x790F00 -- || cloneflags == 0x3D0F00 -- || cloneflags == 0x410F00 -- || cloneflags == 0xF00 -- || cloneflags == 0xF21)) { -- /* OK */ -- } -- else { -- /* Nah. We don't like it. Go away. */ -- goto reject; -- } -- -- /* Only look at the flags we really care about */ -- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -- /* thread creation */ -- SET_STATUS_from_SysRes( -- do_clone(tid, -- ARG1, /* flags */ -- (Addr)ARG2, /* child ESP */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5, /* child_tidptr */ -- (vki_modify_ldt_t *)ARG4)); /* set_tls */ -- break; -- -- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -- /* FALLTHROUGH - assume vfork == fork */ -- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -- -- case 0: /* plain fork */ -- SET_STATUS_from_SysRes( -- ML_(do_fork_clone)(tid, -- cloneflags, /* flags */ -- (Int *)ARG3, /* parent_tidptr */ -- (Int *)ARG5)); /* child_tidptr */ -- break; -- -- default: -- reject: -- /* should we just ENOSYS? */ -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1); -- VG_(message)(Vg_UserMsg, "\n"); -- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n"); -- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n"); -- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n"); -- VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver\n"); -- VG_(unimplemented) -- ("Valgrind does not support general clone()."); -- } -- -- if (SUCCESS) { -- if (ARG1 & VKI_CLONE_PARENT_SETTID) -- POST_MEM_WRITE(ARG3, sizeof(Int)); -- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -- POST_MEM_WRITE(ARG5, sizeof(Int)); -- -- /* Thread creation was successful; let the child have the chance -- to run */ -- *flags |= SfYieldAfter; -- } --} -- - PRE(sys_sigreturn) - { - /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -@@ -1063,7 +783,7 @@ PRE(sys_set_thread_area) - PRE_MEM_READ( "set_thread_area(u_info)", ARG1, sizeof(vki_modify_ldt_t) ); - - /* "do" the syscall ourselves; the kernel never sees it */ -- SET_STATUS_from_SysRes( sys_set_thread_area( tid, (void *)ARG1 ) ); -+ SET_STATUS_from_SysRes( ML_(x86_sys_set_thread_area)( tid, (void *)ARG1 ) ); - } - - PRE(sys_get_thread_area) -@@ -1553,7 +1273,7 @@ static SyscallTableEntry syscall_table[] = { - GENX_(__NR_fsync, sys_fsync), // 118 - PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux - -- PLAX_(__NR_clone, sys_clone), // 120 -+ LINX_(__NR_clone, sys_clone), // 120 - //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) - GENXY(__NR_uname, sys_newuname), // 122 - PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -diff --git a/include/vki/vki-arm64-linux.h b/include/vki/vki-arm64-linux.h -index df34dd6..5a3b08f 100644 ---- a/include/vki/vki-arm64-linux.h -+++ b/include/vki/vki-arm64-linux.h -@@ -586,7 +586,8 @@ struct vki_ucontext { - //ZZ }; - //ZZ - //ZZ // [[Nb: for our convenience within Valgrind, use a more specific name]] --//ZZ typedef struct vki_user_desc vki_modify_ldt_t; -+ -+typedef char vki_modify_ldt_t; - - //---------------------------------------------------------------------- - // From linux-3.10.5/include/asm-generic/ipcbuf.h -diff --git a/include/vki/vki-mips32-linux.h b/include/vki/vki-mips32-linux.h -index 5be8e15..b6c9914 100644 ---- a/include/vki/vki-mips32-linux.h -+++ b/include/vki/vki-mips32-linux.h -@@ -679,7 +679,7 @@ struct vki_ucontext { - }; - - // CAB: TODO --typedef void vki_modify_ldt_t; -+typedef char vki_modify_ldt_t; - - //---------------------------------------------------------------------- - // From linux-2.6.35.5/include/asm-mips/ipcbuf.h -diff --git a/include/vki/vki-mips64-linux.h b/include/vki/vki-mips64-linux.h -index 26b8e9f..ca49b10 100644 ---- a/include/vki/vki-mips64-linux.h -+++ b/include/vki/vki-mips64-linux.h -@@ -710,6 +710,7 @@ struct vki_ucontext { - vki_sigset_t uc_sigmask; /* mask last for extensibility */ - }; - -+typedef char vki_modify_ldt_t; - //---------------------------------------------------------------------- - // From linux-2.6.35.9/include/asm-mips/ipcbuf.h - //---------------------------------------------------------------------- -diff --git a/include/vki/vki-ppc32-linux.h b/include/vki/vki-ppc32-linux.h -index 70c2835..0fd3c79 100644 ---- a/include/vki/vki-ppc32-linux.h -+++ b/include/vki/vki-ppc32-linux.h -@@ -811,10 +811,9 @@ struct vki_ucontext { - //.. }; - //.. - //.. // [[Nb: for our convenience within Valgrind, use a more specific name]] --//.. typedef struct vki_user_desc vki_modify_ldt_t; - - // CAB: TODO --typedef void vki_modify_ldt_t; -+typedef char vki_modify_ldt_t; - - - //---------------------------------------------------------------------- -diff --git a/include/vki/vki-ppc64-linux.h b/include/vki/vki-ppc64-linux.h -index b410663..fd5cea6 100644 ---- a/include/vki/vki-ppc64-linux.h -+++ b/include/vki/vki-ppc64-linux.h -@@ -685,6 +685,9 @@ struct vki_ucontext { - struct vki_sigcontext uc_mcontext; /* last for extensibility */ - }; - -+// CAB: TODO -+typedef char vki_modify_ldt_t; -+ - //---------------------------------------------------------------------- - // From linux-2.6.13/include/asm-ppc64/ipcbuf.h - //---------------------------------------------------------------------- -diff --git a/include/vki/vki-s390x-linux.h b/include/vki/vki-s390x-linux.h -index c3f6d00..1ef5cf7 100644 ---- a/include/vki/vki-s390x-linux.h -+++ b/include/vki/vki-s390x-linux.h -@@ -822,6 +822,8 @@ struct vki_ucontext { - vki_sigset_t uc_sigmask; /* mask last for extensibility */ - }; - -+typedef char vki_modify_ldt_t; -+ - //---------------------------------------------------------------------- - // From linux-2.6.16.60/include/asm-s390/ipcbuf.h - //---------------------------------------------------------------------- diff --git a/SOURCES/valgrind-3.12.0-deregister-stack.patch b/SOURCES/valgrind-3.12.0-deregister-stack.patch deleted file mode 100644 index 5fe4a11..0000000 --- a/SOURCES/valgrind-3.12.0-deregister-stack.patch +++ /dev/null @@ -1,111 +0,0 @@ -commit 2b49317b4f237ea5f648d8b958f96cd03fcabc7d -Author: philippe -Date: Mon Nov 28 19:34:06 2016 +0000 - - Fix 373046 - Stacks registered by core are never deregistered - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16159 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c -index 0363898..49f51d6 100644 ---- a/coregrind/m_scheduler/scheduler.c -+++ b/coregrind/m_scheduler/scheduler.c -@@ -488,6 +488,7 @@ static void os_state_clear(ThreadState *tst) - { - tst->os_state.lwpid = 0; - tst->os_state.threadgroup = 0; -+ tst->os_state.stk_id = NULL_STK_ID; - # if defined(VGO_linux) - /* no other fields to clear */ - # elif defined(VGO_darwin) -@@ -504,7 +505,6 @@ static void os_state_clear(ThreadState *tst) - # if defined(VGP_x86_solaris) - tst->os_state.thrptr = 0; - # endif -- tst->os_state.stk_id = (UWord)-1; - tst->os_state.ustack = NULL; - tst->os_state.in_door_return = False; - tst->os_state.door_return_procedure = 0; -diff --git a/coregrind/m_syswrap/syswrap-generic.c b/coregrind/m_syswrap/syswrap-generic.c -index 6ef6a90..28972ae 100644 ---- a/coregrind/m_syswrap/syswrap-generic.c -+++ b/coregrind/m_syswrap/syswrap-generic.c -@@ -84,11 +84,14 @@ void ML_(guess_and_register_stack) (Addr sp, ThreadState* tst) - tst->client_stack_highest_byte = (Addr)VG_PGROUNDUP(sp)-1; - tst->client_stack_szB = tst->client_stack_highest_byte - seg->start + 1; - -- VG_(register_stack)(seg->start, tst->client_stack_highest_byte); -+ tst->os_state.stk_id -+ = VG_(register_stack)(seg->start, tst->client_stack_highest_byte); - - if (debug) -- VG_(printf)("tid %u: guessed client stack range [%#lx-%#lx]\n", -- tst->tid, seg->start, tst->client_stack_highest_byte); -+ VG_(printf)("tid %u: guessed client stack range [%#lx-%#lx]" -+ " as stk_id %lu\n", -+ tst->tid, seg->start, tst->client_stack_highest_byte, -+ tst->os_state.stk_id); - } else { - VG_(message)(Vg_UserMsg, - "!? New thread %u starts with SP(%#lx) unmapped\n", -diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c -index af10b92..725ad78 100644 ---- a/coregrind/m_syswrap/syswrap-linux.c -+++ b/coregrind/m_syswrap/syswrap-linux.c -@@ -52,6 +52,7 @@ - #include "pub_core_options.h" - #include "pub_core_scheduler.h" - #include "pub_core_signals.h" -+#include "pub_core_stacks.h" - #include "pub_core_syscall.h" - #include "pub_core_syswrap.h" - #include "pub_core_inner.h" -@@ -162,6 +163,10 @@ static void run_a_thread_NORETURN ( Word tidW ) - c = VG_(count_living_threads)(); - vg_assert(c >= 1); /* stay sane */ - -+ /* Deregister thread's stack. */ -+ if (tst->os_state.stk_id != NULL_STK_ID) -+ VG_(deregister_stack)(tst->os_state.stk_id); -+ - // Tell the tool this thread is exiting - VG_TRACK( pre_thread_ll_exit, tid ); - -diff --git a/coregrind/pub_core_threadstate.h b/coregrind/pub_core_threadstate.h -index f3d956c..3307e75 100644 ---- a/coregrind/pub_core_threadstate.h -+++ b/coregrind/pub_core_threadstate.h -@@ -114,6 +114,8 @@ typedef - ThreadArchState; - - -+#define NULL_STK_ID (~(UWord)0) -+ - /* OS-specific thread state. IMPORTANT: if you add fields to this, - you _must_ add code to os_state_clear() to initialise those - fields. */ -@@ -129,6 +131,12 @@ typedef - Addr valgrind_stack_base; // Valgrind's stack (VgStack*) - Addr valgrind_stack_init_SP; // starting value for SP - -+ /* Client stack is registered as stk_id (on linux/darwin, by -+ ML_(guess_and_register_stack)). -+ Stack id NULL_STK_ID means that the user stack is not (yet) -+ registered. */ -+ UWord stk_id; -+ - /* exit details */ - Word exitcode; // in the case of exitgroup, set by someone else - Int fatalsig; // fatal signal -@@ -281,10 +289,6 @@ typedef - the 64-bit offset associated with a %fs value of zero. */ - # endif - -- /* Stack id (value (UWord)(-1) means that there is no stack). This -- tracks a stack that is set in restore_stack(). */ -- UWord stk_id; -- - /* Simulation of the kernel's lwp->lwp_ustack. Set in the PRE wrapper - of the getsetcontext syscall, for SETUSTACK. Used in - VG_(save_context)(), VG_(restore_context)() and diff --git a/SOURCES/valgrind-3.12.0-exit_group.patch b/SOURCES/valgrind-3.12.0-exit_group.patch deleted file mode 100644 index bd07d3f..0000000 --- a/SOURCES/valgrind-3.12.0-exit_group.patch +++ /dev/null @@ -1,52 +0,0 @@ -commit 18b3ffc1a8dc951d8a8cdb076e7e30aafc216571 -Author: philippe -Date: Sat Nov 19 14:54:44 2016 +0000 - - Fix 372504 Hanging on exit_group - - Note that it is unclear if the PRE syscall for rt_sigsuspend - is properly setting up a temporary mask in the thread state - tmp_sig_mask: if an handler is called while a thread is - calling sigsuspend, the mask during the handler run must be - the temporary mask set by sigsuspend. - It is not clear if/where the valgrind sigframe builder/handler - sets the tmp_sig_mask to the value as expected by the user - (i.e. the value of the temporary mask which was given to - the sigsuspend syscall) - - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16141 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c -index 1dcb95d..fda8dd1 100644 ---- a/coregrind/m_syswrap/syswrap-linux.c -+++ b/coregrind/m_syswrap/syswrap-linux.c -@@ -3558,6 +3558,12 @@ PRE(sys_rt_sigsuspend) - PRE_REG_READ2(int, "rt_sigsuspend", vki_sigset_t *, mask, vki_size_t, size) - if (ARG1 != (Addr)NULL) { - PRE_MEM_READ( "rt_sigsuspend(mask)", ARG1, sizeof(vki_sigset_t) ); -+ VG_(sigdelset)((vki_sigset_t*)ARG1, VG_SIGVGKILL); -+ /* We cannot mask VG_SIGVGKILL, as otherwise this thread would not -+ be killable by VG_(nuke_all_threads_except). -+ We thus silently ignore the user request to mask this signal. -+ Note that this is similar to what is done for e.g. -+ sigprocmask (see m_signals.c calculate_SKSS_from_SCSS). */ - } - } - -diff --git a/coregrind/pub_core_threadstate.h b/coregrind/pub_core_threadstate.h -index 861f233..f3d956c 100644 ---- a/coregrind/pub_core_threadstate.h -+++ b/coregrind/pub_core_threadstate.h -@@ -354,7 +354,9 @@ typedef struct { - different values is during the execution of a sigsuspend, where - tmp_sig_mask is the temporary mask which sigsuspend installs. - It is only consulted to compute the signal mask applied to a -- signal handler. */ -+ signal handler. -+ PW Nov 2016 : it is not clear if and where this tmp_sig_mask -+ is set when an handler runs "inside" a sigsuspend. */ - vki_sigset_t tmp_sig_mask; - - /* A little signal queue for signals we can't get the kernel to diff --git a/SOURCES/valgrind-3.12.0-helgrind-dl_allocate_tls-supp.patch b/SOURCES/valgrind-3.12.0-helgrind-dl_allocate_tls-supp.patch deleted file mode 100644 index 339a839..0000000 --- a/SOURCES/valgrind-3.12.0-helgrind-dl_allocate_tls-supp.patch +++ /dev/null @@ -1,47 +0,0 @@ -commit 4b00bfdd73a2cd56a4d9e8de0b249eed2a1b982f -Author: petarj -Date: Fri Feb 3 00:34:52 2017 +0000 - - add suppression for helgrind/tests/tc22_exit_w_lock - - Function pthread_create indirectly calls function memcpy. Helgrind - considers that memcpy is not thread safe function. For error reported - from pthread_create there is the suppression helgrind---_dl_allocate_tls - in the file glibc-2.34567-NPTL-helgrind.supp. - Since glibc version 2.23, memcpy is implemented by __mempcpy_inline. - This causes that call to memcpy from pthread_create is no longer - recognized by the suppression. - In test helgrind/tests/tc22_exit_w_lock, pthread_create is called twice, - and second call reports error, which causes failing of the test. - This patch adds suppression for glibc 2.23 and greater. - - Patch by Tamara Vlahovic. - - Related issue #375806. - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16219 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/glibc-2.34567-NPTL-helgrind.supp b/glibc-2.34567-NPTL-helgrind.supp -index ed105b8..7ebd2c4 100644 ---- a/glibc-2.34567-NPTL-helgrind.supp -+++ b/glibc-2.34567-NPTL-helgrind.supp -@@ -267,6 +267,18 @@ - fun:pthread_create@* - } - -+{ -+ helgrind---_dl_allocate_tls2 -+ Helgrind:Race -+ fun:memcpy -+ fun:__mempcpy_inline -+ fun:_dl_allocate_tls_init -+ ... -+ fun:pthread_create@@GLIBC_2.2* -+ fun:pthread_create_WRK -+ fun:pthread_create@* -+} -+ - #################################################### - # To do with GNU libgomp - # diff --git a/SOURCES/valgrind-3.12.0-ll-sc-fallback1.patch b/SOURCES/valgrind-3.12.0-ll-sc-fallback1.patch deleted file mode 100644 index 4b08704..0000000 --- a/SOURCES/valgrind-3.12.0-ll-sc-fallback1.patch +++ /dev/null @@ -1,611 +0,0 @@ -Only arm64. Removed the MIPS part. - -commit 6b72dc54b722af5f6a87ebe258d3da6bcba059b7 -Author: Julian Seward -Date: Mon Apr 24 09:23:43 2017 +0000 - - Bug 369459 - valgrind on arm64 violates the ARMv8 spec (ldxr/stxr) - - This implements a fallback LL/SC implementation as described in bug 344524. - - The fallback implementation is not enabled by default, and there is no - auto-detection for when it should be used. To use it, run with the - flag --sim-hints=fallback-llsc. This commit also allows the existing - MIPS fallback implementation to be enabled with that flag. - - VEX side changes: - - * priv/main_main.c, pub/libvex.h - - Adds new field guest__use_fallback_LLSC to VexAbiInfo - - * pub/libvex_guest_arm64.h priv/guest_arm64_toIR.c - - add front end support, new guest state fields - guest_LLSC_{SIZE,ADDR,DATA}, also documentation of the scheme - - * priv/guest_mips_toIR.c - - allow manual selection of fallback implementation via - --sim-hints=fallback-llsc - - * priv/host_arm64_defs.c priv/host_arm64_defs.h priv/host_arm64_isel.c - - Add support for generating CAS on arm64, as needed by the front end changes - - - - git-svn-id: svn://svn.valgrind.org/vex/trunk@3352 - -diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c -index 088af55..421db37 100644 ---- a/VEX/priv/guest_arm64_toIR.c -+++ b/VEX/priv/guest_arm64_toIR.c -@@ -1147,6 +1147,10 @@ static IRExpr* narrowFrom64 ( IRType dstTy, IRExpr* e ) - #define OFFB_CMSTART offsetof(VexGuestARM64State,guest_CMSTART) - #define OFFB_CMLEN offsetof(VexGuestARM64State,guest_CMLEN) - -+#define OFFB_LLSC_SIZE offsetof(VexGuestARM64State,guest_LLSC_SIZE) -+#define OFFB_LLSC_ADDR offsetof(VexGuestARM64State,guest_LLSC_ADDR) -+#define OFFB_LLSC_DATA offsetof(VexGuestARM64State,guest_LLSC_DATA) -+ - - /* ---------------- Integer registers ---------------- */ - -@@ -4702,7 +4706,9 @@ const HChar* nameArr_Q_SZ ( UInt bitQ, UInt size ) - - - static --Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn) -+Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, -+ const VexAbiInfo* abiinfo -+) - { - # define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) - -@@ -6457,6 +6463,32 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn) - sz 001000 000 s 0 11111 n t STX{R,RH,RB} Ws, Rt, [Xn|SP] - sz 001000 000 s 1 11111 n t STLX{R,RH,RB} Ws, Rt, [Xn|SP] - */ -+ /* For the "standard" implementation we pass through the LL and SC to -+ the host. For the "fallback" implementation, for details see -+ https://bugs.kde.org/show_bug.cgi?id=344524 and -+ https://bugs.kde.org/show_bug.cgi?id=369459, -+ but in short: -+ -+ LoadLinked(addr) -+ gs.LLsize = load_size // 1, 2, 4 or 8 -+ gs.LLaddr = addr -+ gs.LLdata = zeroExtend(*addr) -+ -+ StoreCond(addr, data) -+ tmp_LLsize = gs.LLsize -+ gs.LLsize = 0 // "no transaction" -+ if tmp_LLsize != store_size -> fail -+ if addr != gs.LLaddr -> fail -+ if zeroExtend(*addr) != gs.LLdata -> fail -+ cas_ok = CAS(store_size, addr, gs.LLdata -> data) -+ if !cas_ok -> fail -+ succeed -+ -+ When thread scheduled -+ gs.LLsize = 0 // "no transaction" -+ (coregrind/m_scheduler/scheduler.c, run_thread_for_a_while() -+ has to do this bit) -+ */ - if (INSN(29,23) == BITS7(0,0,1,0,0,0,0) - && (INSN(23,21) & BITS3(1,0,1)) == BITS3(0,0,0) - && INSN(14,10) == BITS5(1,1,1,1,1)) { -@@ -6478,29 +6510,99 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn) - - if (isLD && ss == BITS5(1,1,1,1,1)) { - IRTemp res = newTemp(ty); -- stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), NULL/*LL*/)); -- putIReg64orZR(tt, widenUto64(ty, mkexpr(res))); -+ if (abiinfo->guest__use_fallback_LLSC) { -+ // Do the load first so we don't update any guest state -+ // if it faults. -+ IRTemp loaded_data64 = newTemp(Ity_I64); -+ assign(loaded_data64, widenUto64(ty, loadLE(ty, mkexpr(ea)))); -+ stmt( IRStmt_Put( OFFB_LLSC_DATA, mkexpr(loaded_data64) )); -+ stmt( IRStmt_Put( OFFB_LLSC_ADDR, mkexpr(ea) )); -+ stmt( IRStmt_Put( OFFB_LLSC_SIZE, mkU64(szB) )); -+ putIReg64orZR(tt, mkexpr(loaded_data64)); -+ } else { -+ stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), NULL/*LL*/)); -+ putIReg64orZR(tt, widenUto64(ty, mkexpr(res))); -+ } - if (isAcqOrRel) { - stmt(IRStmt_MBE(Imbe_Fence)); - } -- DIP("ld%sx%s %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2], -- nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn)); -+ DIP("ld%sx%s %s, [%s] %s\n", isAcqOrRel ? "a" : "", suffix[szBlg2], -+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn), -+ abiinfo->guest__use_fallback_LLSC -+ ? "(fallback implementation)" : ""); - return True; - } - if (!isLD) { - if (isAcqOrRel) { - stmt(IRStmt_MBE(Imbe_Fence)); - } -- IRTemp res = newTemp(Ity_I1); - IRExpr* data = narrowFrom64(ty, getIReg64orZR(tt)); -- stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), data)); -- /* IR semantics: res is 1 if store succeeds, 0 if it fails. -- Need to set rS to 1 on failure, 0 on success. */ -- putIReg64orZR(ss, binop(Iop_Xor64, unop(Iop_1Uto64, mkexpr(res)), -- mkU64(1))); -- DIP("st%sx%s %s, %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2], -+ if (abiinfo->guest__use_fallback_LLSC) { -+ // This is really ugly, since we don't have any way to do -+ // proper if-then-else. First, set up as if the SC failed, -+ // and jump forwards if it really has failed. -+ -+ // Continuation address -+ IRConst* nia = IRConst_U64(guest_PC_curr_instr + 4); -+ -+ // "the SC failed". Any non-zero value means failure. -+ putIReg64orZR(ss, mkU64(1)); -+ -+ IRTemp tmp_LLsize = newTemp(Ity_I64); -+ assign(tmp_LLsize, IRExpr_Get(OFFB_LLSC_SIZE, Ity_I64)); -+ stmt( IRStmt_Put( OFFB_LLSC_SIZE, mkU64(0) // "no transaction" -+ )); -+ // Fail if no or wrong-size transaction -+ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); -+ stmt( IRStmt_Exit( -+ binop(Iop_CmpNE64, mkexpr(tmp_LLsize), mkU64(szB)), -+ Ijk_Boring, nia, OFFB_PC -+ )); -+ // Fail if the address doesn't match the LL address -+ stmt( IRStmt_Exit( -+ binop(Iop_CmpNE64, mkexpr(ea), -+ IRExpr_Get(OFFB_LLSC_ADDR, Ity_I64)), -+ Ijk_Boring, nia, OFFB_PC -+ )); -+ // Fail if the data doesn't match the LL data -+ IRTemp llsc_data64 = newTemp(Ity_I64); -+ assign(llsc_data64, IRExpr_Get(OFFB_LLSC_DATA, Ity_I64)); -+ stmt( IRStmt_Exit( -+ binop(Iop_CmpNE64, widenUto64(ty, loadLE(ty, mkexpr(ea))), -+ mkexpr(llsc_data64)), -+ Ijk_Boring, nia, OFFB_PC -+ )); -+ // Try to CAS the new value in. -+ IRTemp old = newTemp(ty); -+ IRTemp expd = newTemp(ty); -+ assign(expd, narrowFrom64(ty, mkexpr(llsc_data64))); -+ stmt( IRStmt_CAS(mkIRCAS(/*oldHi*/IRTemp_INVALID, old, -+ Iend_LE, mkexpr(ea), -+ /*expdHi*/NULL, mkexpr(expd), -+ /*dataHi*/NULL, data -+ ))); -+ // Fail if the CAS failed (viz, old != expd) -+ stmt( IRStmt_Exit( -+ binop(Iop_CmpNE64, -+ widenUto64(ty, mkexpr(old)), -+ widenUto64(ty, mkexpr(expd))), -+ Ijk_Boring, nia, OFFB_PC -+ )); -+ // Otherwise we succeeded (!) -+ putIReg64orZR(ss, mkU64(0)); -+ } else { -+ IRTemp res = newTemp(Ity_I1); -+ stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), data)); -+ /* IR semantics: res is 1 if store succeeds, 0 if it fails. -+ Need to set rS to 1 on failure, 0 on success. */ -+ putIReg64orZR(ss, binop(Iop_Xor64, unop(Iop_1Uto64, mkexpr(res)), -+ mkU64(1))); -+ } -+ DIP("st%sx%s %s, %s, [%s] %s\n", isAcqOrRel ? "a" : "", suffix[szBlg2], - nameIRegOrZR(False, ss), -- nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn)); -+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn), -+ abiinfo->guest__use_fallback_LLSC -+ ? "(fallback implementation)" : ""); - return True; - } - /* else fall through */ -@@ -6589,7 +6691,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn) - - static - Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn, -- const VexArchInfo* archinfo) -+ const VexArchInfo* archinfo, -+ const VexAbiInfo* abiinfo) - { - # define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) - -@@ -7048,7 +7151,11 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn, - /* AFAICS, this simply cancels a (all?) reservations made by a - (any?) preceding LDREX(es). Arrange to hand it through to - the back end. */ -- stmt( IRStmt_MBE(Imbe_CancelReservation) ); -+ if (abiinfo->guest__use_fallback_LLSC) { -+ stmt( IRStmt_Put( OFFB_LLSC_SIZE, mkU64(0) )); // "no transaction" -+ } else { -+ stmt( IRStmt_MBE(Imbe_CancelReservation) ); -+ } - DIP("clrex #%u\n", mm); - return True; - } -@@ -14411,12 +14518,12 @@ Bool disInstr_ARM64_WRK ( - break; - case BITS4(1,0,1,0): case BITS4(1,0,1,1): - // Branch, exception generation and system instructions -- ok = dis_ARM64_branch_etc(dres, insn, archinfo); -+ ok = dis_ARM64_branch_etc(dres, insn, archinfo, abiinfo); - break; - case BITS4(0,1,0,0): case BITS4(0,1,1,0): - case BITS4(1,1,0,0): case BITS4(1,1,1,0): - // Loads and stores -- ok = dis_ARM64_load_store(dres, insn); -+ ok = dis_ARM64_load_store(dres, insn, abiinfo); - break; - case BITS4(0,1,0,1): case BITS4(1,1,0,1): - // Data processing - register -diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c -index cc7c832..c9affbd 100644 ---- a/VEX/priv/host_arm64_defs.c -+++ b/VEX/priv/host_arm64_defs.c -@@ -1005,6 +1005,13 @@ ARM64Instr* ARM64Instr_StrEX ( Int szB ) { - vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); - return i; - } -+ARM64Instr* ARM64Instr_CAS ( Int szB ) { -+ ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr)); -+ i->tag = ARM64in_CAS; -+ i->ARM64in.CAS.szB = szB; -+ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); -+ return i; -+} - ARM64Instr* ARM64Instr_MFence ( void ) { - ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr)); - i->tag = ARM64in_MFence; -@@ -1569,6 +1576,10 @@ void ppARM64Instr ( const ARM64Instr* i ) { - sz, i->ARM64in.StrEX.szB == 8 ? 'x' : 'w'); - return; - } -+ case ARM64in_CAS: { -+ vex_printf("x1 = cas(%dbit)(x3, x5 -> x7)", 8 * i->ARM64in.CAS.szB); -+ return; -+ } - case ARM64in_MFence: - vex_printf("(mfence) dsb sy; dmb sy; isb"); - return; -@@ -2064,6 +2075,14 @@ void getRegUsage_ARM64Instr ( HRegUsage* u, const ARM64Instr* i, Bool mode64 ) - addHRegUse(u, HRmWrite, hregARM64_X0()); - addHRegUse(u, HRmRead, hregARM64_X2()); - return; -+ case ARM64in_CAS: -+ addHRegUse(u, HRmRead, hregARM64_X3()); -+ addHRegUse(u, HRmRead, hregARM64_X5()); -+ addHRegUse(u, HRmRead, hregARM64_X7()); -+ addHRegUse(u, HRmWrite, hregARM64_X1()); -+ /* Pointless to state this since X8 is not available to RA. */ -+ addHRegUse(u, HRmWrite, hregARM64_X8()); -+ break; - case ARM64in_MFence: - return; - case ARM64in_ClrEX: -@@ -2326,6 +2345,8 @@ void mapRegs_ARM64Instr ( HRegRemap* m, ARM64Instr* i, Bool mode64 ) - return; - case ARM64in_StrEX: - return; -+ case ARM64in_CAS: -+ return; - case ARM64in_MFence: - return; - case ARM64in_ClrEX: -@@ -3803,6 +3824,61 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, - } - goto bad; - } -+ case ARM64in_CAS: { -+ /* This isn't simple. For an explanation see the comment in -+ host_arm64_defs.h on the the definition of ARM64Instr case -+ CAS. */ -+ /* Generate: -+ -- one of: -+ mov x8, x5 // AA0503E8 -+ and x8, x5, #0xFFFFFFFF // 92407CA8 -+ and x8, x5, #0xFFFF // 92403CA8 -+ and x8, x5, #0xFF // 92401CA8 -+ -+ -- one of: -+ ldxr x1, [x3] // C85F7C61 -+ ldxr w1, [x3] // 885F7C61 -+ ldxrh w1, [x3] // 485F7C61 -+ ldxrb w1, [x3] // 085F7C61 -+ -+ -- always: -+ cmp x1, x8 // EB08003F -+ bne out // 54000061 -+ -+ -- one of: -+ stxr w1, x7, [x3] // C8017C67 -+ stxr w1, w7, [x3] // 88017C67 -+ stxrh w1, w7, [x3] // 48017C67 -+ stxrb w1, w7, [x3] // 08017C67 -+ -+ -- always: -+ eor x1, x5, x1 // CA0100A1 -+ out: -+ */ -+ switch (i->ARM64in.CAS.szB) { -+ case 8: *p++ = 0xAA0503E8; break; -+ case 4: *p++ = 0x92407CA8; break; -+ case 2: *p++ = 0x92403CA8; break; -+ case 1: *p++ = 0x92401CA8; break; -+ default: vassert(0); -+ } -+ switch (i->ARM64in.CAS.szB) { -+ case 8: *p++ = 0xC85F7C61; break; -+ case 4: *p++ = 0x885F7C61; break; -+ case 2: *p++ = 0x485F7C61; break; -+ case 1: *p++ = 0x085F7C61; break; -+ } -+ *p++ = 0xEB08003F; -+ *p++ = 0x54000061; -+ switch (i->ARM64in.CAS.szB) { -+ case 8: *p++ = 0xC8017C67; break; -+ case 4: *p++ = 0x88017C67; break; -+ case 2: *p++ = 0x48017C67; break; -+ case 1: *p++ = 0x08017C67; break; -+ } -+ *p++ = 0xCA0100A1; -+ goto done; -+ } - case ARM64in_MFence: { - *p++ = 0xD5033F9F; /* DSB sy */ - *p++ = 0xD5033FBF; /* DMB sy */ -diff --git a/VEX/priv/host_arm64_defs.h b/VEX/priv/host_arm64_defs.h -index 62b25fd..92d247e 100644 ---- a/VEX/priv/host_arm64_defs.h -+++ b/VEX/priv/host_arm64_defs.h -@@ -481,6 +481,7 @@ typedef - ARM64in_Mul, - ARM64in_LdrEX, - ARM64in_StrEX, -+ ARM64in_CAS, - ARM64in_MFence, - ARM64in_ClrEX, - /* ARM64in_V*: scalar ops involving vector registers */ -@@ -668,6 +669,32 @@ typedef - struct { - Int szB; /* 1, 2, 4 or 8 */ - } StrEX; -+ /* x1 = CAS(x3(addr), x5(expected) -> x7(new)), -+ where x1[8*szB-1 : 0] == x5[8*szB-1 : 0] indicates success, -+ x1[8*szB-1 : 0] != x5[8*szB-1 : 0] indicates failure. -+ Uses x8 as scratch (but that's not allocatable). -+ Hence: RD x3, x5, x7; WR x1 -+ -+ (szB=8) mov x8, x5 -+ (szB=4) and x8, x5, #0xFFFFFFFF -+ (szB=2) and x8, x5, #0xFFFF -+ (szB=1) and x8, x5, #0xFF -+ -- x8 is correctly zero-extended expected value -+ ldxr x1, [x3] -+ -- x1 is correctly zero-extended actual value -+ cmp x1, x8 -+ bne after -+ -- if branch taken, failure; x1[[8*szB-1 : 0] holds old value -+ -- attempt to store -+ stxr w1, x7, [x3] -+ -- if store successful, x1==0, so the eor is "x1 := x5" -+ -- if store failed, x1==1, so the eor makes x1 != x5 -+ eor x1, x5, x1 -+ after: -+ */ -+ struct { -+ Int szB; /* 1, 2, 4 or 8 */ -+ } CAS; - /* Mem fence. An insn which fences all loads and stores as - much as possible before continuing. On ARM64 we emit the - sequence "dsb sy ; dmb sy ; isb sy", which is probably -@@ -912,6 +939,7 @@ extern ARM64Instr* ARM64Instr_Mul ( HReg dst, HReg argL, HReg argR, - ARM64MulOp op ); - extern ARM64Instr* ARM64Instr_LdrEX ( Int szB ); - extern ARM64Instr* ARM64Instr_StrEX ( Int szB ); -+extern ARM64Instr* ARM64Instr_CAS ( Int szB ); - extern ARM64Instr* ARM64Instr_MFence ( void ); - extern ARM64Instr* ARM64Instr_ClrEX ( void ); - extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, -diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c -index 42748e4..07ce87a 100644 ---- a/VEX/priv/host_arm64_isel.c -+++ b/VEX/priv/host_arm64_isel.c -@@ -1383,12 +1383,13 @@ static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) - || e->Iex.Binop.op == Iop_CmpLT64S - || e->Iex.Binop.op == Iop_CmpLT64U - || e->Iex.Binop.op == Iop_CmpLE64S -- || e->Iex.Binop.op == Iop_CmpLE64U)) { -+ || e->Iex.Binop.op == Iop_CmpLE64U -+ || e->Iex.Binop.op == Iop_CasCmpEQ64)) { - HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); - ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); - addInstr(env, ARM64Instr_Cmp(argL, argR, True/*is64*/)); - switch (e->Iex.Binop.op) { -- case Iop_CmpEQ64: return ARM64cc_EQ; -+ case Iop_CmpEQ64: case Iop_CasCmpEQ64: return ARM64cc_EQ; - case Iop_CmpNE64: return ARM64cc_NE; - case Iop_CmpLT64S: return ARM64cc_LT; - case Iop_CmpLT64U: return ARM64cc_CC; -@@ -1405,12 +1406,13 @@ static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) - || e->Iex.Binop.op == Iop_CmpLT32S - || e->Iex.Binop.op == Iop_CmpLT32U - || e->Iex.Binop.op == Iop_CmpLE32S -- || e->Iex.Binop.op == Iop_CmpLE32U)) { -+ || e->Iex.Binop.op == Iop_CmpLE32U -+ || e->Iex.Binop.op == Iop_CasCmpEQ32)) { - HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); - ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); - addInstr(env, ARM64Instr_Cmp(argL, argR, False/*!is64*/)); - switch (e->Iex.Binop.op) { -- case Iop_CmpEQ32: return ARM64cc_EQ; -+ case Iop_CmpEQ32: case Iop_CasCmpEQ32: return ARM64cc_EQ; - case Iop_CmpNE32: return ARM64cc_NE; - case Iop_CmpLT32S: return ARM64cc_LT; - case Iop_CmpLT32U: return ARM64cc_CC; -@@ -1420,6 +1422,34 @@ static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) - } - } - -+ /* --- Cmp*16*(x,y) --- */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_CasCmpEQ16)) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg argL2 = widen_z_16_to_64(env, argL); -+ HReg argR2 = widen_z_16_to_64(env, argR); -+ addInstr(env, ARM64Instr_Cmp(argL2, ARM64RIA_R(argR2), True/*is64*/)); -+ switch (e->Iex.Binop.op) { -+ case Iop_CasCmpEQ16: return ARM64cc_EQ; -+ default: vpanic("iselCondCode(arm64): CmpXX16"); -+ } -+ } -+ -+ /* --- Cmp*8*(x,y) --- */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_CasCmpEQ8)) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg argL2 = widen_z_8_to_64(env, argL); -+ HReg argR2 = widen_z_8_to_64(env, argR); -+ addInstr(env, ARM64Instr_Cmp(argL2, ARM64RIA_R(argR2), True/*is64*/)); -+ switch (e->Iex.Binop.op) { -+ case Iop_CasCmpEQ8: return ARM64cc_EQ; -+ default: vpanic("iselCondCode(arm64): CmpXX8"); -+ } -+ } -+ - ppIRExpr(e); - vpanic("iselCondCode"); - } -@@ -3833,6 +3863,57 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) - break; - } - -+ /* --------- ACAS --------- */ -+ case Ist_CAS: { -+ if (stmt->Ist.CAS.details->oldHi == IRTemp_INVALID) { -+ /* "normal" singleton CAS */ -+ UChar sz; -+ IRCAS* cas = stmt->Ist.CAS.details; -+ IRType ty = typeOfIRExpr(env->type_env, cas->dataLo); -+ switch (ty) { -+ case Ity_I64: sz = 8; break; -+ case Ity_I32: sz = 4; break; -+ case Ity_I16: sz = 2; break; -+ case Ity_I8: sz = 1; break; -+ default: goto unhandled_cas; -+ } -+ HReg rAddr = iselIntExpr_R(env, cas->addr); -+ HReg rExpd = iselIntExpr_R(env, cas->expdLo); -+ HReg rData = iselIntExpr_R(env, cas->dataLo); -+ vassert(cas->expdHi == NULL); -+ vassert(cas->dataHi == NULL); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X3(), rAddr)); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X5(), rExpd)); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X7(), rData)); -+ addInstr(env, ARM64Instr_CAS(sz)); -+ /* Now we have the lowest szB bytes of x1 are either equal to -+ the lowest szB bytes of x5, indicating success, or they -+ aren't, indicating failure. The IR semantics actually -+ require us to return the old value at the location, -+ regardless of success or failure, but in the case of -+ failure it's not clear how to do this, since -+ ARM64Instr_CAS can't provide that. Instead we'll just -+ return the relevant bit of x1, since that's at least -+ guaranteed to be different from the lowest bits of x5 on -+ failure. */ -+ HReg rResult = hregARM64_X1(); -+ switch (sz) { -+ case 8: break; -+ case 4: rResult = widen_z_32_to_64(env, rResult); break; -+ case 2: rResult = widen_z_16_to_64(env, rResult); break; -+ case 1: rResult = widen_z_8_to_64(env, rResult); break; -+ default: vassert(0); -+ } -+ // "old" in this case is interpreted somewhat liberally, per -+ // the previous comment. -+ HReg rOld = lookupIRTemp(env, cas->oldLo); -+ addInstr(env, ARM64Instr_MovI(rOld, rResult)); -+ return; -+ } -+ unhandled_cas: -+ break; -+ } -+ - /* --------- MEM FENCE --------- */ - case Ist_MBE: - switch (stmt->Ist.MBE.event) { -diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c -index 8c4845e..26e9880 100644 ---- a/VEX/priv/main_main.c -+++ b/VEX/priv/main_main.c -@@ -1556,6 +1556,7 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) - vbi->guest_amd64_assume_gs_is_const = False; - vbi->guest_ppc_zap_RZ_at_blr = False; - vbi->guest_ppc_zap_RZ_at_bl = NULL; -+ vbi->guest__use_fallback_LLSC = False; - vbi->host_ppc_calls_use_fndescrs = False; - } - -diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h -index 8ac3d9f..cbbb1ad 100644 ---- a/VEX/pub/libvex.h -+++ b/VEX/pub/libvex.h -@@ -369,6 +369,11 @@ void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ); - guest is ppc32-linux ==> const False - guest is other ==> inapplicable - -+ guest__use_fallback_LLSC -+ guest is mips32 ==> applicable, default True -+ guest is mips64 ==> applicable, default True -+ guest is arm64 ==> applicable, default False -+ - host_ppc_calls_use_fndescrs: - host is ppc32-linux ==> False - host is ppc64-linux ==> True -@@ -401,11 +406,17 @@ typedef - is assumed equivalent to a fn which always returns False. */ - Bool (*guest_ppc_zap_RZ_at_bl)(Addr); - -+ /* Potentially for all guests that use LL/SC: use the fallback -+ (synthesised) implementation rather than passing LL/SC on to -+ the host? */ -+ Bool guest__use_fallback_LLSC; -+ - /* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a - function descriptor on the host, or to the function code - itself? True => descriptor, False => code. */ - Bool host_ppc_calls_use_fndescrs; - -+ /* ??? Description ??? */ - Bool guest_mips_fp_mode64; - } - VexAbiInfo; -diff --git a/VEX/pub/libvex_guest_arm64.h b/VEX/pub/libvex_guest_arm64.h -index c438c1e..8b62cdd 100644 ---- a/VEX/pub/libvex_guest_arm64.h -+++ b/VEX/pub/libvex_guest_arm64.h -@@ -159,9 +159,14 @@ typedef - note of bits 23 and 22. */ - UInt guest_FPCR; - -+ /* Fallback LL/SC support. See bugs 344524 and 369459. */ -+ ULong guest_LLSC_SIZE; // 0==no current transaction, else 1,2,4 or 8. -+ ULong guest_LLSC_ADDR; // Address of transaction. -+ ULong guest_LLSC_DATA; // Original value at _ADDR, zero-extended. -+ - /* Padding to make it have an 16-aligned size */ - /* UInt pad_end_0; */ -- /* ULong pad_end_1; */ -+ ULong pad_end_1; - } - VexGuestARM64State; - diff --git a/SOURCES/valgrind-3.12.0-ll-sc-fallback2.patch b/SOURCES/valgrind-3.12.0-ll-sc-fallback2.patch deleted file mode 100644 index 4389a78..0000000 --- a/SOURCES/valgrind-3.12.0-ll-sc-fallback2.patch +++ /dev/null @@ -1,181 +0,0 @@ -commit 9d6e165ea7cf9da0086b9b107d6dd2498f1af6d0 -Author: Julian Seward -Date: Mon Apr 24 09:24:57 2017 +0000 - - Bug 369459 - valgrind on arm64 violates the ARMv8 spec (ldxr/stxr) - - This implements a fallback LL/SC implementation as described in bug 344524. - - Valgrind side changes: - - * Command line plumbing for --sim-hints=fallback-llsc - - * memcheck: handle new arm64 guest state in memcheck/mc_machine.c - - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16309 - -diff --git a/coregrind/m_main.c b/coregrind/m_main.c -index 9a4b60e..424daf7 100644 ---- a/coregrind/m_main.c -+++ b/coregrind/m_main.c -@@ -187,7 +187,7 @@ static void usage_NORETURN ( Bool debug_help ) - " --sim-hints=hint1,hint2,... activate unusual sim behaviours [none] \n" - " where hint is one of:\n" - " lax-ioctls lax-doors fuse-compatible enable-outer\n" --" no-inner-prefix no-nptl-pthread-stackcache none\n" -+" no-inner-prefix no-nptl-pthread-stackcache fallback-llsc none\n" - " --fair-sched=no|yes|try schedule threads fairly on multicore systems [no]\n" - " --kernel-variant=variant1,variant2,...\n" - " handle non-standard kernel variants [none]\n" -@@ -417,7 +417,7 @@ static void early_process_cmd_line_options ( /*OUT*/Int* need_help ) - else if VG_USETX_CLO (str, "--sim-hints", - "lax-ioctls,lax-doors,fuse-compatible," - "enable-outer,no-inner-prefix," -- "no-nptl-pthread-stackcache", -+ "no-nptl-pthread-stackcache,fallback-llsc", - VG_(clo_sim_hints)) {} - } - -diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c -index 9ae3f21..96a24f8 100644 ---- a/coregrind/m_scheduler/scheduler.c -+++ b/coregrind/m_scheduler/scheduler.c -@@ -925,6 +925,14 @@ void run_thread_for_a_while ( /*OUT*/HWord* two_words, - tst->arch.vex.host_EvC_FAILADDR - = (HWord)VG_(fnptr_to_fnentry)( &VG_(disp_cp_evcheck_fail) ); - -+ /* Invalidate any in-flight LL/SC transactions, in the case that we're -+ using the fallback LL/SC implementation. See bugs 344524 and 369459. */ -+# if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ tst->arch.vex.guest_LLaddr = (HWord)(-1); -+# elif defined(VGP_arm64_linux) -+ tst->arch.vex.guest_LLSC_SIZE = 0; -+# endif -+ - if (0) { - vki_sigset_t m; - Int i, err = VG_(sigprocmask)(VKI_SIG_SETMASK, NULL, &m); -diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c -index 2d6d3ba..c467e33 100644 ---- a/coregrind/m_translate.c -+++ b/coregrind/m_translate.c -@@ -1663,30 +1663,51 @@ Bool VG_(translate) ( ThreadId tid, - vex_abiinfo.guest_amd64_assume_fs_is_const = True; - vex_abiinfo.guest_amd64_assume_gs_is_const = True; - # endif -+ - # if defined(VGP_amd64_darwin) - vex_abiinfo.guest_amd64_assume_gs_is_const = True; - # endif -+ -+# if defined(VGP_amd64_solaris) -+ vex_abiinfo.guest_amd64_assume_fs_is_const = True; -+# endif -+ - # if defined(VGP_ppc32_linux) - vex_abiinfo.guest_ppc_zap_RZ_at_blr = False; - vex_abiinfo.guest_ppc_zap_RZ_at_bl = NULL; - # endif -+ - # if defined(VGP_ppc64be_linux) - vex_abiinfo.guest_ppc_zap_RZ_at_blr = True; - vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True; - vex_abiinfo.host_ppc_calls_use_fndescrs = True; - # endif -+ - # if defined(VGP_ppc64le_linux) - vex_abiinfo.guest_ppc_zap_RZ_at_blr = True; - vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True; - vex_abiinfo.host_ppc_calls_use_fndescrs = False; - # endif --# if defined(VGP_amd64_solaris) -- vex_abiinfo.guest_amd64_assume_fs_is_const = True; --# endif -+ - # if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) - ThreadArchState* arch = &VG_(threads)[tid].arch; - vex_abiinfo.guest_mips_fp_mode64 = - !!(arch->vex.guest_CP0_status & MIPS_CP0_STATUS_FR); -+ /* Compute guest__use_fallback_LLSC, overiding any settings of -+ VG_(clo_fallback_llsc) that we know would cause the guest to -+ fail (loop). */ -+ if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) { -+ /* We must use the fallback scheme. */ -+ vex_abiinfo.guest__use_fallback_LLSC = True; -+ } else { -+ vex_abiinfo.guest__use_fallback_LLSC -+ = SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints)); -+ } -+# endif -+ -+# if defined(VGP_arm64_linux) -+ vex_abiinfo.guest__use_fallback_LLSC -+ = SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints)); - # endif - - /* Set up closure args. */ -diff --git a/coregrind/pub_core_options.h b/coregrind/pub_core_options.h -index ba27127..703d08a 100644 ---- a/coregrind/pub_core_options.h -+++ b/coregrind/pub_core_options.h -@@ -222,14 +222,15 @@ typedef - SimHint_fuse_compatible, - SimHint_enable_outer, - SimHint_no_inner_prefix, -- SimHint_no_nptl_pthread_stackcache -+ SimHint_no_nptl_pthread_stackcache, -+ SimHint_fallback_llsc - } - SimHint; - - // Build mask to check or set SimHint a membership - #define SimHint2S(a) (1 << (a)) - // SimHint h is member of the Set s ? --#define SimHintiS(h,s) ((s) & SimHint2S(h)) -+#define SimHintiS(h,s) (((s) & SimHint2S(h)) != 0) - extern UInt VG_(clo_sim_hints); - - /* Show symbols in the form 'name+offset' ? Default: NO */ -diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c -index f6acc0b..608a374 100644 ---- a/memcheck/mc_machine.c -+++ b/memcheck/mc_machine.c -@@ -1040,6 +1040,10 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) - if (o == GOF(CMSTART) && sz == 8) return -1; // untracked - if (o == GOF(CMLEN) && sz == 8) return -1; // untracked - -+ if (o == GOF(LLSC_SIZE) && sz == 8) return -1; // untracked -+ if (o == GOF(LLSC_ADDR) && sz == 8) return o; -+ if (o == GOF(LLSC_DATA) && sz == 8) return o; -+ - VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n", - offset,szB); - tl_assert(0); -diff --git a/none/tests/cmdline1.stdout.exp b/none/tests/cmdline1.stdout.exp -index 4e8bca4..a4d8175 100644 ---- a/none/tests/cmdline1.stdout.exp -+++ b/none/tests/cmdline1.stdout.exp -@@ -101,7 +101,7 @@ usage: valgrind [options] prog-and-args - --sim-hints=hint1,hint2,... activate unusual sim behaviours [none] - where hint is one of: - lax-ioctls lax-doors fuse-compatible enable-outer -- no-inner-prefix no-nptl-pthread-stackcache none -+ no-inner-prefix no-nptl-pthread-stackcache fallback-llsc none - --fair-sched=no|yes|try schedule threads fairly on multicore systems [no] - --kernel-variant=variant1,variant2,... - handle non-standard kernel variants [none] -diff --git a/none/tests/cmdline2.stdout.exp b/none/tests/cmdline2.stdout.exp -index 644013c..461ad2d 100644 ---- a/none/tests/cmdline2.stdout.exp -+++ b/none/tests/cmdline2.stdout.exp -@@ -101,7 +101,7 @@ usage: valgrind [options] prog-and-args - --sim-hints=hint1,hint2,... activate unusual sim behaviours [none] - where hint is one of: - lax-ioctls lax-doors fuse-compatible enable-outer -- no-inner-prefix no-nptl-pthread-stackcache none -+ no-inner-prefix no-nptl-pthread-stackcache fallback-llsc none - --fair-sched=no|yes|try schedule threads fairly on multicore systems [no] - --kernel-variant=variant1,variant2,... - handle non-standard kernel variants [none] diff --git a/SOURCES/valgrind-3.12.0-ll-sc-fallback3.patch b/SOURCES/valgrind-3.12.0-ll-sc-fallback3.patch deleted file mode 100644 index eedd891..0000000 --- a/SOURCES/valgrind-3.12.0-ll-sc-fallback3.patch +++ /dev/null @@ -1,132 +0,0 @@ -commit 306353a8d233c3d7c60e7b02799b8675e745d5c2 -Author: Julian Seward -Date: Tue May 16 05:35:23 2017 +0000 - - arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the - fallback LLSC implementation in that case. Pertains to bug #369459. - - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16380 - -diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c -index 93bdd72..eac1c16 100644 ---- a/coregrind/m_machine.c -+++ b/coregrind/m_machine.c -@@ -634,7 +634,7 @@ static UInt VG_(get_machine_model)(void) - return model; - } - --#endif /* VGA_s390x */ -+#endif /* defined(VGA_s390x) */ - - #if defined(VGA_mips32) || defined(VGA_mips64) - -@@ -755,12 +755,65 @@ static Bool VG_(parse_cpuinfo)(void) - return True; - } - --#endif -+#endif /* defined(VGA_mips32) || defined(VGA_mips64) */ -+ -+#if defined(VGP_arm64_linux) -+ -+/* Check to see whether we are running on a Cavium core, and if so auto-enable -+ the fallback LLSC implementation. See #369459. */ -+ -+static Bool VG_(parse_cpuinfo)(void) -+{ -+ const char *search_Cavium_str = "CPU implementer\t: 0x43"; -+ -+ Int n, fh; -+ SysRes fd; -+ SizeT num_bytes, file_buf_size; -+ HChar *file_buf; -+ -+ /* Slurp contents of /proc/cpuinfo into FILE_BUF */ -+ fd = VG_(open)( "/proc/cpuinfo", 0, VKI_S_IRUSR ); -+ if ( sr_isError(fd) ) return False; -+ -+ fh = sr_Res(fd); -+ -+ /* Determine the size of /proc/cpuinfo. -+ Work around broken-ness in /proc file system implementation. -+ fstat returns a zero size for /proc/cpuinfo although it is -+ claimed to be a regular file. */ -+ num_bytes = 0; -+ file_buf_size = 1000; -+ file_buf = VG_(malloc)("cpuinfo", file_buf_size + 1); -+ while (42) { -+ n = VG_(read)(fh, file_buf, file_buf_size); -+ if (n < 0) break; -+ -+ num_bytes += n; -+ if (n < file_buf_size) break; /* reached EOF */ -+ } -+ -+ if (n < 0) num_bytes = 0; /* read error; ignore contents */ -+ -+ if (num_bytes > file_buf_size) { -+ VG_(free)( file_buf ); -+ VG_(lseek)( fh, 0, VKI_SEEK_SET ); -+ file_buf = VG_(malloc)( "cpuinfo", num_bytes + 1 ); -+ n = VG_(read)( fh, file_buf, num_bytes ); -+ if (n < 0) num_bytes = 0; -+ } - --/* Determine what insn set and insn set variant the host has, and -- record it. To be called once at system startup. Returns False if -- this a CPU incapable of running Valgrind. -- Also determine information about the caches on this host. */ -+ file_buf[num_bytes] = '\0'; -+ VG_(close)(fh); -+ -+ /* Parse file */ -+ if (VG_(strstr)(file_buf, search_Cavium_str) != NULL) -+ vai.arm64_requires_fallback_LLSC = True; -+ -+ VG_(free)(file_buf); -+ return True; -+} -+ -+#endif /* defined(VGP_arm64_linux) */ - - Bool VG_(machine_get_hwcaps)( void ) - { -@@ -1588,6 +1641,11 @@ Bool VG_(machine_get_hwcaps)( void ) - - VG_(machine_get_cache_info)(&vai); - -+ /* Check whether we need to use the fallback LLSC implementation. -+ If the check fails, give up. */ -+ if (! VG_(parse_cpuinfo)()) -+ return False; -+ - /* 0 denotes 'not set'. The range of legitimate values here, - after being set that is, is 2 though 17 inclusive. */ - vg_assert(vai.arm64_dMinLine_lg2_szB == 0); -@@ -1600,6 +1658,8 @@ Bool VG_(machine_get_hwcaps)( void ) - "ctr_el0.iMinLine_szB = %d\n", - 1 << vai.arm64_dMinLine_lg2_szB, - 1 << vai.arm64_iMinLine_lg2_szB); -+ VG_(debugLog)(1, "machine", "ARM64: requires_fallback_LLSC: %s\n", -+ vai.arm64_requires_fallback_LLSC ? "yes" : "no"); - - return True; - } -diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c -index 2f0ceac..55c845d 100644 ---- a/coregrind/m_translate.c -+++ b/coregrind/m_translate.c -@@ -1707,7 +1707,10 @@ Bool VG_(translate) ( ThreadId tid, - - # if defined(VGP_arm64_linux) - vex_abiinfo.guest__use_fallback_LLSC -- = SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints)); -+ = /* The user asked explicitly */ -+ SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints)) -+ || /* we autodetected that it is necessary */ -+ vex_archinfo.arm64_requires_fallback_LLSC; - # endif - - /* Set up closure args. */ diff --git a/SOURCES/valgrind-3.12.0-ll-sc-fallback4.patch b/SOURCES/valgrind-3.12.0-ll-sc-fallback4.patch deleted file mode 100644 index ce60328..0000000 --- a/SOURCES/valgrind-3.12.0-ll-sc-fallback4.patch +++ /dev/null @@ -1,37 +0,0 @@ -commit b1983ee86743f987e28d9fdb363d460bc5f3b23f -Author: Julian Seward -Date: Tue May 16 06:26:48 2017 +0000 - - arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the - fallback LLSC implementation in that case. Pertains to bug #369459. - (VEX side changes) - - - git-svn-id: svn://svn.valgrind.org/vex/trunk@3371 - -diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c -index d4b142d..7c125ce 100644 ---- a/VEX/priv/main_main.c -+++ b/VEX/priv/main_main.c -@@ -1468,6 +1468,7 @@ void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) - vai->ppc_dcbzl_szB = 0; - vai->arm64_dMinLine_lg2_szB = 0; - vai->arm64_iMinLine_lg2_szB = 0; -+ vai->arm64_requires_fallback_LLSC = False; - vai->hwcache_info.num_levels = 0; - vai->hwcache_info.num_caches = 0; - vai->hwcache_info.caches = NULL; -diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h -index b0ce1da..d75919d 100644 ---- a/VEX/pub/libvex.h -+++ b/VEX/pub/libvex.h -@@ -323,6 +323,9 @@ typedef - line size of 64 bytes would be encoded here as 6. */ - UInt arm64_dMinLine_lg2_szB; - UInt arm64_iMinLine_lg2_szB; -+ /* ARM64: does the host require us to use the fallback LLSC -+ implementation? */ -+ Bool arm64_requires_fallback_LLSC; - } - VexArchInfo; - diff --git a/SOURCES/valgrind-3.12.0-nocwd-cleanup.patch b/SOURCES/valgrind-3.12.0-nocwd-cleanup.patch deleted file mode 100644 index fdb736d..0000000 --- a/SOURCES/valgrind-3.12.0-nocwd-cleanup.patch +++ /dev/null @@ -1,23 +0,0 @@ -commit b02baf74e6c14cc6fcf1e4fa94f1a6734c9cffbe -Author: mjw -Date: Sat Nov 12 19:51:51 2016 +0000 - - Cleanup none/tests/nocwd.vgtest tmp dirs. - - The none/tests/nocwd creates a really deep temporary directory structure - that is also inaccessible after the test. This causes issues with some - build wrappers like koji which fail to cleanup such deep subdirectories. - So explicitly cleanup the directory after the test. - - https://bugzilla.redhat.com/show_bug.cgi?id=1390282 - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16134 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/none/tests/nocwd.vgtest b/none/tests/nocwd.vgtest -index 74e2b4a..f8d4c3b 100644 ---- a/none/tests/nocwd.vgtest -+++ b/none/tests/nocwd.vgtest -@@ -1,2 +1,3 @@ - prog: nocwd - vgopts: -q --trace-children=yes -+cleanup: chmod u+rwx /tmp/wd_test_*; rm -rf /tmp/wd_test_* diff --git a/SOURCES/valgrind-3.12.0-powerpc-register-pair.patch b/SOURCES/valgrind-3.12.0-powerpc-register-pair.patch deleted file mode 100644 index 7830863..0000000 --- a/SOURCES/valgrind-3.12.0-powerpc-register-pair.patch +++ /dev/null @@ -1,73 +0,0 @@ -commit 3f055b64899cc4b7c34f9ebdc4beb418a8bced07 -Author: carll -Date: Fri Mar 10 20:07:09 2017 +0000 - - PowerPC: Fix incorrect register pair check for lxv, stxv, stxsd, stxssp, lxsd, - lxssp instructions - - The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The - register pair test must only be applied to these instructions in the - dis_fp_pair() function. - - bugzilla 377427 - - - - git-svn-id: svn://svn.valgrind.org/vex/trunk@3308 8f6e269a-dfd6-0310-a8e1-e2731360e62c - -diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c -index b19dcbc..0d27389 100644 ---- a/VEX/priv/guest_ppc_toIR.c -+++ b/VEX/priv/guest_ppc_toIR.c -@@ -11310,13 +11310,16 @@ static Bool dis_fp_pair ( UInt theInstr ) - UChar b0 = ifieldBIT0(theInstr); - Bool is_load = 0; - -- if ((frT_hi_addr %2) != 0) { -- vex_printf("dis_fp_pair(ppc) : odd frT register\n"); -- return False; -- } -- - switch (opc1) { - case 0x1F: // register offset -+ /* These instructions work on a pair of registers. The specified -+ * register must be even. -+ */ -+ if ((frT_hi_addr %2) != 0) { -+ vex_printf("dis_fp_pair(ppc) ldpx or stdpx: odd frT register\n"); -+ return False; -+ } -+ - switch(opc2) { - case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125) - DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr); -@@ -11346,6 +11349,14 @@ static Bool dis_fp_pair ( UInt theInstr ) - - switch(opc2) { - case 0x0: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125) -+ /* This instruction works on a pair of registers. The specified -+ * register must be even. -+ */ -+ if ((frT_hi_addr %2) != 0) { -+ vex_printf("dis_fp_pair(ppc) lfdp : odd frT register\n"); -+ return False; -+ } -+ - DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr); - assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); - is_load = 1; -@@ -11390,6 +11401,14 @@ static Bool dis_fp_pair ( UInt theInstr ) - switch(opc2) { - case 0x0: - // stfdp (FP Store Double Pair DS-form, ISA 2.05 p125) -+ /* This instruction works on a pair of registers. The specified -+ * register must be even. -+ */ -+ if ((frT_hi_addr %2) != 0) { -+ vex_printf("dis_fp_pair(ppc) stfdp : odd frT register\n"); -+ return False; -+ } -+ - DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr); - assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); - break; diff --git a/SOURCES/valgrind-3.12.0-ppc-xxsel.patch b/SOURCES/valgrind-3.12.0-ppc-xxsel.patch deleted file mode 100644 index e27b8b6..0000000 --- a/SOURCES/valgrind-3.12.0-ppc-xxsel.patch +++ /dev/null @@ -1,505 +0,0 @@ -commit b8fbe1485567fb240404344533c16a82d53b868e -Author: carll -Date: Mon Nov 7 19:41:30 2016 +0000 - - Fix xxsel parsing error. - - The xxsel instruction uses part of the standard opc2 field to specify - a additional operand or other values. A subset of the field is used for - the actual opcode. The masking and array lookup was getting confused by - bits in the the additional operand field. The arrays were split so only - the opcodes that should be found for a given mask is in the array. This - also speeds up the search as you are not searching through values that - cannot match. The small groups of opcodes for a couple of the masks are - now done in a case statement as that is probably faster then doing an array - look up. - - Bugzilla 148000 - - - git-svn-id: svn://svn.valgrind.org/vex/trunk@3284 8f6e269a-dfd6-0310-a8e1-e2731360e62c - -diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c -index c393740..c265645 100644 ---- a/VEX/priv/guest_ppc_toIR.c -+++ b/VEX/priv/guest_ppc_toIR.c -@@ -18146,7 +18146,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - assign( vB, getVSReg( XB ) ); - - switch (opc2) { -- case 0x18C: case 0x38C: // xvcmpeqdp[.] (VSX Vector Compare Equal To Double-Precision [ & Record ]) -+ case 0x18C: // xvcmpeqdp[.] (VSX Vector Compare Equal To Double-Precision [ & Record ]) - { - DIP("xvcmpeqdp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), - XT, XA, XB); -@@ -18154,7 +18154,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - break; - } - -- case 0x1CC: case 0x3CC: // xvcmpgedp[.] (VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ]) -+ case 0x1CC: // xvcmpgedp[.] (VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ]) - { - DIP("xvcmpgedp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), - XT, XA, XB); -@@ -18162,7 +18162,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - break; - } - -- case 0x1AC: case 0x3AC: // xvcmpgtdp[.] (VSX Vector Compare Greater Than Double-Precision [ & Record ]) -+ case 0x1AC: // xvcmpgtdp[.] (VSX Vector Compare Greater Than Double-Precision [ & Record ]) - { - DIP("xvcmpgtdp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), - XT, XA, XB); -@@ -18170,7 +18170,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - break; - } - -- case 0x10C: case 0x30C: // xvcmpeqsp[.] (VSX Vector Compare Equal To Single-Precision [ & Record ]) -+ case 0x10C: // xvcmpeqsp[.] (VSX Vector Compare Equal To Single-Precision [ & Record ]) - { - IRTemp vD = newTemp(Ity_V128); - -@@ -18184,7 +18184,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - break; - } - -- case 0x14C: case 0x34C: // xvcmpgesp[.] (VSX Vector Compare Greater Than or Equal To Single-Precision [ & Record ]) -+ case 0x14C: // xvcmpgesp[.] (VSX Vector Compare Greater Than or Equal To Single-Precision [ & Record ]) - { - IRTemp vD = newTemp(Ity_V128); - -@@ -18198,7 +18198,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - break; - } - -- case 0x12C: case 0x32C: //xvcmpgtsp[.] (VSX Vector Compare Greater Than Single-Precision [ & Record ]) -+ case 0x12C: //xvcmpgtsp[.] (VSX Vector Compare Greater Than Single-Precision [ & Record ]) - { - IRTemp vD = newTemp(Ity_V128); - -@@ -27043,17 +27043,93 @@ struct vsx_insn { - }; - - // ATTENTION: Keep this array sorted on the opcocde!!! --static struct vsx_insn vsx_all[] = { -- { 0x0, "xsaddsp" }, -- { 0x4, "xsmaddasp" }, -- { 0x8, "xxsldwi" }, -+static struct vsx_insn vsx_xx2[] = { - { 0x14, "xsrsqrtesp" }, - { 0x16, "xssqrtsp" }, - { 0x18, "xxsel" }, -+ { 0x34, "xsresp" }, -+ { 0x90, "xscvdpuxws" }, -+ { 0x92, "xsrdpi" }, -+ { 0x94, "xsrsqrtedp" }, -+ { 0x96, "xssqrtdp" }, -+ { 0xb0, "xscvdpsxws" }, -+ { 0xb2, "xsrdpiz" }, -+ { 0xb4, "xsredp" }, -+ { 0xd2, "xsrdpip" }, -+ { 0xd4, "xstsqrtdp" }, -+ { 0xd6, "xsrdpic" }, -+ { 0xf2, "xsrdpim" }, -+ { 0x112, "xvrspi" }, -+ { 0x116, "xvsqrtsp" }, -+ { 0x130, "xvcvspsxws" }, -+ { 0x132, "xvrspiz" }, -+ { 0x134, "xvresp" }, -+ { 0x148, "xxspltw" }, -+ { 0x14A, "xxextractuw" }, -+ { 0x150, "xvcvuxwsp" }, -+ { 0x152, "xvrspip" }, -+ { 0x154, "xvtsqrtsp" }, -+ { 0x156, "xvrspic" }, -+ { 0x16A, "xxinsertw" }, -+ { 0x170, "xvcvsxwsp" }, -+ { 0x172, "xvrspim" }, -+ { 0x190, "xvcvdpuxws" }, -+ { 0x192, "xvrdpi" }, -+ { 0x194, "xvrsqrtedp" }, -+ { 0x196, "xvsqrtdp" }, -+ { 0x1b0, "xvcvdpsxws" }, -+ { 0x1b2, "xvrdpiz" }, -+ { 0x1b4, "xvredp" }, -+ { 0x1d0, "xvcvuxwdp" }, -+ { 0x1d2, "xvrdpip" }, -+ { 0x1d4, "xvtsqrtdp" }, -+ { 0x1d6, "xvrdpic" }, -+ { 0x1f0, "xvcvsxwdp" }, -+ { 0x1f2, "xvrdpim" }, -+ { 0x212, "xscvdpsp" }, -+ { 0x216, "xscvdpspn" }, -+ { 0x232, "xxrsp" }, -+ { 0x250, "xscvuxdsp" }, -+ { 0x254, "xststdcsp" }, -+ { 0x270, "xscvsxdsp" }, -+ { 0x290, "xscvdpuxds" }, -+ { 0x292, "xscvspdp" }, -+ { 0x296, "xscvspdpn" }, -+ { 0x2b0, "xscvdpsxds" }, -+ { 0x2b2, "xsabsdp" }, -+ { 0x2b6, "xsxexpdp_xsxigdp" }, -+ { 0x2d0, "xscvuxddp" }, -+ { 0x2d2, "xsnabsdp" }, -+ { 0x2d4, "xststdcdp" }, -+ { 0x2e4, "xsnmsubmdp" }, -+ { 0x2f0, "xscvsxddp" }, -+ { 0x2f2, "xsnegdp" }, -+ { 0x310, "xvcvspuxds" }, -+ { 0x312, "xvcvdpsp" }, -+ { 0x330, "xvcvspsxds" }, -+ { 0x332, "xvabssp" }, -+ { 0x350, "xvcvuxdsp" }, -+ { 0x352, "xvnabssp" }, -+ { 0x370, "xvcvsxdsp" }, -+ { 0x372, "xvnegsp" }, -+ { 0x390, "xvcvdpuxds" }, -+ { 0x392, "xvcvspdp" }, -+ { 0x3b0, "xvcvdpsxds" }, -+ { 0x3b2, "xvabsdp" }, -+ { 0x3b6, "xxbr[h|w|d|q]|xvxexpdp|xvxexpsp|xvxsigdp|xvxsigsp|xvcvhpsp|xvcvsphp|xscvdphp|xscvhpdp" }, -+ { 0x3d0, "xvcvuxddp" }, -+ { 0x3d2, "xvnabsdp" }, -+ { 0x3f2, "xvnegdp" } -+}; -+#define VSX_XX2_LEN (sizeof vsx_xx2 / sizeof *vsx_xx2) -+ -+// ATTENTION: Keep this array sorted on the opcocde!!! -+static struct vsx_insn vsx_xx3[] = { -+ { 0x0, "xsaddsp" }, -+ { 0x4, "xsmaddasp" }, -+ { 0x9, "xsmaddmsp" }, - { 0x20, "xssubsp" }, - { 0x24, "xsmaddmsp" }, -- { 0x28, "xxpermdi" }, -- { 0x34, "xsresp" }, - { 0x3A, "xxpermr" }, - { 0x40, "xsmulsp" }, - { 0x44, "xsmsubasp" }, -@@ -27064,174 +27140,112 @@ static struct vsx_insn vsx_all[] = { - { 0x80, "xsadddp" }, - { 0x84, "xsmaddadp" }, - { 0x8c, "xscmpudp" }, -- { 0x90, "xscvdpuxws" }, -- { 0x92, "xsrdpi" }, -- { 0x94, "xsrsqrtedp" }, -- { 0x96, "xssqrtdp" }, - { 0xa0, "xssubdp" }, - { 0xa4, "xsmaddmdp" }, - { 0xac, "xscmpodp" }, -- { 0xb0, "xscvdpsxws" }, -- { 0xb2, "xsrdpiz" }, -- { 0xb4, "xsredp" }, - { 0xc0, "xsmuldp" }, - { 0xc4, "xsmsubadp" }, - { 0xc8, "xxmrglw" }, -- { 0xd2, "xsrdpip" }, - { 0xd4, "xstsqrtdp" }, -- { 0xd6, "xsrdpic" }, - { 0xe0, "xsdivdp" }, - { 0xe4, "xsmsubmdp" }, - { 0xe8, "xxpermr" }, - { 0xeC, "xscmpexpdp" }, -- { 0xf2, "xsrdpim" }, - { 0xf4, "xstdivdp" }, - { 0x100, "xvaddsp" }, - { 0x104, "xvmaddasp" }, -- { 0x10c, "xvcmpeqsp" }, -+ { 0x10C, "xvcmpeqsp" }, - { 0x110, "xvcvspuxws" }, -- { 0x112, "xvrspi" }, - { 0x114, "xvrsqrtesp" }, -- { 0x116, "xvsqrtsp" }, - { 0x120, "xvsubsp" }, - { 0x124, "xvmaddmsp" }, -- { 0x12c, "xvcmpgtsp" }, - { 0x130, "xvcvspsxws" }, -- { 0x132, "xvrspiz" }, -- { 0x134, "xvresp" }, - { 0x140, "xvmulsp" }, - { 0x144, "xvmsubasp" }, -- { 0x148, "xxspltw" }, -- { 0x14A, "xxextractuw" }, -- { 0x14c, "xvcmpgesp" }, -- { 0x150, "xvcvuxwsp" }, -- { 0x152, "xvrspip" }, -- { 0x154, "xvtsqrtsp" }, -- { 0x156, "xvrspic" }, -+ { 0x14C, "xvcmpgesp", }, - { 0x160, "xvdivsp" }, - { 0x164, "xvmsubmsp" }, -- { 0x16A, "xxinsertw" }, -- { 0x170, "xvcvsxwsp" }, -- { 0x172, "xvrspim" }, - { 0x174, "xvtdivsp" }, - { 0x180, "xvadddp" }, - { 0x184, "xvmaddadp" }, -- { 0x18c, "xvcmpeqdp" }, -- { 0x190, "xvcvdpuxws" }, -- { 0x192, "xvrdpi" }, -- { 0x194, "xvrsqrtedp" }, -- { 0x196, "xvsqrtdp" }, -+ { 0x18C, "xvcmpeqdp" }, - { 0x1a0, "xvsubdp" }, - { 0x1a4, "xvmaddmdp" }, -- { 0x1ac, "xvcmpgtdp" }, -- { 0x1b0, "xvcvdpsxws" }, -- { 0x1b2, "xvrdpiz" }, -- { 0x1b4, "xvredp" }, -+ { 0x1aC, "xvcmpgtdp" }, - { 0x1c0, "xvmuldp" }, - { 0x1c4, "xvmsubadp" }, - { 0x1cc, "xvcmpgedp" }, -- { 0x1d0, "xvcvuxwdp" }, -- { 0x1d2, "xvrdpip" }, -- { 0x1d4, "xvtsqrtdp" }, -- { 0x1d6, "xvrdpic" }, - { 0x1e0, "xvdivdp" }, - { 0x1e4, "xvmsubmdp" }, -- { 0x1f0, "xvcvsxwdp" }, -- { 0x1f2, "xvrdpim" }, - { 0x1f4, "xvtdivdp" }, - { 0x204, "xsnmaddasp" }, - { 0x208, "xxland" }, -- { 0x212, "xscvdpsp" }, -- { 0x216, "xscvdpspn" }, - { 0x224, "xsnmaddmsp" }, - { 0x228, "xxlandc" }, -- { 0x232, "xxrsp" }, - { 0x244, "xsnmsubasp" }, - { 0x248, "xxlor" }, -- { 0x250, "xscvuxdsp" }, -- { 0x254, "xststdcsp" }, - { 0x264, "xsnmsubmsp" }, - { 0x268, "xxlxor" }, -- { 0x270, "xscvsxdsp" }, - { 0x280, "xsmaxdp" }, - { 0x284, "xsnmaddadp" }, - { 0x288, "xxlnor" }, -- { 0x290, "xscvdpuxds" }, -- { 0x292, "xscvspdp" }, -- { 0x296, "xscvspdpn" }, - { 0x2a0, "xsmindp" }, - { 0x2a4, "xsnmaddmdp" }, - { 0x2a8, "xxlorc" }, -- { 0x2b0, "xscvdpsxds" }, -- { 0x2b2, "xsabsdp" }, -- { 0x2b6, "xsxexpdp_xsxigdp" }, - { 0x2c0, "xscpsgndp" }, - { 0x2c4, "xsnmsubadp" }, - { 0x2c8, "xxlnand" }, -- { 0x2d0, "xscvuxddp" }, -- { 0x2d2, "xsnabsdp" }, -- { 0x2d4, "xststdcdp" }, - { 0x2e4, "xsnmsubmdp" }, - { 0x2e8, "xxleqv" }, -- { 0x2f0, "xscvsxddp" }, -- { 0x2f2, "xsnegdp" }, - { 0x300, "xvmaxsp" }, - { 0x304, "xvnmaddasp" }, -- { 0x30c, "xvcmpeqsp." }, -- { 0x310, "xvcvspuxds" }, -- { 0x312, "xvcvdpsp" }, - { 0x320, "xvminsp" }, - { 0x324, "xvnmaddmsp" }, -- { 0x32c, "xvcmpgtsp." }, -- { 0x330, "xvcvspsxds" }, -- { 0x332, "xvabssp" }, - { 0x340, "xvcpsgnsp" }, - { 0x344, "xvnmsubasp" }, -- { 0x34c, "xvcmpgesp." }, -- { 0x350, "xvcvuxdsp" }, -- { 0x352, "xvnabssp" }, -- { 0x354, "xvtstdcsp" }, - { 0x360, "xviexpsp" }, - { 0x364, "xvnmsubmsp" }, -- { 0x370, "xvcvsxdsp" }, -- { 0x372, "xvnegsp" }, - { 0x380, "xvmaxdp" }, - { 0x384, "xvnmaddadp" }, -- { 0x38c, "xvcmpeqdp." }, -- { 0x390, "xvcvdpuxds" }, -- { 0x392, "xvcvspdp" }, -- { 0x396, "xsiexpdp" }, - { 0x3a0, "xvmindp" }, - { 0x3a4, "xvnmaddmdp" }, -- { 0x3ac, "xvcmpgtdp." }, -- { 0x3b0, "xvcvdpsxds" }, -- { 0x3b2, "xvabsdp" }, -- { 0x3b6, "xxbr[h|w|d|q]|xvxexpdp|xvxexpsp|xvxsigdp|xvxsigsp|xvcvhpsp|xvcvsphp|xscvdphp|xscvhpdp" }, - { 0x3c0, "xvcpsgndp" }, - { 0x3c4, "xvnmsubadp" }, -- { 0x3cc, "xvcmpgedp." }, -- { 0x3d0, "xvcvuxddp" }, -- { 0x3d2, "xvnabsdp" }, -- { 0x3d4, "xvtstdcdp" }, - { 0x3e0, "xviexpdp" }, - { 0x3e4, "xvnmsubmdp" }, - { 0x3f0, "xvcvsxddp" }, -- { 0x3f2, "xvnegdp" } - }; --#define VSX_ALL_LEN (sizeof vsx_all / sizeof *vsx_all) -+#define VSX_XX3_LEN (sizeof vsx_xx3 / sizeof *vsx_xx3) - - --// ATTENTION: This search function assumes vsx_all array is sorted. --static Int findVSXextOpCode(UInt opcode) -+// ATTENTION: This search functions assumes vsx_all array is sorted. -+static Int findVSXextOpCode_xx2(UInt opcode) - { - Int low, mid, high; - low = 0; -- high = VSX_ALL_LEN - 1; -+ high = VSX_XX2_LEN - 1; - while (low <= high) { - mid = (low + high)/2; -- if (opcode < vsx_all[mid].opcode) -+ if (opcode < vsx_xx2[mid].opcode) - high = mid - 1; -- else if (opcode > vsx_all[mid].opcode) -+ else if (opcode > vsx_xx2[mid].opcode) -+ low = mid + 1; -+ else -+ return mid; -+ } -+ return -1; -+} -+ -+static Int findVSXextOpCode_xx3(UInt opcode) -+{ -+ Int low, mid, high; -+ low = 0; -+ high = VSX_XX3_LEN - 1; -+ while (low <= high) { -+ mid = (low + high)/2; -+ if (opcode < vsx_xx3[mid].opcode) -+ high = mid - 1; -+ else if (opcode > vsx_xx3[mid].opcode) - low = mid + 1; - else - return mid; -@@ -27244,31 +27258,68 @@ static Int findVSXextOpCode(UInt opcode) - * passed, and we then try to match it up with one of the VSX forms - * below. - */ --static UInt get_VSX60_opc2(UInt opc2_full) -+static UInt get_VSX60_opc2(UInt opc2_full, UInt theInstr) - { --#define XX2_MASK 0x000003FE -+#define XX2_1_MASK 0x000003FF // xsiexpdp specific -+#define XX2_2_MASK 0x000003FE - #define XX3_1_MASK 0x000003FC - #define XX3_2_MASK 0x000001FC --#define XX3_3_MASK 0x0000007C --#define XX4_MASK 0x00000018 --#define VDCMX_MASK 0x000003B8 -+#define XX3_4_MASK 0x0000027C -+#define XX3_5_MASK 0x000003DC -+#define XX4_MASK 0x00000018 -+ - Int ret; - UInt vsxExtOpcode = 0; - -- if (( ret = findVSXextOpCode(opc2_full & XX2_MASK)) >= 0) -- vsxExtOpcode = vsx_all[ret].opcode; -- else if (( ret = findVSXextOpCode(opc2_full & XX3_1_MASK)) >= 0) -- vsxExtOpcode = vsx_all[ret].opcode; -- else if (( ret = findVSXextOpCode(opc2_full & VDCMX_MASK)) >= 0) -- vsxExtOpcode = vsx_all[ret].opcode; -- else if (( ret = findVSXextOpCode(opc2_full & XX3_2_MASK)) >= 0) -- vsxExtOpcode = vsx_all[ret].opcode; -- else if (( ret = findVSXextOpCode(opc2_full & XX3_3_MASK)) >= 0) -- vsxExtOpcode = vsx_all[ret].opcode; -- else if (( ret = findVSXextOpCode(opc2_full & XX4_MASK)) >= 0) -- vsxExtOpcode = vsx_all[ret].opcode; -+ if (( ret = findVSXextOpCode_xx2(opc2_full & XX2_2_MASK)) >= 0) -+ return vsx_xx2[ret].opcode; -+ else if ((opc2_full & XX2_1_MASK) == 0x396 ) // xsiexpdp -+ return 0x396; -+ else if (( ret = findVSXextOpCode_xx3(opc2_full & XX3_1_MASK)) >= 0) -+ return vsx_xx3[ret].opcode; -+ else { -+ -+ /* There are only a few codes in each of these cases it is -+ * probably faster to check for the codes then do the array lookups. -+ */ -+ vsxExtOpcode = opc2_full & XX3_2_MASK; -+ -+ switch (vsxExtOpcode) { -+ case 0x10C: return vsxExtOpcode; // xvcmpeqsp -+ case 0x12C: return vsxExtOpcode; // xvcmpgtsp, xvcmpgtsp. -+ case 0x14C: return vsxExtOpcode; // xvcmpgesp, xvcmpgesp. -+ case 0x18C: return vsxExtOpcode; // xvcmpeqdp, xvcmpeqdp. -+ case 0x1AC: return vsxExtOpcode; // xvcmpgtdp, xvcmpgtdp. -+ case 0x1CC: return vsxExtOpcode; // xvcmpgedp, xvcmpgedp. -+ default: break; -+ } - -- return vsxExtOpcode; -+ vsxExtOpcode = opc2_full & XX3_4_MASK; -+ -+ switch (vsxExtOpcode) { -+ case 0x8: return vsxExtOpcode; // xxsldwi -+ case 0x28: return vsxExtOpcode; // xxpermdi -+ default: break; -+ } -+ -+ vsxExtOpcode = opc2_full & XX3_5_MASK; -+ -+ switch (vsxExtOpcode) { -+ case 0x354: return vsxExtOpcode; // xvtstdcsp -+ case 0x3D4: return vsxExtOpcode; // xvtstdcdp -+ default: break; -+ } -+ -+ if (( opc2_full & XX4_MASK ) == XX4_MASK ) { // xxsel -+ vsxExtOpcode = 0x18; -+ return vsxExtOpcode; -+ } -+ } -+ -+ vex_printf( "Error: undefined opcode 0x %x, the instruction = 0x %x\n", -+ opc2_full, theInstr ); -+ vpanic( "ERROR: get_VSX60_opc2()\n" ); -+ return 0; - } - - /*------------------------------------------------------------*/ -@@ -27718,7 +27769,7 @@ DisResult disInstr_PPC_WRK ( - opc2 = ifieldOPClo10(theInstr); - UInt opc2hi = IFIELD(theInstr, 7, 4); - UInt opc2lo = IFIELD(theInstr, 3, 3); -- UInt vsxOpc2 = get_VSX60_opc2(opc2); -+ UInt vsxOpc2; - - if (( opc2hi == 13 ) && ( opc2lo == 5)) { //xvtstdcsp - if (dis_vxs_misc(theInstr, 0x354, allow_isa_3_0)) -@@ -27747,6 +27798,8 @@ DisResult disInstr_PPC_WRK ( - goto decode_failure; - } - -+ vsxOpc2 = get_VSX60_opc2(opc2, theInstr); -+ - switch (vsxOpc2) { - case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw - case 0x068: case 0xE8: // xxperm, xxpermr -@@ -27851,12 +27904,12 @@ DisResult disInstr_PPC_WRK ( - if (dis_vx_conv(theInstr, vsxOpc2)) goto decode_success; - goto decode_failure; - -- case 0x18C: case 0x38C: // xvcmpeqdp[.] -- case 0x10C: case 0x30C: // xvcmpeqsp[.] -- case 0x14C: case 0x34C: // xvcmpgesp[.] -- case 0x12C: case 0x32C: // xvcmpgtsp[.] -- case 0x1CC: case 0x3CC: // xvcmpgedp[.] -- case 0x1AC: case 0x3AC: // xvcmpgtdp[.] -+ case 0x18C: // xvcmpeqdp[.] -+ case 0x10C: // xvcmpeqsp[.] -+ case 0x14C: // xvcmpgesp[.] -+ case 0x12C: // xvcmpgtsp[.] -+ case 0x1CC: // xvcmpgedp[.] -+ case 0x1AC: // xvcmpgtdp[.] - if (dis_vvec_cmp(theInstr, vsxOpc2)) goto decode_success; - goto decode_failure; - diff --git a/SOURCES/valgrind-3.12.0-ppc64-isa-3_00.patch b/SOURCES/valgrind-3.12.0-ppc64-isa-3_00.patch deleted file mode 100644 index b1e9ed4..0000000 --- a/SOURCES/valgrind-3.12.0-ppc64-isa-3_00.patch +++ /dev/null @@ -1,54 +0,0 @@ -PPC64: ISA 3.0 setup fixes. - -There is a typo in the configure.ac file that causes the HAS_ISA_3_00 -variable to not be set. - -The mask64 value is missing the HWCAPS bit for ISA3.0. -bugzilla ---- - VEX/priv/guest_ppc_toIR.c | 2 +- - configure.ac | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c -index 0d27389..6fede61 100644 ---- a/VEX/priv/guest_ppc_toIR.c -+++ b/VEX/priv/guest_ppc_toIR.c -@@ -29122,7 +29122,7 @@ DisResult disInstr_PPC ( IRSB* irsb_IN, - - mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX - | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP -- | VEX_HWCAPS_PPC64_ISA2_07; -+ | VEX_HWCAPS_PPC64_ISA2_07 | VEX_HWCAPS_PPC64_ISA3_0; - - if (mode64) { - vassert((hwcaps_guest & mask32) == 0); -diff --git a/configure.ac b/configure.ac -index 587917b..4c3cc58 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -1537,7 +1537,7 @@ ac_asm_have_isa_3_00=no - AC_MSG_RESULT([no]) - ]) - --AM_CONDITIONAL(HAS_ISA_3_00, test x$ac_asm_have_isa_3_00 = xyes \ -+AM_CONDITIONAL(HAS_ISA_3_00, [test x$ac_asm_have_isa_3_00 = xyes \ - -a x$HWCAP_HAS_ISA_3_00 = xyes]) - - # Check for pthread_create@GLIBC2.0 --- -1.8.3.1 - -Only in valgrind-3.12.0: autom4te.cache -diff -ur valgrind-3.12.0.orig/configure valgrind-3.12.0/configure ---- valgrind-3.12.0.orig/configure 2016-12-16 16:52:17.101832444 +0100 -+++ valgrind-3.12.0/configure 2017-03-28 23:38:32.997776458 +0200 -@@ -8122,7 +8122,7 @@ - rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext - - if test x$ac_asm_have_isa_3_00 = xyes \ -- -a x$HWCAP_HAS_ISA_3_00 = xyes]; then -+ -a x$HWCAP_HAS_ISA_3_00 = xyes; then - HAS_ISA_3_00_TRUE= - HAS_ISA_3_00_FALSE='#' - else diff --git a/SOURCES/valgrind-3.12.0-ppc64-r2.patch b/SOURCES/valgrind-3.12.0-ppc64-r2.patch deleted file mode 100644 index f70043a..0000000 --- a/SOURCES/valgrind-3.12.0-ppc64-r2.patch +++ /dev/null @@ -1,52 +0,0 @@ - - On ppc64*, R2 is the TOC pointer, should not be considered a - scratch register, and thus should not be in the clobber list. - This is called out in newer GCC releases and triggers a - compile time error. - - Thusly, remove R2 from the clobber list. - -diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c -index dc6e26d..be77680 100644 ---- a/coregrind/m_debuglog.c -+++ b/coregrind/m_debuglog.c -@@ -215,7 +215,7 @@ static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - : - : "b" (block) - : "cc","memory","cr0","ctr", -- "r0","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12" -+ "r0","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12" - ); - if (block[0] < 0) - block[0] = -1; -@@ -231,7 +231,7 @@ static UInt local_sys_getpid ( void ) - : "=&r" (__res) - : "i" (__NR_getpid) - : "cc","memory","cr0","ctr", -- "r0","r2","r4","r5","r6","r7","r8","r9","r10","r11","r12" -+ "r0","r4","r5","r6","r7","r8","r9","r10","r11","r12" - ); - return (UInt)__res; - } -diff --git a/include/valgrind.h b/include/valgrind.h -index 6892007..d2e7c38 100644 ---- a/include/valgrind.h -+++ b/include/valgrind.h -@@ -2708,7 +2708,7 @@ typedef - #define __CALLER_SAVED_REGS \ - "lr", "ctr", "xer", \ - "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ -- "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ -+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ - "r11", "r12", "r13" - - /* Macros to save and align the stack before making a function -@@ -3264,7 +3264,7 @@ typedef - #define __CALLER_SAVED_REGS \ - "lr", "ctr", "xer", \ - "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ -- "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ -+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ - "r11", "r12", "r13" - - /* Macros to save and align the stack before making a function diff --git a/SOURCES/valgrind-3.12.0-quick-fatal-sigs.patch b/SOURCES/valgrind-3.12.0-quick-fatal-sigs.patch deleted file mode 100644 index c9133fc..0000000 --- a/SOURCES/valgrind-3.12.0-quick-fatal-sigs.patch +++ /dev/null @@ -1,103 +0,0 @@ -commit eee2c95b91b2fdcb36c0b1a2ab15df4a44ee2986 -Author: philippe -Date: Sat Nov 19 13:51:41 2016 +0000 - - Fix Bug 372600 - process loops forever when fatal signals are arriving quickly - - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16140 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c -index 168b681..b398882 100644 ---- a/coregrind/m_signals.c -+++ b/coregrind/m_signals.c -@@ -2430,8 +2430,14 @@ void async_signalhandler ( Int sigNo, - info->si_code = sanitize_si_code(info->si_code); - - if (VG_(clo_trace_signals)) -- VG_(dmsg)("async signal handler: signal=%d, tid=%u, si_code=%d\n", -- sigNo, tid, info->si_code); -+ VG_(dmsg)("async signal handler: signal=%d, tid=%u, si_code=%d, " -+ "exitreason %s\n", -+ sigNo, tid, info->si_code, -+ VG_(name_of_VgSchedReturnCode)(tst->exitreason)); -+ -+ /* */ -+ if (tst->exitreason == VgSrc_FatalSig) -+ resume_scheduler(tid); - - /* Update thread state properly. The signal can only have been - delivered whilst we were in -@@ -2479,8 +2485,16 @@ void async_signalhandler ( Int sigNo, - ); - - /* (2) */ -- /* Set up the thread's state to deliver a signal */ -- if (!is_sig_ign(info, tid)) -+ /* Set up the thread's state to deliver a signal. -+ However, if exitreason is VgSrc_FatalSig, then thread tid was -+ taken out of a syscall by VG_(nuke_all_threads_except). -+ But after the emission of VKI_SIGKILL, another (fatal) async -+ signal might be sent. In such a case, we must not handle this -+ signal, as the thread is supposed to die first. -+ => resume the scheduler for such a thread, so that the scheduler -+ can let the thread die. */ -+ if (tst->exitreason != VgSrc_FatalSig -+ && !is_sig_ign(info, tid)) - deliver_signal(tid, info, uc); - - /* It's crucial that (1) and (2) happen in the order (1) then (2) -@@ -2946,6 +2960,20 @@ void VG_(poll_signals)(ThreadId tid) - ThreadState *tst = VG_(get_ThreadState)(tid); - vki_sigset_t saved_mask; - -+ if (tst->exitreason == VgSrc_FatalSig) { -+ /* This task has been requested to die due to a fatal signal -+ received by the process. So, we cannot poll new signals, -+ as we are supposed to die asap. If we would poll and deliver -+ a new (maybe fatal) signal, this could cause a deadlock, as -+ this thread would believe it has to terminate the other threads -+ and wait for them to die, while we already have a thread doing -+ that. */ -+ if (VG_(clo_trace_signals)) -+ VG_(dmsg)("poll_signals: not polling as thread %u is exitreason %s\n", -+ tid, VG_(name_of_VgSchedReturnCode)(tst->exitreason)); -+ return; -+ } -+ - /* look for all the signals this thread isn't blocking */ - /* pollset = ~tst->sig_mask */ - VG_(sigcomplementset)( &pollset, &tst->sig_mask ); -@@ -2961,15 +2989,18 @@ void VG_(poll_signals)(ThreadId tid) - /* If there was nothing queued, ask the kernel for a pending signal */ - if (sip == NULL && VG_(sigtimedwait_zero)(&pollset, &si) > 0) { - if (VG_(clo_trace_signals)) -- VG_(dmsg)("poll_signals: got signal %d for thread %u\n", -- si.si_signo, tid); -+ VG_(dmsg)("poll_signals: got signal %d for thread %u exitreason %s\n", -+ si.si_signo, tid, -+ VG_(name_of_VgSchedReturnCode)(tst->exitreason)); - sip = &si; - } - - if (sip != NULL) { - /* OK, something to do; deliver it */ - if (VG_(clo_trace_signals)) -- VG_(dmsg)("Polling found signal %d for tid %u\n", sip->si_signo, tid); -+ VG_(dmsg)("Polling found signal %d for tid %u exitreason %s\n", -+ sip->si_signo, tid, -+ VG_(name_of_VgSchedReturnCode)(tst->exitreason)); - if (!is_sig_ign(sip, tid)) - deliver_signal(tid, sip, NULL); - else if (VG_(clo_trace_signals)) -@@ -3073,7 +3104,8 @@ void VG_(sigstartup_actions) ( void ) - } - - if (VG_(clo_trace_signals)) -- VG_(dmsg)("Max kernel-supported signal is %d\n", VG_(max_signal)); -+ VG_(dmsg)("Max kernel-supported signal is %d, VG_SIGVGKILL is %d\n", -+ VG_(max_signal), VG_SIGVGKILL); - - /* Our private internal signals are treated as ignored */ - scss.scss_per_sig[VG_SIGVGKILL].scss_handler = VKI_SIG_IGN; diff --git a/SOURCES/valgrind-3.12.0-skip-cond-var.patch b/SOURCES/valgrind-3.12.0-skip-cond-var.patch deleted file mode 100644 index ab15928..0000000 --- a/SOURCES/valgrind-3.12.0-skip-cond-var.patch +++ /dev/null @@ -1,190 +0,0 @@ -commit 88cf06207b074f387c04de4938a0bb20366616b0 -Author: mjw -Date: Fri Oct 21 00:02:10 2016 +0000 - - Add libc_test to workaround pth_cond_destroy_busy test hangs. - - This is a workaround for bug #371396. It adds a new test program - that can be used skip tests given a specific libc implementation - and optionally a specific minimum version. Currently only glibc - is recognized. This is used for the drd and helgrind tests - pth_cond_destroy_busy to be skipped on glibc 2.24.90+. - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16097 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/drd/tests/pth_cond_destroy_busy.vgtest b/drd/tests/pth_cond_destroy_busy.vgtest -index eafbd74..f3cf778 100644 ---- a/drd/tests/pth_cond_destroy_busy.vgtest -+++ b/drd/tests/pth_cond_destroy_busy.vgtest -@@ -1,2 +1,2 @@ --prereq: ./supported_libpthread -+prereq: ./supported_libpthread && ! ../../tests/libc_test glibc 2.24.90 - prog: pth_cond_destroy_busy -diff --git a/helgrind/tests/pth_cond_destroy_busy.vgtest b/helgrind/tests/pth_cond_destroy_busy.vgtest -index 45d7853..2957cc3 100644 ---- a/helgrind/tests/pth_cond_destroy_busy.vgtest -+++ b/helgrind/tests/pth_cond_destroy_busy.vgtest -@@ -1,2 +1,2 @@ --prereq: ! ../../tests/os_test darwin -+prereq: ! ../../tests/os_test darwin && ! ../../tests/libc_test glibc 2.24.90 - prog: ../../drd/tests/pth_cond_destroy_busy -diff --git a/tests/Makefile.am b/tests/Makefile.am -index 9c0cc3a..7233626 100644 ---- a/tests/Makefile.am -+++ b/tests/Makefile.am -@@ -44,6 +44,7 @@ noinst_HEADERS = \ - check_PROGRAMS = \ - arch_test \ - os_test \ -+ libc_test \ - true \ - x86_amd64_features \ - s390x_features \ -diff --git a/tests/libc_test.c b/tests/libc_test.c -new file mode 100644 -index 0000000..0de3d5d ---- /dev/null -+++ b/tests/libc_test.c -@@ -0,0 +1,78 @@ -+// Compare given libc name and version number to system name and version. -+ -+// Returns -+// - 0 if the libc name matches is at least the minimum version (if given). -+// - 1 if the libc name doesn't match or the version is lower than requested. -+// - 2 if the requested libc name isn't recognised. -+// - 3 if there was a usage error (it also prints an error message). -+ -+#include -+#include -+#include -+ -+#ifdef __GLIBC__ -+#include -+#endif -+ -+#define False 0 -+#define True 1 -+typedef int Bool; -+ -+/* Assumes the versions are x.y.z, with y and z optional. */ -+static Bool matches_version(char *min_version) { -+ int a1=0, a2=0, a3=0, g1=0, g2=0, g3=0; // 'a' = actual; 'g' = given -+ const char *aversion; -+ -+ if (min_version == NULL) return True; // no version specified -+ -+ // get actual version number -+#ifdef __GLIBC__ -+ aversion = gnu_get_libc_version(); -+#else -+ aversion = "unknown"; -+#endif -+ // We expect at least one number. -+ if (sscanf(aversion, "%d.%d.%d", &a1, &a2, &a3) < 1) return False; -+ -+ // parse given version number. -+ if (sscanf(min_version, "%d.%d.%d", &g1, &g2, &g3) < 1) return False; -+ -+ if (a1 > g1) return True; -+ if (a1 < g1) return False; -+ if (a2 > g2) return True; -+ if (a2 < g2) return False; -+ if (a3 >= g3) return True; -+ -+ return False; -+} -+ -+static Bool go(char* libc, char *min_version) -+{ -+#ifdef __GLIBC__ -+ if ( 0 == strcmp( libc, "glibc" ) -+ && matches_version( min_version )) -+ return True; -+#endif -+ -+ return False; -+} -+ -+//--------------------------------------------------------------------------- -+// main -+//--------------------------------------------------------------------------- -+int main(int argc, char **argv) -+{ -+ if ( argc < 2 ) { -+ fprintf( stderr, "usage: libc_test []\n" ); -+ exit(3); // Usage error. -+ } -+ if (go( argv[1], argv[2] )) { -+ return 0; // Matched. -+ } -+ -+ if ( 0 == strcmp ( argv[1], "glibc" ) ) { -+ return 1; // Requested libc name known, but this isn't it. -+ // Or it wasn't the minimum requested version. -+ } -+ return 2; // Didn't match any known libc name. -+} -Only in valgrind-3.12.0.RC2: autom4te.cache -diff -ur valgrind-3.12.0.RC2.orig/tests/Makefile.in valgrind-3.12.0.RC2/tests/Makefile.in ---- valgrind-3.12.0.RC2.orig/tests/Makefile.in 2016-10-21 02:10:24.283643034 +0200 -+++ valgrind-3.12.0.RC2/tests/Makefile.in 2016-10-21 02:11:09.668003685 +0200 -@@ -121,10 +121,11 @@ - @COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \ - @COMPILER_IS_CLANG_TRUE@ clang 3.0.0 - @COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp --check_PROGRAMS = arch_test$(EXEEXT) os_test$(EXEEXT) true$(EXEEXT) \ -- x86_amd64_features$(EXEEXT) s390x_features$(EXEEXT) \ -- mips_features$(EXEEXT) power_insn_available$(EXEEXT) \ -- is_ppc64_BE$(EXEEXT) min_power_isa$(EXEEXT) -+check_PROGRAMS = arch_test$(EXEEXT) os_test$(EXEEXT) \ -+ libc_test$(EXEEXT) true$(EXEEXT) x86_amd64_features$(EXEEXT) \ -+ s390x_features$(EXEEXT) mips_features$(EXEEXT) \ -+ power_insn_available$(EXEEXT) is_ppc64_BE$(EXEEXT) \ -+ min_power_isa$(EXEEXT) - subdir = tests - ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 - am__aclocal_m4_deps = $(top_srcdir)/configure.ac -@@ -142,6 +143,9 @@ - is_ppc64_BE_SOURCES = is_ppc64_BE.c - is_ppc64_BE_OBJECTS = is_ppc64_BE.$(OBJEXT) - is_ppc64_BE_LDADD = $(LDADD) -+libc_test_SOURCES = libc_test.c -+libc_test_OBJECTS = libc_test.$(OBJEXT) -+libc_test_LDADD = $(LDADD) - min_power_isa_SOURCES = min_power_isa.c - min_power_isa_OBJECTS = min_power_isa-min_power_isa.$(OBJEXT) - min_power_isa_LDADD = $(LDADD) -@@ -201,10 +205,10 @@ - am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@) - am__v_CCLD_0 = @echo " CCLD " $@; - am__v_CCLD_1 = --SOURCES = arch_test.c is_ppc64_BE.c min_power_isa.c mips_features.c \ -- os_test.c power_insn_available.c s390x_features.c true.c \ -- x86_amd64_features.c --DIST_SOURCES = arch_test.c is_ppc64_BE.c min_power_isa.c \ -+SOURCES = arch_test.c is_ppc64_BE.c libc_test.c min_power_isa.c \ -+ mips_features.c os_test.c power_insn_available.c \ -+ s390x_features.c true.c x86_amd64_features.c -+DIST_SOURCES = arch_test.c is_ppc64_BE.c libc_test.c min_power_isa.c \ - mips_features.c os_test.c power_insn_available.c \ - s390x_features.c true.c x86_amd64_features.c - am__can_run_installinfo = \ -@@ -681,6 +685,10 @@ - @rm -f is_ppc64_BE$(EXEEXT) - $(AM_V_CCLD)$(LINK) $(is_ppc64_BE_OBJECTS) $(is_ppc64_BE_LDADD) $(LIBS) - -+libc_test$(EXEEXT): $(libc_test_OBJECTS) $(libc_test_DEPENDENCIES) $(EXTRA_libc_test_DEPENDENCIES) -+ @rm -f libc_test$(EXEEXT) -+ $(AM_V_CCLD)$(LINK) $(libc_test_OBJECTS) $(libc_test_LDADD) $(LIBS) -+ - min_power_isa$(EXEEXT): $(min_power_isa_OBJECTS) $(min_power_isa_DEPENDENCIES) $(EXTRA_min_power_isa_DEPENDENCIES) - @rm -f min_power_isa$(EXEEXT) - $(AM_V_CCLD)$(min_power_isa_LINK) $(min_power_isa_OBJECTS) $(min_power_isa_LDADD) $(LIBS) -@@ -717,6 +725,7 @@ - - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arch_test.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is_ppc64_BE.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libc_test.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/min_power_isa-min_power_isa.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mips_features.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/os_test.Po@am__quote@ diff --git a/SOURCES/valgrind-3.12.0-tests-cxx11_abi_0.patch b/SOURCES/valgrind-3.12.0-tests-cxx11_abi_0.patch deleted file mode 100644 index 271ed6b..0000000 --- a/SOURCES/valgrind-3.12.0-tests-cxx11_abi_0.patch +++ /dev/null @@ -1,85 +0,0 @@ -commit 4e66d0f7ca6ef2cac6c303e761af605c82b78456 -Author: petarj -Date: Tue Jan 31 18:22:20 2017 +0000 - - force old implementation of std::string for leak_cpp_interior test - - This patch forces leak_cpp_interior to be compiled using old implementation - of std::string. - - Related issue #373069 - - Patch by Aleksandar Rikalo. - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16217 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/memcheck/tests/leak_cpp_interior.cpp b/memcheck/tests/leak_cpp_interior.cpp -index f66fc89..a4b4824 100644 ---- a/memcheck/tests/leak_cpp_interior.cpp -+++ b/memcheck/tests/leak_cpp_interior.cpp -@@ -1,3 +1,4 @@ -+#define _GLIBCXX_USE_CXX11_ABI 0 - #define __STDC_FORMAT_MACROS - #include - #include -diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp b/memcheck/tests/leak_cpp_interior.stderr.exp -index 3228f74..70e2764 100644 ---- a/memcheck/tests/leak_cpp_interior.stderr.exp -+++ b/memcheck/tests/leak_cpp_interior.stderr.exp -@@ -2,8 +2,8 @@ - valgrind output will go to log - VALGRIND_DO_LEAK_CHECK - 4 bytes in 1 blocks are definitely lost in loss record ... of ... -- by 0x........: doit() (leak_cpp_interior.cpp:115) -- by 0x........: main (leak_cpp_interior.cpp:130) -+ by 0x........: doit() (leak_cpp_interior.cpp:116) -+ by 0x........: main (leak_cpp_interior.cpp:131) - - LEAK SUMMARY: - definitely lost: 4 bytes in 1 blocks -diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit -index 7a862a3..612fa3e 100644 ---- a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit -+++ b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit -@@ -2,8 +2,8 @@ - valgrind output will go to log - VALGRIND_DO_LEAK_CHECK - 8 bytes in 1 blocks are definitely lost in loss record ... of ... -- by 0x........: doit() (leak_cpp_interior.cpp:115) -- by 0x........: main (leak_cpp_interior.cpp:130) -+ by 0x........: doit() (leak_cpp_interior.cpp:116) -+ by 0x........: main (leak_cpp_interior.cpp:131) - - LEAK SUMMARY: - definitely lost: 8 bytes in 1 blocks -diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris -index d53e4ce..f7e1a07 100644 ---- a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris -+++ b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris -@@ -2,8 +2,8 @@ - valgrind output will go to log - VALGRIND_DO_LEAK_CHECK - 8 bytes in 1 blocks are definitely lost in loss record ... of ... -- by 0x........: doit() (leak_cpp_interior.cpp:115) -- by 0x........: main (leak_cpp_interior.cpp:130) -+ by 0x........: doit() (leak_cpp_interior.cpp:116) -+ by 0x........: main (leak_cpp_interior.cpp:131) - - LEAK SUMMARY: - definitely lost: 8 bytes in 1 blocks -diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp-solaris b/memcheck/tests/leak_cpp_interior.stderr.exp-solaris -index 80cd5c3..f9fc390 100644 ---- a/memcheck/tests/leak_cpp_interior.stderr.exp-solaris -+++ b/memcheck/tests/leak_cpp_interior.stderr.exp-solaris -@@ -2,8 +2,8 @@ - valgrind output will go to log - VALGRIND_DO_LEAK_CHECK - 4 bytes in 1 blocks are definitely lost in loss record ... of ... -- by 0x........: doit() (leak_cpp_interior.cpp:115) -- by 0x........: main (leak_cpp_interior.cpp:130) -+ by 0x........: doit() (leak_cpp_interior.cpp:116) -+ by 0x........: main (leak_cpp_interior.cpp:131) - - LEAK SUMMARY: - definitely lost: 4 bytes in 1 blocks diff --git a/SOURCES/valgrind-3.12.0-x86-gdt-and-ss.patch b/SOURCES/valgrind-3.12.0-x86-gdt-and-ss.patch deleted file mode 100644 index fbaf984..0000000 --- a/SOURCES/valgrind-3.12.0-x86-gdt-and-ss.patch +++ /dev/null @@ -1,139 +0,0 @@ -commit c7bcd1f2ee2d466fb556bfc2b33c5ab039b0898d -Author: sewardj -Date: Fri Jan 20 09:58:15 2017 +0000 - - x86-linux: Initialize x86 system GDT on first use. Bug 344139 comment 3. - Patch from Sebastian Lackner, sebastian@fds-team.de. - - - git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16204 a5019735-40e9-0310-863c-91ae7b9d1cf9 - -diff --git a/coregrind/m_syswrap/syswrap-x86-linux.c b/coregrind/m_syswrap/syswrap-x86-linux.c -index f8c4eb4..2f879d8 100644 ---- a/coregrind/m_syswrap/syswrap-x86-linux.c -+++ b/coregrind/m_syswrap/syswrap-x86-linux.c -@@ -294,11 +294,37 @@ void translate_to_hw_format ( /* IN */ vki_modify_ldt_t* inn, - out->LdtEnt.Words.word2 = entry_2; - } - --/* Create a zeroed-out GDT. */ --static VexGuestX86SegDescr* alloc_zeroed_x86_GDT ( void ) -+/* Create initial GDT. */ -+static VexGuestX86SegDescr* alloc_system_x86_GDT ( void ) - { - Int nbytes = VEX_GUEST_X86_GDT_NENT * sizeof(VexGuestX86SegDescr); -- return VG_(calloc)("di.syswrap-x86.azxG.1", nbytes, 1); -+ VexGuestX86SegDescr* gdt = VG_(calloc)("di.syswrap-x86.azxG.1", nbytes, 1); -+ vki_modify_ldt_t info; -+ UShort seg; -+ -+ VG_(memset)(&info, 0, sizeof(info)); -+ info.entry_number = 0; -+ info.base_addr = 0; -+ info.limit = 0xfffff; -+ info.seg_32bit = 1; -+ info.contents = 0; -+ info.read_exec_only = 0; -+ info.limit_in_pages = 1; -+ info.seg_not_present = 0; -+ info.useable = 0; -+ info.reserved = 0; -+ -+ asm volatile("movw %%ds, %0" : : "m" (seg)); -+ if (!(seg & 4)) translate_to_hw_format(&info, &gdt[seg >> 3], 0); -+ asm volatile("movw %%ss, %0" : : "m" (seg)); -+ if (!(seg & 4)) translate_to_hw_format(&info, &gdt[seg >> 3], 0); -+ -+ info.contents = 2; -+ -+ asm volatile("movw %%cs, %0" : : "m" (seg)); -+ if (!(seg & 4)) translate_to_hw_format(&info, &gdt[seg >> 3], 0); -+ -+ return gdt; - } - - /* Create a zeroed-out LDT. */ -@@ -505,7 +531,7 @@ SysRes ML_(x86_sys_set_thread_area) ( ThreadId tid, vki_modify_ldt_t* info ) - - /* If the thread doesn't have a GDT, allocate it now. */ - if (!gdt) { -- gdt = alloc_zeroed_x86_GDT(); -+ gdt = alloc_system_x86_GDT(); - VG_(threads)[tid].arch.vex.guest_GDT = (HWord)gdt; - } - -@@ -564,7 +590,7 @@ static SysRes sys_get_thread_area ( ThreadId tid, vki_modify_ldt_t* info ) - - /* If the thread doesn't have a GDT, allocate it now. */ - if (!gdt) { -- gdt = alloc_zeroed_x86_GDT(); -+ gdt = alloc_system_x86_GDT(); - VG_(threads)[tid].arch.vex.guest_GDT = (HWord)gdt; - } - -@@ -616,7 +642,7 @@ void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child, - child->vex.guest_GDT = (HWord)NULL; - - if (parent->vex.guest_GDT != (HWord)NULL) { -- child->vex.guest_GDT = (HWord)alloc_zeroed_x86_GDT(); -+ child->vex.guest_GDT = (HWord)alloc_system_x86_GDT(); - copy_GDT_from_to( (VexGuestX86SegDescr*)parent->vex.guest_GDT, - (VexGuestX86SegDescr*)child->vex.guest_GDT ); - } -commit 5f4041b376f7465cd108ad4d1696b0b8a603a175 -Author: sewardj -Date: Fri Jan 20 10:01:42 2017 +0000 - - x86: Recognize the SS segment prefix on x86. Bug 344139 comment 4. - Patch from Sebastian Lackner, sebastian@fds-team.de. - - - git-svn-id: svn://svn.valgrind.org/vex/trunk@3299 8f6e269a-dfd6-0310-a8e1-e2731360e62c - -diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c -index de09d3a..234d68e 100644 ---- a/VEX/priv/guest_x86_toIR.c -+++ b/VEX/priv/guest_x86_toIR.c -@@ -1409,6 +1409,7 @@ const HChar* sorbTxt ( UChar sorb ) - case 0x26: return "%es:"; - case 0x64: return "%fs:"; - case 0x65: return "%gs:"; -+ case 0x36: return "%ss:"; - default: vpanic("sorbTxt(x86,guest)"); - } - } -@@ -1433,6 +1434,7 @@ IRExpr* handleSegOverride ( UChar sorb, IRExpr* virtual ) - case 0x26: sreg = R_ES; break; - case 0x64: sreg = R_FS; break; - case 0x65: sreg = R_GS; break; -+ case 0x36: sreg = R_SS; break; - default: vpanic("handleSegOverride(x86,guest)"); - } - -@@ -8101,7 +8103,7 @@ DisResult disInstr_X86_WRK ( - Int sz = 4; - - /* sorb holds the segment-override-prefix byte, if any. Zero if no -- prefix has been seen, else one of {0x26, 0x3E, 0x64, 0x65} -+ prefix has been seen, else one of {0x26, 0x36, 0x3E, 0x64, 0x65} - indicating the prefix. */ - UChar sorb = 0; - -@@ -8255,6 +8257,7 @@ DisResult disInstr_X86_WRK ( - case 0x26: /* %ES: */ - case 0x64: /* %FS: */ - case 0x65: /* %GS: */ -+ case 0x36: /* %SS: */ - if (sorb != 0) - goto decode_failure; /* only one seg override allowed */ - sorb = pre; -@@ -8274,9 +8277,6 @@ DisResult disInstr_X86_WRK ( - } - break; - } -- case 0x36: /* %SS: */ -- /* SS override cases are not handled */ -- goto decode_failure; - default: - goto not_a_prefix; - } diff --git a/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch b/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch new file mode 100644 index 0000000..c2cef5a --- /dev/null +++ b/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch @@ -0,0 +1,2104 @@ +commit 4c8c3af18adc0a202d0e342b8ca3731a5b724a1d +Author: Tom Hughes +Date: Wed Aug 30 19:26:37 2017 +0100 + + Fix eflags handling in amd64 instruction tests + + In 64 bit mode there's no way to just save eflags so we save the + whole of rflags but we were doing so to a 32 bit variable! + + Replace that with proper rflags support that knows it is dealing + with the full 64 bit flags word in 64 bit mode. + +diff --git a/none/tests/amd64/gen_insn_test.pl b/none/tests/amd64/gen_insn_test.pl +index 863e560..a144ec4 100644 +--- a/none/tests/amd64/gen_insn_test.pl ++++ b/none/tests/amd64/gen_insn_test.pl +@@ -16,7 +16,7 @@ our %ArgTypes = ( + m32 => "reg32_t", + m64 => "reg64_t", + m128 => "reg128_t", +- eflags => "reg32_t", ++ rflags => "reg64_t", + st => "reg64_t", + fpucw => "reg16_t", + fpusw => "reg16_t" +@@ -222,8 +222,8 @@ while (<>) + + my @presets; + my $presetc = 0; +- my $eflagsmask; +- my $eflagsset; ++ my $rflagsmask; ++ my $rflagsset; + my $fpucwmask; + my $fpucwset; + my $fpuswmask; +@@ -305,7 +305,7 @@ while (<>) + + $presetc++; + } +- elsif ($preset =~ /^(eflags)\[([^\]]+)\]$/) ++ elsif ($preset =~ /^(rflags)\[([^\]]+)\]$/) + { + my $type = $1; + my @values = split(/,/, $2); +@@ -313,8 +313,8 @@ while (<>) + $values[0] = oct($values[0]) if $values[0] =~ /^0/; + $values[1] = oct($values[1]) if $values[1] =~ /^0/; + +- $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff; +- $eflagsset = sprintf "0x%08x", $values[1]; ++ $rflagsmask = sprintf "0x%016x", ~$values[0]; ++ $rflagsset = sprintf "0x%016x", $values[1]; + } + elsif ($preset =~ /^(fpucw)\[([^\]]+)\]$/) + { +@@ -544,7 +544,7 @@ while (<>) + + print qq| $ArgTypes{$type} $name;\n|; + } +- elsif ($result =~ /^eflags\[([^\]]+)\]$/) ++ elsif ($result =~ /^rflags\[([^\]]+)\]$/) + { + my @values = split(/,/, $1); + +@@ -553,19 +553,19 @@ while (<>) + + my $result = { + name => $name, +- type => "eflags", +- subtype => "ud", +- values => [ map { sprintf "0x%08x", $_ } @values ] ++ type => "rflags", ++ subtype => "uq", ++ values => [ map { sprintf "0x%016x", $_ } @values ] + }; + + push @results, $result; + +- print qq| $ArgTypes{eflags} $name;\n|; ++ print qq| $ArgTypes{rflags} $name;\n|; + +- if (!defined($eflagsmask) && !defined($eflagsset)) ++ if (!defined($rflagsmask) && !defined($rflagsset)) + { +- $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff; +- $eflagsset = sprintf "0x%08x", $values[0] & ~$values[1]; ++ $rflagsmask = sprintf "0x%016x", ~$values[0]; ++ $rflagsset = sprintf "0x%016x", $values[0] & ~$values[1]; + } + } + elsif ($result =~ /^fpucw\[([^\]]+)\]$/) +@@ -722,12 +722,11 @@ while (<>) + } + } + +- if (defined($eflagsmask) || defined($eflagsset)) ++ if (defined($rflagsmask) || defined($rflagsset)) + { + print qq| \"pushfq\\n\"\n|; +- print qq| \"andl \$$eflagsmask, (%%rsp)\\n\"\n| if defined($eflagsmask); +- print qq| \"andl \$0, 4(%%rsp)\\n\"\n| if defined($eflagsmask); +- print qq| \"orq \$$eflagsset, (%%rsp)\\n\"\n| if defined($eflagsset); ++ print qq| \"andq \$$rflagsmask, (%%rsp)\\n\"\n| if defined($rflagsmask); ++ print qq| \"orq \$$rflagsset, (%%rsp)\\n\"\n| if defined($rflagsset); + print qq| \"popfq\\n\"\n|; + } + +@@ -747,7 +746,7 @@ while (<>) + + foreach my $arg (@args) + { +- next if $arg->{type} eq "eflags"; ++ next if $arg->{type} eq "rflags"; + + if ($arg->{type} =~ /^(r8|r16|r32|r64|mm|xmm)$/) + { +@@ -815,7 +814,7 @@ while (<>) + { + $fpresults[$RegNums{$result->{register}}] = $result; + } +- elsif ($result->{type} eq "eflags") ++ elsif ($result->{type} eq "rflags") + { + print qq| \"pushfq\\n\"\n|; + print qq| \"popq %$result->{argnum}\\n\"\n|; +@@ -925,9 +924,9 @@ while (<>) + my $suffix = $SubTypeSuffixes{$subtype}; + my @values = @{$result->{values}}; + +- if ($type eq "eflags") ++ if ($type eq "rflags") + { +- print qq|${prefix}\($result->{name}.ud[0] & $values[0]UL\) == $values[1]UL|; ++ print qq|${prefix}\($result->{name}.uq[0] & $values[0]UL\) == $values[1]UL|; + } + elsif ($type =~ /^fpu[cs]w$/) + { +@@ -972,9 +971,9 @@ while (<>) + my $suffix = $SubTypeSuffixes{$subtype}; + my @values = @{$result->{values}}; + +- if ($type eq "eflags") ++ if ($type eq "rflags") + { +- print qq| printf(" eflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|; ++ print qq| printf(" rflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|; + } + elsif ($type =~ /^fpu[cs]w$/) + { +diff --git a/none/tests/amd64/insn_basic.def b/none/tests/amd64/insn_basic.def +index 8b10da1..c3bef75 100644 +--- a/none/tests/amd64/insn_basic.def ++++ b/none/tests/amd64/insn_basic.def +@@ -1,57 +1,57 @@ +-adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47] +-###adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] +-###adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] +-adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] +-adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] +-###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] +-###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913] +-adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] +-adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] +-###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] +-###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] +-adcq eflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333] +-adcq eflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334] +-###adcq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999] +-###adcq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000] +-adcq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999] +-adcq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000] +-adcq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999] +-adcq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000] +-adcq eflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] +-adcq eflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] +-adcq eflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999] +-adcq eflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000] +-adcq eflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] +-adcq eflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] ++adcb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47] ++###adcb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] ++###adcb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] ++adcw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] ++adcw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] ++###adcw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] ++###adcw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913] ++adcl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] ++adcl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] ++###adcl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] ++###adcl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] ++adcq rflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333] ++adcq rflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334] ++###adcq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999] ++###adcq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000] ++adcq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999] ++adcq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000] ++adcq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999] ++adcq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000] ++adcq rflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] ++adcq rflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] ++adcq rflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999] ++adcq rflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000] ++adcq rflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] ++adcq rflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] + addb imm8[12] al.ub[34] => 1.ub[46] + addb imm8[12] bl.ub[34] => 1.ub[46] + addb imm8[12] m8.ub[34] => 1.ub[46] +@@ -123,430 +123,430 @@ bsrq r64.uq[0x1357246813572468] r64.uq[0] => 1.uq[60] + bsrq m64.uq[0x7531864275318642] r64.uq[0] => 1.uq[62] + bswapl r32.ud[0x12345678] => 0.ud[0x78563412] + bswapq r64.uq[0x1234567813572468] => 0.uq[0x6824571378563412] +-btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] ++btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] + cbw al.sb[123] : => ax.sw[123] + cbw al.sb[-123] : => ax.sw[-123] + cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678] + cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98] + cdqe eax.ud[0x12345678] : => rax.uq[0x0000000012345678] + cdqe eax.ud[0xfedcba98] : => rax.uq[0xfffffffffedcba98] +-###clc eflags[0x001,0x000] : => eflags[0x001,0x000] +-###clc eflags[0x001,0x001] : => eflags[0x001,0x000] +-cld eflags[0x400,0x000] : => eflags[0x400,0x000] +-cld eflags[0x400,0x400] : => eflags[0x400,0x000] +-###cmc eflags[0x001,0x000] : => eflags[0x001,0x001] +-###cmc eflags[0x001,0x001] : => eflags[0x001,0x000] +-cmpb imm8[3] al.ub[2] => eflags[0x010,0x010] +-cmpb imm8[2] al.ub[3] => eflags[0x010,0x000] +-cmpb imm8[12] al.ub[12] => eflags[0x044,0x044] +-cmpb imm8[12] al.ub[34] => eflags[0x044,0x000] +-cmpb imm8[34] al.ub[12] => eflags[0x081,0x081] +-cmpb imm8[12] al.ub[34] => eflags[0x081,0x000] +-cmpb imm8[100] al.sb[-100] => eflags[0x800,0x800] +-cmpb imm8[50] al.sb[-50] => eflags[0x800,0x000] +-cmpb imm8[-50] al.sb[50] => eflags[0x800,0x000] +-cmpb imm8[-100] al.sb[100] => eflags[0x800,0x800] +-cmpb imm8[3] r8.ub[2] => eflags[0x010,0x010] +-cmpb imm8[2] r8.ub[3] => eflags[0x010,0x000] +-cmpb imm8[12] r8.ub[12] => eflags[0x044,0x044] +-cmpb imm8[12] r8.ub[34] => eflags[0x044,0x000] +-cmpb imm8[34] r8.ub[12] => eflags[0x081,0x081] +-cmpb imm8[12] r8.ub[34] => eflags[0x081,0x000] +-cmpb imm8[100] r8.sb[-100] => eflags[0x800,0x800] +-cmpb imm8[50] r8.sb[-50] => eflags[0x800,0x000] +-cmpb imm8[-50] r8.sb[50] => eflags[0x800,0x000] +-cmpb imm8[-100] r8.sb[100] => eflags[0x800,0x800] +-cmpb imm8[3] m8.ub[2] => eflags[0x010,0x010] +-cmpb imm8[2] m8.ub[3] => eflags[0x010,0x000] +-cmpb imm8[12] m8.ub[12] => eflags[0x044,0x044] +-cmpb imm8[12] m8.ub[34] => eflags[0x044,0x000] +-cmpb imm8[34] m8.ub[12] => eflags[0x081,0x081] +-cmpb imm8[12] m8.ub[34] => eflags[0x081,0x000] +-cmpb imm8[100] m8.sb[-100] => eflags[0x800,0x800] +-cmpb imm8[50] m8.sb[-50] => eflags[0x800,0x000] +-cmpb imm8[-50] m8.sb[50] => eflags[0x800,0x000] +-cmpb imm8[-100] m8.sb[100] => eflags[0x800,0x800] +-cmpb r8.ub[3] r8.ub[2] => eflags[0x010,0x010] +-cmpb r8.ub[2] r8.ub[3] => eflags[0x010,0x000] +-cmpb r8.ub[12] r8.ub[12] => eflags[0x044,0x044] +-cmpb r8.ub[12] r8.ub[34] => eflags[0x044,0x000] +-cmpb r8.ub[34] r8.ub[12] => eflags[0x081,0x081] +-cmpb r8.ub[12] r8.ub[34] => eflags[0x081,0x000] +-cmpb r8.ub[100] r8.sb[-100] => eflags[0x800,0x800] +-cmpb r8.ub[50] r8.sb[-50] => eflags[0x800,0x000] +-cmpb r8.sb[-50] r8.sb[50] => eflags[0x800,0x000] +-cmpb r8.sb[-100] r8.sb[100] => eflags[0x800,0x800] +-cmpb r8.ub[3] m8.ub[2] => eflags[0x010,0x010] +-cmpb r8.ub[2] m8.ub[3] => eflags[0x010,0x000] +-cmpb r8.ub[12] m8.ub[12] => eflags[0x044,0x044] +-cmpb r8.ub[12] m8.ub[34] => eflags[0x044,0x000] +-cmpb r8.ub[34] m8.ub[12] => eflags[0x081,0x081] +-cmpb r8.ub[12] m8.ub[34] => eflags[0x081,0x000] +-cmpb r8.ub[100] m8.sb[-100] => eflags[0x800,0x800] +-cmpb r8.ub[50] m8.sb[-50] => eflags[0x800,0x000] +-cmpb r8.sb[-50] m8.sb[50] => eflags[0x800,0x000] +-cmpb r8.sb[-100] m8.sb[100] => eflags[0x800,0x800] +-cmpb m8.ub[3] r8.ub[2] => eflags[0x010,0x010] +-cmpb m8.ub[2] r8.ub[3] => eflags[0x010,0x000] +-cmpb m8.ub[12] r8.ub[12] => eflags[0x044,0x044] +-cmpb m8.ub[12] r8.ub[34] => eflags[0x044,0x000] +-cmpb m8.ub[34] r8.ub[12] => eflags[0x081,0x081] +-cmpb m8.ub[12] r8.ub[34] => eflags[0x081,0x000] +-cmpb m8.ub[100] r8.sb[-100] => eflags[0x800,0x800] +-cmpb m8.ub[50] r8.sb[-50] => eflags[0x800,0x000] +-cmpb m8.sb[-50] r8.sb[50] => eflags[0x800,0x000] +-cmpb m8.sb[-100] r8.sb[100] => eflags[0x800,0x800] +-cmpw imm8[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw imm8[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw imm8[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw imm8[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw imm8[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw imm8[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw imm8[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm8[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw imm8[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw imm8[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpw imm8[3] m16.uw[2] => eflags[0x010,0x010] +-cmpw imm8[2] m16.uw[3] => eflags[0x010,0x000] +-cmpw imm8[12] m16.uw[12] => eflags[0x044,0x044] +-cmpw imm8[12] m16.uw[34] => eflags[0x044,0x000] +-cmpw imm8[34] m16.uw[12] => eflags[0x081,0x081] +-cmpw imm8[12] m16.uw[34] => eflags[0x081,0x000] +-cmpw imm8[100] m16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm8[50] m16.sw[-50] => eflags[0x800,0x000] +-cmpw imm8[-50] m16.sw[50] => eflags[0x800,0x000] +-cmpw imm8[-100] m16.sw[32700] => eflags[0x800,0x800] +-cmpw imm16[3] ax.uw[2] => eflags[0x010,0x010] +-cmpw imm16[2] ax.uw[3] => eflags[0x010,0x000] +-cmpw imm16[12] ax.uw[12] => eflags[0x044,0x044] +-cmpw imm16[12] ax.uw[34] => eflags[0x044,0x000] +-cmpw imm16[34] ax.uw[12] => eflags[0x081,0x081] +-cmpw imm16[12] ax.uw[34] => eflags[0x081,0x000] +-cmpw imm16[100] ax.sw[-32700] => eflags[0x800,0x800] +-cmpw imm16[50] ax.sw[-50] => eflags[0x800,0x000] +-cmpw imm16[-50] ax.sw[50] => eflags[0x800,0x000] +-cmpw imm16[-100] ax.sw[32700] => eflags[0x800,0x800] +-cmpw imm16[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw imm16[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw imm16[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw imm16[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw imm16[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw imm16[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw imm16[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm16[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw imm16[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw imm16[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpw imm16[3] m16.uw[2] => eflags[0x010,0x010] +-cmpw imm16[2] m16.uw[3] => eflags[0x010,0x000] +-cmpw imm16[12] m16.uw[12] => eflags[0x044,0x044] +-cmpw imm16[12] m16.uw[34] => eflags[0x044,0x000] +-cmpw imm16[34] m16.uw[12] => eflags[0x081,0x081] +-cmpw imm16[12] m16.uw[34] => eflags[0x081,0x000] +-cmpw imm16[100] m16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm16[50] m16.sw[-50] => eflags[0x800,0x000] +-cmpw imm16[-50] m16.sw[50] => eflags[0x800,0x000] +-cmpw imm16[-100] m16.sw[32700] => eflags[0x800,0x800] +-cmpw r16.uw[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw r16.uw[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw r16.uw[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw r16.uw[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw r16.uw[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw r16.uw[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw r16.uw[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw r16.uw[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw r16.sw[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw r16.sw[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpw r16.uw[3] m16.uw[2] => eflags[0x010,0x010] +-cmpw r16.uw[2] m16.uw[3] => eflags[0x010,0x000] +-cmpw r16.uw[12] m16.uw[12] => eflags[0x044,0x044] +-cmpw r16.uw[12] m16.uw[34] => eflags[0x044,0x000] +-cmpw r16.uw[34] m16.uw[12] => eflags[0x081,0x081] +-cmpw r16.uw[12] m16.uw[34] => eflags[0x081,0x000] +-cmpw r16.uw[100] m16.sw[-32700] => eflags[0x800,0x800] +-cmpw r16.uw[50] m16.sw[-50] => eflags[0x800,0x000] +-cmpw r16.sw[-50] m16.sw[50] => eflags[0x800,0x000] +-cmpw r16.sw[-100] m16.sw[32700] => eflags[0x800,0x800] +-cmpw m16.uw[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw m16.uw[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw m16.uw[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw m16.uw[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw m16.uw[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw m16.uw[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw m16.uw[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw m16.uw[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw m16.sw[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw m16.sw[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044] +-###cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000] +-cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010] +-cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000] +-cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044] +-cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000] +-cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081] +-cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000] +-cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000] +-cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000] +-cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010] +-cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000] +-cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044] +-cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000] +-cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081] +-cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000] +-cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000] +-cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000] +-cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044] +-cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000] +-cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010] +-cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000] +-cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044] +-cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000] +-cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081] +-cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000] +-cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000] +-cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000] +-cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044] +-cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000] +-cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010] +-cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000] +-cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044] +-cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000] +-cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081] +-cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000] +-cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000] +-cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000] +-cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800] +-cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044] +-cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000] +-###cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpq imm8[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq imm8[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq imm8[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq imm8[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq imm8[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq imm8[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq imm8[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm8[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq imm8[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq imm8[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm8[3] m64.uq[2] => eflags[0x010,0x010] +-cmpq imm8[2] m64.uq[3] => eflags[0x010,0x000] +-cmpq imm8[12] m64.uq[12] => eflags[0x044,0x044] +-cmpq imm8[12] m64.uq[34] => eflags[0x044,0x000] +-cmpq imm8[34] m64.uq[12] => eflags[0x081,0x081] +-cmpq imm8[12] m64.uq[34] => eflags[0x081,0x000] +-cmpq imm8[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm8[50] m64.sq[-50] => eflags[0x800,0x000] +-cmpq imm8[-50] m64.sq[50] => eflags[0x800,0x000] +-cmpq imm8[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[3] rax.uq[2] => eflags[0x010,0x010] +-cmpq imm32[2] rax.uq[3] => eflags[0x010,0x000] +-cmpq imm32[12] rax.uq[12] => eflags[0x044,0x044] +-cmpq imm32[12] rax.uq[34] => eflags[0x044,0x000] +-cmpq imm32[34] rax.uq[12] => eflags[0x081,0x081] +-cmpq imm32[12] rax.uq[34] => eflags[0x081,0x000] +-cmpq imm32[100] rax.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[50] rax.sq[-50] => eflags[0x800,0x000] +-cmpq imm32[-50] rax.sq[50] => eflags[0x800,0x000] +-cmpq imm32[-100] rax.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq imm32[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq imm32[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq imm32[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq imm32[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq imm32[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq imm32[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq imm32[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq imm32[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[3] m64.uq[2] => eflags[0x010,0x010] +-cmpq imm32[2] m64.uq[3] => eflags[0x010,0x000] +-cmpq imm32[12] m64.uq[12] => eflags[0x044,0x044] +-cmpq imm32[12] m64.uq[34] => eflags[0x044,0x000] +-cmpq imm32[34] m64.uq[12] => eflags[0x081,0x081] +-cmpq imm32[12] m64.uq[34] => eflags[0x081,0x000] +-cmpq imm32[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[50] m64.sq[-50] => eflags[0x800,0x000] +-cmpq imm32[-50] m64.sq[50] => eflags[0x800,0x000] +-cmpq imm32[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq r64.uq[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq r64.uq[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq r64.uq[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq r64.uq[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq r64.uq[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq r64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq r64.sq[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq r64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[3] m64.uq[2] => eflags[0x010,0x010] +-cmpq r64.uq[2] m64.uq[3] => eflags[0x010,0x000] +-cmpq r64.uq[12] m64.uq[12] => eflags[0x044,0x044] +-cmpq r64.uq[12] m64.uq[34] => eflags[0x044,0x000] +-cmpq r64.uq[34] m64.uq[12] => eflags[0x081,0x081] +-cmpq r64.uq[12] m64.uq[34] => eflags[0x081,0x000] +-cmpq r64.uq[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[50] m64.sq[-50] => eflags[0x800,0x000] +-cmpq r64.sq[-50] m64.sq[50] => eflags[0x800,0x000] +-cmpq r64.sq[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq m64.uq[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq m64.uq[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq m64.uq[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq m64.uq[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq m64.uq[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq m64.uq[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq m64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq m64.uq[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq m64.sq[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq m64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] +-###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] +-###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] +-###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] +-###cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] +-###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] +-cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] +-###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] +-###cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] +-###cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] +-cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] +-cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] +-###cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] +-###cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] +-cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] +-cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] ++###clc rflags[0x001,0x000] : => rflags[0x001,0x000] ++###clc rflags[0x001,0x001] : => rflags[0x001,0x000] ++cld rflags[0x400,0x000] : => rflags[0x400,0x000] ++cld rflags[0x400,0x400] : => rflags[0x400,0x000] ++###cmc rflags[0x001,0x000] : => rflags[0x001,0x001] ++###cmc rflags[0x001,0x001] : => rflags[0x001,0x000] ++cmpb imm8[3] al.ub[2] => rflags[0x010,0x010] ++cmpb imm8[2] al.ub[3] => rflags[0x010,0x000] ++cmpb imm8[12] al.ub[12] => rflags[0x044,0x044] ++cmpb imm8[12] al.ub[34] => rflags[0x044,0x000] ++cmpb imm8[34] al.ub[12] => rflags[0x081,0x081] ++cmpb imm8[12] al.ub[34] => rflags[0x081,0x000] ++cmpb imm8[100] al.sb[-100] => rflags[0x800,0x800] ++cmpb imm8[50] al.sb[-50] => rflags[0x800,0x000] ++cmpb imm8[-50] al.sb[50] => rflags[0x800,0x000] ++cmpb imm8[-100] al.sb[100] => rflags[0x800,0x800] ++cmpb imm8[3] r8.ub[2] => rflags[0x010,0x010] ++cmpb imm8[2] r8.ub[3] => rflags[0x010,0x000] ++cmpb imm8[12] r8.ub[12] => rflags[0x044,0x044] ++cmpb imm8[12] r8.ub[34] => rflags[0x044,0x000] ++cmpb imm8[34] r8.ub[12] => rflags[0x081,0x081] ++cmpb imm8[12] r8.ub[34] => rflags[0x081,0x000] ++cmpb imm8[100] r8.sb[-100] => rflags[0x800,0x800] ++cmpb imm8[50] r8.sb[-50] => rflags[0x800,0x000] ++cmpb imm8[-50] r8.sb[50] => rflags[0x800,0x000] ++cmpb imm8[-100] r8.sb[100] => rflags[0x800,0x800] ++cmpb imm8[3] m8.ub[2] => rflags[0x010,0x010] ++cmpb imm8[2] m8.ub[3] => rflags[0x010,0x000] ++cmpb imm8[12] m8.ub[12] => rflags[0x044,0x044] ++cmpb imm8[12] m8.ub[34] => rflags[0x044,0x000] ++cmpb imm8[34] m8.ub[12] => rflags[0x081,0x081] ++cmpb imm8[12] m8.ub[34] => rflags[0x081,0x000] ++cmpb imm8[100] m8.sb[-100] => rflags[0x800,0x800] ++cmpb imm8[50] m8.sb[-50] => rflags[0x800,0x000] ++cmpb imm8[-50] m8.sb[50] => rflags[0x800,0x000] ++cmpb imm8[-100] m8.sb[100] => rflags[0x800,0x800] ++cmpb r8.ub[3] r8.ub[2] => rflags[0x010,0x010] ++cmpb r8.ub[2] r8.ub[3] => rflags[0x010,0x000] ++cmpb r8.ub[12] r8.ub[12] => rflags[0x044,0x044] ++cmpb r8.ub[12] r8.ub[34] => rflags[0x044,0x000] ++cmpb r8.ub[34] r8.ub[12] => rflags[0x081,0x081] ++cmpb r8.ub[12] r8.ub[34] => rflags[0x081,0x000] ++cmpb r8.ub[100] r8.sb[-100] => rflags[0x800,0x800] ++cmpb r8.ub[50] r8.sb[-50] => rflags[0x800,0x000] ++cmpb r8.sb[-50] r8.sb[50] => rflags[0x800,0x000] ++cmpb r8.sb[-100] r8.sb[100] => rflags[0x800,0x800] ++cmpb r8.ub[3] m8.ub[2] => rflags[0x010,0x010] ++cmpb r8.ub[2] m8.ub[3] => rflags[0x010,0x000] ++cmpb r8.ub[12] m8.ub[12] => rflags[0x044,0x044] ++cmpb r8.ub[12] m8.ub[34] => rflags[0x044,0x000] ++cmpb r8.ub[34] m8.ub[12] => rflags[0x081,0x081] ++cmpb r8.ub[12] m8.ub[34] => rflags[0x081,0x000] ++cmpb r8.ub[100] m8.sb[-100] => rflags[0x800,0x800] ++cmpb r8.ub[50] m8.sb[-50] => rflags[0x800,0x000] ++cmpb r8.sb[-50] m8.sb[50] => rflags[0x800,0x000] ++cmpb r8.sb[-100] m8.sb[100] => rflags[0x800,0x800] ++cmpb m8.ub[3] r8.ub[2] => rflags[0x010,0x010] ++cmpb m8.ub[2] r8.ub[3] => rflags[0x010,0x000] ++cmpb m8.ub[12] r8.ub[12] => rflags[0x044,0x044] ++cmpb m8.ub[12] r8.ub[34] => rflags[0x044,0x000] ++cmpb m8.ub[34] r8.ub[12] => rflags[0x081,0x081] ++cmpb m8.ub[12] r8.ub[34] => rflags[0x081,0x000] ++cmpb m8.ub[100] r8.sb[-100] => rflags[0x800,0x800] ++cmpb m8.ub[50] r8.sb[-50] => rflags[0x800,0x000] ++cmpb m8.sb[-50] r8.sb[50] => rflags[0x800,0x000] ++cmpb m8.sb[-100] r8.sb[100] => rflags[0x800,0x800] ++cmpw imm8[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw imm8[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw imm8[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw imm8[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw imm8[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw imm8[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw imm8[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm8[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw imm8[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw imm8[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpw imm8[3] m16.uw[2] => rflags[0x010,0x010] ++cmpw imm8[2] m16.uw[3] => rflags[0x010,0x000] ++cmpw imm8[12] m16.uw[12] => rflags[0x044,0x044] ++cmpw imm8[12] m16.uw[34] => rflags[0x044,0x000] ++cmpw imm8[34] m16.uw[12] => rflags[0x081,0x081] ++cmpw imm8[12] m16.uw[34] => rflags[0x081,0x000] ++cmpw imm8[100] m16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm8[50] m16.sw[-50] => rflags[0x800,0x000] ++cmpw imm8[-50] m16.sw[50] => rflags[0x800,0x000] ++cmpw imm8[-100] m16.sw[32700] => rflags[0x800,0x800] ++cmpw imm16[3] ax.uw[2] => rflags[0x010,0x010] ++cmpw imm16[2] ax.uw[3] => rflags[0x010,0x000] ++cmpw imm16[12] ax.uw[12] => rflags[0x044,0x044] ++cmpw imm16[12] ax.uw[34] => rflags[0x044,0x000] ++cmpw imm16[34] ax.uw[12] => rflags[0x081,0x081] ++cmpw imm16[12] ax.uw[34] => rflags[0x081,0x000] ++cmpw imm16[100] ax.sw[-32700] => rflags[0x800,0x800] ++cmpw imm16[50] ax.sw[-50] => rflags[0x800,0x000] ++cmpw imm16[-50] ax.sw[50] => rflags[0x800,0x000] ++cmpw imm16[-100] ax.sw[32700] => rflags[0x800,0x800] ++cmpw imm16[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw imm16[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw imm16[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw imm16[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw imm16[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw imm16[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw imm16[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm16[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw imm16[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw imm16[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpw imm16[3] m16.uw[2] => rflags[0x010,0x010] ++cmpw imm16[2] m16.uw[3] => rflags[0x010,0x000] ++cmpw imm16[12] m16.uw[12] => rflags[0x044,0x044] ++cmpw imm16[12] m16.uw[34] => rflags[0x044,0x000] ++cmpw imm16[34] m16.uw[12] => rflags[0x081,0x081] ++cmpw imm16[12] m16.uw[34] => rflags[0x081,0x000] ++cmpw imm16[100] m16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm16[50] m16.sw[-50] => rflags[0x800,0x000] ++cmpw imm16[-50] m16.sw[50] => rflags[0x800,0x000] ++cmpw imm16[-100] m16.sw[32700] => rflags[0x800,0x800] ++cmpw r16.uw[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw r16.uw[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw r16.uw[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw r16.uw[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw r16.uw[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw r16.uw[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw r16.uw[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw r16.uw[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw r16.sw[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw r16.sw[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpw r16.uw[3] m16.uw[2] => rflags[0x010,0x010] ++cmpw r16.uw[2] m16.uw[3] => rflags[0x010,0x000] ++cmpw r16.uw[12] m16.uw[12] => rflags[0x044,0x044] ++cmpw r16.uw[12] m16.uw[34] => rflags[0x044,0x000] ++cmpw r16.uw[34] m16.uw[12] => rflags[0x081,0x081] ++cmpw r16.uw[12] m16.uw[34] => rflags[0x081,0x000] ++cmpw r16.uw[100] m16.sw[-32700] => rflags[0x800,0x800] ++cmpw r16.uw[50] m16.sw[-50] => rflags[0x800,0x000] ++cmpw r16.sw[-50] m16.sw[50] => rflags[0x800,0x000] ++cmpw r16.sw[-100] m16.sw[32700] => rflags[0x800,0x800] ++cmpw m16.uw[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw m16.uw[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw m16.uw[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw m16.uw[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw m16.uw[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw m16.uw[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw m16.uw[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw m16.uw[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw m16.sw[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw m16.sw[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpl imm8[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl imm8[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl imm8[12] r32.ud[12] => rflags[0x044,0x044] ++###cmpl imm8[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl imm8[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl imm8[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl imm8[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm8[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl imm8[-50] r32.sd[50] => rflags[0x800,0x000] ++cmpl imm8[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm8[3] m32.ud[2] => rflags[0x010,0x010] ++cmpl imm8[2] m32.ud[3] => rflags[0x010,0x000] ++cmpl imm8[12] m32.ud[12] => rflags[0x044,0x044] ++cmpl imm8[12] m32.ud[34] => rflags[0x044,0x000] ++cmpl imm8[34] m32.ud[12] => rflags[0x081,0x081] ++cmpl imm8[12] m32.ud[34] => rflags[0x081,0x000] ++cmpl imm8[100] m32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm8[50] m32.sd[-50] => rflags[0x800,0x000] ++cmpl imm8[-50] m32.sd[50] => rflags[0x800,0x000] ++cmpl imm8[-100] m32.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm32[3] eax.ud[2] => rflags[0x010,0x010] ++cmpl imm32[2] eax.ud[3] => rflags[0x010,0x000] ++cmpl imm32[12] eax.ud[12] => rflags[0x044,0x044] ++cmpl imm32[12] eax.ud[34] => rflags[0x044,0x000] ++cmpl imm32[34] eax.ud[12] => rflags[0x081,0x081] ++cmpl imm32[12] eax.ud[34] => rflags[0x081,0x000] ++cmpl imm32[100] eax.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm32[50] eax.sd[-50] => rflags[0x800,0x000] ++cmpl imm32[-50] eax.sd[50] => rflags[0x800,0x000] ++cmpl imm32[-100] eax.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm32[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl imm32[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl imm32[12] r32.ud[12] => rflags[0x044,0x044] ++cmpl imm32[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl imm32[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl imm32[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl imm32[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm32[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl imm32[-50] r32.sd[50] => rflags[0x800,0x000] ++cmpl imm32[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm32[3] m32.ud[2] => rflags[0x010,0x010] ++cmpl imm32[2] m32.ud[3] => rflags[0x010,0x000] ++cmpl imm32[12] m32.ud[12] => rflags[0x044,0x044] ++cmpl imm32[12] m32.ud[34] => rflags[0x044,0x000] ++cmpl imm32[34] m32.ud[12] => rflags[0x081,0x081] ++cmpl imm32[12] m32.ud[34] => rflags[0x081,0x000] ++cmpl imm32[100] m32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm32[50] m32.sd[-50] => rflags[0x800,0x000] ++cmpl imm32[-50] m32.sd[50] => rflags[0x800,0x000] ++cmpl imm32[-100] m32.sd[2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl r32.ud[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl r32.ud[12] r32.ud[12] => rflags[0x044,0x044] ++cmpl r32.ud[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl r32.ud[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl r32.ud[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl r32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl r32.sd[-50] r32.sd[50] => rflags[0x800,0x000] ++cmpl r32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[3] m32.ud[2] => rflags[0x010,0x010] ++cmpl r32.ud[2] m32.ud[3] => rflags[0x010,0x000] ++cmpl r32.ud[12] m32.ud[12] => rflags[0x044,0x044] ++cmpl r32.ud[12] m32.ud[34] => rflags[0x044,0x000] ++cmpl r32.ud[34] m32.ud[12] => rflags[0x081,0x081] ++cmpl r32.ud[12] m32.ud[34] => rflags[0x081,0x000] ++cmpl r32.ud[100] m32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[50] m32.sd[-50] => rflags[0x800,0x000] ++cmpl r32.sd[-50] m32.sd[50] => rflags[0x800,0x000] ++cmpl r32.sd[-100] m32.sd[2147483600] => rflags[0x800,0x800] ++cmpl m32.ud[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl m32.ud[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl m32.ud[12] r32.ud[12] => rflags[0x044,0x044] ++cmpl m32.ud[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl m32.ud[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl m32.ud[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl m32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl m32.ud[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl m32.sd[-50] r32.sd[50] => rflags[0x800,0x000] ++###cmpl m32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpq imm8[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq imm8[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq imm8[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq imm8[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq imm8[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq imm8[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq imm8[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm8[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq imm8[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq imm8[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm8[3] m64.uq[2] => rflags[0x010,0x010] ++cmpq imm8[2] m64.uq[3] => rflags[0x010,0x000] ++cmpq imm8[12] m64.uq[12] => rflags[0x044,0x044] ++cmpq imm8[12] m64.uq[34] => rflags[0x044,0x000] ++cmpq imm8[34] m64.uq[12] => rflags[0x081,0x081] ++cmpq imm8[12] m64.uq[34] => rflags[0x081,0x000] ++cmpq imm8[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm8[50] m64.sq[-50] => rflags[0x800,0x000] ++cmpq imm8[-50] m64.sq[50] => rflags[0x800,0x000] ++cmpq imm8[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[3] rax.uq[2] => rflags[0x010,0x010] ++cmpq imm32[2] rax.uq[3] => rflags[0x010,0x000] ++cmpq imm32[12] rax.uq[12] => rflags[0x044,0x044] ++cmpq imm32[12] rax.uq[34] => rflags[0x044,0x000] ++cmpq imm32[34] rax.uq[12] => rflags[0x081,0x081] ++cmpq imm32[12] rax.uq[34] => rflags[0x081,0x000] ++cmpq imm32[100] rax.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[50] rax.sq[-50] => rflags[0x800,0x000] ++cmpq imm32[-50] rax.sq[50] => rflags[0x800,0x000] ++cmpq imm32[-100] rax.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq imm32[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq imm32[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq imm32[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq imm32[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq imm32[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq imm32[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq imm32[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq imm32[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[3] m64.uq[2] => rflags[0x010,0x010] ++cmpq imm32[2] m64.uq[3] => rflags[0x010,0x000] ++cmpq imm32[12] m64.uq[12] => rflags[0x044,0x044] ++cmpq imm32[12] m64.uq[34] => rflags[0x044,0x000] ++cmpq imm32[34] m64.uq[12] => rflags[0x081,0x081] ++cmpq imm32[12] m64.uq[34] => rflags[0x081,0x000] ++cmpq imm32[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[50] m64.sq[-50] => rflags[0x800,0x000] ++cmpq imm32[-50] m64.sq[50] => rflags[0x800,0x000] ++cmpq imm32[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq r64.uq[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq r64.uq[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq r64.uq[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq r64.uq[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq r64.uq[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq r64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq r64.sq[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq r64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[3] m64.uq[2] => rflags[0x010,0x010] ++cmpq r64.uq[2] m64.uq[3] => rflags[0x010,0x000] ++cmpq r64.uq[12] m64.uq[12] => rflags[0x044,0x044] ++cmpq r64.uq[12] m64.uq[34] => rflags[0x044,0x000] ++cmpq r64.uq[34] m64.uq[12] => rflags[0x081,0x081] ++cmpq r64.uq[12] m64.uq[34] => rflags[0x081,0x000] ++cmpq r64.uq[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[50] m64.sq[-50] => rflags[0x800,0x000] ++cmpq r64.sq[-50] m64.sq[50] => rflags[0x800,0x000] ++cmpq r64.sq[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq m64.uq[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq m64.uq[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq m64.uq[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq m64.uq[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq m64.uq[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq m64.uq[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq m64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq m64.uq[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq m64.sq[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq m64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] ++###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] ++###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] ++###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] ++###cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] ++###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] ++cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] ++###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] ++###cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] ++###cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] ++cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] ++cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] ++###cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] ++###cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] ++cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] ++cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] + cqo rax.uq[0x0123456789abcdef] : => rdx.uq[0x0000000000000000] rax.uq[0x0123456789abcdef] + cqo rax.uq[0xfedcba9876543210] : => rdx.uq[0xffffffffffffffff] rax.uq[0xfedcba9876543210] + cwd ax.uw[0x1234] : => dx.uw[0x0000] ax.uw[0x1234] +@@ -617,8 +617,8 @@ incl r32.ud[12345678] => 0.ud[12345679] + incl m32.ud[12345678] => 0.ud[12345679] + incq r64.uq[1234567813572468] => 0.uq[1234567813572469] + incq m64.uq[1234567813572468] => 0.uq[1234567813572469] +-###lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] +-###lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] ++###lahf rflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] ++###lahf rflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] + movb imm8[123] r8.ub[0] => 1.ub[123] + movb imm8[123] m8.ub[0] => 1.ub[123] + movb r8.ub[123] r8.ub[0] => 1.ub[123] +@@ -714,54 +714,54 @@ orq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0xffffffff96767779] + orq r64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff] + orq r64.uq[0xeca86420fdb97531] m64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff] + orq m64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff] +-###rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] +-rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] +-rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrw eflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0] +-rcrw eflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0] +-rcrw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0] +-rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0] +-rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrq eflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0] +-rcrq eflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0] +-rcrq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] +-rcrq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] +-rcrq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] +-rcrq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++rcrb rflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0] ++rcrb rflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0] ++rcrb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrw rflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0] ++rcrw rflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0] ++rcrw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrl rflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0] ++rcrl rflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0] ++rcrl rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrl rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrl rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrl rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrq rflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0] ++rcrq rflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0] ++rcrq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] ++rcrq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] ++rcrq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] ++rcrq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] + rolb r8.ub[0xca] => 0.ub[0x95] + rolb m8.ub[0xca] => 0.ub[0x95] + rolb imm8[2] r8.ub[0xca] => 1.ub[0x2b] +@@ -810,8 +810,8 @@ rorq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] + rorq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] + rorq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] + rorq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] +-###sahf eflags[0xff,0x28] ah.ub[0xfd] : => eflags[0xfd,0xd5] +-###sahf eflags[0xff,0xfd] ah.ub[0x28] : => eflags[0xfd,0x00] ++###sahf rflags[0xff,0x28] ah.ub[0xfd] : => rflags[0xfd,0xd5] ++###sahf rflags[0xff,0xfd] ah.ub[0x28] : => rflags[0xfd,0x00] + salb r8.ub[0xca] => 0.ub[0x94] + salb m8.ub[0xca] => 0.ub[0x94] + salb imm8[2] r8.ub[0xca] => 1.ub[0x28] +@@ -860,252 +860,252 @@ sarq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] + sarq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] + sarq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] + sarq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] +-###sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] +-###sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] +-sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22] +-sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21] +-sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22] +-sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21] +-sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22] +-sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21] +-###sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22] +-###sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21] +-###sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] +-###sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] +-sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444] +-sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443] +-###sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] +-###sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443] +-###sbbw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444] +-###sbbw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443] +-sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309] +-sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308] +-###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] +-###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] +-###sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643] +-###sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] +-sbbq eflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630] +-sbbq eflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629] +-###sbbq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964] +-###sbbq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963] +-sbbq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964] +-sbbq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963] +-sbbq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964] +-sbbq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963] +-sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] +-sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] +-###sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174] +-###sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173] +-sbbq eflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] +-sbbq eflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] +-seta eflags[0x041,0x000] : r8.ub[123] => 0.ub[1] +-seta eflags[0x041,0x001] : r8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x040] : r8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x041] : r8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x000] : m8.ub[123] => 0.ub[1] +-seta eflags[0x041,0x001] : m8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x040] : m8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x041] : m8.ub[123] => 0.ub[0] +-setae eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] +-setae eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] +-setae eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] +-setae eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] +-setb eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] +-setb eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] +-setb eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] +-setb eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[0] +-setbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[0] +-setbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[1] +-setc eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] +-setc eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] +-setc eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] +-setc eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] +-sete eflags[0x040,0x000] : r8.ub[123] => 0.ub[0] +-sete eflags[0x040,0x040] : r8.ub[123] => 0.ub[1] +-sete eflags[0x040,0x000] : m8.ub[123] => 0.ub[0] +-sete eflags[0x040,0x040] : m8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x000] : r8.ub[123] => 0.ub[0] +-setna eflags[0x041,0x001] : r8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x040] : r8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x041] : r8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x000] : m8.ub[123] => 0.ub[0] +-setna eflags[0x041,0x001] : m8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x040] : m8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x041] : m8.ub[123] => 0.ub[1] +-setnae eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] +-setnae eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] +-setnae eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] +-setnae eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] +-setnb eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] +-setnb eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] +-setnb eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] +-setnb eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[1] +-setnbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[1] +-setnbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[0] +-setnc eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] +-setnc eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] +-setnc eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] +-setnc eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] +-setne eflags[0x040,0x000] : r8.ub[123] => 0.ub[1] +-setne eflags[0x040,0x040] : r8.ub[123] => 0.ub[0] +-setne eflags[0x040,0x000] : m8.ub[123] => 0.ub[1] +-setne eflags[0x040,0x040] : m8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setnge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setnge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setnge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setnl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setnl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setnl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] +-setno eflags[0x800,0x000] : r8.ub[123] => 0.ub[1] +-setno eflags[0x800,0x800] : r8.ub[123] => 0.ub[0] +-setno eflags[0x800,0x000] : m8.ub[123] => 0.ub[1] +-setno eflags[0x800,0x800] : m8.ub[123] => 0.ub[0] +-setnp eflags[0x004,0x000] : r8.ub[123] => 0.ub[1] +-setnp eflags[0x004,0x004] : r8.ub[123] => 0.ub[0] +-setnp eflags[0x004,0x000] : m8.ub[123] => 0.ub[1] +-setnp eflags[0x004,0x004] : m8.ub[123] => 0.ub[0] +-setns eflags[0x080,0x000] : r8.ub[123] => 0.ub[1] +-setns eflags[0x080,0x080] : r8.ub[123] => 0.ub[0] +-setns eflags[0x080,0x000] : m8.ub[123] => 0.ub[1] +-setns eflags[0x080,0x080] : m8.ub[123] => 0.ub[0] +-setnz eflags[0x040,0x000] : r8.ub[123] => 0.ub[1] +-setnz eflags[0x040,0x040] : r8.ub[123] => 0.ub[0] +-setnz eflags[0x040,0x000] : m8.ub[123] => 0.ub[1] +-setnz eflags[0x040,0x040] : m8.ub[123] => 0.ub[0] +-seto eflags[0x800,0x000] : r8.ub[123] => 0.ub[0] +-seto eflags[0x800,0x800] : r8.ub[123] => 0.ub[1] +-seto eflags[0x800,0x000] : m8.ub[123] => 0.ub[0] +-seto eflags[0x800,0x800] : m8.ub[123] => 0.ub[1] +-setp eflags[0x004,0x000] : r8.ub[123] => 0.ub[0] +-setp eflags[0x004,0x004] : r8.ub[123] => 0.ub[1] +-setp eflags[0x004,0x000] : m8.ub[123] => 0.ub[0] +-setp eflags[0x004,0x004] : m8.ub[123] => 0.ub[1] +-sets eflags[0x080,0x000] : r8.ub[123] => 0.ub[0] +-sets eflags[0x080,0x080] : r8.ub[123] => 0.ub[1] +-sets eflags[0x080,0x000] : m8.ub[123] => 0.ub[0] +-sets eflags[0x080,0x080] : m8.ub[123] => 0.ub[1] +-setz eflags[0x040,0x000] : r8.ub[123] => 0.ub[0] +-setz eflags[0x040,0x040] : r8.ub[123] => 0.ub[1] +-setz eflags[0x040,0x000] : m8.ub[123] => 0.ub[0] +-setz eflags[0x040,0x040] : m8.ub[123] => 0.ub[1] ++###sbbb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] ++###sbbb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] ++sbbb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22] ++sbbb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21] ++sbbb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22] ++sbbb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21] ++sbbb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22] ++sbbb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21] ++###sbbb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22] ++###sbbb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21] ++###sbbb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] ++###sbbb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] ++sbbw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444] ++sbbw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443] ++###sbbw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] ++###sbbw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443] ++###sbbw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444] ++###sbbw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443] ++sbbl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309] ++sbbl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308] ++###sbbl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] ++###sbbl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] ++###sbbl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643] ++###sbbl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] ++sbbq rflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630] ++sbbq rflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629] ++###sbbq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964] ++###sbbq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963] ++sbbq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964] ++sbbq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963] ++sbbq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964] ++sbbq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963] ++sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] ++sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] ++###sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174] ++###sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173] ++sbbq rflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] ++sbbq rflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] ++seta rflags[0x041,0x000] : r8.ub[123] => 0.ub[1] ++seta rflags[0x041,0x001] : r8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x040] : r8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x041] : r8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x000] : m8.ub[123] => 0.ub[1] ++seta rflags[0x041,0x001] : m8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x040] : m8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x041] : m8.ub[123] => 0.ub[0] ++setae rflags[0x001,0x000] : r8.ub[123] => 0.ub[1] ++setae rflags[0x001,0x001] : r8.ub[123] => 0.ub[0] ++setae rflags[0x001,0x000] : m8.ub[123] => 0.ub[1] ++setae rflags[0x001,0x001] : m8.ub[123] => 0.ub[0] ++setb rflags[0x001,0x000] : r8.ub[123] => 0.ub[0] ++setb rflags[0x001,0x001] : r8.ub[123] => 0.ub[1] ++setb rflags[0x001,0x000] : m8.ub[123] => 0.ub[0] ++setb rflags[0x001,0x001] : m8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[0] ++setbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[0] ++setbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[1] ++setc rflags[0x001,0x000] : r8.ub[123] => 0.ub[0] ++setc rflags[0x001,0x001] : r8.ub[123] => 0.ub[1] ++setc rflags[0x001,0x000] : m8.ub[123] => 0.ub[0] ++setc rflags[0x001,0x001] : m8.ub[123] => 0.ub[1] ++sete rflags[0x040,0x000] : r8.ub[123] => 0.ub[0] ++sete rflags[0x040,0x040] : r8.ub[123] => 0.ub[1] ++sete rflags[0x040,0x000] : m8.ub[123] => 0.ub[0] ++sete rflags[0x040,0x040] : m8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x000] : r8.ub[123] => 0.ub[0] ++setna rflags[0x041,0x001] : r8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x040] : r8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x041] : r8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x000] : m8.ub[123] => 0.ub[0] ++setna rflags[0x041,0x001] : m8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x040] : m8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x041] : m8.ub[123] => 0.ub[1] ++setnae rflags[0x001,0x000] : r8.ub[123] => 0.ub[0] ++setnae rflags[0x001,0x001] : r8.ub[123] => 0.ub[1] ++setnae rflags[0x001,0x000] : m8.ub[123] => 0.ub[0] ++setnae rflags[0x001,0x001] : m8.ub[123] => 0.ub[1] ++setnb rflags[0x001,0x000] : r8.ub[123] => 0.ub[1] ++setnb rflags[0x001,0x001] : r8.ub[123] => 0.ub[0] ++setnb rflags[0x001,0x000] : m8.ub[123] => 0.ub[1] ++setnb rflags[0x001,0x001] : m8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[1] ++setnbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[1] ++setnbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[0] ++setnc rflags[0x001,0x000] : r8.ub[123] => 0.ub[1] ++setnc rflags[0x001,0x001] : r8.ub[123] => 0.ub[0] ++setnc rflags[0x001,0x000] : m8.ub[123] => 0.ub[1] ++setnc rflags[0x001,0x001] : m8.ub[123] => 0.ub[0] ++setne rflags[0x040,0x000] : r8.ub[123] => 0.ub[1] ++setne rflags[0x040,0x040] : r8.ub[123] => 0.ub[0] ++setne rflags[0x040,0x000] : m8.ub[123] => 0.ub[1] ++setne rflags[0x040,0x040] : m8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setnge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setnge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setnge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setnl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setnl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setnl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] ++setno rflags[0x800,0x000] : r8.ub[123] => 0.ub[1] ++setno rflags[0x800,0x800] : r8.ub[123] => 0.ub[0] ++setno rflags[0x800,0x000] : m8.ub[123] => 0.ub[1] ++setno rflags[0x800,0x800] : m8.ub[123] => 0.ub[0] ++setnp rflags[0x004,0x000] : r8.ub[123] => 0.ub[1] ++setnp rflags[0x004,0x004] : r8.ub[123] => 0.ub[0] ++setnp rflags[0x004,0x000] : m8.ub[123] => 0.ub[1] ++setnp rflags[0x004,0x004] : m8.ub[123] => 0.ub[0] ++setns rflags[0x080,0x000] : r8.ub[123] => 0.ub[1] ++setns rflags[0x080,0x080] : r8.ub[123] => 0.ub[0] ++setns rflags[0x080,0x000] : m8.ub[123] => 0.ub[1] ++setns rflags[0x080,0x080] : m8.ub[123] => 0.ub[0] ++setnz rflags[0x040,0x000] : r8.ub[123] => 0.ub[1] ++setnz rflags[0x040,0x040] : r8.ub[123] => 0.ub[0] ++setnz rflags[0x040,0x000] : m8.ub[123] => 0.ub[1] ++setnz rflags[0x040,0x040] : m8.ub[123] => 0.ub[0] ++seto rflags[0x800,0x000] : r8.ub[123] => 0.ub[0] ++seto rflags[0x800,0x800] : r8.ub[123] => 0.ub[1] ++seto rflags[0x800,0x000] : m8.ub[123] => 0.ub[0] ++seto rflags[0x800,0x800] : m8.ub[123] => 0.ub[1] ++setp rflags[0x004,0x000] : r8.ub[123] => 0.ub[0] ++setp rflags[0x004,0x004] : r8.ub[123] => 0.ub[1] ++setp rflags[0x004,0x000] : m8.ub[123] => 0.ub[0] ++setp rflags[0x004,0x004] : m8.ub[123] => 0.ub[1] ++sets rflags[0x080,0x000] : r8.ub[123] => 0.ub[0] ++sets rflags[0x080,0x080] : r8.ub[123] => 0.ub[1] ++sets rflags[0x080,0x000] : m8.ub[123] => 0.ub[0] ++sets rflags[0x080,0x080] : m8.ub[123] => 0.ub[1] ++setz rflags[0x040,0x000] : r8.ub[123] => 0.ub[0] ++setz rflags[0x040,0x040] : r8.ub[123] => 0.ub[1] ++setz rflags[0x040,0x000] : m8.ub[123] => 0.ub[0] ++setz rflags[0x040,0x040] : m8.ub[123] => 0.ub[1] + shlb r8.ub[0xca] => 0.ub[0x94] + shlb m8.ub[0xca] => 0.ub[0x94] + shlb imm8[2] r8.ub[0xca] => 1.ub[0x28] +@@ -1202,10 +1202,10 @@ shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0x7 + shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0x7fff80007f807865] + shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00] + shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00] +-###stc eflags[0x001,0x000] : => eflags[0x001,0x001] +-###stc eflags[0x001,0x001] : => eflags[0x001,0x001] +-std eflags[0x400,0x000] : => eflags[0x400,0x400] +-std eflags[0x400,0x400] : => eflags[0x400,0x400] ++###stc rflags[0x001,0x000] : => rflags[0x001,0x001] ++###stc rflags[0x001,0x001] : => rflags[0x001,0x001] ++std rflags[0x400,0x000] : => rflags[0x400,0x400] ++std rflags[0x400,0x400] : => rflags[0x400,0x400] + subb imm8[12] al.ub[34] => 1.ub[22] + subb imm8[12] bl.ub[34] => 1.ub[22] + subb imm8[12] m8.ub[34] => 1.ub[22] +@@ -1233,106 +1233,106 @@ subq imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964] + subq r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] + subq r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174] + subq m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] +-testb imm8[0x1a] al.ub[0x1a] => eflags[0x8c5,0x000] +-testb imm8[0x5a] al.ub[0x5a] => eflags[0x8c5,0x004] +-testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044] +-testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080] +-testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084] +-testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000] +-testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004] +-testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044] +-testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080] +-testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084] +-testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000] +-testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004] +-testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044] +-testb imm8[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080] +-testb imm8[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084] +-testb r8.ub[0x1a] r8.ub[0x1a] => eflags[0x8c5,0x000] +-testb r8.ub[0x5a] r8.ub[0x5a] => eflags[0x8c5,0x004] +-testb r8.ub[0x1a] r8.ub[0xa1] => eflags[0x8c5,0x044] +-testb r8.ub[0xa1] r8.ub[0xa1] => eflags[0x8c5,0x080] +-testb r8.ub[0xa5] r8.ub[0xa5] => eflags[0x8c5,0x084] +-testb r8.ub[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000] +-testb r8.ub[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004] +-testb r8.ub[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044] +-testb r8.ub[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080] +-testb r8.ub[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084] +-testw imm16[0x1a1a] ax.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw imm16[0x5a5a] ax.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw imm16[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw imm16[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw r16.uw[0x1a1a] r16.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw r16.uw[0x5a5a] r16.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw r16.uw[0x1a1a] r16.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw r16.uw[0xa1a1] r16.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw r16.uw[0xa5a5] r16.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw r16.uw[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw r16.uw[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw r16.uw[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw r16.uw[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw r16.uw[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084] +-testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080] +-testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084] +-testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080] +-testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084] +-testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080] +-testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000] +-testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044] +-testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080] +-testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000] +-testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044] +-testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080] +-testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084] ++testb imm8[0x1a] al.ub[0x1a] => rflags[0x8c5,0x000] ++testb imm8[0x5a] al.ub[0x5a] => rflags[0x8c5,0x004] ++testb imm8[0x1a] al.ub[0xa1] => rflags[0x8c5,0x044] ++testb imm8[0xa1] al.ub[0xa1] => rflags[0x8c5,0x080] ++testb imm8[0xa5] al.ub[0xa5] => rflags[0x8c5,0x084] ++testb imm8[0x1a] bl.ub[0x1a] => rflags[0x8c5,0x000] ++testb imm8[0x5a] bl.ub[0x5a] => rflags[0x8c5,0x004] ++testb imm8[0x1a] bl.ub[0xa1] => rflags[0x8c5,0x044] ++testb imm8[0xa1] bl.ub[0xa1] => rflags[0x8c5,0x080] ++testb imm8[0xa5] bl.ub[0xa5] => rflags[0x8c5,0x084] ++testb imm8[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000] ++testb imm8[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004] ++testb imm8[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044] ++testb imm8[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080] ++testb imm8[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084] ++testb r8.ub[0x1a] r8.ub[0x1a] => rflags[0x8c5,0x000] ++testb r8.ub[0x5a] r8.ub[0x5a] => rflags[0x8c5,0x004] ++testb r8.ub[0x1a] r8.ub[0xa1] => rflags[0x8c5,0x044] ++testb r8.ub[0xa1] r8.ub[0xa1] => rflags[0x8c5,0x080] ++testb r8.ub[0xa5] r8.ub[0xa5] => rflags[0x8c5,0x084] ++testb r8.ub[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000] ++testb r8.ub[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004] ++testb r8.ub[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044] ++testb r8.ub[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080] ++testb r8.ub[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084] ++testw imm16[0x1a1a] ax.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw imm16[0x5a5a] ax.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw imm16[0x1a1a] ax.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw imm16[0xa1a1] ax.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw imm16[0xa5a5] ax.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw imm16[0x1a1a] bx.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw imm16[0x5a5a] bx.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw imm16[0x1a1a] bx.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw imm16[0xa1a1] bx.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw imm16[0xa5a5] bx.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw imm16[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw imm16[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw imm16[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw imm16[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw imm16[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw r16.uw[0x1a1a] r16.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw r16.uw[0x5a5a] r16.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw r16.uw[0x1a1a] r16.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw r16.uw[0xa1a1] r16.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw r16.uw[0xa5a5] r16.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw r16.uw[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw r16.uw[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw r16.uw[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw r16.uw[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw r16.uw[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084] ++testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080] ++testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084] ++testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080] ++testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084] ++testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080] ++testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000] ++testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044] ++testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080] ++testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000] ++testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044] ++testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080] ++testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084] + ###xaddb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[46] + ###xaddb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[46] + ###xaddw r16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[6912] +diff --git a/none/tests/amd64/insn_fpu.def b/none/tests/amd64/insn_fpu.def +index 590f584..525fd1b 100644 +--- a/none/tests/amd64/insn_fpu.def ++++ b/none/tests/amd64/insn_fpu.def +@@ -70,30 +70,30 @@ fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.43 + fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000] + fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[7654321.1234567] fpusw[0x4700,0x0100] + fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[7654321.1234567] fpusw[0x4700,0x4000] +-fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00] +-fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01] +-fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40] +-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00] +-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01] +-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40] +-fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00] +-fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01] +-fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40] +-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00] +-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01] +-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40] +-fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00] +-fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01] +-fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40] +-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00] +-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01] +-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40] +-fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00] +-fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01] +-fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40] +-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00] +-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01] +-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40] ++fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00] ++fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01] ++fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40] ++fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00] ++fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01] ++fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40] ++fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00] ++fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01] ++fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40] ++fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00] ++fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01] ++fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40] ++fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00] ++fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01] ++fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40] ++fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00] ++fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01] ++fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40] ++fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00] ++fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01] ++fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40] ++fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00] ++fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01] ++fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40] + fchs st0.ps[1234.5678] : => st0.ps[-1234.5678] + fchs st0.ps[-1234.5678] : => st0.ps[1234.5678] + fchs st0.pd[12345678.87654321] : => st0.pd[-12345678.87654321] +diff --git a/none/tests/amd64/insn_sse.def b/none/tests/amd64/insn_sse.def +index a9e92a0..277a062 100644 +--- a/none/tests/amd64/insn_sse.def ++++ b/none/tests/amd64/insn_sse.def +@@ -38,12 +38,12 @@ cmpordps xmm.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,23 + cmpordps m128.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,234.5679,234.5677] => 1.ud[0xffffffff,0xffffffff,0xffffffff,0xffffffff] + cmpordss xmm.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5679,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0] + cmpordss m128.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5676,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0] +-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] +-comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] ++comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] ++comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] + cvtpi2ps mm.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4] + cvtpi2ps m64.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4] + cvtps2pi xmm.ps[12.34,56.78,1.11,2.22] mm.sd[1,2] => 1.sd[12,57] +@@ -140,12 +140,12 @@ subps xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66, + subps m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,-23.77,-21.21,-76.65] + subss xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0] + subss m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0] +-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] +-ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] ++ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] ++ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] + unpckhps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65] + unpckhps m128.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65] + unpcklps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[11.22,12.34,33.44,56.78] +diff --git a/none/tests/amd64/insn_sse2.def b/none/tests/amd64/insn_sse2.def +index 3cbdd41..7e0890e 100644 +--- a/none/tests/amd64/insn_sse2.def ++++ b/none/tests/amd64/insn_sse2.def +@@ -38,12 +38,12 @@ cmpnlesd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff, + cmpnlesd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0x0000000000000000,0] + cmpordsd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff,0] + cmpordsd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0xffffffffffffffff,0] +-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] +-comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] ++comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] ++comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] + cvtdq2pd xmm.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0] + cvtdq2pd m128.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0] + cvtdq2ps xmm.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0] +@@ -329,12 +329,12 @@ subpd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4 + subpd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4321] + subsd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0] + subsd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0] +-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] +-ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] ++ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] ++ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] + unpckhpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321] + unpckhpd m128.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321] + unpcklpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[1122.3344,1234.5678] diff --git a/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch b/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch new file mode 100644 index 0000000..4b718e3 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch @@ -0,0 +1,86 @@ +diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c +index b8cc022..d54cae7 100644 +--- a/coregrind/m_redir.c ++++ b/coregrind/m_redir.c +@@ -1485,6 +1485,17 @@ void VG_(redir_initialise) ( void ) + (Addr)&VG_(arm_linux_REDIR_FOR_strcmp), + complain_about_stripped_glibc_ldso + ); ++ /* index */ ++ add_hardwired_spec( ++ "ld-linux.so.3", "index", ++ (Addr)&VG_(arm_linux_REDIR_FOR_index), ++ complain_about_stripped_glibc_ldso ++ ); ++ add_hardwired_spec( ++ "ld-linux-armhf.so.3", "index", ++ (Addr)&VG_(arm_linux_REDIR_FOR_index), ++ complain_about_stripped_glibc_ldso ++ ); + } + + # elif defined(VGP_arm64_linux) +diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S +index a532071..0488b54 100644 +--- a/coregrind/m_trampoline.S ++++ b/coregrind/m_trampoline.S +@@ -625,26 +625,26 @@ VG_(arm_linux_REDIR_FOR_strlen): + bx lr + UD2_4 + +-//.global VG_(arm_linux_REDIR_FOR_index) +-//VG_(arm_linux_REDIR_FOR_index): +-// ldrb r3, [r0, #0] @ zero_extendqisi2 +-// and r1, r1, #255 +-// cmp r3, r1 +-// @ lr needed for prologue +-// bne .L9 +-// bx lr +-//.L12: +-// ldrb r3, [r0, #1]! @ zero_extendqisi2 +-// cmp r3, r1 +-// beq .L11 +-//.L9: +-// cmp r3, #0 +-// bne .L12 +-// mov r0, #0 +-// bx lr +-//.L11: +-// bx lr +-// UD2_4 ++.global VG_(arm_linux_REDIR_FOR_index) ++VG_(arm_linux_REDIR_FOR_index): ++ ldrb r3, [r0, #0] @ zero_extendqisi2 ++ and r1, r1, #255 ++ cmp r3, r1 ++ @ lr needed for prologue ++ bne .L9 ++ bx lr ++.L12: ++ ldrb r3, [r0, #1]! @ zero_extendqisi2 ++ cmp r3, r1 ++ beq .L11 ++.L9: ++ cmp r3, #0 ++ bne .L12 ++ mov r0, #0 ++ bx lr ++.L11: ++ bx lr ++ UD2_4 + + .global VG_(arm_linux_REDIR_FOR_memcpy) + VG_(arm_linux_REDIR_FOR_memcpy): +diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h +index 3a9bafe..e29427d 100644 +--- a/coregrind/pub_core_trampoline.h ++++ b/coregrind/pub_core_trampoline.h +@@ -100,7 +100,7 @@ extern Addr VG_(ppctoc_magic_redirect_return_stub); + extern Addr VG_(arm_linux_SUBST_FOR_sigreturn); + extern Addr VG_(arm_linux_SUBST_FOR_rt_sigreturn); + extern UInt VG_(arm_linux_REDIR_FOR_strlen)( void* ); +-//extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int ); ++extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int ); + extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int ); + extern void* VG_(arm_linux_REDIR_FOR_strcmp)( void*, void* ); + #endif diff --git a/SOURCES/valgrind-3.13.0-arm64-hwcap.patch b/SOURCES/valgrind-3.13.0-arm64-hwcap.patch new file mode 100644 index 0000000..8f2a070 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-arm64-hwcap.patch @@ -0,0 +1,17 @@ +diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c +index 30e1f85..387beae 100644 +--- a/coregrind/m_initimg/initimg-linux.c ++++ b/coregrind/m_initimg/initimg-linux.c +@@ -703,6 +703,12 @@ Addr setup_client_stack( void* init_sp, + (and anything above) are not supported by Valgrind. */ + auxv->u.a_val &= VKI_HWCAP_S390_TE - 1; + } ++# elif defined(VGP_arm64_linux) ++ { ++ /* Linux 4.11 started pupulating this for arm64, but we ++ currently don't support any. */ ++ auxv->u.a_val = 0; ++ } + # endif + break; + # if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) diff --git a/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch b/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch new file mode 100644 index 0000000..4f9537a --- /dev/null +++ b/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch @@ -0,0 +1,36 @@ +commit 59af5db9c15d8ea03c1521736fb1f107d66bce08 +Author: philippe +Date: Sun Jun 25 20:25:50 2017 +0000 + + After fork, vgdb activity is polled according to the nr of bbs done : + once the nr of bbs done reaches the next vgdb poll, a check for vgdb + activity is done. + This might lead to the activation of gdbserver after fork. + Such poll is however not expected, unless the children is + to be trace. + This spurious poll in the forked child can cause failures + depending on the nr of bbs done before the fork, and the + nr of bbs done between the fork and the exec. + + => disable vgdb poll in the child in the cleanup after fork + in the child, unless the children have to be traced. + + + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16454 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c +index 87fbce2..648d543 100644 +--- a/coregrind/m_gdbserver/m_gdbserver.c ++++ b/coregrind/m_gdbserver/m_gdbserver.c +@@ -646,6 +646,10 @@ static void gdbserver_cleanup_in_child_after_fork(ThreadId me) + + if (VG_(clo_trace_children)) { + VG_(gdbserver_prerun_action) (me); ++ } else { ++ /* After fork, if we do not trace the children, disable vgdb ++ poll to avoid gdbserver being called unexpectedly. */ ++ VG_(disable_vgdb_poll) (); + } + } + diff --git a/SOURCES/valgrind-3.13.0-epoll_pwait.patch b/SOURCES/valgrind-3.13.0-epoll_pwait.patch new file mode 100644 index 0000000..8a7516b --- /dev/null +++ b/SOURCES/valgrind-3.13.0-epoll_pwait.patch @@ -0,0 +1,68 @@ +commit 79865f0eed7cf0e0ad687ee0a59d59a1d505b514 +Author: mjw +Date: Sat Jun 17 13:49:22 2017 +0000 + + epoll_pwait can have a NULL sigmask. + + According to the epoll_pwait(2) man page: + + The sigmask argument may be specified as NULL, in which case + epoll_pwait() is equivalent to epoll_wait(). + + But doing that under valgrind gives: + + ==13887== Syscall param epoll_pwait(sigmask) points to unaddressable byte(s) + ==13887== at 0x4F2B940: epoll_pwait (epoll_pwait.c:43) + ==13887== by 0x400ADE: main (syscalls-2007.c:89) + ==13887== Address 0x0 is not stack'd, malloc'd or (recently) free'd + + This is because the sys_epoll_pwait wrapper has: + + if (ARG4) + PRE_MEM_READ( "epoll_pwait(sigmask)", ARG5, sizeof(vki_sigset_t) ); + + Which looks like a typo (ARG4 is timeout and ARG5 is sigmask). + + This shows up with newer glibc which translates an epoll_wait call into + an epoll_pwait call with NULL sigmask. + + Fix typo and add a testcase. + + https://bugs.kde.org/show_bug.cgi?id=381289 + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16451 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c +index 26e02fd..4120c1d 100644 +--- a/coregrind/m_syswrap/syswrap-linux.c ++++ b/coregrind/m_syswrap/syswrap-linux.c +@@ -1901,7 +1901,7 @@ PRE(sys_epoll_pwait) + int, maxevents, int, timeout, vki_sigset_t *, sigmask, + vki_size_t, sigsetsize); + PRE_MEM_WRITE( "epoll_pwait(events)", ARG2, sizeof(struct vki_epoll_event)*ARG3); +- if (ARG4) ++ if (ARG5) + PRE_MEM_READ( "epoll_pwait(sigmask)", ARG5, sizeof(vki_sigset_t) ); + } + POST(sys_epoll_pwait) +diff --git a/memcheck/tests/linux/syscalls-2007.c b/memcheck/tests/linux/syscalls-2007.c +index b61c6d5..5494623 100644 +--- a/memcheck/tests/linux/syscalls-2007.c ++++ b/memcheck/tests/linux/syscalls-2007.c +@@ -79,5 +79,16 @@ int main (void) + } + #endif + ++#if defined(HAVE_EPOLL_CREATE) && defined(HAVE_EPOLL_PWAIT) ++ { ++ int fd3; ++ struct epoll_event evs[10]; ++ ++ fd3 = epoll_create (10); ++ /* epoll_pwait can take a NULL sigmask. */ ++ epoll_pwait (fd3, evs, 10, 1, NULL); ++ } ++#endif ++ + return 0; + } diff --git a/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch b/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch new file mode 100644 index 0000000..f34da04 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch @@ -0,0 +1,183 @@ +commit 21788250c945713fa25c16f2683e1f9cd0bb6ccf +Author: philippe +Date: Sun Jun 25 12:40:53 2017 +0000 + + Fix some tests failure with GDB 8.0 + + At the beginning of a Valgrind gdbserver test, + 2 messages are produced when launching the command + target remote | vgdb + + A message output by vgdb: + relaying data between gdb and process + (this message is read by GDB from the vgdb pipe, and re-output + on stderr) + and a message produced by GDB: + Remote debugging using | ./vgdb + + GDB 8.0 changes the order in which the above messages are output. + This causes 2 tests to fail, as the 'relaying' line appears + then in a part of the output deleted by a filter script. + + To avoid this, change the filter scripts to always remove + this 'relaying line', which is not particularly interesting to check. + All the .exp files containining such a 'relaying' line are updated + accordingly. + + This has been tested with various gdb versions (7.5, 7.7, 7.12, 8.0) + on amd64 and/or ppc64. + + Thanks to Mark Wielaard, which helped to investigate this problem + by bisecting the GDB patches in GDB 8.0 causing this change of + behaviour. + + + + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16453 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/gdbserver_tests/filter_gdb b/gdbserver_tests/filter_gdb +index 7177720..ed78cfe 100755 +--- a/gdbserver_tests/filter_gdb ++++ b/gdbserver_tests/filter_gdb +@@ -72,7 +72,7 @@ sed -e '/Remote debugging using/,/vgdb launched process attached/d' + -e '/^Missing separate debuginfo/d' \ + -e '/\/_exit.c: No such file or directory/d' \ + -e '/^Try: zypper install -C/d' \ +- -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../' \ ++ -e '/relaying data between gdb and process/d' \ + -e 's/pid [0-9][0-9]*/pid ..../g' \ + -e 's/Thread [0-9][0-9]*/Thread ..../g' \ + -e '/\[Switching to Thread ....\]/d' \ +diff --git a/gdbserver_tests/filter_vgdb b/gdbserver_tests/filter_vgdb +index 2442ec5..f8028a3 100755 +--- a/gdbserver_tests/filter_vgdb ++++ b/gdbserver_tests/filter_vgdb +@@ -11,7 +11,7 @@ $dir/../tests/filter_addresses | + # pid + # gdb 7.2 sometimes tries to access address 0x0 (same as with standard gdbserver) + # filter a debian 6.0/ppc32 line +-sed -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../' \ ++sed -e '/relaying data between gdb and process/d' \ + -e 's/\(sending command .* to pid \)[0-9][0-9]*/\1..../' \ + -e '/Cannot access memory at address 0x......../d' \ + -e '/^[1-9][0-9]* \.\.\/sysdeps\/powerpc\/powerpc32\/dl-start\.S: No such file or directory\./d' | +diff --git a/gdbserver_tests/hginfo.stderrB.exp b/gdbserver_tests/hginfo.stderrB.exp +index df47f11..669ff92 100644 +--- a/gdbserver_tests/hginfo.stderrB.exp ++++ b/gdbserver_tests/hginfo.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Lock ga 0x........ { + Address 0x........ is 0 bytes inside data symbol "mx" +diff --git a/gdbserver_tests/mcblocklistsearch.stderrB.exp b/gdbserver_tests/mcblocklistsearch.stderrB.exp +index 312d776..1313321 100644 +--- a/gdbserver_tests/mcblocklistsearch.stderrB.exp ++++ b/gdbserver_tests/mcblocklistsearch.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Breakpoint 1 at 0x........: file leak-tree.c, line 42. + Breakpoint 2 at 0x........: file leak-tree.c, line 67. +diff --git a/gdbserver_tests/mcbreak.stderrB.exp b/gdbserver_tests/mcbreak.stderrB.exp +index 65281d2..0f051d1 100644 +--- a/gdbserver_tests/mcbreak.stderrB.exp ++++ b/gdbserver_tests/mcbreak.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + vgdb-error value changed from 999999 to 0 + n_errs_found 1 n_errs_shown 1 (vgdb-error 0) +diff --git a/gdbserver_tests/mcclean_after_fork.stderrB.exp b/gdbserver_tests/mcclean_after_fork.stderrB.exp +index 995b42f..e812b8e 100644 +--- a/gdbserver_tests/mcclean_after_fork.stderrB.exp ++++ b/gdbserver_tests/mcclean_after_fork.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + monitor command request to kill this process + Remote connection closed +diff --git a/gdbserver_tests/mcinfcallWSRU.stderrB.exp b/gdbserver_tests/mcinfcallWSRU.stderrB.exp +index 7789123..a2f2b87 100644 +--- a/gdbserver_tests/mcinfcallWSRU.stderrB.exp ++++ b/gdbserver_tests/mcinfcallWSRU.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Breakpoint 1 at 0x........: file sleepers.c, line 74. + Continuing. +diff --git a/gdbserver_tests/mcleak.stderrB.exp b/gdbserver_tests/mcleak.stderrB.exp +index 7782119..7ed3920 100644 +--- a/gdbserver_tests/mcleak.stderrB.exp ++++ b/gdbserver_tests/mcleak.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + 10 bytes in 1 blocks are still reachable in loss record ... of ... + at 0x........: malloc (vg_replace_malloc.c:...) +diff --git a/gdbserver_tests/mcmain_pic.stderrB.exp b/gdbserver_tests/mcmain_pic.stderrB.exp +index c90e1fa..53ec0ce 100644 +--- a/gdbserver_tests/mcmain_pic.stderrB.exp ++++ b/gdbserver_tests/mcmain_pic.stderrB.exp +@@ -1,2 +1 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 +diff --git a/gdbserver_tests/mcvabits.stderrB.exp b/gdbserver_tests/mcvabits.stderrB.exp +index bdabb1e..f9ced7a 100644 +--- a/gdbserver_tests/mcvabits.stderrB.exp ++++ b/gdbserver_tests/mcvabits.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Address 0x........ len 10 addressable + Address 0x........ is 0 bytes inside data symbol "undefined" +diff --git a/gdbserver_tests/mssnapshot.stderrB.exp b/gdbserver_tests/mssnapshot.stderrB.exp +index 8bee8fc..e419ce6 100644 +--- a/gdbserver_tests/mssnapshot.stderrB.exp ++++ b/gdbserver_tests/mssnapshot.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + general valgrind monitor commands: + help [debug] : monitor command help. With debug: + debugging commands +diff --git a/gdbserver_tests/nlgone_abrt.stderrB.exp b/gdbserver_tests/nlgone_abrt.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlgone_abrt.stderrB.exp ++++ b/gdbserver_tests/nlgone_abrt.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlgone_exit.stderrB.exp b/gdbserver_tests/nlgone_exit.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlgone_exit.stderrB.exp ++++ b/gdbserver_tests/nlgone_exit.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlgone_return.stderrB.exp b/gdbserver_tests/nlgone_return.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlgone_return.stderrB.exp ++++ b/gdbserver_tests/nlgone_return.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlpasssigalrm.stderrB.exp b/gdbserver_tests/nlpasssigalrm.stderrB.exp +index c90e1fa..53ec0ce 100644 +--- a/gdbserver_tests/nlpasssigalrm.stderrB.exp ++++ b/gdbserver_tests/nlpasssigalrm.stderrB.exp +@@ -1,2 +1 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 +diff --git a/gdbserver_tests/nlself_invalidate.stderrB.exp b/gdbserver_tests/nlself_invalidate.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlself_invalidate.stderrB.exp ++++ b/gdbserver_tests/nlself_invalidate.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlsigvgdb.stderrB.exp b/gdbserver_tests/nlsigvgdb.stderrB.exp +index 672fea5..ed5bb61 100644 +--- a/gdbserver_tests/nlsigvgdb.stderrB.exp ++++ b/gdbserver_tests/nlsigvgdb.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + gdbserver: continuing in 5000 ms ... + gdbserver: continuing after wait ... diff --git a/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch b/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch new file mode 100644 index 0000000..8356773 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch @@ -0,0 +1,161 @@ +commit 326d53c8378984c50f29bd124d3f2b4a1242306c +Author: mjw +Date: Fri Jun 16 09:33:35 2017 +0000 + + ppc64 doesn't compile test_isa_2_06_partx.c without VSX support + + The #ifdef HAS_VSX guard is wrongly placed. It makes the standard + include headers not be used. Causing a build failure. Fix by moving + the #ifdef HAS_VSX after the standard includes. + + https://bugs.kde.org/show_bug.cgi?id=381272 + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16450 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/none/tests/ppc32/test_isa_2_06_part1.c b/none/tests/ppc32/test_isa_2_06_part1.c +index 7cd4930..7a14c6d 100644 +--- a/none/tests/ppc32/test_isa_2_06_part1.c ++++ b/none/tests/ppc32/test_isa_2_06_part1.c +@@ -20,13 +20,14 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include ++ ++#ifdef HAS_VSX ++ + #include + + #ifndef __powerpc64__ +diff --git a/none/tests/ppc32/test_isa_2_06_part2.c b/none/tests/ppc32/test_isa_2_06_part2.c +index c7bf4fe..2ee7b53 100644 +--- a/none/tests/ppc32/test_isa_2_06_part2.c ++++ b/none/tests/ppc32/test_isa_2_06_part2.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else +diff --git a/none/tests/ppc32/test_isa_2_06_part3.c b/none/tests/ppc32/test_isa_2_06_part3.c +index 8c74c09..5ebc1a5 100644 +--- a/none/tests/ppc32/test_isa_2_06_part3.c ++++ b/none/tests/ppc32/test_isa_2_06_part3.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else + +diff --git a/none/tests/ppc64/test_isa_2_06_part1.c b/none/tests/ppc64/test_isa_2_06_part1.c +index 7cd4930..7a14c6d 100644 +--- a/none/tests/ppc64/test_isa_2_06_part1.c ++++ b/none/tests/ppc64/test_isa_2_06_part1.c +@@ -20,13 +20,14 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include ++ ++#ifdef HAS_VSX ++ + #include + + #ifndef __powerpc64__ +diff --git a/none/tests/ppc64/test_isa_2_06_part2.c b/none/tests/ppc64/test_isa_2_06_part2.c +index c7bf4fe..2ee7b53 100644 +--- a/none/tests/ppc64/test_isa_2_06_part2.c ++++ b/none/tests/ppc64/test_isa_2_06_part2.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else +diff --git a/none/tests/ppc64/test_isa_2_06_part3.c b/none/tests/ppc64/test_isa_2_06_part3.c +index 8c74c09..5ebc1a5 100644 +--- a/none/tests/ppc64/test_isa_2_06_part3.c ++++ b/none/tests/ppc64/test_isa_2_06_part3.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else diff --git a/SOURCES/valgrind-3.13.0-ppc64-diag.patch b/SOURCES/valgrind-3.13.0-ppc64-diag.patch new file mode 100644 index 0000000..eba0acb --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-diag.patch @@ -0,0 +1,109 @@ +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index e16e837..a8d4926 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -29356,62 +29356,70 @@ DisResult disInstr_PPC_WRK ( + + decode_noF: + vassert(!allow_F); +- vex_printf("disInstr(ppc): found the Floating Point instruction 0x%x that\n" +- "can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports Floating Point instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Floating Point instruction 0x%x that\n" ++ "can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports Floating Point instructions.\n", ++ theInstr); + goto not_supported; + decode_noV: + vassert(!allow_V); +- vex_printf("disInstr(ppc): found an AltiVec or an e500 instruction 0x%x\n" +- "that can't be handled by Valgrind. If this instruction is an\n" +- "Altivec instruction, Valgrind must be run on a host that supports" +- "AltiVec instructions. If the application was compiled for e500, then\n" +- "unfortunately Valgrind does not yet support e500 instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found an AltiVec or an e500 instruction 0x%x\n" ++ "that can't be handled by Valgrind. If this instruction is an\n" ++ "Altivec instruction, Valgrind must be run on a host that supports" ++ "AltiVec instructions. If the application was compiled for e500, then\n" ++ "unfortunately Valgrind does not yet support e500 instructions.\n", ++ theInstr); + goto not_supported; + decode_noVX: + vassert(!allow_VX); +- vex_printf("disInstr(ppc): found the instruction 0x%x that is defined in the\n" +- "Power ISA 2.06 ABI but can't be handled by Valgrind on this host.\n" +- "This instruction \nrequires a host that supports the ISA 2.06 ABI.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the instruction 0x%x that is defined in the\n" ++ "Power ISA 2.06 ABI but can't be handled by Valgrind on this host.\n" ++ "This instruction \nrequires a host that supports the ISA 2.06 ABI.\n", ++ theInstr); + goto not_supported; + decode_noFX: + vassert(!allow_FX); +- vex_printf("disInstr(ppc): found the General Purpose-Optional instruction 0x%x\n" +- "that can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports the General Purpose-Optional instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the General Purpose-Optional instruction 0x%x\n" ++ "that can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports the General Purpose-Optional instructions.\n", ++ theInstr); + goto not_supported; + decode_noGX: + vassert(!allow_GX); +- vex_printf("disInstr(ppc): found the Graphics-Optional instruction 0x%x\n" +- "that can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports the Graphic-Optional instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Graphics-Optional instruction 0x%x\n" ++ "that can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports the Graphic-Optional instructions.\n", ++ theInstr); + goto not_supported; + decode_noDFP: + vassert(!allow_DFP); +- vex_printf("disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x\n" +- "that can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports DFP instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x\n" ++ "that can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports DFP instructions.\n", ++ theInstr); + goto not_supported; + decode_noP8: + vassert(!allow_isa_2_07); +- vex_printf("disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled\n" +- "by Valgrind on this host. This instruction requires a host that\n" +- "supports Power 8 instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled\n" ++ "by Valgrind on this host. This instruction requires a host that\n" ++ "supports Power 8 instructions.\n", ++ theInstr); + goto not_supported; + + decode_noP9: + vassert(!allow_isa_3_0); +- vex_printf("disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled\n" +- "by Valgrind on this host. This instruction requires a host that\n" +- "supports Power 9 instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled\n" ++ "by Valgrind on this host. This instruction requires a host that\n" ++ "supports Power 9 instructions.\n", ++ theInstr); + goto not_supported; + + decode_failure: diff --git a/SOURCES/valgrind-3.13.0-ppc64-timebase.patch b/SOURCES/valgrind-3.13.0-ppc64-timebase.patch new file mode 100644 index 0000000..d862b81 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-timebase.patch @@ -0,0 +1,99 @@ +commit 6a55b1e82ccda3f0d663d2cc89eb543ae2d096bf +Author: Carl Love +Date: Tue Oct 31 13:45:28 2017 -0500 + + Fix access to time base register to return 64-bits. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index f63146e7e..4ec37f5f9 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -9419,26 +9419,60 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + putIReg( rD_addr, getGST( PPC_GST_SPRG3_RO ) ); + break; + +- /* Even a lowly PPC7400 can run the associated helper, so no +- obvious need for feature testing at this point. */ +- case 268 /* 0x10C */: +- case 269 /* 0x10D */: { +- UInt arg = SPR==268 ? 0 : 1; +- IRTemp val = newTemp(Ity_I32); +- IRExpr** args = mkIRExprVec_1( mkU32(arg) ); ++ case 268 /* 0x10C TB - 64 bit time base register */: ++ { ++ IRTemp val = newTemp(Ity_I64); ++ IRExpr** args = mkIRExprVec_0(); + IRDirty* d = unsafeIRDirty_1_N( +- val, +- 0/*regparms*/, +- "ppc32g_dirtyhelper_MFSPR_268_269", +- fnptr_to_fnentry +- (vbi, &ppc32g_dirtyhelper_MFSPR_268_269), +- args +- ); ++ val, ++ 0/*regparms*/, ++ "ppcg_dirtyhelper_MFTB", ++ fnptr_to_fnentry(vbi, ++ &ppcg_dirtyhelper_MFTB), ++ args ); ++ /* execute the dirty call, dumping the result in val. */ ++ stmt( IRStmt_Dirty(d) ); ++ putIReg( rD_addr, (mode64) ? mkexpr(val) : ++ unop(Iop_64to32, mkexpr(val)) ); ++ ++ break; ++ } ++ case 269 /* 0x10D TBU - upper 32-bits of time base register */: ++ { ++ DIP("mfspr r%u,%u", rD_addr, SPR); ++ IRTemp val = newTemp(Ity_I64); ++ IRExpr** args = mkIRExprVec_0(); ++ IRDirty* d = unsafeIRDirty_1_N( ++ val, ++ 0/*regparms*/, ++ "ppcg_dirtyhelper_MFTB", ++ fnptr_to_fnentry(vbi, ++ &ppcg_dirtyhelper_MFTB), ++ args ); + /* execute the dirty call, dumping the result in val. */ + stmt( IRStmt_Dirty(d) ); + putIReg( rD_addr, +- mkWidenFrom32(ty, mkexpr(val), False/*unsigned*/) ); ++ mkWidenFrom32(ty, unop(Iop_64HIto32, mkexpr(val)), ++ /* Signed */False) ); ++ break; ++ } ++ case 284 /* 0x1 TBL - lower 32-bits of time base register */: ++ { + DIP("mfspr r%u,%u", rD_addr, SPR); ++ IRTemp val = newTemp(Ity_I64); ++ IRExpr** args = mkIRExprVec_0(); ++ IRDirty* d = unsafeIRDirty_1_N( ++ val, ++ 0/*regparms*/, ++ "ppcg_dirtyhelper_MFTB", ++ fnptr_to_fnentry(vbi, ++ &ppcg_dirtyhelper_MFTB), ++ args ); ++ /* execute the dirty call, dumping the result in val. */ ++ stmt( IRStmt_Dirty(d) ); ++ putIReg( rD_addr, ++ mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(val)), ++ /* Signed */False) ); + break; + } + +@@ -9493,6 +9527,12 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + putIReg( rD_addr, (mode64) ? mkexpr(val) : + unop(Iop_64to32, mkexpr(val)) ); + break; ++ case 284: ++ DIP("mftbl r%u", rD_addr); ++ putIReg( rD_addr, ++ mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(val)), ++ /* Signed */False) ); ++ break; + default: + return False; /* illegal instruction */ + } diff --git a/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch b/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch new file mode 100644 index 0000000..bc41de6 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch @@ -0,0 +1,5703 @@ +commit 7fce2c5269f82a7d063c87335a25de84fc9acc64 +Author: Carl Love +Date: Tue Oct 3 12:03:22 2017 -0500 + + PPC64, Add support for the Data Stream Control Register (DSCR) + +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index 8230d65..34adf62 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -921,6 +921,7 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state ) + vex_state->guest_TEXASR = 0; + vex_state->guest_PPR = 0x4ULL << 50; // medium priority + vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with ++ vex_state->guest_DSCR = 0; + } + + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index a8d4926..2467f70 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -296,6 +296,7 @@ static Bool OV32_CA32_supported = False; + #define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR) + #define OFFB_PPR offsetofPPCGuestState(guest_PPR) + #define OFFB_PSPB offsetofPPCGuestState(guest_PSPB) ++#define OFFB_DSCR offsetofPPCGuestState(guest_DSCR) + + + /*------------------------------------------------------------*/ +@@ -459,6 +460,7 @@ typedef enum { + * automatically decrement. Could be added later if + * needed. + */ ++ PPC_GST_DSCR, // Data Stream Control Register + PPC_GST_MAX + } PPC_GST; + +@@ -3068,6 +3070,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg ) + case PPC_GST_PSPB: + return IRExpr_Get( OFFB_PSPB, ty ); + ++ case PPC_GST_DSCR: ++ return IRExpr_Get( OFFB_DSCR, ty ); ++ + default: + vex_printf("getGST(ppc): reg = %u", reg); + vpanic("getGST(ppc)"); +@@ -3344,6 +3349,11 @@ static void putGST ( PPC_GST reg, IRExpr* src ) + mkU64( 0x1C000000000000) ) ) ); + break; + } ++ case PPC_GST_DSCR: ++ vassert( ty_src == Ity_I64 ); ++ stmt( IRStmt_Put( OFFB_DSCR, src ) ); ++ break; ++ + default: + vex_printf("putGST(ppc): reg = %u", reg); + vpanic("putGST(ppc)"); +@@ -9407,6 +9417,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ), + /* Signed */False) ); + break; ++ case 0x3: // 131 ++ DIP("mfspr r%u (DSCR)\n", rD_addr); ++ putIReg( rD_addr, getGST( PPC_GST_DSCR) ); ++ break; + case 0x8: + DIP("mflr r%u\n", rD_addr); + putIReg( rD_addr, getGST( PPC_GST_LR ) ); +@@ -9575,6 +9589,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + DIP("mtxer r%u\n", rS_addr); + putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) ); + break; ++ case 0x3: ++ DIP("mtspr r%u (DSCR)\n", rS_addr); ++ putGST( PPC_GST_DSCR, mkexpr(rS) ); ++ break; + case 0x8: + DIP("mtlr r%u\n", rS_addr); + putGST( PPC_GST_LR, mkexpr(rS) ); +diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h +index 816ef5a..bb48ac5 100644 +--- a/VEX/pub/libvex_guest_ppc32.h ++++ b/VEX/pub/libvex_guest_ppc32.h +@@ -252,8 +252,8 @@ typedef + /* 1388 */ ULong guest_PPR; // Program Priority register + /* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper + /* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register ++ /* 1404 */ ULong guest_DSCR; // Data Stream Control register + /* Padding to make it have an 16-aligned size */ +- /* 1404 */ UInt padding2; + /* 1408 */ UInt padding3; + /* 1412 */ UInt padding4; + } +diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h +index 02c4020..8c01fa6 100644 +--- a/VEX/pub/libvex_guest_ppc64.h ++++ b/VEX/pub/libvex_guest_ppc64.h +@@ -292,11 +292,12 @@ typedef + /* 1686 */ ULong guest_PPR; // Program Priority register + /* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper + /* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register ++ /* 1702 */ ULong guest_DSCR; // Data Stream Control register + + /* Padding to make it have an 16-aligned size */ +- /* 1698 */ UInt padding1; +- /* 1702 UInt padding2; */ +- /* 1706 UInt padding3; */ ++ /* 1710 */ UInt padding1; ++ /* 1714 */ UInt padding2; ++ /* 1718 */ UInt padding3; + + } + VexGuestPPC64State; +diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c +index 3ff7c44..1d57e0c 100644 +--- a/memcheck/mc_machine.c ++++ b/memcheck/mc_machine.c +@@ -194,6 +194,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) + if (o == GOF(TFIAR) && sz == 8) return -1; + if (o == GOF(PPR) && sz == 8) return -1; + if (o == GOF(PSPB) && sz == 8) return -1; ++ if (o == GOF(DSCR) && sz == 8) return -1; + + // With ISA 2.06, the "Vector-Scalar Floating-point" category + // provides facilities to support vector and scalar binary floating- +diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c +index a9a565b..892e503 100644 +--- a/memcheck/mc_main.c ++++ b/memcheck/mc_main.c +@@ -4468,7 +4468,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid, + static void mc_post_reg_write ( CorePart part, ThreadId tid, + PtrdiffT offset, SizeT size) + { +-# define MAX_REG_WRITE_SIZE 1728 ++# define MAX_REG_WRITE_SIZE 1744 + UChar area[MAX_REG_WRITE_SIZE]; + tl_assert(size <= MAX_REG_WRITE_SIZE); + VG_(memset)(area, V_BITS8_DEFINED, size); + +commit acdeb75d2a58f4f3910ddaf9b2bc2ec74378fa3a +Author: Carl Love +Date: Tue Oct 3 12:08:09 2017 -0500 + + PPC64, Replace body of generate_store_FPRF with C helper function. + + The function calculates the floating point condition code values + and stores them into the floating point condition code register. + The function is used by a number of instructions. The calculation + generates a lot of Iops as it much check the operatds for NaN, SNaN, + zero, dnorm, norm and infinity. The large number of Iops exhausts + temporary memory. + +diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h +index fe411f7..f3eb956 100644 +--- a/VEX/priv/guest_ppc_defs.h ++++ b/VEX/priv/guest_ppc_defs.h +@@ -156,6 +156,7 @@ extern ULong convert_to_zoned_helper( ULong src_hi, ULong src_low, + extern ULong convert_to_national_helper( ULong src, ULong return_upper ); + extern ULong convert_from_zoned_helper( ULong src_hi, ULong src_low ); + extern ULong convert_from_national_helper( ULong src_hi, ULong src_low ); ++extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src ); + + + /* --- DIRTY HELPERS --- */ +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index 34adf62..bf2d071 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -216,6 +216,110 @@ IRExpr* guest_ppc64_spechelper ( const HChar* function_name, + } + + ++/* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */ ++#define I16_EXP_MASK 0x7C00 ++#define I16_FRACTION_MASK 0x03FF ++#define I32_EXP_MASK 0x7F800000 ++#define I32_FRACTION_MASK 0x007FFFFF ++#define I64_EXP_MASK 0x7FF0000000000000ULL ++#define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL ++#define V128_EXP_MASK 0x7FFF000000000000ULL ++#define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL /* upper 64-bit fractional mask */ ++ ++ULong generate_C_FPCC_helper( ULong irType, ULong src_hi, ULong src ) ++{ ++ UInt NaN, inf, zero, norm, dnorm, pos; ++ UInt bit0, bit1, bit2, bit3; ++ UInt sign_bit = 0; ++ ULong exp_mask = 0, exp_part = 0, frac_part = 0; ++ ULong fpcc, c; ++ ++ if ( irType == Ity_I16 ) { ++ frac_part = I16_FRACTION_MASK & src; ++ exp_mask = I16_EXP_MASK; ++ exp_part = exp_mask & src; ++ sign_bit = src >> 15; ++ ++ } else if ( irType == Ity_I32 ) { ++ frac_part = I32_FRACTION_MASK & src; ++ exp_mask = I32_EXP_MASK; ++ exp_part = exp_mask & src; ++ sign_bit = src >> 31; ++ ++ } else if ( irType == Ity_I64 ) { ++ frac_part = I64_FRACTION_MASK & src; ++ exp_mask = I64_EXP_MASK; ++ exp_part = exp_mask & src; ++ sign_bit = src >> 63; ++ ++ } else if ( irType == Ity_F128 ) { ++ /* only care if the frac part is zero or non-zero */ ++ frac_part = (V128_FRACTION_MASK & src_hi) | src; ++ exp_mask = V128_EXP_MASK; ++ exp_part = exp_mask & src_hi; ++ sign_bit = src_hi >> 63; ++ } else { ++ vassert(0); // Unknown value of irType ++ } ++ ++ /* NaN: exponene is all ones, fractional part not zero */ ++ if ((exp_part == exp_mask) && (frac_part != 0)) ++ NaN = 1; ++ else ++ NaN = 0; ++ ++ /* inf: exponent all 1's, fraction part is zero */ ++ if ((exp_part == exp_mask) && (frac_part == 0)) ++ inf = 1; ++ else ++ inf = 0; ++ ++ /* zero: exponent is 0, fraction part is zero */ ++ if ((exp_part == 0) && (frac_part == 0)) ++ zero = 1; ++ else ++ zero = 0; ++ ++ /* norm: exponent is not 0, exponent is not all 1's */ ++ if ((exp_part != 0) && (exp_part != exp_mask)) ++ norm = 1; ++ else ++ norm = 0; ++ ++ /* dnorm: exponent is all 0's, fraction is not 0 */ ++ if ((exp_part == 0) && (frac_part != 0)) ++ dnorm = 1; ++ else ++ dnorm = 0; ++ ++ /* pos: MSB is 1 */ ++ if (sign_bit == 0) ++ pos = 1; ++ else ++ pos = 0; ++ ++ /* calculate FPCC */ ++ /* If the result is NaN then must force bits 1, 2 and 3 to zero ++ * to get correct result. ++ */ ++ bit0 = NaN | inf; ++ ++ bit1 = (!NaN) & zero; ++ bit2 = (!NaN) & ((pos & dnorm) | (pos & norm) | (pos & inf)) ++ & ((!zero) & (!NaN)); ++ bit3 = (!NaN) & (((!pos) & dnorm) |((!pos) & norm) | ((!pos) & inf)) ++ & ((!zero) & (!NaN)); ++ ++ fpcc = (bit3 << 3) | (bit2 << 2) | (bit1 << 1) | bit0; ++ ++ /* calculate C */ ++ c = NaN | ((!pos) & dnorm) | ((!pos) & zero) | (pos & dnorm); ++ ++ /* return C in the upper 32-bits and FPCC in the lower 32 bits */ ++ return (c <<32) | fpcc; ++} ++ ++ + /*---------------------------------------------------------------*/ + /*--- Misc BCD clean helpers. ---*/ + /*---------------------------------------------------------------*/ +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 2467f70..0dae368 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -3860,7 +3860,7 @@ static IRExpr * is_Denorm( IRType size, IRTemp src ) + + setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); + +- /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ ++ /* check exponent is all zeros */ + zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) ); + + /* check fractional part is not zero */ +@@ -3871,8 +3871,11 @@ static IRExpr * is_Denorm( IRType size, IRTemp src ) + return mkAND1( zero_exp, not_zero_frac ); + } + ++#if 0 + /* Normalized number has exponent between 1 and max_exp -1, or in other words + the exponent is not zero and not equal to the max exponent value. */ ++ Currently not needed since generate_C_FPCC is now done with a C helper. ++ Keep it around, might be useful in the future. + static IRExpr * is_Norm( IRType size, IRTemp src ) + { + IRExpr *not_zero_exp, *not_max_exp; +@@ -3919,72 +3922,18 @@ static IRExpr * is_Norm( IRType size, IRTemp src ) + + return mkAND1( not_zero_exp, not_max_exp ); + } ++#endif + +- +-static IRExpr * create_FPCC( IRTemp NaN, IRTemp inf, +- IRTemp zero, IRTemp norm, +- IRTemp dnorm, IRTemp pos, +- IRTemp neg ) { +- IRExpr *bit0, *bit1, *bit2, *bit3; +- +- /* If the result is NaN then must force bits 1, 2 and 3 to zero +- * to get correct result. +- */ +- bit0 = unop( Iop_1Uto32, mkOR1( mkexpr( NaN ), mkexpr( inf ) ) ); +- bit1 = unop( Iop_1Uto32, mkAND1( mkNOT1( mkexpr( NaN ) ), mkexpr( zero ) ) ); +- bit2 = unop( Iop_1Uto32, +- mkAND1( mkNOT1( mkexpr( NaN ) ), +- mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( pos ), +- mkexpr( dnorm ) ), +- mkAND1( mkexpr( pos ), +- mkexpr( norm ) ) ), +- mkAND1( mkexpr( pos ), +- mkexpr( inf ) ) ), +- mkAND1( mkNOT1 ( mkexpr( zero ) ), +- mkNOT1( mkexpr( NaN ) ) ) ) ) ); +- bit3 = unop( Iop_1Uto32, +- mkAND1( mkNOT1( mkexpr( NaN ) ), +- mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( neg ), +- mkexpr( dnorm ) ), +- mkAND1( mkexpr( neg ), +- mkexpr( norm ) ) ), +- mkAND1( mkexpr( neg ), +- mkexpr( inf ) ) ), +- mkAND1( mkNOT1 ( mkexpr( zero ) ), +- mkNOT1( mkexpr( NaN ) ) ) ) ) ); +- +- return binop( Iop_Or32, +- binop( Iop_Or32, +- bit0, +- binop( Iop_Shl32, bit1, mkU8( 1 ) ) ), +- binop( Iop_Or32, +- binop( Iop_Shl32, bit2, mkU8( 2 ) ), +- binop( Iop_Shl32, bit3, mkU8( 3 ) ) ) ); +-} +- +-static IRExpr * create_C( IRTemp NaN, IRTemp zero, +- IRTemp dnorm, IRTemp pos, +- IRTemp neg ) +-{ +- +- return unop( Iop_1Uto32, +- mkOR1( mkOR1( mkexpr( NaN ), +- mkAND1( mkexpr( neg ), mkexpr( dnorm ) ) ), +- mkOR1( mkAND1( mkexpr( neg ), mkexpr( zero ) ), +- mkAND1( mkexpr( pos ), mkexpr( dnorm ) ) ) ) ); +-} +- +-static void generate_store_FPRF( IRType size, IRTemp src ) ++static void generate_store_FPRF( IRType size, IRTemp src, ++ const VexAbiInfo* vbi ) + { +- IRExpr *FPCC, *C; +- IRTemp NaN = newTemp( Ity_I1 ), inf = newTemp( Ity_I1 ); +- IRTemp dnorm = newTemp( Ity_I1 ), norm = newTemp( Ity_I1 ); +- IRTemp pos = newTemp( Ity_I1 ), neg = newTemp( Ity_I1 ); +- IRTemp zero = newTemp( Ity_I1 ); + +- IRTemp sign_bit = newTemp( Ity_I1 ); +- IRTemp value; ++ /* This function was originally written using IR code. It has been ++ * replaced with a clean helper due to the large amount of IR code ++ * needed by this function. ++ */ + ++ IRTemp tmp = newTemp( Ity_I64 ); + vassert( ( size == Ity_I16 ) || ( size == Ity_I32 ) + || ( size == Ity_I64 ) || ( size == Ity_F128 ) ); + +@@ -3993,82 +3942,45 @@ static void generate_store_FPRF( IRType size, IRTemp src ) + || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_F128 ) ); + + if( size == Ity_I16 ) { +- /* The 16-bit floating point value is in the lower 16-bits of +- the 32-bit input value */ +- value = newTemp( Ity_I32 ); +- assign( value, mkexpr( src ) ); +- assign( sign_bit, +- unop ( Iop_32to1, +- binop( Iop_And32, +- binop( Iop_Shr32, mkexpr( value ), mkU8( 15 ) ), +- mkU32( 0x1 ) ) ) ); +- ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), mkU64( 0 ), ++ mkexpr( src ) ) ) ); + } else if( size == Ity_I32 ) { +- value = newTemp( size ); +- assign( value, mkexpr( src ) ); +- assign( sign_bit, +- unop ( Iop_32to1, +- binop( Iop_And32, +- binop( Iop_Shr32, mkexpr( value ), mkU8( 31 ) ), +- mkU32( 0x1 ) ) ) ); +- ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), mkU64( 0 ), ++ mkexpr( src ) ) ) ); + } else if( size == Ity_I64 ) { +- value = newTemp( size ); +- assign( value, mkexpr( src ) ); +- assign( sign_bit, +- unop ( Iop_64to1, +- binop( Iop_And64, +- binop( Iop_Shr64, mkexpr( value ), mkU8( 63 ) ), +- mkU64( 0x1 ) ) ) ); +- +- } else { +- /* Move the F128 bit pattern to an integer V128 bit pattern */ +- value = newTemp( Ity_V128 ); +- assign( value, +- binop( Iop_64HLtoV128, +- unop( Iop_ReinterpF64asI64, +- unop( Iop_F128HItoF64, mkexpr( src ) ) ), +- unop( Iop_ReinterpF64asI64, +- unop( Iop_F128LOtoF64, mkexpr( src ) ) ) ) ); +- +- size = Ity_V128; +- assign( sign_bit, +- unop ( Iop_64to1, +- binop( Iop_And64, +- binop( Iop_Shr64, +- unop( Iop_V128HIto64, mkexpr( value ) ), +- mkU8( 63 ) ), +- mkU64( 0x1 ) ) ) ); ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), mkU64( 0 ), ++ mkexpr( src ) ) ) ); ++ } else if( size == Ity_F128 ) { ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), ++ unop( Iop_ReinterpF64asI64, ++ unop( Iop_F128HItoF64, ++ mkexpr( src ) ) ), ++ unop( Iop_ReinterpF64asI64, ++ unop( Iop_F128LOtoF64, ++ mkexpr( src ) ) ) ) ) ); + } + +- /* Calculate the floating point result field FPRF */ +- assign( NaN, is_NaN( size, value ) ); +- assign( inf, is_Inf( size, value ) ); +- assign( zero, is_Zero( size, value ) ); +- assign( norm, is_Norm( size, value ) ); +- assign( dnorm, is_Denorm( size, value ) ); +- assign( pos, mkAND1( mkNOT1( mkexpr( sign_bit ) ), mkU1( 1 ) ) ); +- assign( neg, mkAND1( mkexpr( sign_bit ), mkU1( 1 ) ) ); +- +- /* create the FPRF bit field +- * +- * FPRF field[4:0] type of value +- * 10001 QNaN +- * 01001 - infininity +- * 01000 - Normalized +- * 11000 - Denormalized +- * 10010 - zero +- * 00010 + zero +- * 10100 + Denormalized +- * 00100 + Normalized +- * 00101 + infinity ++ /* C is in the upper 32-bits, FPCC is in the lower 32-bits of the ++ * value returned by the helper function + */ +- FPCC = create_FPCC( NaN, inf, zero, norm, dnorm, pos, neg ); +- C = create_C( NaN, zero, dnorm, pos, neg ); +- +- /* Write the C and FPCC fields of the FPRF field */ +- putC( C ); +- putFPCC( FPCC ); ++ putC( unop( Iop_64HIto32, mkexpr( tmp) ) ); ++ putFPCC( unop( Iop_64to32, mkexpr( tmp) ) ); + } + + /* This function takes an Ity_I32 input argument interpreted +@@ -18538,7 +18450,8 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) + * Miscellaneous VSX Scalar Instructions + */ + static Bool +-dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 ) ++dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, ++ int allow_isa_3_0 ) + { + #define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL + /* XX3-Form and XX2-Form */ +@@ -18783,7 +18696,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 ) + putVSReg( XT, mkexpr( result ) ); + + assign( value, unop( Iop_V128HIto64, mkexpr( result ) ) ); +- generate_store_FPRF( Ity_I64, value ); ++ generate_store_FPRF( Ity_I64, value, vbi ); + return True; + + } else if (inst_select == 17) { // xscvdphp +@@ -18798,7 +18711,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 ) + assign( value, unop( Iop_64to32, unop( Iop_V128HIto64, + mkexpr( result ) ) ) ); + putVSReg( XT, mkexpr( result ) ); +- generate_store_FPRF( Ity_I16, value ); ++ generate_store_FPRF( Ity_I16, value, vbi ); + return True; + + } else { +@@ -21475,7 +21388,7 @@ dis_vx_store ( UInt theInstr ) + } + + static Bool +-dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) ++dis_vx_Scalar_Round_to_quad_integer( UInt theInstr, const VexAbiInfo* vbi ) + { + /* The ISA 3.0 instructions supported in this function require + * the underlying hardware platform that supports the ISA3.0 +@@ -21514,7 +21427,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) + DIP("xsrqpix %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC); + assign( vT, binop( Iop_F128toI128S, rm, mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + } /* case 0x005 */ + break; + case 0x025: // xsrqpxp VSX Scalar Round Quad-Precision to +@@ -21530,7 +21443,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) + + DIP("xsrqpxp %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC); + assign( vT, binop( Iop_RndF128, rm, mkexpr( vB ) ) ); +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + } /* case 0x025 */ + break; + default: +@@ -21542,7 +21455,8 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) + } + + static Bool +-dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) ++dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr, ++ const VexAbiInfo* vbi ) + { + /* The ISA 3.0 instructions supported in this function require + * the underlying hardware platform that supports the ISA 3.0 +@@ -21582,7 +21496,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_AddF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x024: // xsmulqp (VSX Scalar Multiply Quad-Precision[using round to Odd]) +@@ -21600,7 +21514,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_MulF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x184: // xsmaddqp (VSX Scalar Multiply add Quad-Precision[using round to Odd]) +@@ -21625,7 +21539,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_MAddF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x1A4: // xsmsubqp (VSX Scalar Multiply Subtract Quad-Precision[using round to Odd]) +@@ -21649,7 +21563,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_MSubF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x1C4: // xsnmaddqp (VSX Scalar Negative Multiply Add Quad-Precision[using round to Odd]) +@@ -21673,7 +21587,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_NegMAddF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x1E4: // xsmsubqp (VSX Scalar Negatve Multiply Subtract Quad-Precision[using round to Odd]) +@@ -21697,7 +21611,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_NegMSubF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x204: // xssubqp (VSX Scalar Subtract Quad-Precision[using round to Odd]) +@@ -21714,7 +21628,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_SubF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x224: // xsdivqp (VSX Scalar Divide Quad-Precision[using round to Odd]) +@@ -21731,7 +21645,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_DivF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x324: // xssqrtqp (VSX Scalar Square root Quad-Precision[using round to Odd]) +@@ -21752,7 +21666,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, binop( Iop_SqrtF128, set_round_to_Oddmode(), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } /* end case 27 */ + default: +@@ -21783,7 +21697,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( tmp, unop( Iop_ReinterpF64asI64, + unop( Iop_F128HItoF64, mkexpr( vB ) ) ) ); + assign( vT, unop( Iop_I64UtoF128, mkexpr( tmp ) ) ); +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 9: // xsvqpswz VSX Scalar Truncate & Convert Quad-Precision +@@ -21803,7 +21717,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( tmp, unop( Iop_ReinterpF64asI64, + unop( Iop_F128HItoF64, mkexpr( vB ) ) ) ); + assign( vT, unop( Iop_I64StoF128, mkexpr( tmp ) ) ); +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 17: // xsvqpudz VSX Scalar Truncate & Convert Quad-Precision +@@ -21855,7 +21769,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( tmp, unop( Iop_ReinterpF64asI64, + unop( Iop_F128HItoF64, mkexpr( vT ) ) ) ); + +- generate_store_FPRF( Ity_I64, tmp ); ++ generate_store_FPRF( Ity_I64, tmp, vbi ); + break; + } + case 22: // xscvdpqp VSX Scalar Convert from Double-Precision +@@ -21866,7 +21780,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, unop( Iop_F64toF128, + unop( Iop_F128HItoF64, mkexpr( vB ) ) ) ); + +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 25: // xsvqpsdz VSX Scalar Truncate & Convert Quad-Precision +@@ -28199,13 +28113,13 @@ DisResult disInstr_PPC_WRK ( + UInt vsxOpc2; + + if (( opc2hi == 13 ) && ( opc2lo == 5)) { //xvtstdcsp +- if (dis_vxs_misc(theInstr, 0x354, allow_isa_3_0)) ++ if (dis_vxs_misc(theInstr, abiinfo, 0x354, allow_isa_3_0)) + goto decode_success; + goto decode_failure; + } + + if (( opc2hi == 15 ) && ( opc2lo == 5)) { //xvtstdcdp +- if (dis_vxs_misc(theInstr, 0x3D4, allow_isa_3_0)) ++ if (dis_vxs_misc(theInstr, abiinfo, 0x3D4, allow_isa_3_0)) + goto decode_success; + goto decode_failure; + } +@@ -28221,7 +28135,7 @@ DisResult disInstr_PPC_WRK ( + /* This is a special case of the XX1 form where the RA, RB + * fields hold an immediate value. + */ +- if (dis_vxs_misc(theInstr, opc2, allow_isa_3_0)) goto decode_success; ++ if (dis_vxs_misc(theInstr, abiinfo, opc2, allow_isa_3_0)) goto decode_success; + goto decode_failure; + } + +@@ -28231,7 +28145,8 @@ DisResult disInstr_PPC_WRK ( + case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw + case 0x068: case 0xE8: // xxperm, xxpermr + case 0x018: case 0x148: // xxsel, xxspltw +- if (dis_vx_permute_misc(theInstr, vsxOpc2)) goto decode_success; ++ if (dis_vx_permute_misc(theInstr, vsxOpc2 )) ++ goto decode_success; + goto decode_failure; + case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor, + case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc +@@ -28255,7 +28170,7 @@ DisResult disInstr_PPC_WRK ( + case 0x354: // xvtstdcsp + case 0x360:case 0x396: // xviexpsp, xsiexpdp + case 0x3D4: case 0x3E0: // xvtstdcdp, xviexpdp +- if (dis_vxs_misc(theInstr, vsxOpc2, allow_isa_3_0)) ++ if (dis_vxs_misc(theInstr, abiinfo, vsxOpc2, allow_isa_3_0)) + goto decode_success; + goto decode_failure; + case 0x08C: case 0x0AC: // xscmpudp, xscmpodp +@@ -28409,7 +28324,7 @@ DisResult disInstr_PPC_WRK ( + case 0x5: // xsrqpi, xsrqpix + case 0x25: // xsrqpxp + if ( !mode64 || !allow_isa_3_0 ) goto decode_failure; +- if ( dis_vx_Scalar_Round_to_quad_integer( theInstr ) ) ++ if ( dis_vx_Scalar_Round_to_quad_integer( theInstr, abiinfo ) ) + goto decode_success; + goto decode_failure; + default: +@@ -28531,7 +28446,8 @@ DisResult disInstr_PPC_WRK ( + + case 0x324: // xsabsqp, xsxexpqp,xsnabsqp, xsnegqp, xsxsigqp + if ( inst_select == 27 ) { // xssqrtqp +- if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) ) ++ if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr, ++ abiinfo ) ) + goto decode_success; + } + +@@ -28566,7 +28482,8 @@ DisResult disInstr_PPC_WRK ( + case 0x344: // xscvudqp, xscvsdqp, xscvqpdp, xscvqpdpo, xsvqpdp + // xscvqpswz, xscvqpuwz, xscvqpudz, xscvqpsdz + if ( !mode64 || !allow_isa_3_0 ) goto decode_failure; +- if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) ) ++ if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr, ++ abiinfo ) ) + goto decode_success; + goto decode_failure; + + +commit a1d03d0d11c0b31a6d9f57baa4d46317fdd5f6ef +Author: Carl Love +Date: Tue Oct 3 15:09:22 2017 -0500 + + PPC64, Use the vperm code to implement the xxperm inst. + + The current xxperm instruction implementation generates a huge + number of Iops to explicitly do the permutation. The code + was changed to use the Iop_Perm8x16 which is much more efficient + so temporary memory doesn't get exhausted. + + Bugzilla 385208 + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 0dae368..1373d1c 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -22319,15 +22319,17 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + case 0x68: // xxperm (VSX Permute ) + case 0xE8: // xxpermr (VSX Permute right-index ) + { +- int i; +- IRTemp new_Vt[17]; +- IRTemp perm_val[16]; +- IRTemp perm_val_gt16[16]; +- IRTemp tmp_val[16]; +- IRTemp perm_idx[16]; +- IRTemp perm_mask = newTemp( Ity_V128 ); +- IRTemp val_mask = newTemp( Ity_V128 ); +- int dest_shift_amount = 0; ++ ++ /* The xxperm instruction performs the same operation as ++ the vperm except the xxperm operates on the VSR register ++ file. while vperm operates on the VR register file. ++ Lets borrow some code here from vperm. The mapping of ++ the source registers is also a little different. ++ */ ++ IRTemp a_perm = newTemp(Ity_V128); ++ IRTemp b_perm = newTemp(Ity_V128); ++ IRTemp mask = newTemp(Ity_V128); ++ IRTemp perm_val = newTemp(Ity_V128); + + if ( opc2 == 0x68 ) { + DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); +@@ -22337,119 +22339,40 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + DIP("xxpermr v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); + } + +- new_Vt[0] = newTemp( Ity_V128 ); +- + assign( vT, getVSReg( XT ) ); + +- assign( new_Vt[0], binop( Iop_64HLtoV128, +- mkU64( 0x0 ), mkU64( 0x0 ) ) ); +- assign( perm_mask, binop( Iop_64HLtoV128, +- mkU64( 0x0 ), mkU64( 0x1F ) ) ); +- assign( val_mask, binop( Iop_64HLtoV128, +- mkU64( 0x0 ), mkU64( 0xFF ) ) ); +- +- /* For each permute index in XB, the permute list, select the byte +- * from XA indexed by the permute index if the permute index is less +- * then 16. Copy the selected byte to the destination location in +- * the result. +- */ +- for ( i = 0; i < 16; i++ ) { +- perm_val_gt16[i] = newTemp( Ity_V128 ); +- perm_val[i] = newTemp( Ity_V128 ); +- perm_idx[i] = newTemp( Ity_I8 ); +- tmp_val[i] = newTemp( Ity_V128 ); +- new_Vt[i+1] = newTemp( Ity_V128 ); +- +- /* create mask to extract the permute index value from vB, +- * store value in least significant bits of perm_val +- */ +- if ( opc2 == 0x68 ) +- /* xxperm, the perm value is the index value in XB */ +- assign( perm_val[i], binop( Iop_ShrV128, +- binop( Iop_AndV128, +- mkexpr(vB), +- binop( Iop_ShlV128, +- mkexpr( perm_mask ), +- mkU8( (15 - i) * 8 ) ) ), +- mkU8( (15 - i) * 8 ) ) ); ++ if ( opc2 == 0x68 ) // xxperm ++ assign( perm_val, ++ binop( Iop_AndV128, mkexpr( vB ), ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ); + +- else +- /* xxpermr, the perm value is 31 - index value in XB */ +- assign( perm_val[i], +- binop( Iop_Sub8x16, +- binop( Iop_64HLtoV128, +- mkU64( 0 ), mkU64( 31 ) ), +- binop( Iop_ShrV128, +- binop( Iop_AndV128, +- mkexpr( vB ), +- binop( Iop_ShlV128, +- mkexpr( perm_mask ), +- mkU8( ( 15 - i ) * 8 ) ) ), +- mkU8( ( 15 - i ) * 8 ) ) ) ); +- +- /* Determine if the perm_val[] > 16. If it is, then the value +- * will come from xT otherwise it comes from xA. Either way, +- * create the mask to get the value from the source using the +- * lower 3 bits of perm_val[]. Create a 128 bit mask from the +- * upper bit of perm_val[] to be used to select from xT or xA. +- */ +- assign( perm_val_gt16[i], +- binop(Iop_64HLtoV128, +- unop( Iop_1Sto64, +- unop( Iop_64to1, +- unop( Iop_V128to64, +- binop( Iop_ShrV128, +- mkexpr( perm_val[i] ), +- mkU8( 4 ) ) ) ) ), +- unop( Iop_1Sto64, +- unop( Iop_64to1, +- unop( Iop_V128to64, +- binop( Iop_ShrV128, +- mkexpr( perm_val[i] ), +- mkU8( 4 ) ) ) ) ) ) ); +- +- assign( perm_idx[i], +- unop(Iop_32to8, +- binop( Iop_Mul32, +- binop( Iop_Sub32, +- mkU32( 15 ), +- unop( Iop_64to32, +- binop( Iop_And64, +- unop( Iop_V128to64, +- mkexpr( perm_val[i] ) ), +- mkU64( 0xF ) ) ) ), +- mkU32( 8 ) ) ) ); +- +- dest_shift_amount = ( 15 - i )*8; +- +- /* Use perm_val_gt16 to select value from vA or vT */ +- assign( tmp_val[i], +- binop( Iop_ShlV128, +- binop( Iop_ShrV128, +- binop( Iop_OrV128, +- binop( Iop_AndV128, +- mkexpr( vA ), +- binop( Iop_AndV128, +- unop( Iop_NotV128, +- mkexpr( perm_val_gt16[i] ) ), +- binop( Iop_ShlV128, +- mkexpr( val_mask ), +- mkexpr( perm_idx[i] ) ) ) ), +- binop( Iop_AndV128, +- mkexpr( vT ), +- binop( Iop_AndV128, +- mkexpr( perm_val_gt16[i] ), +- binop( Iop_ShlV128, +- mkexpr( val_mask ), +- mkexpr( perm_idx[i] ) ) ) ) ), +- mkexpr( perm_idx[i] ) ), +- mkU8( dest_shift_amount ) ) ); +- +- assign( new_Vt[i+1], binop( Iop_OrV128, +- mkexpr( tmp_val[i] ), +- mkexpr( new_Vt[i] ) ) ); +- } +- putVSReg( XT, mkexpr( new_Vt[16] ) ); ++ else // xxpermr ++ assign( perm_val, ++ binop( Iop_Sub16x8, ++ binop( Iop_64HLtoV128, ++ mkU64( 0x1F1F1F1F1F1F1F1F ), ++ mkU64( 0x1F1F1F1F1F1F1F1F ) ), ++ binop( Iop_AndV128, mkexpr( vB ), ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ ++ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ IR specifies, and also to hide irrelevant bits from ++ memcheck. ++ */ ++ assign( a_perm, ++ binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) ); ++ assign( b_perm, ++ binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) ); ++ assign( mask, binop( Iop_SarN8x16, ++ binop( Iop_ShlN8x16, mkexpr( perm_val ), ++ mkU8( 3 ) ), ++ mkU8( 7 ) ) ); ++ // dst = (a & ~mask) | (b & mask) ++ putVSReg( XT, binop( Iop_OrV128, ++ binop( Iop_AndV128, mkexpr( a_perm ), ++ unop( Iop_NotV128, mkexpr( mask ) ) ), ++ binop( Iop_AndV128, mkexpr( b_perm ), ++ mkexpr( mask ) ) ) ); + break; + } + + +commit b0aef250a74804423341b3ce804355037211e330 +Author: Carl Love +Date: Tue Oct 3 15:18:09 2017 -0500 + + PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16. + + The current implementation will generate a lot of Iops. The number + of generated Iops can lead to Valgrind running out of temporary space. + See bugzilla https://bugs.kde.org/show_bug.cgi?id=385208 as an example + of the issue. Using Iop_Perm8x16 reduces the number of Iops significantly. + + bugzilla 385210 + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 1373d1c..1785959 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -24107,107 +24107,40 @@ static Bool dis_av_permute ( UInt theInstr ) + } + + case 0x3B: { // vpermr (Vector Permute Right-indexed) +- int i; +- IRTemp new_Vt[17]; +- IRTemp tmp[16]; +- IRTemp index[16]; +- IRTemp index_gt16[16]; +- IRTemp mask[16]; +- +- DIP("vpermr v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr); +- +- new_Vt[0] = newTemp( Ity_V128 ); +- assign( new_Vt[0], binop( Iop_64HLtoV128, +- mkU64( 0x0 ), +- mkU64( 0x0 ) ) ); +- +- for ( i = 0; i < 16; i++ ) { +- index_gt16[i] = newTemp( Ity_V128 ); +- mask[i] = newTemp( Ity_V128 ); +- index[i] = newTemp( Ity_I32 ); +- tmp[i] = newTemp( Ity_V128 ); +- new_Vt[i+1] = newTemp( Ity_V128 ); +- +- assign( index[i], +- binop( Iop_Sub32, +- mkU32( 31 ), +- unop( Iop_64to32, +- unop( Iop_V128to64, +- binop( Iop_ShrV128, +- binop( Iop_AndV128, +- binop( Iop_ShlV128, +- binop( Iop_64HLtoV128, +- mkU64( 0x0 ), +- mkU64( 0x3F ) ), +- mkU8( (15 - i) * 8 ) ), +- mkexpr( vC ) ), +- mkU8( (15 - i) * 8 ) ) ) ) ) ); +- +- /* Determine if index < 16, src byte is vA[index], otherwise +- * vB[31-index]. Check if msb of index is 1 or not. +- */ +- assign( index_gt16[i], +- binop( Iop_64HLtoV128, +- unop( Iop_1Sto64, +- unop( Iop_32to1, +- binop( Iop_Shr32, +- mkexpr( index[i] ), +- mkU8( 4 ) ) ) ), +- unop( Iop_1Sto64, +- unop( Iop_32to1, +- binop( Iop_Shr32, +- mkexpr( index[i] ), +- mkU8( 4 ) ) ) ) ) ); +- assign( mask[i], +- binop( Iop_ShlV128, +- binop( Iop_64HLtoV128, +- mkU64( 0x0 ), +- mkU64( 0xFF ) ), +- unop( Iop_32to8, +- binop( Iop_Mul32, +- binop( Iop_Sub32, +- mkU32( 15 ), +- binop( Iop_And32, +- mkexpr( index[i] ), +- mkU32( 0xF ) ) ), +- mkU32( 8 ) ) ) ) ); +- +- /* Extract the indexed byte from vA and vB using the lower 4-bits +- * of the index. Then use the index_gt16 mask to select vA if the +- * index < 16 or vB if index > 15. Put the selected byte in the +- * least significant byte. +- */ +- assign( tmp[i], +- binop( Iop_ShrV128, +- binop( Iop_OrV128, +- binop( Iop_AndV128, +- binop( Iop_AndV128, +- mkexpr( mask[i] ), +- mkexpr( vA ) ), +- unop( Iop_NotV128, +- mkexpr( index_gt16[i] ) ) ), +- binop( Iop_AndV128, +- binop( Iop_AndV128, +- mkexpr( mask[i] ), +- mkexpr( vB ) ), +- mkexpr( index_gt16[i] ) ) ), +- unop( Iop_32to8, +- binop( Iop_Mul32, +- binop( Iop_Sub32, +- mkU32( 15 ), +- binop( Iop_And32, +- mkexpr( index[i] ), +- mkU32( 0xF ) ) ), +- mkU32( 8 ) ) ) ) ); +- +- /* Move the selected byte to the position to store in the result */ +- assign( new_Vt[i+1], binop( Iop_OrV128, +- binop( Iop_ShlV128, +- mkexpr( tmp[i] ), +- mkU8( (15 - i) * 8 ) ), +- mkexpr( new_Vt[i] ) ) ); +- } +- putVReg( vD_addr, mkexpr( new_Vt[16] ) ); ++ /* limited to two args for IR, so have to play games... */ ++ IRTemp a_perm = newTemp( Ity_V128 ); ++ IRTemp b_perm = newTemp( Ity_V128 ); ++ IRTemp mask = newTemp( Ity_V128 ); ++ IRTemp vC_andF = newTemp( Ity_V128 ); ++ ++ DIP( "vpermr v%d,v%d,v%d,v%d\n", ++ vD_addr, vA_addr, vB_addr, vC_addr); ++ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ IR specifies, and also to hide irrelevant bits from ++ memcheck. ++ */ ++ ++ assign( vC_andF, ++ binop( Iop_Sub16x8, ++ binop( Iop_64HLtoV128, ++ mkU64( 0x1F1F1F1F1F1F1F1F ), ++ mkU64( 0x1F1F1F1F1F1F1F1F ) ), ++ binop( Iop_AndV128, mkexpr( vC ), ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ assign( a_perm, ++ binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) ); ++ assign( b_perm, ++ binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) ); ++ // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0 ++ assign( mask, binop(Iop_SarN8x16, ++ binop( Iop_ShlN8x16, mkexpr( vC_andF ), ++ mkU8( 3 ) ), mkU8( 7 ) ) ); ++ // dst = (a & ~mask) | (b & mask) ++ putVReg( vD_addr, binop( Iop_OrV128, ++ binop( Iop_AndV128, mkexpr( a_perm ), ++ unop( Iop_NotV128, mkexpr( mask ) ) ), ++ binop( Iop_AndV128, mkexpr( b_perm ), ++ mkexpr( mask ) ) ) ); + return True; + } + + +commit f0c4da68ca9e8c99f55965d8e074273a33ab916d +Author: Carl Love +Date: Tue Oct 3 10:49:48 2017 -0500 + + PPC64, Fix bug in vperm instruction. + + The ISA says: + + Let the source vector be the concatenation of the + contents of VR[VRA] followed by the contents of + VR[VRB]. + + For each integer value i from 0 to 15, do the following. + Let index be the value specified by bits 3:7 of byte + element i of VR[VRC]. + + So, the index value is 5-bits wide ([3:7]), not 4-bits wide. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 1785959..97664c2 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -24047,12 +24047,12 @@ static Bool dis_av_permute ( UInt theInstr ) + IRTemp vC_andF = newTemp(Ity_V128); + DIP("vperm v%d,v%d,v%d,v%d\n", + vD_addr, vA_addr, vB_addr, vC_addr); +- /* Limit the Perm8x16 steering values to 0 .. 15 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck */ + assign( vC_andF, + binop(Iop_AndV128, mkexpr(vC), +- unop(Iop_Dup8x16, mkU8(0xF))) ); ++ unop(Iop_Dup8x16, mkU8(0x1F))) ); + assign( a_perm, + binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); + assign( b_perm, + +commit 5398a9f9cb9db6805df03e43258e65fa799a7caa +Author: Carl Love +Date: Wed Oct 4 10:24:36 2017 -0500 + + PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions. + + These are Power 9 instructions. + + Add test cases for the new instructions to test_isa_3_0.c + + Bugzilla 385183. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 97664c2..6b2157d 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -3629,18 +3629,22 @@ static IRExpr * fp_exp_part( IRType size, IRTemp src ) + /* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */ + #define I16_EXP_MASK 0x7C00 + #define I16_FRACTION_MASK 0x03FF ++#define I16_MSB_FRACTION_MASK 0x0200 + #define I32_EXP_MASK 0x7F800000 + #define I32_FRACTION_MASK 0x007FFFFF ++#define I32_MSB_FRACTION_MASK 0x00400000 + #define I64_EXP_MASK 0x7FF0000000000000ULL + #define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL ++#define I64_MSB_FRACTION_MASK 0x0008000000000000ULL + #define V128_EXP_MASK 0x7FFF000000000000ULL + #define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL /* upper 64-bit fractional mask */ ++#define V128_MSB_FRACTION_MASK 0x0000800000000000ULL /* upper 64-bit fractional mask */ + + void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask, +- IRTemp *zero ); ++ IRTemp *msb_frac_mask, IRTemp *zero ); + + void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask, +- IRTemp *zero ) { ++ IRTemp *msb_frac_mask, IRTemp *zero ) { + + vassert( ( size == Ity_I16 ) || ( size == Ity_I32 ) + || ( size == Ity_I64 ) || ( size == Ity_V128 ) ); +@@ -3649,37 +3653,45 @@ void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask, + /* The 16-bit floating point value is in the lower 16-bits of + the 32-bit input value */ + *frac_mask = newTemp( Ity_I32 ); ++ *msb_frac_mask = newTemp( Ity_I32 ); + *exp_mask = newTemp( Ity_I32 ); + *zero = newTemp( Ity_I32 ); + assign( *exp_mask, mkU32( I16_EXP_MASK ) ); + assign( *frac_mask, mkU32( I16_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU32( I16_MSB_FRACTION_MASK ) ); + assign( *zero, mkU32( 0 ) ); + + } else if( size == Ity_I32 ) { + *frac_mask = newTemp( Ity_I32 ); ++ *msb_frac_mask = newTemp( Ity_I32 ); + *exp_mask = newTemp( Ity_I32 ); + *zero = newTemp( Ity_I32 ); + assign( *exp_mask, mkU32( I32_EXP_MASK ) ); + assign( *frac_mask, mkU32( I32_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU32( I32_MSB_FRACTION_MASK ) ); + assign( *zero, mkU32( 0 ) ); + + } else if( size == Ity_I64 ) { + *frac_mask = newTemp( Ity_I64 ); ++ *msb_frac_mask = newTemp( Ity_I64 ); + *exp_mask = newTemp( Ity_I64 ); + *zero = newTemp( Ity_I64 ); + assign( *exp_mask, mkU64( I64_EXP_MASK ) ); + assign( *frac_mask, mkU64( I64_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU64( I64_MSB_FRACTION_MASK ) ); + assign( *zero, mkU64( 0 ) ); + + } else { + /* V128 is converted to upper and lower 64 bit values, */ + /* uses 64-bit operators and temps */ + *frac_mask = newTemp( Ity_I64 ); ++ *msb_frac_mask = newTemp( Ity_I64 ); + *exp_mask = newTemp( Ity_I64 ); + *zero = newTemp( Ity_I64 ); + assign( *exp_mask, mkU64( V128_EXP_MASK ) ); + /* upper 64-bit fractional mask */ + assign( *frac_mask, mkU64( V128_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU64( V128_MSB_FRACTION_MASK ) ); + assign( *zero, mkU64( 0 ) ); + } + } +@@ -3801,9 +3813,10 @@ static IRExpr *fractional_part_compare( IRType size, IRTemp src, + static IRExpr * is_Inf( IRType size, IRTemp src ) + { + IRExpr *max_exp, *zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ + max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) ); +@@ -3818,9 +3831,10 @@ static IRExpr * is_Inf( IRType size, IRTemp src ) + static IRExpr * is_Zero( IRType size, IRTemp src ) + { + IRExpr *zero_exp, *zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check the exponent is all zeros, i.e. (exp AND exp_mask) = zero */ + zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) ); +@@ -3837,9 +3851,10 @@ static IRExpr * is_Zero( IRType size, IRTemp src ) + static IRExpr * is_NaN( IRType size, IRTemp src ) + { + IRExpr *max_exp, *not_zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ + max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) ); +@@ -3852,13 +3867,37 @@ static IRExpr * is_NaN( IRType size, IRTemp src ) + return mkAND1( max_exp, not_zero_frac ); + } + ++static IRExpr * is_sNaN( IRType size, IRTemp src ) ++{ ++ IRExpr *max_exp, *not_zero_frac, *msb_zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; ++ ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); ++ ++ /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ ++ max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) ); ++ ++ /* Most significant fractional bit is zero for sNaN */ ++ msb_zero = fractional_part_compare ( size, src, msb_frac_mask, ++ mkexpr( zero ) ); ++ ++ /* check fractional part is not zero */ ++ not_zero_frac = unop( Iop_Not1, ++ fractional_part_compare( size, src, frac_mask, ++ mkexpr( zero ) ) ); ++ ++ return mkAND1( msb_zero, mkAND1( max_exp, not_zero_frac ) ); ++} ++ + /* Denormalized number has a zero exponent and non zero fraction. */ + static IRExpr * is_Denorm( IRType size, IRTemp src ) + { + IRExpr *zero_exp, *not_zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check exponent is all zeros */ + zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) ); +@@ -19712,6 +19751,216 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, + } + + /* ++ * VSX vector miscellaneous instructions ++ */ ++ ++static Bool ++dis_vx_misc ( UInt theInstr, UInt opc2 ) ++{ ++ /* XX3-Form */ ++ UChar XT = ifieldRegXT ( theInstr ); ++ UChar XA = ifieldRegXA ( theInstr ); ++ UChar XB = ifieldRegXB ( theInstr ); ++ IRTemp vA = newTemp( Ity_V128 ); ++ IRTemp vB = newTemp( Ity_V128 ); ++ IRTemp src1 = newTemp(Ity_I64); ++ IRTemp src2 = newTemp(Ity_I64); ++ IRTemp result_mask = newTemp(Ity_I64); ++ IRTemp cmp_mask = newTemp(Ity_I64); ++ IRTemp nan_mask = newTemp(Ity_I64); ++ IRTemp snan_mask = newTemp(Ity_I64); ++ IRTemp word_result = newTemp(Ity_I64); ++ IRTemp check_result = newTemp(Ity_I64); ++ IRTemp xT = newTemp( Ity_V128 ); ++ IRTemp nan_cmp_value = newTemp(Ity_I64); ++ UInt trap_enabled = 0; /* 0 - trap enabled is False */ ++ ++ assign( vA, getVSReg( XA ) ); ++ assign( vB, getVSReg( XB ) ); ++ assign( xT, getVSReg( XT ) ); ++ ++ assign(src1, unop( Iop_V128HIto64, mkexpr( vA ) ) ); ++ assign(src2, unop( Iop_V128HIto64, mkexpr( vB ) ) ); ++ ++ assign( nan_mask, ++ binop( Iop_Or64, ++ unop( Iop_1Sto64, is_NaN( Ity_I64, src1 ) ), ++ unop( Iop_1Sto64, is_NaN( Ity_I64, src2 ) ) ) ); ++ ++ if ( trap_enabled == 0 ) ++ /* Traps on invalid operation are assumed not enabled, assign ++ result of comparison to xT. ++ */ ++ assign( snan_mask, mkU64( 0 ) ); ++ ++ else ++ assign( snan_mask, ++ binop( Iop_Or64, ++ unop( Iop_1Sto64, is_sNaN( Ity_I64, src1 ) ), ++ unop( Iop_1Sto64, is_sNaN( Ity_I64, src2 ) ) ) ); ++ ++ assign (result_mask, binop( Iop_Or64, ++ mkexpr( snan_mask ), ++ mkexpr( nan_mask ) ) ); ++ ++ switch (opc2) { ++ case 0xC: //xscmpeqdp ++ { ++ DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* extract double-precision floating point source values from ++ double word 0 */ ++ ++ /* result of Iop_CmpF64 is 0x40 if operands are equal, ++ mask is all 1's if equal. */ ++ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop(Iop_32to1, ++ binop(Iop_Shr32, ++ binop( Iop_CmpF64, ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ) ), ++ mkU8( 6 ) ) ) ) ); ++ ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), ++ mkU64( 0xFFFFFFFFFFFFFFFF ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkU64( 0x0 ) ) ) ); ++ assign( nan_cmp_value, mkU64( 0 ) ); ++ break; ++ } ++ ++ case 0x2C: //xscmpgtdp ++ { ++ DIP("xscmpgtdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* Test for src1 > src2 */ ++ ++ /* Result of Iop_CmpF64 is 0x1 if op1 < op2, set mask to all 1's. */ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop(Iop_32to1, ++ binop(Iop_CmpF64, ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ) ) ) ) ); ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), ++ mkU64( 0xFFFFFFFFFFFFFFFF ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkU64( 0x0 ) ) ) ); ++ assign( nan_cmp_value, mkU64( 0 ) ); ++ break; ++ } ++ ++ case 0x4C: //xscmpgedp ++ { ++ DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* compare src 1 >= src 2 */ ++ /* result of Iop_CmpF64 is 0x40 if operands are equal, ++ mask is all 1's if equal. */ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop(Iop_32to1, ++ binop( Iop_Or32, ++ binop( Iop_Shr32, ++ binop(Iop_CmpF64, /* EQ test */ ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ) ), ++ mkU8( 6 ) ), ++ binop(Iop_CmpF64, /* src2 < src 1 test */ ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ) ) ) ) ) ); ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), ++ mkU64( 0xFFFFFFFFFFFFFFFF ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkU64( 0x0 ) ) ) ); ++ assign( nan_cmp_value, mkU64( 0 ) ); ++ break; ++ } ++ ++ case 0x220: //xsmincdp ++ { ++ DIP("xsmincdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* extract double-precision floating point source values from ++ double word 0 */ ++ ++ /* result of Iop_CmpF64 is 0x1 if src1 less then src2, */ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop( Iop_32to1, ++ binop(Iop_CmpF64, ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ) ) ) ) ); ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), mkexpr( src1 ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkexpr( src2 ) ) ) ); ++ assign( nan_cmp_value, mkexpr( src2 ) ); ++ break; ++ } ++ ++ default: ++ vex_printf( "dis_vx_misc(ppc)(opc2)\n" ); ++ return False; ++ } ++ ++ /* If either argument is NaN, result is src2. If either argument is ++ SNaN, we are supposed to generate invalid operation exception. ++ Currently don't support generating exceptions. In case of an ++ trap enabled invalid operation (SNaN) XT is not changed. The ++ snan_mask is setup appropriately for trap enabled or not. ++ */ ++ assign( check_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( snan_mask ), ++ unop( Iop_V128HIto64, mkexpr( xT ) ) ), ++ binop( Iop_And64, unop( Iop_Not64, ++ mkexpr( snan_mask ) ), ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( nan_mask ), ++ mkexpr( nan_cmp_value ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, ++ mkexpr( nan_mask ) ), ++ mkU64( 0 ) ) ) ) ) ); ++ ++ /* If SNaN is true, then the result is unchanged if a trap-enabled ++ Invalid Operation occurs. Result mask already setup for trap-enabled ++ case. ++ */ ++ putVSReg( XT, ++ binop( Iop_64HLtoV128, ++ binop( Iop_Or64, ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( result_mask ) ), ++ mkexpr( word_result ) ), ++ binop( Iop_And64, ++ mkexpr( result_mask ), ++ mkexpr( check_result ) ) ), ++ mkU64( 0 ) ) ); ++ return True; ++} ++ ++/* + * VSX Logical Instructions + */ + static Bool +@@ -27319,12 +27568,15 @@ static struct vsx_insn vsx_xx3[] = { + { 0x0, "xsaddsp" }, + { 0x4, "xsmaddasp" }, + { 0x9, "xsmaddmsp" }, ++ { 0xC, "xscmpeqdp" }, + { 0x20, "xssubsp" }, + { 0x24, "xsmaddmsp" }, ++ { 0x2C, "xscmpgtdp" }, + { 0x3A, "xxpermr" }, + { 0x40, "xsmulsp" }, + { 0x44, "xsmsubasp" }, + { 0x48, "xxmrghw" }, ++ { 0x4C, "xscmpgedp" }, + { 0x60, "xsdivsp" }, + { 0x64, "xsmsubmsp" }, + { 0x68, "xxperm" }, +@@ -27371,6 +27623,7 @@ static struct vsx_insn vsx_xx3[] = { + { 0x1f4, "xvtdivdp" }, + { 0x204, "xsnmaddasp" }, + { 0x208, "xxland" }, ++ { 0x220, "xsmincdp" }, + { 0x224, "xsnmaddmsp" }, + { 0x228, "xxlandc" }, + { 0x244, "xsnmsubasp" }, +@@ -28004,9 +28257,13 @@ DisResult disInstr_PPC_WRK ( + if (dis_vx_permute_misc(theInstr, vsxOpc2 )) + goto decode_success; + goto decode_failure; ++ case 0xC: case 0x2C: case 0x4C: // xscmpeqdp, xscmpgtdp, xscmpgedp ++ case 0x220: //xsmincdp ++ if (dis_vx_misc(theInstr, vsxOpc2)) goto decode_success; ++ goto decode_failure; + case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor, +- case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc +- case 0x2C8: case 0x2E8: // xxlnand, xxleqv ++ case 0x208: case 0x228: // xxland, xxlandc ++ case 0x2A8: case 0x2C8: case 0x2E8: // xxlorc, xxlnand, xxleqv + if (dis_vx_logic(theInstr, vsxOpc2)) goto decode_success; + goto decode_failure; + case 0x0ec: // xscmpexpdp +diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c +index 6e4e7dc..4b07f8b 100644 +--- a/none/tests/ppc64/test_isa_3_0.c ++++ b/none/tests/ppc64/test_isa_3_0.c +@@ -1172,8 +1172,28 @@ static void test_xscmpexpdp(void) { + }; + } + +-static test_list_t testgroup_vector_scalar_compare_exp_double[] = { ++static void test_xscmpeqdp(void) { ++ __asm__ __volatile__ ("xscmpeqdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static void test_xscmpgtdp(void) { ++ __asm__ __volatile__ ("xscmpgtdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static void test_xscmpgedp(void) { ++ __asm__ __volatile__ ("xscmpgedp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static void test_xsmincdp(void) { ++ __asm__ __volatile__ ("xsmincdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static test_list_t testgroup_vector_scalar_compare_double[] = { + { &test_xscmpexpdp , "xscmpexpdp " }, ++ { &test_xscmpeqdp , "xscmpeqdp " }, ++ { &test_xscmpgtdp , "xscmpgtdp " }, ++ { &test_xscmpgedp , "xscmpgedp " }, ++ { &test_xsmincdp , "xsmincdp " }, + { NULL , NULL }, + }; + +@@ -2301,8 +2321,8 @@ static test_group_table_t all_tests[] = { + PPC_MISC | PPC_TWO_ARGS, + }, + { +- testgroup_vector_scalar_compare_exp_double, +- "ppc vector scalar compare exponents doubles", ++ testgroup_vector_scalar_compare_double, ++ "ppc vector scalar compare doubles", + PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS, + }, + { +@@ -3125,8 +3145,16 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name, + } + } + ++/* helper macro. Use below to limit output to only dword[0] for the inputs ++ * to the instructions listed here. */ ++#define instruction_only_uses_dword0_inputs(instruction_name) \ ++ ((strncmp(instruction_name, "xscmpeqdp",9) == 0) || \ ++ (strncmp(instruction_name, "xscmpgtdp",9) == 0) || \ ++ (strncmp(instruction_name, "xscmpgedp",9) == 0) || \ ++ (strncmp(instruction_name, "xsmincdp",8) == 0) ) ++ + static void +-testfunction_vector_scalar_compare_exp_double (const char* instruction_name, ++testfunction_vector_scalar_compare_double (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_test_flags){ + int i,j; +@@ -3154,11 +3182,15 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name, + */ + SET_CR_ZERO + SET_FPSCR_ZERO +- +- printf("%s %016lx %016lx %016lx %016lx", +- instruction_name, +- vec_xa[0], vec_xa[1], +- vec_xb[0], vec_xb[1]); ++ if (instruction_only_uses_dword0_inputs(instruction_name)) { ++ printf("%s %016lx %016lx", ++ instruction_name, vec_xa[1], vec_xb[1]); ++ } else { ++ printf("%s %016lx %016lx %016lx %016lx", ++ instruction_name, ++ vec_xa[0], vec_xa[1], ++ vec_xb[0], vec_xb[1]); ++ } + + if (verbose) printf(" cr#%d ", x_index); + +@@ -3166,6 +3198,10 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name, + + (*test_function)(); + ++ if (instruction_only_uses_dword0_inputs(instruction_name)) { ++ printf("%016lx %016lx", vec_xt[0], vec_xt[1]); ++ } ++ + dissect_fpscr(local_fpscr); + dissect_fpscr_result_value_class(local_fpscr); + dissect_cr_rn(local_cr, x_index); +@@ -4094,7 +4130,7 @@ static void do_tests ( insn_sel_flags_t seln_flags) + break; + + case PPC_COMPARE_ARGS: +- group_function = &testfunction_vector_scalar_compare_exp_double; ++ group_function = &testfunction_vector_scalar_compare_double; + break; + + default: +diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE +index c4ad35f..7d3c94c 100644 +--- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE ++++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE +@@ -53311,8 +53311,8 @@ stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0 + 00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ] + + All done. Tested 135 different instructions +-ppc vector scalar compare exponents doubles: +-Test instruction group [ppc vector scalar compare exponents doubles] ++ppc vector scalar compare doubles: ++Test instruction group [ppc vector scalar compare doubles] + xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ) + xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ) + xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ) +@@ -54275,7 +54275,3855 @@ xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 + xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO) + xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO) + +-All done. Tested 136 different instructions ++xscmpeqdp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++ ++xscmpgtdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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=> 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++ ++xsmincdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) 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0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 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fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++ ++All done. Tested 140 different instructions + ppc vector scalar test data class tests: + Test instruction group [ppc vector scalar test data class tests] + xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a +@@ -55453,7 +59301,7 @@ xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 000000000000 + xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000 + xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff + +-All done. Tested 141 different instructions ++All done. Tested 145 different instructions + ppc vector scalar tests against float double two args : + Test instruction group [ppc vector scalar tests against float double two args ] + xsiexpdp r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000 +@@ -56261,4 +60109,4 @@ xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f800 + xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff + xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff + +-All done. Tested 146 different instructions ++All done. Tested 150 different instructions + +commit c618e707d3e24853cd1e0b71deb981f2dc4ae8d4 +Author: Carl Love +Date: Wed Oct 4 10:54:07 2017 -0500 + + PPC64, revert the change to vperm instruction. + + The patch was in my git tree with the patch I intended to apply. + I didn't realize the patch was in the tree. Git applied both + patches. Still investigating the vperm change to see if it is + really needed. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 6b2157d..b5b0d03 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -24296,12 +24296,12 @@ static Bool dis_av_permute ( UInt theInstr ) + IRTemp vC_andF = newTemp(Ity_V128); + DIP("vperm v%d,v%d,v%d,v%d\n", + vD_addr, vA_addr, vB_addr, vC_addr); +- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck */ + assign( vC_andF, + binop(Iop_AndV128, mkexpr(vC), +- unop(Iop_Dup8x16, mkU8(0x1F))) ); ++ unop(Iop_Dup8x16, mkU8(0xF))) ); + assign( a_perm, + binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); + assign( b_perm, + +commit 856d45eb7e3661a61ace32be2cfa10bf198620c8 +Author: Carl Love +Date: Thu Oct 5 12:19:59 2017 -0500 + + PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field + + The implementation of the vpermr, xxperm, xxpermr violate this by + using a mask of 0x1F. Fix the code and the corresponding comments + to met the definition for Iop_Perm8x16. Use Iop_Dup8x16 to generate + vector value for subtraction. + + Bugzilla 385334. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index b5b0d03..f63146e 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -22579,6 +22579,7 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + IRTemp b_perm = newTemp(Ity_V128); + IRTemp mask = newTemp(Ity_V128); + IRTemp perm_val = newTemp(Ity_V128); ++ IRTemp vB_adj = newTemp( Ity_V128 ); + + if ( opc2 == 0x68 ) { + DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); +@@ -22591,29 +22592,27 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + assign( vT, getVSReg( XT ) ); + + if ( opc2 == 0x68 ) // xxperm +- assign( perm_val, +- binop( Iop_AndV128, mkexpr( vB ), +- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ); ++ assign( vB_adj, mkexpr( vB ) ); + + else // xxpermr +- assign( perm_val, ++ assign( vB_adj, + binop( Iop_Sub16x8, +- binop( Iop_64HLtoV128, +- mkU64( 0x1F1F1F1F1F1F1F1F ), +- mkU64( 0x1F1F1F1F1F1F1F1F ) ), +- binop( Iop_AndV128, mkexpr( vB ), +- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ), ++ mkexpr( vB ) ) ); + +- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck. + */ ++ assign( perm_val, ++ binop( Iop_AndV128, mkexpr( vB_adj ), ++ unop( Iop_Dup8x16, mkU8( 0xF ) ) ) ); + assign( a_perm, + binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) ); + assign( b_perm, + binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) ); + assign( mask, binop( Iop_SarN8x16, +- binop( Iop_ShlN8x16, mkexpr( perm_val ), ++ binop( Iop_ShlN8x16, mkexpr( vB_adj ), + mkU8( 3 ) ), + mkU8( 7 ) ) ); + // dst = (a & ~mask) | (b & mask) +@@ -24361,28 +24360,29 @@ static Bool dis_av_permute ( UInt theInstr ) + IRTemp b_perm = newTemp( Ity_V128 ); + IRTemp mask = newTemp( Ity_V128 ); + IRTemp vC_andF = newTemp( Ity_V128 ); ++ IRTemp vC_adj = newTemp( Ity_V128 ); + + DIP( "vpermr v%d,v%d,v%d,v%d\n", + vD_addr, vA_addr, vB_addr, vC_addr); +- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck. + */ + ++ assign( vC_adj, ++ binop( Iop_Sub16x8, ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ), ++ mkexpr( vC ) ) ); + assign( vC_andF, +- binop( Iop_Sub16x8, +- binop( Iop_64HLtoV128, +- mkU64( 0x1F1F1F1F1F1F1F1F ), +- mkU64( 0x1F1F1F1F1F1F1F1F ) ), +- binop( Iop_AndV128, mkexpr( vC ), +- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ binop( Iop_AndV128, mkexpr( vC_adj), ++ unop( Iop_Dup8x16, mkU8( 0xF ) ) ) ); + assign( a_perm, + binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) ); + assign( b_perm, + binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) ); + // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0 + assign( mask, binop(Iop_SarN8x16, +- binop( Iop_ShlN8x16, mkexpr( vC_andF ), ++ binop( Iop_ShlN8x16, mkexpr( vC_adj ), + mkU8( 3 ) ), mkU8( 7 ) ) ); + // dst = (a & ~mask) | (b & mask) + putVReg( vD_addr, binop( Iop_OrV128, diff --git a/SOURCES/valgrind-3.13.0-static-tls.patch b/SOURCES/valgrind-3.13.0-static-tls.patch new file mode 100644 index 0000000..578a3c5 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-static-tls.patch @@ -0,0 +1,81 @@ +commit f1ff8597ef9c37ff1a853411b9e3be1696c36d92 +Author: Philippe Waroquiers +Date: Tue Sep 19 23:17:48 2017 +0200 + + Implement static TLS code for more platforms + + gdbserver_tests/hgtls is failing on a number of platforms + as it looks like static tls handling is now needed. + So, omplement static tls for a few more platforms. + The formulas that are platform dependent are somewhat wild guesses + obtained with trial and errors. + Note that arm/arm64/ppc32 are not (yet) done + +diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c +index 10e52fc..1f03c12 100644 +--- a/coregrind/m_gdbserver/target.c ++++ b/coregrind/m_gdbserver/target.c +@@ -712,6 +712,7 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + // Check we can read the modid + CHECK_DEREF(lm+lm_modid_offset, sizeof(unsigned long int), "link_map modid"); + modid = *(unsigned long int *)(lm+lm_modid_offset); ++ dlog (2, "tid %u modid %lu\n", tst->tid, modid); + + // Check we can access the dtv entry for modid + CHECK_DEREF(dtv + 2 * modid, sizeof(CORE_ADDR), "dtv[2*modid]"); +@@ -719,7 +720,6 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + // Compute the base address of the tls block. + *tls_addr = *(dtv + 2 * modid); + +-#if defined(VGA_mips32) || defined(VGA_mips64) + if (*tls_addr & 1) { + /* This means that computed address is not valid, most probably + because given module uses Static TLS. +@@ -731,17 +731,24 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + CORE_ADDR tls_offset_addr; + PtrdiffT tls_offset; + +- dlog(1, "computing tls_addr using static TLS\n"); ++ dlog(2, "tls_addr (%p & 1) => computing tls_addr using static TLS\n", ++ (void*) *tls_addr); + + /* Assumes that tls_offset is placed right before tls_modid. + To check the assumption, start a gdb on none/tests/tls and do: +- p &((struct link_map*)0x0)->l_tls_modid +- p &((struct link_map*)0x0)->l_tls_offset */ ++ p &((struct link_map*)0x0)->l_tls_modid ++ p &((struct link_map*)0x0)->l_tls_offset ++ Instead of assuming this, we could calculate this similarly to ++ lm_modid_offset, by extending getplatformoffset to support querying ++ more than one offset. ++ */ + tls_offset_addr = lm + lm_modid_offset - sizeof(PtrdiffT); + + // Check we can read the tls_offset. + CHECK_DEREF(tls_offset_addr, sizeof(PtrdiffT), "link_map tls_offset"); + tls_offset = *(PtrdiffT *)(tls_offset_addr); ++ dlog(2, "tls_offset_addr %p tls_offset %ld\n", ++ (void*)tls_offset_addr, (long)tls_offset); + + /* Following two values represent platform dependent constants + NO_TLS_OFFSET and FORCED_DYNAMIC_TLS_OFFSET, respectively. */ +@@ -751,9 +758,18 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + } + + // This calculation is also platform dependent. ++#if defined(VGA_mips32) || defined(VGA_mips64) + *tls_addr = ((CORE_ADDR)dtv_loc + 2 * sizeof(CORE_ADDR) + tls_offset); +- } ++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) ++ *tls_addr = ((CORE_ADDR)dtv_loc + sizeof(CORE_ADDR) + tls_offset); ++#elif defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) ++ *tls_addr = (CORE_ADDR)dtv_loc - tls_offset - sizeof(CORE_ADDR); ++#else ++ // ppc32, arm, arm64 ++ dlog(0, "target.c is missing platform code for static TLS\n"); ++ return False; + #endif ++ } + + // Finally, add tls variable offset to tls block base address. + *tls_addr += offset; diff --git a/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch b/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch new file mode 100644 index 0000000..77405fc --- /dev/null +++ b/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch @@ -0,0 +1,36 @@ +commit 3c3aa1c62767c48ac8f2015df66f04f354dd897b +Author: Mark Wielaard +Date: Tue Oct 17 17:49:26 2017 +0200 + + Suppress _dl_runtime_resolve_avx_slow for memcheck conditional. + + glibc ld.so has an optimization when resolving a symbol that checks + whether or not the upper 128 bits of the ymm registers are zero. If + so it uses "cheaper" instructions to save/restore them using the xmm + registers. If those upper 128 bits contain undefined values memcheck + will issue an Conditional jump or move depends on uninitialised value(s) + warning whenever trying to resolve a symbol. + + This triggers in our sh-mem-vecxxx test cases. Suppress the warning + by default. + +diff --git a/glibc-2.X.supp.in b/glibc-2.X.supp.in +index 8edeb4a..126e8b3 100644 +--- a/glibc-2.X.supp.in ++++ b/glibc-2.X.supp.in +@@ -236,3 +236,15 @@ + Memcheck:Cond + fun:_dl_relocate_object + } ++ ++# glibc ld.so has an optimization when resolving a symbol that checks ++# whether or not the upper 128 bits of the ymm registers are zero. If ++# so it uses "cheaper" instructions to save/restore them using the xmm ++# registers. If those upper 128 bits contain undefined values memcheck ++# will issue an Conditional jump or move depends on uninitialised value(s) ++# warning whenever trying to resolve a symbol. ++{ ++ dl-trampoline-sse-avx ++ Memcheck:Cond ++ fun:_dl_runtime_resolve_avx_slow ++} diff --git a/SOURCES/valgrind-3.13.0-ucontext_t.patch b/SOURCES/valgrind-3.13.0-ucontext_t.patch new file mode 100644 index 0000000..0abcef2 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ucontext_t.patch @@ -0,0 +1,25 @@ +commit 9b37074f7609cd496c067e88ef8c436981aa7267 +Author: mjw +Date: Thu Jun 29 15:26:30 2017 +0000 + + memcheck/tests: Use ucontext_t instead of struct ucontext + + glibc 2.26 does not expose struct ucontext anymore. + + Signed-off-by: Khem Raj + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16457 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/memcheck/tests/linux/stack_changes.c b/memcheck/tests/linux/stack_changes.c +index a978fc2..7f97b90 100644 +--- a/memcheck/tests/linux/stack_changes.c ++++ b/memcheck/tests/linux/stack_changes.c +@@ -10,7 +10,7 @@ + // This test is checking the libc context calls (setcontext, etc.) and + // checks that Valgrind notices their stack changes properly. + +-typedef struct ucontext mycontext; ++typedef ucontext_t mycontext; + + mycontext ctx1, ctx2, oldc; + int count; diff --git a/SOURCES/valgrind-3.13.0-xml-socket.patch b/SOURCES/valgrind-3.13.0-xml-socket.patch new file mode 100644 index 0000000..e1b79d3 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-xml-socket.patch @@ -0,0 +1,25 @@ +commit 34dd8493de39314033509bb7ad62673f33dcf3db +Author: Ivo Raisr +Date: Thu Aug 3 05:22:01 2017 +0000 + + Fix handling command line option --xml-socket. + Fixes BZ#382998 + Patch by: Orgad Shaneh + + + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16467 + +diff --git a/coregrind/m_libcprint.c b/coregrind/m_libcprint.c +index d66c67d..f6ba202 100644 +--- a/coregrind/m_libcprint.c ++++ b/coregrind/m_libcprint.c +@@ -526,7 +526,7 @@ void VG_(init_log_xml_sinks)(VgLogTo log_to, VgLogTo xml_to, + break; + + case VgLogTo_Socket: +- log_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded), ++ xml_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded), + &VG_(xml_output_sink), True); + break; + } diff --git a/SPECS/valgrind.spec b/SPECS/valgrind.spec index a59435e..9879ba2 100644 --- a/SPECS/valgrind.spec +++ b/SPECS/valgrind.spec @@ -2,8 +2,8 @@ Summary: Tool for finding memory management bugs in programs Name: %{?scl_prefix}valgrind -Version: 3.12.0 -Release: 9%{?dist} +Version: 3.13.0 +Release: 10%{?dist} Epoch: 1 License: GPLv2+ URL: http://www.valgrind.org/ @@ -51,6 +51,29 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) %endif %endif +# Whether to run the full regtest or only a limited set +# The full regtest includes gdb_server integration tests. +# On arm the gdb integration tests hang for unknown reasons. +# On rhel6 the gdb_server tests hang. +# On rhel7 they hang on ppc64 and ppc64le. +%ifarch %{arm} + %global run_full_regtest 0 +%else + %if 0%{?rhel} == 6 + %global run_full_regtest 0 + %else + %if 0%{?rhel} == 7 + %ifarch ppc64 ppc64le + %global run_full_regtest 0 + %else + %global run_full_regtest 1 + %endif + %else + %global run_full_regtest 1 + %endif + %endif +%endif + # Generating minisymtabs doesn't really work for the staticly linked # tools. Note (below) that we don't strip the vgpreload libraries at all # because valgrind might read and need the debuginfo in those (client) @@ -58,7 +81,7 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) # So those will already have their full symbol table. %undefine _include_minidebuginfo -Source0: http://www.valgrind.org/downloads/valgrind-%{version}.tar.bz2 +Source0: ftp://sourceware.org/pub/valgrind/valgrind-%{version}.tar.bz2 # Needs investigation and pushing upstream Patch1: valgrind-3.9.0-cachegrind-improvements.patch @@ -69,75 +92,60 @@ Patch2: valgrind-3.9.0-helgrind-race-supp.patch # Make ld.so supressions slightly less specific. Patch3: valgrind-3.9.0-ldso-supp.patch -# KDE#371396 - workaround helgrind and drd pth_cond_destroy_busy testcase hangs -Patch4: valgrind-3.12.0-skip-cond-var.patch - -# RHBZ#1390282 upstream svn r16134 -# Cleanup none/tests/nocwd.vgtest tmp dirs. -Patch5: valgrind-3.12.0-nocwd-cleanup.patch - -# RHBZ#1424367 -# GCC7 now diagnoses inline assembly that clobbers register r2. -# This has always been invalid code, and is no longer quietly tolerated. -Patch6: valgrind-3.12.0-ppc64-r2.patch - -# KDE#376611 ppc64 and arm64 don't know about prlimit64 syscall -Patch7: valgrind-3.12.0-arm64-ppc64-prlimit64.patch +# KDE#381272 ppc64 doesn't compile test_isa_2_06_partx.c without VSX support +Patch4: valgrind-3.13.0-ppc64-check-no-vsx.patch -# KDE#376279 Handle unknown HINT instructions on aarch64 by ignoring them. -Patch8: valgrind-3.12.0-arm64-hint.patch +# KDE#381289 epoll_pwait can have a NULL sigmask. +Patch5: valgrind-3.13.0-epoll_pwait.patch -# KDE#342040 Valgrind mishandles clone with CLONE_VFORK | CLONE_VM -# that clones to a different stack -# KDE#373192 Calling posix_spawn in glibc 2.24 completely broken -Patch9: valgrind-3.12.0-clone-spawn.patch +# KDE#381274 powerpc too chatty even with --sigill-diagnostics=no +Patch6: valgrind-3.13.0-ppc64-diag.patch -# KDE#372600 process loops forever when fatal signals are arriving quickly -Patch10: valgrind-3.12.0-quick-fatal-sigs.patch +# KDE#381556 arm64: Handle feature registers access on 4.11 Linux kernel +# Workaround that masks CPUID support in HWCAP on aarch64 (#1464211) +Patch7: valgrind-3.13.0-arm64-hwcap.patch -# KDE#372504 Hanging on exit_group -Patch11: valgrind-3.12.0-exit_group.patch +# RHBZ#1466017 ARM ld.so index warnings. +# KDE#381805 arm32 needs ld.so index hardwire for new glibc security fixes +Patch8: valgrind-3.13.0-arm-index-hardwire.patch -# KDE#373046 Stacks registered by core are never deregistered -Patch12: valgrind-3.12.0-deregister-stack.patch +# KDE#381769 Use ucontext_t instead of struct ucontext +Patch9: valgrind-3.13.0-ucontext_t.patch -# KDE#344139 -# Initialize x86 system GDT on first use. -# VEX: Recognize the SS segment prefix on x86. -Patch13: valgrind-3.12.0-x86-gdt-and-ss.patch +# valgrind svn r16453 Fix some tests failure with GDB 8.0 +Patch10: valgrind-3.13.0-gdb-8-testfix.patch -# KDE#352767 - Wine/valgrind: noted but unhandled ioctl 0x5307 (CDROMSTOP) -# KDE#348616 - Wine/valgrind: noted but unhandled ioctl 0x5390 (DVD_READ_STRUCT) -Patch14: valgrind-3.12.0-cd-dvd-ioctl.patch +# valgrind svn r16454. disable vgdb poll in the child after fork +Patch11: valgrind-3.13.0-disable-vgdb-child.patch -# KDE#373069 force old implementation of std::string for leak_cpp_interior test -Patch15: valgrind-3.12.0-tests-cxx11_abi_0.patch +# KDE#382998 xml-socket doesn't work +Patch12: valgrind-3.13.0-xml-socket.patch -# KDE#375806 add suppression for helgrind/tests/tc22_exit_w_lock -Patch16: valgrind-3.12.0-helgrind-dl_allocate_tls-supp.patch +# KDE#385334 +# PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field +# PPC64, revert the change to vperm instruction. +# KDE#385183 +# PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions +# PPC64, Fix bug in vperm instruction. +# KDE#385210 +# PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16. +# KDE#385208 +# PPC64, Use the vperm code to implement the xxperm inst. +# PPC64, Replace body of generate_store_FPRF with C helper function. +# PPC64, Add support for the Data Stream Control Register (DSCR) +Patch13: valgrind-3.13.0-ppc64-vex-fixes.patch -# KDE#372195 Power PC, xxsel instruction is not always recognized. -Patch17: valgrind-3.12.0-ppc-xxsel.patch +# Fix eflags handling in amd64 instruction tests +Patch14: valgrind-3.13.0-amd64-eflags-tests.patch -# Combined valgrind svn r16229:r16248 patches. -# Enables pivot_root, sync_file_range, unshare, get_robust_list, -# delete_module, sched_rr_get_interval, tkill, request_key, move_pages, -# rt_tgsigqueueinfo, fanotify_init, fanotify_mark, clock_adjtime, kcmp, -# getcpu and sethostname syscalls on arm64. -Patch18: valgrind-3.12.0-aarch64-syscalls.patch +# KDE#385868 ld.so _dl_runtime_resolve_avx_slow conditional jump warning +Patch15: valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch -# KDE#377427 Fix incorrect register pair check for lxv, stxv, stxsd, -# stxssp, lxsd, lxssp instructions -Patch19: valgrind-3.12.0-powerpc-register-pair.patch +# Implement static TLS code for more platforms +Patch16: valgrind-3.13.0-static-tls.patch -# KDE#377478 PPC64: ISA 3.0 setup fixes -Patch20: valgrind-3.12.0-ppc64-isa-3_00.patch - -# KDE#369459 valgrind on arm64 violates the ARMv8 spec (ldxr/stxr) -Patch21: valgrind-3.12.0-ll-sc-fallback1.patch -Patch22: valgrind-3.12.0-ll-sc-fallback2.patch -Patch23: valgrind-3.12.0-ll-sc-fallback3.patch -Patch24: valgrind-3.12.0-ll-sc-fallback4.patch +# KDE#386397 PPC64 valgrind truncates powerpc timebase to 32-bits. +Patch17: valgrind-3.13.0-ppc64-timebase.patch # RHEL7 specific patches. @@ -146,8 +154,8 @@ Patch24: valgrind-3.12.0-ll-sc-fallback4.patch # public header under /usr/include/valgrind causing multilib problems. # The result would only be used for two test cases. Patch7001: valgrind-3.11.0-ppc-fppo.patch - %if %{build_multilib} + # Ensure glibc{,-devel} is installed for both multilib arches BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so %endif @@ -168,7 +176,9 @@ BuildRequires: openmpi-devel >= 1.3.3 # For %%build and %%check. # In case of a software collection, pick the matching gdb and binutils. +%if %{run_full_regtest} BuildRequires: %{?scl_prefix}gdb +%endif BuildRequires: %{?scl_prefix}binutils # gdbserver_tests/filter_make_empty uses ps in test @@ -224,12 +234,15 @@ ExclusiveArch: %{ix86} x86_64 ppc ppc64 ppc64le s390x armv7hl aarch64 %endif %description -Valgrind is a tool to help you find memory-management problems in your -programs. When a program is run under Valgrind's supervision, all -reads and writes of memory are checked, and calls to -malloc/new/free/delete are intercepted. As a result, Valgrind can -detect a lot of problems that are otherwise very hard to -find/diagnose. +Valgrind is an instrumentation framework for building dynamic analysis +tools. There are Valgrind tools that can automatically detect many +memory management and threading bugs, and profile your programs in +detail. You can also use Valgrind to build new tools. The Valgrind +distribution currently includes six production-quality tools: a memory +error detector (memcheck, the default tool), two thread error +detectors (helgrind and drd), a cache and branch-prediction profiler +(cachegrind), a call-graph generating cache and branch-prediction +profiler (callgrind), and a heap profiler (massif). %package devel Summary: Development files for valgrind @@ -273,15 +286,6 @@ Valgrind User Manual for details. %patch15 -p1 %patch16 -p1 %patch17 -p1 -%patch18 -p1 -%patch19 -p1 -%patch20 -p1 -%patch21 -p1 -%patch22 -p1 -%patch23 -p1 -%patch24 -p1 -# Remove patch artifacts from tests to pacify makefile consistency checker. -rm -f none/tests/cmdline?.stdout.exp.orig # RHEL7 specific patches %patch7001 -p1 @@ -396,13 +400,19 @@ chmod 644 $RPM_BUILD_ROOT%{_libdir}/valgrind/vgpreload*-%{valarch}-*so %check # Make sure some info about the system is in the build.log +# Add || true because rpm on copr EPEL6 acts weirdly and we don't want +# to break the build. uname -a -rpm -q glibc gcc %{?scl_prefix}binutils %{?scl_prefix}gdb +rpm -q glibc gcc %{?scl_prefix}binutils || true +%if %{run_full_regtest} +rpm -q %{?scl_prefix}gdb || true +%endif + LD_SHOW_AUXV=1 /bin/true cat /proc/cpuinfo -# Make sure a basic binary runs. -./vg-in-place /bin/true +# Make sure a basic binary runs. There should be no errors. +./vg-in-place --error-exitcode=1 /bin/true # Build the test files with the software collection compiler if available. %{?scl:PATH=%{_bindir}${PATH:+:${PATH}}} @@ -410,13 +420,15 @@ cat /proc/cpuinfo # the testsuite sets all flags necessary. See also configure above. make %{?_smp_mflags} CFLAGS="" CXXFLAGS="" LDFLAGS="" check +# Workaround https://bugzilla.redhat.com/show_bug.cgi?id=1434601 +# for gdbserver tests. +export PYTHONCOERCECLOCALE=0 + echo ===============TESTING=================== -# On arm the gdb integration tests hang for unknown reasons. -# Only run the main tools tests. -%ifarch %{arm} -./close_fds make nonexp-regtest || : +%if %{run_full_regtest} + ./close_fds make regtest || : %else -./close_fds make regtest || : + ./close_fds make nonexp-regtest || : %endif # Make sure test failures show up in build.log @@ -479,6 +491,29 @@ echo ===============END TESTING=============== %endif %changelog +* Thu Nov 2 2017 Mark Wielaard - 3.13.0-10 +- Add valgrind-3.13.0-ppc64-timebase.patch (#1508148) + +* Tue Oct 17 2017 Mark Wielaard - 3.13.0-9 +- valgrind 3.13.0 (fedora). +- Update description. +- Drop all upstreamed patches. +- Add valgrind-3.13.0-ppc64-check-no-vsx.patch +- Add valgrind-3.13.0-epoll_pwait.patch (#1462258) +- Add valgrind-3.13.0-ppc64-diag.patch +- Add valgrind-3.13.0-arm64-hwcap.patch (#1464211) +- Add valgrind-3.13.0-arm-index-hardwire.patch (#1466017) +- Add valgrind-3.13.0-ucontext_t.patch +- Add valgrind-3.13.0-gdb-8-testfix.patch +- Add valgrind-3.13.0-disable-vgdb-child.patch +- Add --error-exitcode=1 to /bin/true check. +- Add valgrind-3.13.0-xml-socket.patch +- Add valgrind-3.13.0-ppc64-vex-fixes.patch +- Add valgrind-3.13.0-amd64-eflags-tests.patch +- Add valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch +- Add valgrind-3.13.0-static-tls.patch +- Workaround gdb/python bug in testsuite (#1434601) + * Thu Sep 21 2017 Mark Wielaard - 3.12.0-9 - Add valgrind-3.12.0-ll-sc-fallback[1234].patch (#1492753)