diff --git a/.gitignore b/.gitignore
index 8c09a8a..bbdca62 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1 @@
-SOURCES/valgrind-3.13.0.tar.bz2
+SOURCES/valgrind-3.14.0.tar.bz2
diff --git a/.valgrind.metadata b/.valgrind.metadata
index 03d59c3..1d53adb 100644
--- a/.valgrind.metadata
+++ b/.valgrind.metadata
@@ -1 +1 @@
-ddf13e22dd0ee688bd533fc66b94cf88f75fad86 SOURCES/valgrind-3.13.0.tar.bz2
+182afd405b92ddb6f52c6729e848eacf4b1daf46 SOURCES/valgrind-3.14.0.tar.bz2
diff --git a/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch b/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch
deleted file mode 100644
index c2cef5a..0000000
--- a/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch
+++ /dev/null
@@ -1,2104 +0,0 @@
-commit 4c8c3af18adc0a202d0e342b8ca3731a5b724a1d
-Author: Tom Hughes <tom@compton.nu>
-Date:   Wed Aug 30 19:26:37 2017 +0100
-
-    Fix eflags handling in amd64 instruction tests
-    
-    In 64 bit mode there's no way to just save eflags so we save the
-    whole of rflags but we were doing so to a 32 bit variable!
-    
-    Replace that with proper rflags support that knows it is dealing
-    with the full 64 bit flags word in 64 bit mode.
-
-diff --git a/none/tests/amd64/gen_insn_test.pl b/none/tests/amd64/gen_insn_test.pl
-index 863e560..a144ec4 100644
---- a/none/tests/amd64/gen_insn_test.pl
-+++ b/none/tests/amd64/gen_insn_test.pl
-@@ -16,7 +16,7 @@ our %ArgTypes = (
-                  m32 => "reg32_t",
-                  m64 => "reg64_t",
-                  m128 => "reg128_t",
--                 eflags => "reg32_t",
-+                 rflags => "reg64_t",
-                  st => "reg64_t",
-                  fpucw => "reg16_t",
-                  fpusw => "reg16_t"
-@@ -222,8 +222,8 @@ while (<>)
- 
-     my @presets;
-     my $presetc = 0;
--    my $eflagsmask;
--    my $eflagsset;
-+    my $rflagsmask;
-+    my $rflagsset;
-     my $fpucwmask;
-     my $fpucwset;
-     my $fpuswmask;
-@@ -305,7 +305,7 @@ while (<>)
- 
-             $presetc++;
-         }
--        elsif ($preset =~ /^(eflags)\[([^\]]+)\]$/)
-+        elsif ($preset =~ /^(rflags)\[([^\]]+)\]$/)
-         {
-             my $type = $1;
-             my @values = split(/,/, $2);
-@@ -313,8 +313,8 @@ while (<>)
-             $values[0] = oct($values[0]) if $values[0] =~ /^0/;
-             $values[1] = oct($values[1]) if $values[1] =~ /^0/;
- 
--            $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff;
--            $eflagsset = sprintf "0x%08x", $values[1];
-+            $rflagsmask = sprintf "0x%016x", ~$values[0];
-+            $rflagsset = sprintf "0x%016x", $values[1];
-         }
-         elsif ($preset =~ /^(fpucw)\[([^\]]+)\]$/)
-         {
-@@ -544,7 +544,7 @@ while (<>)
- 
-             print qq|   $ArgTypes{$type} $name;\n|;
-         }
--        elsif ($result =~ /^eflags\[([^\]]+)\]$/)
-+        elsif ($result =~ /^rflags\[([^\]]+)\]$/)
-         {
-             my @values = split(/,/, $1);
-             
-@@ -553,19 +553,19 @@ while (<>)
-             
-             my $result = {
-                 name => $name,
--                type => "eflags",
--                subtype => "ud",
--                values => [ map { sprintf "0x%08x", $_ } @values ]
-+                type => "rflags",
-+                subtype => "uq",
-+                values => [ map { sprintf "0x%016x", $_ } @values ]
-             };
- 
-             push @results, $result;
-             
--            print qq|   $ArgTypes{eflags} $name;\n|;
-+            print qq|   $ArgTypes{rflags} $name;\n|;
- 
--            if (!defined($eflagsmask) && !defined($eflagsset))
-+            if (!defined($rflagsmask) && !defined($rflagsset))
-             {
--                $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff;
--                $eflagsset = sprintf "0x%08x", $values[0] & ~$values[1];
-+                $rflagsmask = sprintf "0x%016x", ~$values[0];
-+                $rflagsset = sprintf "0x%016x", $values[0] & ~$values[1];
-             }
-         }
-         elsif ($result =~ /^fpucw\[([^\]]+)\]$/)
-@@ -722,12 +722,11 @@ while (<>)
-         }
-     }
- 
--    if (defined($eflagsmask) || defined($eflagsset))
-+    if (defined($rflagsmask) || defined($rflagsset))
-     {
-         print qq|         \"pushfq\\n\"\n|;
--        print qq|         \"andl \$$eflagsmask, (%%rsp)\\n\"\n| if defined($eflagsmask);
--        print qq|         \"andl \$0, 4(%%rsp)\\n\"\n| if defined($eflagsmask);
--        print qq|         \"orq \$$eflagsset, (%%rsp)\\n\"\n| if defined($eflagsset);
-+        print qq|         \"andq \$$rflagsmask, (%%rsp)\\n\"\n| if defined($rflagsmask);
-+        print qq|         \"orq \$$rflagsset, (%%rsp)\\n\"\n| if defined($rflagsset);
-         print qq|         \"popfq\\n\"\n|;
-     }
- 
-@@ -747,7 +746,7 @@ while (<>)
-     
-     foreach my $arg (@args)
-     {
--        next if $arg->{type} eq "eflags";
-+        next if $arg->{type} eq "rflags";
- 
-         if ($arg->{type} =~ /^(r8|r16|r32|r64|mm|xmm)$/)
-         {
-@@ -815,7 +814,7 @@ while (<>)
-         {
-             $fpresults[$RegNums{$result->{register}}] = $result;
-         }
--        elsif ($result->{type} eq "eflags")
-+        elsif ($result->{type} eq "rflags")
-         {
-             print qq|         \"pushfq\\n\"\n|;
-             print qq|         \"popq %$result->{argnum}\\n\"\n|;
-@@ -925,9 +924,9 @@ while (<>)
-             my $suffix = $SubTypeSuffixes{$subtype};
-             my @values = @{$result->{values}};
-             
--            if ($type eq "eflags")
-+            if ($type eq "rflags")
-             {
--                print qq|${prefix}\($result->{name}.ud[0] & $values[0]UL\) == $values[1]UL|;
-+                print qq|${prefix}\($result->{name}.uq[0] & $values[0]UL\) == $values[1]UL|;
-             }
-             elsif ($type =~ /^fpu[cs]w$/)
-             {
-@@ -972,9 +971,9 @@ while (<>)
-             my $suffix = $SubTypeSuffixes{$subtype};
-             my @values = @{$result->{values}};
-             
--            if ($type eq "eflags")
-+            if ($type eq "rflags")
-             {
--                print qq|         printf("  eflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|;
-+                print qq|         printf("  rflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|;
-             }
-             elsif ($type =~ /^fpu[cs]w$/)
-             {
-diff --git a/none/tests/amd64/insn_basic.def b/none/tests/amd64/insn_basic.def
-index 8b10da1..c3bef75 100644
---- a/none/tests/amd64/insn_basic.def
-+++ b/none/tests/amd64/insn_basic.def
-@@ -1,57 +1,57 @@
--adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
--adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
--adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
--adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
--adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
--adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
--adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46]
--adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47]
--adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46]
--adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47]
--###adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46]
--###adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47]
--adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
--adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
--###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
--###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
--adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
--adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
--adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
--adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
--adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912]
--adcw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913]
--adcw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912]
--adcw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913]
--adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912]
--adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913]
--adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
--adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
--###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
--###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
--adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
--adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
--adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
--adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
--adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
--adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
--adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
--adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
--adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
--adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
--adcq eflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333]
--adcq eflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334]
--###adcq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999]
--###adcq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000]
--adcq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999]
--adcq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000]
--adcq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999]
--adcq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000]
--adcq eflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
--adcq eflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
--adcq eflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999]
--adcq eflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000]
--adcq eflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
--adcq eflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
-+adcb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
-+adcb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
-+adcb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
-+adcb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
-+adcb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
-+adcb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
-+adcb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46]
-+adcb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47]
-+adcb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46]
-+adcb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47]
-+###adcb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46]
-+###adcb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47]
-+adcw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
-+adcw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
-+###adcw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
-+###adcw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
-+adcw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
-+adcw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
-+adcw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
-+adcw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
-+adcw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912]
-+adcw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913]
-+adcw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912]
-+adcw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913]
-+adcw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912]
-+adcw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913]
-+adcl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
-+adcl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
-+###adcl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
-+###adcl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
-+adcl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
-+adcl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
-+adcl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
-+adcl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
-+adcl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
-+adcl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
-+adcl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
-+adcl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
-+adcl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
-+adcl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
-+adcq rflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333]
-+adcq rflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334]
-+###adcq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999]
-+###adcq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000]
-+adcq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999]
-+adcq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000]
-+adcq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999]
-+adcq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000]
-+adcq rflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
-+adcq rflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
-+adcq rflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999]
-+adcq rflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000]
-+adcq rflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
-+adcq rflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
- addb imm8[12] al.ub[34] => 1.ub[46]
- addb imm8[12] bl.ub[34] => 1.ub[46]
- addb imm8[12] m8.ub[34] => 1.ub[46]
-@@ -123,430 +123,430 @@ bsrq r64.uq[0x1357246813572468] r64.uq[0] => 1.uq[60]
- bsrq m64.uq[0x7531864275318642] r64.uq[0] => 1.uq[62]
- bswapl r32.ud[0x12345678] => 0.ud[0x78563412]
- bswapq r64.uq[0x1234567813572468] => 0.uq[0x6824571378563412]
--btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
--###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
--btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
--btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
--btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
--btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
--btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
--###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
--btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
--btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
--btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
--btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
--btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
-+btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
-+###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
-+btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
-+btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
-+btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
-+btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
-+btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
-+###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
-+btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
-+btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
-+btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
-+btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
-+btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
- cbw al.sb[123] : => ax.sw[123]
- cbw al.sb[-123] : => ax.sw[-123]
- cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678]
- cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98]
- cdqe eax.ud[0x12345678] : => rax.uq[0x0000000012345678]
- cdqe eax.ud[0xfedcba98] : => rax.uq[0xfffffffffedcba98]
--###clc eflags[0x001,0x000] : => eflags[0x001,0x000]
--###clc eflags[0x001,0x001] : => eflags[0x001,0x000]
--cld eflags[0x400,0x000] : => eflags[0x400,0x000]
--cld eflags[0x400,0x400] : => eflags[0x400,0x000]
--###cmc eflags[0x001,0x000] : => eflags[0x001,0x001]
--###cmc eflags[0x001,0x001] : => eflags[0x001,0x000]
--cmpb imm8[3] al.ub[2] => eflags[0x010,0x010]
--cmpb imm8[2] al.ub[3] => eflags[0x010,0x000]
--cmpb imm8[12] al.ub[12] => eflags[0x044,0x044]
--cmpb imm8[12] al.ub[34] => eflags[0x044,0x000]
--cmpb imm8[34] al.ub[12] => eflags[0x081,0x081]
--cmpb imm8[12] al.ub[34] => eflags[0x081,0x000]
--cmpb imm8[100] al.sb[-100] => eflags[0x800,0x800]
--cmpb imm8[50] al.sb[-50] => eflags[0x800,0x000]
--cmpb imm8[-50] al.sb[50] => eflags[0x800,0x000]
--cmpb imm8[-100] al.sb[100] => eflags[0x800,0x800]
--cmpb imm8[3] r8.ub[2] => eflags[0x010,0x010]
--cmpb imm8[2] r8.ub[3] => eflags[0x010,0x000]
--cmpb imm8[12] r8.ub[12] => eflags[0x044,0x044]
--cmpb imm8[12] r8.ub[34] => eflags[0x044,0x000]
--cmpb imm8[34] r8.ub[12] => eflags[0x081,0x081]
--cmpb imm8[12] r8.ub[34] => eflags[0x081,0x000]
--cmpb imm8[100] r8.sb[-100] => eflags[0x800,0x800]
--cmpb imm8[50] r8.sb[-50] => eflags[0x800,0x000]
--cmpb imm8[-50] r8.sb[50] => eflags[0x800,0x000]
--cmpb imm8[-100] r8.sb[100] => eflags[0x800,0x800]
--cmpb imm8[3] m8.ub[2] => eflags[0x010,0x010]
--cmpb imm8[2] m8.ub[3] => eflags[0x010,0x000]
--cmpb imm8[12] m8.ub[12] => eflags[0x044,0x044]
--cmpb imm8[12] m8.ub[34] => eflags[0x044,0x000]
--cmpb imm8[34] m8.ub[12] => eflags[0x081,0x081]
--cmpb imm8[12] m8.ub[34] => eflags[0x081,0x000]
--cmpb imm8[100] m8.sb[-100] => eflags[0x800,0x800]
--cmpb imm8[50] m8.sb[-50] => eflags[0x800,0x000]
--cmpb imm8[-50] m8.sb[50] => eflags[0x800,0x000]
--cmpb imm8[-100] m8.sb[100] => eflags[0x800,0x800]
--cmpb r8.ub[3] r8.ub[2] => eflags[0x010,0x010]
--cmpb r8.ub[2] r8.ub[3] => eflags[0x010,0x000]
--cmpb r8.ub[12] r8.ub[12] => eflags[0x044,0x044]
--cmpb r8.ub[12] r8.ub[34] => eflags[0x044,0x000]
--cmpb r8.ub[34] r8.ub[12] => eflags[0x081,0x081]
--cmpb r8.ub[12] r8.ub[34] => eflags[0x081,0x000]
--cmpb r8.ub[100] r8.sb[-100] => eflags[0x800,0x800]
--cmpb r8.ub[50] r8.sb[-50] => eflags[0x800,0x000]
--cmpb r8.sb[-50] r8.sb[50] => eflags[0x800,0x000]
--cmpb r8.sb[-100] r8.sb[100] => eflags[0x800,0x800]
--cmpb r8.ub[3] m8.ub[2] => eflags[0x010,0x010]
--cmpb r8.ub[2] m8.ub[3] => eflags[0x010,0x000]
--cmpb r8.ub[12] m8.ub[12] => eflags[0x044,0x044]
--cmpb r8.ub[12] m8.ub[34] => eflags[0x044,0x000]
--cmpb r8.ub[34] m8.ub[12] => eflags[0x081,0x081]
--cmpb r8.ub[12] m8.ub[34] => eflags[0x081,0x000]
--cmpb r8.ub[100] m8.sb[-100] => eflags[0x800,0x800]
--cmpb r8.ub[50] m8.sb[-50] => eflags[0x800,0x000]
--cmpb r8.sb[-50] m8.sb[50] => eflags[0x800,0x000]
--cmpb r8.sb[-100] m8.sb[100] => eflags[0x800,0x800]
--cmpb m8.ub[3] r8.ub[2] => eflags[0x010,0x010]
--cmpb m8.ub[2] r8.ub[3] => eflags[0x010,0x000]
--cmpb m8.ub[12] r8.ub[12] => eflags[0x044,0x044]
--cmpb m8.ub[12] r8.ub[34] => eflags[0x044,0x000]
--cmpb m8.ub[34] r8.ub[12] => eflags[0x081,0x081]
--cmpb m8.ub[12] r8.ub[34] => eflags[0x081,0x000]
--cmpb m8.ub[100] r8.sb[-100] => eflags[0x800,0x800]
--cmpb m8.ub[50] r8.sb[-50] => eflags[0x800,0x000]
--cmpb m8.sb[-50] r8.sb[50] => eflags[0x800,0x000]
--cmpb m8.sb[-100] r8.sb[100] => eflags[0x800,0x800]
--cmpw imm8[3] r16.uw[2] => eflags[0x010,0x010]
--cmpw imm8[2] r16.uw[3] => eflags[0x010,0x000]
--cmpw imm8[12] r16.uw[12] => eflags[0x044,0x044]
--cmpw imm8[12] r16.uw[34] => eflags[0x044,0x000]
--cmpw imm8[34] r16.uw[12] => eflags[0x081,0x081]
--cmpw imm8[12] r16.uw[34] => eflags[0x081,0x000]
--cmpw imm8[100] r16.sw[-32700] => eflags[0x800,0x800]
--cmpw imm8[50] r16.sw[-50] => eflags[0x800,0x000]
--cmpw imm8[-50] r16.sw[50] => eflags[0x800,0x000]
--cmpw imm8[-100] r16.sw[32700] => eflags[0x800,0x800]
--cmpw imm8[3] m16.uw[2] => eflags[0x010,0x010]
--cmpw imm8[2] m16.uw[3] => eflags[0x010,0x000]
--cmpw imm8[12] m16.uw[12] => eflags[0x044,0x044]
--cmpw imm8[12] m16.uw[34] => eflags[0x044,0x000]
--cmpw imm8[34] m16.uw[12] => eflags[0x081,0x081]
--cmpw imm8[12] m16.uw[34] => eflags[0x081,0x000]
--cmpw imm8[100] m16.sw[-32700] => eflags[0x800,0x800]
--cmpw imm8[50] m16.sw[-50] => eflags[0x800,0x000]
--cmpw imm8[-50] m16.sw[50] => eflags[0x800,0x000]
--cmpw imm8[-100] m16.sw[32700] => eflags[0x800,0x800]
--cmpw imm16[3] ax.uw[2] => eflags[0x010,0x010]
--cmpw imm16[2] ax.uw[3] => eflags[0x010,0x000]
--cmpw imm16[12] ax.uw[12] => eflags[0x044,0x044]
--cmpw imm16[12] ax.uw[34] => eflags[0x044,0x000]
--cmpw imm16[34] ax.uw[12] => eflags[0x081,0x081]
--cmpw imm16[12] ax.uw[34] => eflags[0x081,0x000]
--cmpw imm16[100] ax.sw[-32700] => eflags[0x800,0x800]
--cmpw imm16[50] ax.sw[-50] => eflags[0x800,0x000]
--cmpw imm16[-50] ax.sw[50] => eflags[0x800,0x000]
--cmpw imm16[-100] ax.sw[32700] => eflags[0x800,0x800]
--cmpw imm16[3] r16.uw[2] => eflags[0x010,0x010]
--cmpw imm16[2] r16.uw[3] => eflags[0x010,0x000]
--cmpw imm16[12] r16.uw[12] => eflags[0x044,0x044]
--cmpw imm16[12] r16.uw[34] => eflags[0x044,0x000]
--cmpw imm16[34] r16.uw[12] => eflags[0x081,0x081]
--cmpw imm16[12] r16.uw[34] => eflags[0x081,0x000]
--cmpw imm16[100] r16.sw[-32700] => eflags[0x800,0x800]
--cmpw imm16[50] r16.sw[-50] => eflags[0x800,0x000]
--cmpw imm16[-50] r16.sw[50] => eflags[0x800,0x000]
--cmpw imm16[-100] r16.sw[32700] => eflags[0x800,0x800]
--cmpw imm16[3] m16.uw[2] => eflags[0x010,0x010]
--cmpw imm16[2] m16.uw[3] => eflags[0x010,0x000]
--cmpw imm16[12] m16.uw[12] => eflags[0x044,0x044]
--cmpw imm16[12] m16.uw[34] => eflags[0x044,0x000]
--cmpw imm16[34] m16.uw[12] => eflags[0x081,0x081]
--cmpw imm16[12] m16.uw[34] => eflags[0x081,0x000]
--cmpw imm16[100] m16.sw[-32700] => eflags[0x800,0x800]
--cmpw imm16[50] m16.sw[-50] => eflags[0x800,0x000]
--cmpw imm16[-50] m16.sw[50] => eflags[0x800,0x000]
--cmpw imm16[-100] m16.sw[32700] => eflags[0x800,0x800]
--cmpw r16.uw[3] r16.uw[2] => eflags[0x010,0x010]
--cmpw r16.uw[2] r16.uw[3] => eflags[0x010,0x000]
--cmpw r16.uw[12] r16.uw[12] => eflags[0x044,0x044]
--cmpw r16.uw[12] r16.uw[34] => eflags[0x044,0x000]
--cmpw r16.uw[34] r16.uw[12] => eflags[0x081,0x081]
--cmpw r16.uw[12] r16.uw[34] => eflags[0x081,0x000]
--cmpw r16.uw[100] r16.sw[-32700] => eflags[0x800,0x800]
--cmpw r16.uw[50] r16.sw[-50] => eflags[0x800,0x000]
--cmpw r16.sw[-50] r16.sw[50] => eflags[0x800,0x000]
--cmpw r16.sw[-100] r16.sw[32700] => eflags[0x800,0x800]
--cmpw r16.uw[3] m16.uw[2] => eflags[0x010,0x010]
--cmpw r16.uw[2] m16.uw[3] => eflags[0x010,0x000]
--cmpw r16.uw[12] m16.uw[12] => eflags[0x044,0x044]
--cmpw r16.uw[12] m16.uw[34] => eflags[0x044,0x000]
--cmpw r16.uw[34] m16.uw[12] => eflags[0x081,0x081]
--cmpw r16.uw[12] m16.uw[34] => eflags[0x081,0x000]
--cmpw r16.uw[100] m16.sw[-32700] => eflags[0x800,0x800]
--cmpw r16.uw[50] m16.sw[-50] => eflags[0x800,0x000]
--cmpw r16.sw[-50] m16.sw[50] => eflags[0x800,0x000]
--cmpw r16.sw[-100] m16.sw[32700] => eflags[0x800,0x800]
--cmpw m16.uw[3] r16.uw[2] => eflags[0x010,0x010]
--cmpw m16.uw[2] r16.uw[3] => eflags[0x010,0x000]
--cmpw m16.uw[12] r16.uw[12] => eflags[0x044,0x044]
--cmpw m16.uw[12] r16.uw[34] => eflags[0x044,0x000]
--cmpw m16.uw[34] r16.uw[12] => eflags[0x081,0x081]
--cmpw m16.uw[12] r16.uw[34] => eflags[0x081,0x000]
--cmpw m16.uw[100] r16.sw[-32700] => eflags[0x800,0x800]
--cmpw m16.uw[50] r16.sw[-50] => eflags[0x800,0x000]
--cmpw m16.sw[-50] r16.sw[50] => eflags[0x800,0x000]
--cmpw m16.sw[-100] r16.sw[32700] => eflags[0x800,0x800]
--cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010]
--cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000]
--cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044]
--###cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000]
--cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081]
--cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000]
--cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000]
--cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000]
--cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800]
--cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010]
--cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000]
--cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044]
--cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000]
--cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081]
--cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000]
--cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000]
--cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000]
--cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800]
--cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010]
--cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000]
--cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044]
--cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000]
--cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081]
--cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000]
--cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800]
--cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000]
--cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000]
--cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800]
--cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010]
--cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000]
--cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044]
--cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000]
--cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081]
--cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000]
--cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000]
--cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000]
--cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800]
--cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010]
--cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000]
--cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044]
--cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000]
--cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081]
--cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000]
--cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000]
--cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000]
--cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800]
--cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010]
--cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000]
--cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044]
--cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000]
--cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081]
--cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000]
--cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
--cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
--cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
--cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010]
--cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000]
--cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044]
--cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000]
--cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081]
--cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000]
--cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000]
--cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000]
--cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800]
--cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010]
--cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000]
--cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044]
--cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000]
--cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081]
--cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000]
--cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
--cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
--cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
--###cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
--cmpq imm8[3] r64.uq[2] => eflags[0x010,0x010]
--cmpq imm8[2] r64.uq[3] => eflags[0x010,0x000]
--cmpq imm8[12] r64.uq[12] => eflags[0x044,0x044]
--cmpq imm8[12] r64.uq[34] => eflags[0x044,0x000]
--cmpq imm8[34] r64.uq[12] => eflags[0x081,0x081]
--cmpq imm8[12] r64.uq[34] => eflags[0x081,0x000]
--cmpq imm8[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq imm8[50] r64.sq[-50] => eflags[0x800,0x000]
--cmpq imm8[-50] r64.sq[50] => eflags[0x800,0x000]
--cmpq imm8[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq imm8[3] m64.uq[2] => eflags[0x010,0x010]
--cmpq imm8[2] m64.uq[3] => eflags[0x010,0x000]
--cmpq imm8[12] m64.uq[12] => eflags[0x044,0x044]
--cmpq imm8[12] m64.uq[34] => eflags[0x044,0x000]
--cmpq imm8[34] m64.uq[12] => eflags[0x081,0x081]
--cmpq imm8[12] m64.uq[34] => eflags[0x081,0x000]
--cmpq imm8[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq imm8[50] m64.sq[-50] => eflags[0x800,0x000]
--cmpq imm8[-50] m64.sq[50] => eflags[0x800,0x000]
--cmpq imm8[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq imm32[3] rax.uq[2] => eflags[0x010,0x010]
--cmpq imm32[2] rax.uq[3] => eflags[0x010,0x000]
--cmpq imm32[12] rax.uq[12] => eflags[0x044,0x044]
--cmpq imm32[12] rax.uq[34] => eflags[0x044,0x000]
--cmpq imm32[34] rax.uq[12] => eflags[0x081,0x081]
--cmpq imm32[12] rax.uq[34] => eflags[0x081,0x000]
--cmpq imm32[100] rax.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq imm32[50] rax.sq[-50] => eflags[0x800,0x000]
--cmpq imm32[-50] rax.sq[50] => eflags[0x800,0x000]
--cmpq imm32[-100] rax.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq imm32[3] r64.uq[2] => eflags[0x010,0x010]
--cmpq imm32[2] r64.uq[3] => eflags[0x010,0x000]
--cmpq imm32[12] r64.uq[12] => eflags[0x044,0x044]
--cmpq imm32[12] r64.uq[34] => eflags[0x044,0x000]
--cmpq imm32[34] r64.uq[12] => eflags[0x081,0x081]
--cmpq imm32[12] r64.uq[34] => eflags[0x081,0x000]
--cmpq imm32[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq imm32[50] r64.sq[-50] => eflags[0x800,0x000]
--cmpq imm32[-50] r64.sq[50] => eflags[0x800,0x000]
--cmpq imm32[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq imm32[3] m64.uq[2] => eflags[0x010,0x010]
--cmpq imm32[2] m64.uq[3] => eflags[0x010,0x000]
--cmpq imm32[12] m64.uq[12] => eflags[0x044,0x044]
--cmpq imm32[12] m64.uq[34] => eflags[0x044,0x000]
--cmpq imm32[34] m64.uq[12] => eflags[0x081,0x081]
--cmpq imm32[12] m64.uq[34] => eflags[0x081,0x000]
--cmpq imm32[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq imm32[50] m64.sq[-50] => eflags[0x800,0x000]
--cmpq imm32[-50] m64.sq[50] => eflags[0x800,0x000]
--cmpq imm32[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq r64.uq[3] r64.uq[2] => eflags[0x010,0x010]
--cmpq r64.uq[2] r64.uq[3] => eflags[0x010,0x000]
--cmpq r64.uq[12] r64.uq[12] => eflags[0x044,0x044]
--cmpq r64.uq[12] r64.uq[34] => eflags[0x044,0x000]
--cmpq r64.uq[34] r64.uq[12] => eflags[0x081,0x081]
--cmpq r64.uq[12] r64.uq[34] => eflags[0x081,0x000]
--cmpq r64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq r64.uq[50] r64.sq[-50] => eflags[0x800,0x000]
--cmpq r64.sq[-50] r64.sq[50] => eflags[0x800,0x000]
--cmpq r64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq r64.uq[3] m64.uq[2] => eflags[0x010,0x010]
--cmpq r64.uq[2] m64.uq[3] => eflags[0x010,0x000]
--cmpq r64.uq[12] m64.uq[12] => eflags[0x044,0x044]
--cmpq r64.uq[12] m64.uq[34] => eflags[0x044,0x000]
--cmpq r64.uq[34] m64.uq[12] => eflags[0x081,0x081]
--cmpq r64.uq[12] m64.uq[34] => eflags[0x081,0x000]
--cmpq r64.uq[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq r64.uq[50] m64.sq[-50] => eflags[0x800,0x000]
--cmpq r64.sq[-50] m64.sq[50] => eflags[0x800,0x000]
--cmpq r64.sq[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
--cmpq m64.uq[3] r64.uq[2] => eflags[0x010,0x010]
--cmpq m64.uq[2] r64.uq[3] => eflags[0x010,0x000]
--cmpq m64.uq[12] r64.uq[12] => eflags[0x044,0x044]
--cmpq m64.uq[12] r64.uq[34] => eflags[0x044,0x000]
--cmpq m64.uq[34] r64.uq[12] => eflags[0x081,0x081]
--cmpq m64.uq[12] r64.uq[34] => eflags[0x081,0x000]
--cmpq m64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
--cmpq m64.uq[50] r64.sq[-50] => eflags[0x800,0x000]
--cmpq m64.sq[-50] r64.sq[50] => eflags[0x800,0x000]
--cmpq m64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
--###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
--###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
--###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
--###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
--###cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
--###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
--cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
--###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
--###cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
--###cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
--cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
--cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
--###cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
--###cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
--cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
--cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
-+###clc rflags[0x001,0x000] : => rflags[0x001,0x000]
-+###clc rflags[0x001,0x001] : => rflags[0x001,0x000]
-+cld rflags[0x400,0x000] : => rflags[0x400,0x000]
-+cld rflags[0x400,0x400] : => rflags[0x400,0x000]
-+###cmc rflags[0x001,0x000] : => rflags[0x001,0x001]
-+###cmc rflags[0x001,0x001] : => rflags[0x001,0x000]
-+cmpb imm8[3] al.ub[2] => rflags[0x010,0x010]
-+cmpb imm8[2] al.ub[3] => rflags[0x010,0x000]
-+cmpb imm8[12] al.ub[12] => rflags[0x044,0x044]
-+cmpb imm8[12] al.ub[34] => rflags[0x044,0x000]
-+cmpb imm8[34] al.ub[12] => rflags[0x081,0x081]
-+cmpb imm8[12] al.ub[34] => rflags[0x081,0x000]
-+cmpb imm8[100] al.sb[-100] => rflags[0x800,0x800]
-+cmpb imm8[50] al.sb[-50] => rflags[0x800,0x000]
-+cmpb imm8[-50] al.sb[50] => rflags[0x800,0x000]
-+cmpb imm8[-100] al.sb[100] => rflags[0x800,0x800]
-+cmpb imm8[3] r8.ub[2] => rflags[0x010,0x010]
-+cmpb imm8[2] r8.ub[3] => rflags[0x010,0x000]
-+cmpb imm8[12] r8.ub[12] => rflags[0x044,0x044]
-+cmpb imm8[12] r8.ub[34] => rflags[0x044,0x000]
-+cmpb imm8[34] r8.ub[12] => rflags[0x081,0x081]
-+cmpb imm8[12] r8.ub[34] => rflags[0x081,0x000]
-+cmpb imm8[100] r8.sb[-100] => rflags[0x800,0x800]
-+cmpb imm8[50] r8.sb[-50] => rflags[0x800,0x000]
-+cmpb imm8[-50] r8.sb[50] => rflags[0x800,0x000]
-+cmpb imm8[-100] r8.sb[100] => rflags[0x800,0x800]
-+cmpb imm8[3] m8.ub[2] => rflags[0x010,0x010]
-+cmpb imm8[2] m8.ub[3] => rflags[0x010,0x000]
-+cmpb imm8[12] m8.ub[12] => rflags[0x044,0x044]
-+cmpb imm8[12] m8.ub[34] => rflags[0x044,0x000]
-+cmpb imm8[34] m8.ub[12] => rflags[0x081,0x081]
-+cmpb imm8[12] m8.ub[34] => rflags[0x081,0x000]
-+cmpb imm8[100] m8.sb[-100] => rflags[0x800,0x800]
-+cmpb imm8[50] m8.sb[-50] => rflags[0x800,0x000]
-+cmpb imm8[-50] m8.sb[50] => rflags[0x800,0x000]
-+cmpb imm8[-100] m8.sb[100] => rflags[0x800,0x800]
-+cmpb r8.ub[3] r8.ub[2] => rflags[0x010,0x010]
-+cmpb r8.ub[2] r8.ub[3] => rflags[0x010,0x000]
-+cmpb r8.ub[12] r8.ub[12] => rflags[0x044,0x044]
-+cmpb r8.ub[12] r8.ub[34] => rflags[0x044,0x000]
-+cmpb r8.ub[34] r8.ub[12] => rflags[0x081,0x081]
-+cmpb r8.ub[12] r8.ub[34] => rflags[0x081,0x000]
-+cmpb r8.ub[100] r8.sb[-100] => rflags[0x800,0x800]
-+cmpb r8.ub[50] r8.sb[-50] => rflags[0x800,0x000]
-+cmpb r8.sb[-50] r8.sb[50] => rflags[0x800,0x000]
-+cmpb r8.sb[-100] r8.sb[100] => rflags[0x800,0x800]
-+cmpb r8.ub[3] m8.ub[2] => rflags[0x010,0x010]
-+cmpb r8.ub[2] m8.ub[3] => rflags[0x010,0x000]
-+cmpb r8.ub[12] m8.ub[12] => rflags[0x044,0x044]
-+cmpb r8.ub[12] m8.ub[34] => rflags[0x044,0x000]
-+cmpb r8.ub[34] m8.ub[12] => rflags[0x081,0x081]
-+cmpb r8.ub[12] m8.ub[34] => rflags[0x081,0x000]
-+cmpb r8.ub[100] m8.sb[-100] => rflags[0x800,0x800]
-+cmpb r8.ub[50] m8.sb[-50] => rflags[0x800,0x000]
-+cmpb r8.sb[-50] m8.sb[50] => rflags[0x800,0x000]
-+cmpb r8.sb[-100] m8.sb[100] => rflags[0x800,0x800]
-+cmpb m8.ub[3] r8.ub[2] => rflags[0x010,0x010]
-+cmpb m8.ub[2] r8.ub[3] => rflags[0x010,0x000]
-+cmpb m8.ub[12] r8.ub[12] => rflags[0x044,0x044]
-+cmpb m8.ub[12] r8.ub[34] => rflags[0x044,0x000]
-+cmpb m8.ub[34] r8.ub[12] => rflags[0x081,0x081]
-+cmpb m8.ub[12] r8.ub[34] => rflags[0x081,0x000]
-+cmpb m8.ub[100] r8.sb[-100] => rflags[0x800,0x800]
-+cmpb m8.ub[50] r8.sb[-50] => rflags[0x800,0x000]
-+cmpb m8.sb[-50] r8.sb[50] => rflags[0x800,0x000]
-+cmpb m8.sb[-100] r8.sb[100] => rflags[0x800,0x800]
-+cmpw imm8[3] r16.uw[2] => rflags[0x010,0x010]
-+cmpw imm8[2] r16.uw[3] => rflags[0x010,0x000]
-+cmpw imm8[12] r16.uw[12] => rflags[0x044,0x044]
-+cmpw imm8[12] r16.uw[34] => rflags[0x044,0x000]
-+cmpw imm8[34] r16.uw[12] => rflags[0x081,0x081]
-+cmpw imm8[12] r16.uw[34] => rflags[0x081,0x000]
-+cmpw imm8[100] r16.sw[-32700] => rflags[0x800,0x800]
-+cmpw imm8[50] r16.sw[-50] => rflags[0x800,0x000]
-+cmpw imm8[-50] r16.sw[50] => rflags[0x800,0x000]
-+cmpw imm8[-100] r16.sw[32700] => rflags[0x800,0x800]
-+cmpw imm8[3] m16.uw[2] => rflags[0x010,0x010]
-+cmpw imm8[2] m16.uw[3] => rflags[0x010,0x000]
-+cmpw imm8[12] m16.uw[12] => rflags[0x044,0x044]
-+cmpw imm8[12] m16.uw[34] => rflags[0x044,0x000]
-+cmpw imm8[34] m16.uw[12] => rflags[0x081,0x081]
-+cmpw imm8[12] m16.uw[34] => rflags[0x081,0x000]
-+cmpw imm8[100] m16.sw[-32700] => rflags[0x800,0x800]
-+cmpw imm8[50] m16.sw[-50] => rflags[0x800,0x000]
-+cmpw imm8[-50] m16.sw[50] => rflags[0x800,0x000]
-+cmpw imm8[-100] m16.sw[32700] => rflags[0x800,0x800]
-+cmpw imm16[3] ax.uw[2] => rflags[0x010,0x010]
-+cmpw imm16[2] ax.uw[3] => rflags[0x010,0x000]
-+cmpw imm16[12] ax.uw[12] => rflags[0x044,0x044]
-+cmpw imm16[12] ax.uw[34] => rflags[0x044,0x000]
-+cmpw imm16[34] ax.uw[12] => rflags[0x081,0x081]
-+cmpw imm16[12] ax.uw[34] => rflags[0x081,0x000]
-+cmpw imm16[100] ax.sw[-32700] => rflags[0x800,0x800]
-+cmpw imm16[50] ax.sw[-50] => rflags[0x800,0x000]
-+cmpw imm16[-50] ax.sw[50] => rflags[0x800,0x000]
-+cmpw imm16[-100] ax.sw[32700] => rflags[0x800,0x800]
-+cmpw imm16[3] r16.uw[2] => rflags[0x010,0x010]
-+cmpw imm16[2] r16.uw[3] => rflags[0x010,0x000]
-+cmpw imm16[12] r16.uw[12] => rflags[0x044,0x044]
-+cmpw imm16[12] r16.uw[34] => rflags[0x044,0x000]
-+cmpw imm16[34] r16.uw[12] => rflags[0x081,0x081]
-+cmpw imm16[12] r16.uw[34] => rflags[0x081,0x000]
-+cmpw imm16[100] r16.sw[-32700] => rflags[0x800,0x800]
-+cmpw imm16[50] r16.sw[-50] => rflags[0x800,0x000]
-+cmpw imm16[-50] r16.sw[50] => rflags[0x800,0x000]
-+cmpw imm16[-100] r16.sw[32700] => rflags[0x800,0x800]
-+cmpw imm16[3] m16.uw[2] => rflags[0x010,0x010]
-+cmpw imm16[2] m16.uw[3] => rflags[0x010,0x000]
-+cmpw imm16[12] m16.uw[12] => rflags[0x044,0x044]
-+cmpw imm16[12] m16.uw[34] => rflags[0x044,0x000]
-+cmpw imm16[34] m16.uw[12] => rflags[0x081,0x081]
-+cmpw imm16[12] m16.uw[34] => rflags[0x081,0x000]
-+cmpw imm16[100] m16.sw[-32700] => rflags[0x800,0x800]
-+cmpw imm16[50] m16.sw[-50] => rflags[0x800,0x000]
-+cmpw imm16[-50] m16.sw[50] => rflags[0x800,0x000]
-+cmpw imm16[-100] m16.sw[32700] => rflags[0x800,0x800]
-+cmpw r16.uw[3] r16.uw[2] => rflags[0x010,0x010]
-+cmpw r16.uw[2] r16.uw[3] => rflags[0x010,0x000]
-+cmpw r16.uw[12] r16.uw[12] => rflags[0x044,0x044]
-+cmpw r16.uw[12] r16.uw[34] => rflags[0x044,0x000]
-+cmpw r16.uw[34] r16.uw[12] => rflags[0x081,0x081]
-+cmpw r16.uw[12] r16.uw[34] => rflags[0x081,0x000]
-+cmpw r16.uw[100] r16.sw[-32700] => rflags[0x800,0x800]
-+cmpw r16.uw[50] r16.sw[-50] => rflags[0x800,0x000]
-+cmpw r16.sw[-50] r16.sw[50] => rflags[0x800,0x000]
-+cmpw r16.sw[-100] r16.sw[32700] => rflags[0x800,0x800]
-+cmpw r16.uw[3] m16.uw[2] => rflags[0x010,0x010]
-+cmpw r16.uw[2] m16.uw[3] => rflags[0x010,0x000]
-+cmpw r16.uw[12] m16.uw[12] => rflags[0x044,0x044]
-+cmpw r16.uw[12] m16.uw[34] => rflags[0x044,0x000]
-+cmpw r16.uw[34] m16.uw[12] => rflags[0x081,0x081]
-+cmpw r16.uw[12] m16.uw[34] => rflags[0x081,0x000]
-+cmpw r16.uw[100] m16.sw[-32700] => rflags[0x800,0x800]
-+cmpw r16.uw[50] m16.sw[-50] => rflags[0x800,0x000]
-+cmpw r16.sw[-50] m16.sw[50] => rflags[0x800,0x000]
-+cmpw r16.sw[-100] m16.sw[32700] => rflags[0x800,0x800]
-+cmpw m16.uw[3] r16.uw[2] => rflags[0x010,0x010]
-+cmpw m16.uw[2] r16.uw[3] => rflags[0x010,0x000]
-+cmpw m16.uw[12] r16.uw[12] => rflags[0x044,0x044]
-+cmpw m16.uw[12] r16.uw[34] => rflags[0x044,0x000]
-+cmpw m16.uw[34] r16.uw[12] => rflags[0x081,0x081]
-+cmpw m16.uw[12] r16.uw[34] => rflags[0x081,0x000]
-+cmpw m16.uw[100] r16.sw[-32700] => rflags[0x800,0x800]
-+cmpw m16.uw[50] r16.sw[-50] => rflags[0x800,0x000]
-+cmpw m16.sw[-50] r16.sw[50] => rflags[0x800,0x000]
-+cmpw m16.sw[-100] r16.sw[32700] => rflags[0x800,0x800]
-+cmpl imm8[3] r32.ud[2] => rflags[0x010,0x010]
-+cmpl imm8[2] r32.ud[3] => rflags[0x010,0x000]
-+cmpl imm8[12] r32.ud[12] => rflags[0x044,0x044]
-+###cmpl imm8[12] r32.ud[34] => rflags[0x044,0x000]
-+cmpl imm8[34] r32.ud[12] => rflags[0x081,0x081]
-+cmpl imm8[12] r32.ud[34] => rflags[0x081,0x000]
-+cmpl imm8[100] r32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl imm8[50] r32.sd[-50] => rflags[0x800,0x000]
-+cmpl imm8[-50] r32.sd[50] => rflags[0x800,0x000]
-+cmpl imm8[-100] r32.sd[2147483600] => rflags[0x800,0x800]
-+cmpl imm8[3] m32.ud[2] => rflags[0x010,0x010]
-+cmpl imm8[2] m32.ud[3] => rflags[0x010,0x000]
-+cmpl imm8[12] m32.ud[12] => rflags[0x044,0x044]
-+cmpl imm8[12] m32.ud[34] => rflags[0x044,0x000]
-+cmpl imm8[34] m32.ud[12] => rflags[0x081,0x081]
-+cmpl imm8[12] m32.ud[34] => rflags[0x081,0x000]
-+cmpl imm8[100] m32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl imm8[50] m32.sd[-50] => rflags[0x800,0x000]
-+cmpl imm8[-50] m32.sd[50] => rflags[0x800,0x000]
-+cmpl imm8[-100] m32.sd[2147483600] => rflags[0x800,0x800]
-+cmpl imm32[3] eax.ud[2] => rflags[0x010,0x010]
-+cmpl imm32[2] eax.ud[3] => rflags[0x010,0x000]
-+cmpl imm32[12] eax.ud[12] => rflags[0x044,0x044]
-+cmpl imm32[12] eax.ud[34] => rflags[0x044,0x000]
-+cmpl imm32[34] eax.ud[12] => rflags[0x081,0x081]
-+cmpl imm32[12] eax.ud[34] => rflags[0x081,0x000]
-+cmpl imm32[100] eax.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl imm32[50] eax.sd[-50] => rflags[0x800,0x000]
-+cmpl imm32[-50] eax.sd[50] => rflags[0x800,0x000]
-+cmpl imm32[-100] eax.sd[2147483600] => rflags[0x800,0x800]
-+cmpl imm32[3] r32.ud[2] => rflags[0x010,0x010]
-+cmpl imm32[2] r32.ud[3] => rflags[0x010,0x000]
-+cmpl imm32[12] r32.ud[12] => rflags[0x044,0x044]
-+cmpl imm32[12] r32.ud[34] => rflags[0x044,0x000]
-+cmpl imm32[34] r32.ud[12] => rflags[0x081,0x081]
-+cmpl imm32[12] r32.ud[34] => rflags[0x081,0x000]
-+cmpl imm32[100] r32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl imm32[50] r32.sd[-50] => rflags[0x800,0x000]
-+cmpl imm32[-50] r32.sd[50] => rflags[0x800,0x000]
-+cmpl imm32[-100] r32.sd[2147483600] => rflags[0x800,0x800]
-+cmpl imm32[3] m32.ud[2] => rflags[0x010,0x010]
-+cmpl imm32[2] m32.ud[3] => rflags[0x010,0x000]
-+cmpl imm32[12] m32.ud[12] => rflags[0x044,0x044]
-+cmpl imm32[12] m32.ud[34] => rflags[0x044,0x000]
-+cmpl imm32[34] m32.ud[12] => rflags[0x081,0x081]
-+cmpl imm32[12] m32.ud[34] => rflags[0x081,0x000]
-+cmpl imm32[100] m32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl imm32[50] m32.sd[-50] => rflags[0x800,0x000]
-+cmpl imm32[-50] m32.sd[50] => rflags[0x800,0x000]
-+cmpl imm32[-100] m32.sd[2147483600] => rflags[0x800,0x800]
-+cmpl r32.ud[3] r32.ud[2] => rflags[0x010,0x010]
-+cmpl r32.ud[2] r32.ud[3] => rflags[0x010,0x000]
-+cmpl r32.ud[12] r32.ud[12] => rflags[0x044,0x044]
-+cmpl r32.ud[12] r32.ud[34] => rflags[0x044,0x000]
-+cmpl r32.ud[34] r32.ud[12] => rflags[0x081,0x081]
-+cmpl r32.ud[12] r32.ud[34] => rflags[0x081,0x000]
-+cmpl r32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl r32.ud[50] r32.sd[-50] => rflags[0x800,0x000]
-+cmpl r32.sd[-50] r32.sd[50] => rflags[0x800,0x000]
-+cmpl r32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800]
-+cmpl r32.ud[3] m32.ud[2] => rflags[0x010,0x010]
-+cmpl r32.ud[2] m32.ud[3] => rflags[0x010,0x000]
-+cmpl r32.ud[12] m32.ud[12] => rflags[0x044,0x044]
-+cmpl r32.ud[12] m32.ud[34] => rflags[0x044,0x000]
-+cmpl r32.ud[34] m32.ud[12] => rflags[0x081,0x081]
-+cmpl r32.ud[12] m32.ud[34] => rflags[0x081,0x000]
-+cmpl r32.ud[100] m32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl r32.ud[50] m32.sd[-50] => rflags[0x800,0x000]
-+cmpl r32.sd[-50] m32.sd[50] => rflags[0x800,0x000]
-+cmpl r32.sd[-100] m32.sd[2147483600] => rflags[0x800,0x800]
-+cmpl m32.ud[3] r32.ud[2] => rflags[0x010,0x010]
-+cmpl m32.ud[2] r32.ud[3] => rflags[0x010,0x000]
-+cmpl m32.ud[12] r32.ud[12] => rflags[0x044,0x044]
-+cmpl m32.ud[12] r32.ud[34] => rflags[0x044,0x000]
-+cmpl m32.ud[34] r32.ud[12] => rflags[0x081,0x081]
-+cmpl m32.ud[12] r32.ud[34] => rflags[0x081,0x000]
-+cmpl m32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800]
-+cmpl m32.ud[50] r32.sd[-50] => rflags[0x800,0x000]
-+cmpl m32.sd[-50] r32.sd[50] => rflags[0x800,0x000]
-+###cmpl m32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800]
-+cmpq imm8[3] r64.uq[2] => rflags[0x010,0x010]
-+cmpq imm8[2] r64.uq[3] => rflags[0x010,0x000]
-+cmpq imm8[12] r64.uq[12] => rflags[0x044,0x044]
-+cmpq imm8[12] r64.uq[34] => rflags[0x044,0x000]
-+cmpq imm8[34] r64.uq[12] => rflags[0x081,0x081]
-+cmpq imm8[12] r64.uq[34] => rflags[0x081,0x000]
-+cmpq imm8[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm8[50] r64.sq[-50] => rflags[0x800,0x000]
-+cmpq imm8[-50] r64.sq[50] => rflags[0x800,0x000]
-+cmpq imm8[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm8[3] m64.uq[2] => rflags[0x010,0x010]
-+cmpq imm8[2] m64.uq[3] => rflags[0x010,0x000]
-+cmpq imm8[12] m64.uq[12] => rflags[0x044,0x044]
-+cmpq imm8[12] m64.uq[34] => rflags[0x044,0x000]
-+cmpq imm8[34] m64.uq[12] => rflags[0x081,0x081]
-+cmpq imm8[12] m64.uq[34] => rflags[0x081,0x000]
-+cmpq imm8[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm8[50] m64.sq[-50] => rflags[0x800,0x000]
-+cmpq imm8[-50] m64.sq[50] => rflags[0x800,0x000]
-+cmpq imm8[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm32[3] rax.uq[2] => rflags[0x010,0x010]
-+cmpq imm32[2] rax.uq[3] => rflags[0x010,0x000]
-+cmpq imm32[12] rax.uq[12] => rflags[0x044,0x044]
-+cmpq imm32[12] rax.uq[34] => rflags[0x044,0x000]
-+cmpq imm32[34] rax.uq[12] => rflags[0x081,0x081]
-+cmpq imm32[12] rax.uq[34] => rflags[0x081,0x000]
-+cmpq imm32[100] rax.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm32[50] rax.sq[-50] => rflags[0x800,0x000]
-+cmpq imm32[-50] rax.sq[50] => rflags[0x800,0x000]
-+cmpq imm32[-100] rax.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm32[3] r64.uq[2] => rflags[0x010,0x010]
-+cmpq imm32[2] r64.uq[3] => rflags[0x010,0x000]
-+cmpq imm32[12] r64.uq[12] => rflags[0x044,0x044]
-+cmpq imm32[12] r64.uq[34] => rflags[0x044,0x000]
-+cmpq imm32[34] r64.uq[12] => rflags[0x081,0x081]
-+cmpq imm32[12] r64.uq[34] => rflags[0x081,0x000]
-+cmpq imm32[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm32[50] r64.sq[-50] => rflags[0x800,0x000]
-+cmpq imm32[-50] r64.sq[50] => rflags[0x800,0x000]
-+cmpq imm32[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm32[3] m64.uq[2] => rflags[0x010,0x010]
-+cmpq imm32[2] m64.uq[3] => rflags[0x010,0x000]
-+cmpq imm32[12] m64.uq[12] => rflags[0x044,0x044]
-+cmpq imm32[12] m64.uq[34] => rflags[0x044,0x000]
-+cmpq imm32[34] m64.uq[12] => rflags[0x081,0x081]
-+cmpq imm32[12] m64.uq[34] => rflags[0x081,0x000]
-+cmpq imm32[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq imm32[50] m64.sq[-50] => rflags[0x800,0x000]
-+cmpq imm32[-50] m64.sq[50] => rflags[0x800,0x000]
-+cmpq imm32[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq r64.uq[3] r64.uq[2] => rflags[0x010,0x010]
-+cmpq r64.uq[2] r64.uq[3] => rflags[0x010,0x000]
-+cmpq r64.uq[12] r64.uq[12] => rflags[0x044,0x044]
-+cmpq r64.uq[12] r64.uq[34] => rflags[0x044,0x000]
-+cmpq r64.uq[34] r64.uq[12] => rflags[0x081,0x081]
-+cmpq r64.uq[12] r64.uq[34] => rflags[0x081,0x000]
-+cmpq r64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq r64.uq[50] r64.sq[-50] => rflags[0x800,0x000]
-+cmpq r64.sq[-50] r64.sq[50] => rflags[0x800,0x000]
-+cmpq r64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq r64.uq[3] m64.uq[2] => rflags[0x010,0x010]
-+cmpq r64.uq[2] m64.uq[3] => rflags[0x010,0x000]
-+cmpq r64.uq[12] m64.uq[12] => rflags[0x044,0x044]
-+cmpq r64.uq[12] m64.uq[34] => rflags[0x044,0x000]
-+cmpq r64.uq[34] m64.uq[12] => rflags[0x081,0x081]
-+cmpq r64.uq[12] m64.uq[34] => rflags[0x081,0x000]
-+cmpq r64.uq[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq r64.uq[50] m64.sq[-50] => rflags[0x800,0x000]
-+cmpq r64.sq[-50] m64.sq[50] => rflags[0x800,0x000]
-+cmpq r64.sq[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800]
-+cmpq m64.uq[3] r64.uq[2] => rflags[0x010,0x010]
-+cmpq m64.uq[2] r64.uq[3] => rflags[0x010,0x000]
-+cmpq m64.uq[12] r64.uq[12] => rflags[0x044,0x044]
-+cmpq m64.uq[12] r64.uq[34] => rflags[0x044,0x000]
-+cmpq m64.uq[34] r64.uq[12] => rflags[0x081,0x081]
-+cmpq m64.uq[12] r64.uq[34] => rflags[0x081,0x000]
-+cmpq m64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
-+cmpq m64.uq[50] r64.sq[-50] => rflags[0x800,0x000]
-+cmpq m64.sq[-50] r64.sq[50] => rflags[0x800,0x000]
-+cmpq m64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
-+###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
-+###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
-+###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
-+###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
-+###cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
-+###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
-+cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
-+###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
-+###cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
-+###cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
-+cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
-+cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
-+###cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
-+###cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
-+cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
-+cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
- cqo rax.uq[0x0123456789abcdef] : => rdx.uq[0x0000000000000000] rax.uq[0x0123456789abcdef]
- cqo rax.uq[0xfedcba9876543210] : => rdx.uq[0xffffffffffffffff] rax.uq[0xfedcba9876543210]
- cwd ax.uw[0x1234] : => dx.uw[0x0000] ax.uw[0x1234]
-@@ -617,8 +617,8 @@ incl r32.ud[12345678] => 0.ud[12345679]
- incl m32.ud[12345678] => 0.ud[12345679]
- incq r64.uq[1234567813572468] => 0.uq[1234567813572469]
- incq m64.uq[1234567813572468] => 0.uq[1234567813572469]
--###lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7]
--###lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02]
-+###lahf rflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7]
-+###lahf rflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02]
- movb imm8[123] r8.ub[0] => 1.ub[123]
- movb imm8[123] m8.ub[0] => 1.ub[123]
- movb r8.ub[123] r8.ub[0] => 1.ub[123]
-@@ -714,54 +714,54 @@ orq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0xffffffff96767779]
- orq r64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff]
- orq r64.uq[0xeca86420fdb97531] m64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff]
- orq m64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff]
--###rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1]
--###rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1]
--###rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
--###rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
--###rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
--###rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
--###rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1]
--###rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1]
--###rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
--###rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
--###rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
--###rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
--###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
--###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
--###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
--###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
--###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
--###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
--###rclq eflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1]
--###rclq eflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1]
--###rclq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
--###rclq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
--###rclq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
--###rclq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
--rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0]
--rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0]
--rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
--rcrb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
--rcrb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
--rcrb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
--rcrw eflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0]
--rcrw eflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0]
--rcrw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
--rcrw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
--rcrw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
--rcrw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
--rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
--rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
--rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
--rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
--rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
--rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
--rcrq eflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0]
--rcrq eflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0]
--rcrq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
--rcrq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
--rcrq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
--rcrq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
-+###rclb rflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1]
-+###rclb rflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1]
-+###rclb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
-+###rclb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
-+###rclb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
-+###rclb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
-+###rclw rflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1]
-+###rclw rflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1]
-+###rclw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
-+###rclw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
-+###rclw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
-+###rclw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
-+###rcll rflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1]
-+###rcll rflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1]
-+###rcll rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
-+###rcll rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
-+###rcll rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
-+###rcll rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
-+###rclq rflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1]
-+###rclq rflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1]
-+###rclq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
-+###rclq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
-+###rclq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
-+###rclq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
-+rcrb rflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0]
-+rcrb rflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0]
-+rcrb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
-+rcrb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
-+rcrb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
-+rcrb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
-+rcrw rflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0]
-+rcrw rflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0]
-+rcrw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
-+rcrw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
-+rcrw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
-+rcrw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
-+rcrl rflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0]
-+rcrl rflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0]
-+rcrl rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
-+rcrl rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
-+rcrl rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
-+rcrl rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
-+rcrq rflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0]
-+rcrq rflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0]
-+rcrq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
-+rcrq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
-+rcrq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
-+rcrq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
- rolb r8.ub[0xca] => 0.ub[0x95]
- rolb m8.ub[0xca] => 0.ub[0x95]
- rolb imm8[2] r8.ub[0xca] => 1.ub[0x2b]
-@@ -810,8 +810,8 @@ rorq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
- rorq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
- rorq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
- rorq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
--###sahf eflags[0xff,0x28] ah.ub[0xfd] : => eflags[0xfd,0xd5]
--###sahf eflags[0xff,0xfd] ah.ub[0x28] : => eflags[0xfd,0x00]
-+###sahf rflags[0xff,0x28] ah.ub[0xfd] : => rflags[0xfd,0xd5]
-+###sahf rflags[0xff,0xfd] ah.ub[0x28] : => rflags[0xfd,0x00]
- salb r8.ub[0xca] => 0.ub[0x94]
- salb m8.ub[0xca] => 0.ub[0x94]
- salb imm8[2] r8.ub[0xca] => 1.ub[0x28]
-@@ -860,252 +860,252 @@ sarq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
- sarq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
- sarq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
- sarq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
--###sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22]
--###sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21]
--sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22]
--sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21]
--sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22]
--sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21]
--sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22]
--sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21]
--###sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22]
--###sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21]
--###sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22]
--###sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21]
--sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444]
--sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443]
--###sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444]
--###sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443]
--sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444]
--sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443]
--sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444]
--sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443]
--sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444]
--sbbw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443]
--###sbbw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444]
--###sbbw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443]
--sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444]
--sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443]
--sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
--sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
--###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
--###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
--sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
--sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
--sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
--sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
--sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
--sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
--###sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
--###sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
--sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
--sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
--sbbq eflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630]
--sbbq eflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629]
--###sbbq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964]
--###sbbq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963]
--sbbq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
--sbbq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963]
--sbbq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964]
--sbbq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963]
--sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
--sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
--###sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174]
--###sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173]
--sbbq eflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
--sbbq eflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
--seta eflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
--seta eflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
--seta eflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
--seta eflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
--seta eflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
--seta eflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
--seta eflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
--seta eflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
--setae eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
--setae eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
--setae eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
--setae eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
--setb eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
--setb eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
--setb eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
--setb eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
--setbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
--setbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
--setbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
--setbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
--setbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
--setbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
--setbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
--setbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
--setc eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
--setc eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
--setc eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
--setc eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
--sete eflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
--sete eflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
--sete eflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
--sete eflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
--setg eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
--setg eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
--setg eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
--setg eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
--setg eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
--setg eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
--setge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
--setge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
--setge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
--setge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
--setge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
--setge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
--setge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
--setge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
--setl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
--setl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
--setl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
--setl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
--setl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
--setl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
--setl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
--setl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
--setle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
--setle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
--setle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
--setle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
--setle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
--setle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
--setna eflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
--setna eflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
--setna eflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
--setna eflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
--setna eflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
--setna eflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
--setna eflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
--setna eflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
--setnae eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
--setnae eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
--setnae eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
--setnae eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
--setnb eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
--setnb eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
--setnb eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
--setnb eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
--setnbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
--setnbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
--setnbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
--setnbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
--setnbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
--setnbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
--setnbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
--setnbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
--setnc eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
--setnc eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
--setnc eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
--setnc eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
--setne eflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
--setne eflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
--setne eflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
--setne eflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
--setng eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
--setng eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
--setng eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
--setng eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
--setng eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
--setng eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
--setnge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
--setnge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
--setnge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
--setnge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
--setnge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
--setnge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
--setnge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
--setnge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
--setnl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
--setnl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
--setnl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
--setnl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
--setnl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
--setnl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
--setnl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
--setnl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
--setnle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
--setnle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
--setnle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
--setnle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
--setnle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
--setnle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
--setno eflags[0x800,0x000] : r8.ub[123] => 0.ub[1]
--setno eflags[0x800,0x800] : r8.ub[123] => 0.ub[0]
--setno eflags[0x800,0x000] : m8.ub[123] => 0.ub[1]
--setno eflags[0x800,0x800] : m8.ub[123] => 0.ub[0]
--setnp eflags[0x004,0x000] : r8.ub[123] => 0.ub[1]
--setnp eflags[0x004,0x004] : r8.ub[123] => 0.ub[0]
--setnp eflags[0x004,0x000] : m8.ub[123] => 0.ub[1]
--setnp eflags[0x004,0x004] : m8.ub[123] => 0.ub[0]
--setns eflags[0x080,0x000] : r8.ub[123] => 0.ub[1]
--setns eflags[0x080,0x080] : r8.ub[123] => 0.ub[0]
--setns eflags[0x080,0x000] : m8.ub[123] => 0.ub[1]
--setns eflags[0x080,0x080] : m8.ub[123] => 0.ub[0]
--setnz eflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
--setnz eflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
--setnz eflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
--setnz eflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
--seto eflags[0x800,0x000] : r8.ub[123] => 0.ub[0]
--seto eflags[0x800,0x800] : r8.ub[123] => 0.ub[1]
--seto eflags[0x800,0x000] : m8.ub[123] => 0.ub[0]
--seto eflags[0x800,0x800] : m8.ub[123] => 0.ub[1]
--setp eflags[0x004,0x000] : r8.ub[123] => 0.ub[0]
--setp eflags[0x004,0x004] : r8.ub[123] => 0.ub[1]
--setp eflags[0x004,0x000] : m8.ub[123] => 0.ub[0]
--setp eflags[0x004,0x004] : m8.ub[123] => 0.ub[1]
--sets eflags[0x080,0x000] : r8.ub[123] => 0.ub[0]
--sets eflags[0x080,0x080] : r8.ub[123] => 0.ub[1]
--sets eflags[0x080,0x000] : m8.ub[123] => 0.ub[0]
--sets eflags[0x080,0x080] : m8.ub[123] => 0.ub[1]
--setz eflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
--setz eflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
--setz eflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
--setz eflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
-+###sbbb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22]
-+###sbbb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21]
-+sbbb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22]
-+sbbb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21]
-+sbbb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22]
-+sbbb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21]
-+sbbb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22]
-+sbbb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21]
-+###sbbb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22]
-+###sbbb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21]
-+###sbbb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22]
-+###sbbb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21]
-+sbbw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444]
-+sbbw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443]
-+###sbbw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444]
-+###sbbw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443]
-+sbbw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444]
-+sbbw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443]
-+sbbw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444]
-+sbbw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443]
-+sbbw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444]
-+sbbw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443]
-+###sbbw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444]
-+###sbbw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443]
-+sbbw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444]
-+sbbw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443]
-+sbbl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
-+sbbl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
-+###sbbl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
-+###sbbl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
-+sbbl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
-+sbbl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
-+sbbl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
-+sbbl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
-+sbbl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
-+sbbl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
-+###sbbl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
-+###sbbl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
-+sbbl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
-+sbbl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
-+sbbq rflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630]
-+sbbq rflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629]
-+###sbbq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964]
-+###sbbq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963]
-+sbbq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
-+sbbq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963]
-+sbbq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964]
-+sbbq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963]
-+sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
-+sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
-+###sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174]
-+###sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173]
-+sbbq rflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
-+sbbq rflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
-+seta rflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
-+seta rflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
-+seta rflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
-+seta rflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
-+seta rflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
-+seta rflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
-+seta rflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
-+seta rflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
-+setae rflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
-+setae rflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
-+setae rflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
-+setae rflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
-+setb rflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
-+setb rflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
-+setb rflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
-+setb rflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
-+setbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
-+setbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
-+setbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
-+setbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
-+setbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
-+setbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
-+setbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
-+setbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
-+setc rflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
-+setc rflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
-+setc rflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
-+setc rflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
-+sete rflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
-+sete rflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
-+sete rflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
-+sete rflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
-+setg rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
-+setg rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
-+setg rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
-+setg rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
-+setg rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
-+setg rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
-+setge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
-+setge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
-+setge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
-+setge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
-+setge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
-+setge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
-+setge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
-+setge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
-+setl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
-+setl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
-+setl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
-+setl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
-+setl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
-+setl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
-+setl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
-+setl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
-+setle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
-+setle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
-+setle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
-+setle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
-+setle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
-+setle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
-+setna rflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
-+setna rflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
-+setna rflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
-+setna rflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
-+setna rflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
-+setna rflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
-+setna rflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
-+setna rflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
-+setnae rflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
-+setnae rflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
-+setnae rflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
-+setnae rflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
-+setnb rflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
-+setnb rflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
-+setnb rflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
-+setnb rflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
-+setnbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
-+setnbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
-+setnbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
-+setnbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
-+setnbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
-+setnbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
-+setnbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
-+setnbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
-+setnc rflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
-+setnc rflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
-+setnc rflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
-+setnc rflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
-+setne rflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
-+setne rflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
-+setne rflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
-+setne rflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
-+setng rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
-+setng rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
-+setng rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
-+setng rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
-+setng rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
-+setng rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
-+setnge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
-+setnge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
-+setnge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
-+setnge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
-+setnge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
-+setnge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
-+setnge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
-+setnge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
-+setnl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
-+setnl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
-+setnl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
-+setnl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
-+setnl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
-+setnl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
-+setnl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
-+setnl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
-+setnle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
-+setnle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
-+setnle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
-+setnle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
-+setnle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
-+setnle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
-+setno rflags[0x800,0x000] : r8.ub[123] => 0.ub[1]
-+setno rflags[0x800,0x800] : r8.ub[123] => 0.ub[0]
-+setno rflags[0x800,0x000] : m8.ub[123] => 0.ub[1]
-+setno rflags[0x800,0x800] : m8.ub[123] => 0.ub[0]
-+setnp rflags[0x004,0x000] : r8.ub[123] => 0.ub[1]
-+setnp rflags[0x004,0x004] : r8.ub[123] => 0.ub[0]
-+setnp rflags[0x004,0x000] : m8.ub[123] => 0.ub[1]
-+setnp rflags[0x004,0x004] : m8.ub[123] => 0.ub[0]
-+setns rflags[0x080,0x000] : r8.ub[123] => 0.ub[1]
-+setns rflags[0x080,0x080] : r8.ub[123] => 0.ub[0]
-+setns rflags[0x080,0x000] : m8.ub[123] => 0.ub[1]
-+setns rflags[0x080,0x080] : m8.ub[123] => 0.ub[0]
-+setnz rflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
-+setnz rflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
-+setnz rflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
-+setnz rflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
-+seto rflags[0x800,0x000] : r8.ub[123] => 0.ub[0]
-+seto rflags[0x800,0x800] : r8.ub[123] => 0.ub[1]
-+seto rflags[0x800,0x000] : m8.ub[123] => 0.ub[0]
-+seto rflags[0x800,0x800] : m8.ub[123] => 0.ub[1]
-+setp rflags[0x004,0x000] : r8.ub[123] => 0.ub[0]
-+setp rflags[0x004,0x004] : r8.ub[123] => 0.ub[1]
-+setp rflags[0x004,0x000] : m8.ub[123] => 0.ub[0]
-+setp rflags[0x004,0x004] : m8.ub[123] => 0.ub[1]
-+sets rflags[0x080,0x000] : r8.ub[123] => 0.ub[0]
-+sets rflags[0x080,0x080] : r8.ub[123] => 0.ub[1]
-+sets rflags[0x080,0x000] : m8.ub[123] => 0.ub[0]
-+sets rflags[0x080,0x080] : m8.ub[123] => 0.ub[1]
-+setz rflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
-+setz rflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
-+setz rflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
-+setz rflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
- shlb r8.ub[0xca] => 0.ub[0x94]
- shlb m8.ub[0xca] => 0.ub[0x94]
- shlb imm8[2] r8.ub[0xca] => 1.ub[0x28]
-@@ -1202,10 +1202,10 @@ shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0x7
- shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0x7fff80007f807865]
- shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00]
- shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00]
--###stc eflags[0x001,0x000] : => eflags[0x001,0x001]
--###stc eflags[0x001,0x001] : => eflags[0x001,0x001]
--std eflags[0x400,0x000] : => eflags[0x400,0x400]
--std eflags[0x400,0x400] : => eflags[0x400,0x400]
-+###stc rflags[0x001,0x000] : => rflags[0x001,0x001]
-+###stc rflags[0x001,0x001] : => rflags[0x001,0x001]
-+std rflags[0x400,0x000] : => rflags[0x400,0x400]
-+std rflags[0x400,0x400] : => rflags[0x400,0x400]
- subb imm8[12] al.ub[34] => 1.ub[22]
- subb imm8[12] bl.ub[34] => 1.ub[22]
- subb imm8[12] m8.ub[34] => 1.ub[22]
-@@ -1233,106 +1233,106 @@ subq imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
- subq r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
- subq r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174]
- subq m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
--testb imm8[0x1a] al.ub[0x1a] => eflags[0x8c5,0x000]
--testb imm8[0x5a] al.ub[0x5a] => eflags[0x8c5,0x004]
--testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044]
--testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080]
--testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084]
--testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000]
--testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004]
--testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044]
--testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080]
--testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084]
--testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
--testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
--testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
--testb imm8[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080]
--testb imm8[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084]
--testb r8.ub[0x1a] r8.ub[0x1a] => eflags[0x8c5,0x000]
--testb r8.ub[0x5a] r8.ub[0x5a] => eflags[0x8c5,0x004]
--testb r8.ub[0x1a] r8.ub[0xa1] => eflags[0x8c5,0x044]
--testb r8.ub[0xa1] r8.ub[0xa1] => eflags[0x8c5,0x080]
--testb r8.ub[0xa5] r8.ub[0xa5] => eflags[0x8c5,0x084]
--testb r8.ub[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
--testb r8.ub[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
--testb r8.ub[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
--testb r8.ub[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080]
--testb r8.ub[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084]
--testw imm16[0x1a1a] ax.uw[0x1a1a] => eflags[0x8c5,0x000]
--testw imm16[0x5a5a] ax.uw[0x5a5a] => eflags[0x8c5,0x004]
--testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044]
--testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080]
--testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084]
--testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000]
--testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004]
--testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044]
--testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080]
--testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084]
--testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
--testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
--testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
--testw imm16[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080]
--testw imm16[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084]
--testw r16.uw[0x1a1a] r16.uw[0x1a1a] => eflags[0x8c5,0x000]
--testw r16.uw[0x5a5a] r16.uw[0x5a5a] => eflags[0x8c5,0x004]
--testw r16.uw[0x1a1a] r16.uw[0xa1a1] => eflags[0x8c5,0x044]
--testw r16.uw[0xa1a1] r16.uw[0xa1a1] => eflags[0x8c5,0x080]
--testw r16.uw[0xa5a5] r16.uw[0xa5a5] => eflags[0x8c5,0x084]
--testw r16.uw[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
--testw r16.uw[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
--testw r16.uw[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
--testw r16.uw[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080]
--testw r16.uw[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084]
--testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
--testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
--testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
--testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
--testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
--testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
--testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
--testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
--testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
--testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
--testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
--testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
--testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
--testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
--testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
--testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
--testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
--testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
--testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
--testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000]
--testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004]
--testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044]
--testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080]
--testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084]
--testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000]
--testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004]
--testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044]
--testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080]
--testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084]
-+testb imm8[0x1a] al.ub[0x1a] => rflags[0x8c5,0x000]
-+testb imm8[0x5a] al.ub[0x5a] => rflags[0x8c5,0x004]
-+testb imm8[0x1a] al.ub[0xa1] => rflags[0x8c5,0x044]
-+testb imm8[0xa1] al.ub[0xa1] => rflags[0x8c5,0x080]
-+testb imm8[0xa5] al.ub[0xa5] => rflags[0x8c5,0x084]
-+testb imm8[0x1a] bl.ub[0x1a] => rflags[0x8c5,0x000]
-+testb imm8[0x5a] bl.ub[0x5a] => rflags[0x8c5,0x004]
-+testb imm8[0x1a] bl.ub[0xa1] => rflags[0x8c5,0x044]
-+testb imm8[0xa1] bl.ub[0xa1] => rflags[0x8c5,0x080]
-+testb imm8[0xa5] bl.ub[0xa5] => rflags[0x8c5,0x084]
-+testb imm8[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000]
-+testb imm8[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004]
-+testb imm8[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044]
-+testb imm8[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080]
-+testb imm8[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084]
-+testb r8.ub[0x1a] r8.ub[0x1a] => rflags[0x8c5,0x000]
-+testb r8.ub[0x5a] r8.ub[0x5a] => rflags[0x8c5,0x004]
-+testb r8.ub[0x1a] r8.ub[0xa1] => rflags[0x8c5,0x044]
-+testb r8.ub[0xa1] r8.ub[0xa1] => rflags[0x8c5,0x080]
-+testb r8.ub[0xa5] r8.ub[0xa5] => rflags[0x8c5,0x084]
-+testb r8.ub[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000]
-+testb r8.ub[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004]
-+testb r8.ub[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044]
-+testb r8.ub[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080]
-+testb r8.ub[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084]
-+testw imm16[0x1a1a] ax.uw[0x1a1a] => rflags[0x8c5,0x000]
-+testw imm16[0x5a5a] ax.uw[0x5a5a] => rflags[0x8c5,0x004]
-+testw imm16[0x1a1a] ax.uw[0xa1a1] => rflags[0x8c5,0x044]
-+testw imm16[0xa1a1] ax.uw[0xa1a1] => rflags[0x8c5,0x080]
-+testw imm16[0xa5a5] ax.uw[0xa5a5] => rflags[0x8c5,0x084]
-+testw imm16[0x1a1a] bx.uw[0x1a1a] => rflags[0x8c5,0x000]
-+testw imm16[0x5a5a] bx.uw[0x5a5a] => rflags[0x8c5,0x004]
-+testw imm16[0x1a1a] bx.uw[0xa1a1] => rflags[0x8c5,0x044]
-+testw imm16[0xa1a1] bx.uw[0xa1a1] => rflags[0x8c5,0x080]
-+testw imm16[0xa5a5] bx.uw[0xa5a5] => rflags[0x8c5,0x084]
-+testw imm16[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000]
-+testw imm16[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004]
-+testw imm16[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044]
-+testw imm16[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080]
-+testw imm16[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084]
-+testw r16.uw[0x1a1a] r16.uw[0x1a1a] => rflags[0x8c5,0x000]
-+testw r16.uw[0x5a5a] r16.uw[0x5a5a] => rflags[0x8c5,0x004]
-+testw r16.uw[0x1a1a] r16.uw[0xa1a1] => rflags[0x8c5,0x044]
-+testw r16.uw[0xa1a1] r16.uw[0xa1a1] => rflags[0x8c5,0x080]
-+testw r16.uw[0xa5a5] r16.uw[0xa5a5] => rflags[0x8c5,0x084]
-+testw r16.uw[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000]
-+testw r16.uw[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004]
-+testw r16.uw[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044]
-+testw r16.uw[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080]
-+testw r16.uw[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084]
-+testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
-+testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
-+testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
-+testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
-+testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
-+testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
-+testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
-+testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
-+testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
-+testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
-+testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080]
-+testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084]
-+testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080]
-+testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084]
-+testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => rflags[0x8c5,0x000]
-+testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => rflags[0x8c5,0x004]
-+testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => rflags[0x8c5,0x044]
-+testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080]
-+testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084]
-+testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000]
-+testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004]
-+testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044]
-+testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080]
-+testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084]
-+testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000]
-+testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004]
-+testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044]
-+testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080]
-+testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084]
- ###xaddb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[46]
- ###xaddb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[46]
- ###xaddw r16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[6912]
-diff --git a/none/tests/amd64/insn_fpu.def b/none/tests/amd64/insn_fpu.def
-index 590f584..525fd1b 100644
---- a/none/tests/amd64/insn_fpu.def
-+++ b/none/tests/amd64/insn_fpu.def
-@@ -70,30 +70,30 @@ fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.43
- fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000]
- fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[7654321.1234567] fpusw[0x4700,0x0100]
- fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[7654321.1234567] fpusw[0x4700,0x4000]
--fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00]
--fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01]
--fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40]
--fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00]
--fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01]
--fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40]
--fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00]
--fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01]
--fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40]
--fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00]
--fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01]
--fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40]
--fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00]
--fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01]
--fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40]
--fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00]
--fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01]
--fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40]
--fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00]
--fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01]
--fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40]
--fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00]
--fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01]
--fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40]
-+fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00]
-+fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01]
-+fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40]
-+fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00]
-+fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01]
-+fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40]
-+fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00]
-+fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01]
-+fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40]
-+fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00]
-+fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01]
-+fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40]
-+fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00]
-+fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01]
-+fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40]
-+fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00]
-+fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01]
-+fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40]
-+fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00]
-+fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01]
-+fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40]
-+fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00]
-+fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01]
-+fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40]
- fchs st0.ps[1234.5678] : => st0.ps[-1234.5678]
- fchs st0.ps[-1234.5678] : => st0.ps[1234.5678]
- fchs st0.pd[12345678.87654321] : => st0.pd[-12345678.87654321]
-diff --git a/none/tests/amd64/insn_sse.def b/none/tests/amd64/insn_sse.def
-index a9e92a0..277a062 100644
---- a/none/tests/amd64/insn_sse.def
-+++ b/none/tests/amd64/insn_sse.def
-@@ -38,12 +38,12 @@ cmpordps xmm.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,23
- cmpordps m128.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,234.5679,234.5677] => 1.ud[0xffffffff,0xffffffff,0xffffffff,0xffffffff]
- cmpordss xmm.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5679,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0]
- cmpordss m128.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5676,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0]
--comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
--comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
--comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
--comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
--comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
--comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
-+comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
-+comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
-+comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
-+comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
-+comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
-+comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
- cvtpi2ps mm.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4]
- cvtpi2ps m64.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4]
- cvtps2pi xmm.ps[12.34,56.78,1.11,2.22] mm.sd[1,2] => 1.sd[12,57]
-@@ -140,12 +140,12 @@ subps xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,
- subps m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,-23.77,-21.21,-76.65]
- subss xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
- subss m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
--ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
--ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
--ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
--ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
--ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
--ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
-+ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
-+ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
-+ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
-+ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
-+ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
-+ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
- unpckhps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65]
- unpckhps m128.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65]
- unpcklps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[11.22,12.34,33.44,56.78]
-diff --git a/none/tests/amd64/insn_sse2.def b/none/tests/amd64/insn_sse2.def
-index 3cbdd41..7e0890e 100644
---- a/none/tests/amd64/insn_sse2.def
-+++ b/none/tests/amd64/insn_sse2.def
-@@ -38,12 +38,12 @@ cmpnlesd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff,
- cmpnlesd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0x0000000000000000,0]
- cmpordsd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff,0]
- cmpordsd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0xffffffffffffffff,0]
--comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
--comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
--comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
--comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
--comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
--comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
-+comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
-+comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
-+comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
-+comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
-+comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
-+comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
- cvtdq2pd xmm.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0]
- cvtdq2pd m128.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0]
- cvtdq2ps xmm.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0]
-@@ -329,12 +329,12 @@ subpd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4
- subpd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4321]
- subsd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0]
- subsd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0]
--ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
--ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
--ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
--ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
--ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
--ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
-+ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
-+ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
-+ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
-+ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
-+ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
-+ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
- unpckhpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321]
- unpckhpd m128.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321]
- unpcklpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[1122.3344,1234.5678]
diff --git a/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch b/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch
deleted file mode 100644
index 4b718e3..0000000
--- a/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c
-index b8cc022..d54cae7 100644
---- a/coregrind/m_redir.c
-+++ b/coregrind/m_redir.c
-@@ -1485,6 +1485,17 @@ void VG_(redir_initialise) ( void )
-          (Addr)&VG_(arm_linux_REDIR_FOR_strcmp),
-          complain_about_stripped_glibc_ldso
-       );
-+      /* index */
-+      add_hardwired_spec(
-+         "ld-linux.so.3", "index",
-+         (Addr)&VG_(arm_linux_REDIR_FOR_index),
-+         complain_about_stripped_glibc_ldso
-+      );
-+      add_hardwired_spec(
-+         "ld-linux-armhf.so.3", "index",
-+         (Addr)&VG_(arm_linux_REDIR_FOR_index),
-+         complain_about_stripped_glibc_ldso
-+      );
-    }
- 
- #  elif defined(VGP_arm64_linux)
-diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S
-index a532071..0488b54 100644
---- a/coregrind/m_trampoline.S
-+++ b/coregrind/m_trampoline.S
-@@ -625,26 +625,26 @@ VG_(arm_linux_REDIR_FOR_strlen):
- 	bx	lr
- 	UD2_4
- 
--//.global VG_(arm_linux_REDIR_FOR_index)
--//VG_(arm_linux_REDIR_FOR_index):
--//	ldrb	r3, [r0, #0]	@ zero_extendqisi2
--//	and	r1, r1, #255
--//	cmp	r3, r1
--//	@ lr needed for prologue
--//	bne	.L9
--//	bx	lr
--//.L12:
--//	ldrb	r3, [r0, #1]!	@ zero_extendqisi2
--//	cmp	r3, r1
--//	beq	.L11
--//.L9:
--//	cmp	r3, #0
--//	bne	.L12
--//	mov	r0, #0
--//	bx	lr
--//.L11:
--//	bx	lr
--//	UD2_4
-+.global VG_(arm_linux_REDIR_FOR_index)
-+VG_(arm_linux_REDIR_FOR_index):
-+	ldrb	r3, [r0, #0]	@ zero_extendqisi2
-+	and	r1, r1, #255
-+	cmp	r3, r1
-+	@ lr needed for prologue
-+	bne	.L9
-+	bx	lr
-+.L12:
-+	ldrb	r3, [r0, #1]!	@ zero_extendqisi2
-+	cmp	r3, r1
-+	beq	.L11
-+.L9:
-+	cmp	r3, #0
-+	bne	.L12
-+	mov	r0, #0
-+	bx	lr
-+.L11:
-+	bx	lr
-+	UD2_4
- 
- .global VG_(arm_linux_REDIR_FOR_memcpy)
- VG_(arm_linux_REDIR_FOR_memcpy):
-diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h
-index 3a9bafe..e29427d 100644
---- a/coregrind/pub_core_trampoline.h
-+++ b/coregrind/pub_core_trampoline.h
-@@ -100,7 +100,7 @@ extern Addr VG_(ppctoc_magic_redirect_return_stub);
- extern Addr  VG_(arm_linux_SUBST_FOR_sigreturn);
- extern Addr  VG_(arm_linux_SUBST_FOR_rt_sigreturn);
- extern UInt  VG_(arm_linux_REDIR_FOR_strlen)( void* );
--//extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int );
-+extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int );
- extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int );
- extern void* VG_(arm_linux_REDIR_FOR_strcmp)( void*, void* );
- #endif
diff --git a/SOURCES/valgrind-3.13.0-arm64-hwcap.patch b/SOURCES/valgrind-3.13.0-arm64-hwcap.patch
deleted file mode 100644
index 676b647..0000000
--- a/SOURCES/valgrind-3.13.0-arm64-hwcap.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-commit 6bb6c8a65a341a67bd059ec6e1c805813eb17264
-Author: Mark Wielaard <mark@klomp.org>
-Date:   Tue Jun 19 18:00:45 2018 +0200
-
-    Mask AT_HWCAPS on arm64 to those instructions VEX implements.
-    
-    This patch makes sure that the process running under valgrind only sees
-    the AES, PMULL, SHA1, SHA2, CRC32, FP, and ASIMD features in auxv AT_HWCAPS.
-    
-    https://bugs.kde.org/show_bug.cgi?id=381556
-
-diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
-index 30e1f85..61cc458 100644
---- a/coregrind/m_initimg/initimg-linux.c
-+++ b/coregrind/m_initimg/initimg-linux.c
-@@ -703,6 +703,19 @@ Addr setup_client_stack( void*  init_sp,
-                   (and anything above) are not supported by Valgrind. */
-                auxv->u.a_val &= VKI_HWCAP_S390_TE - 1;
-             }
-+#           elif defined(VGP_arm64_linux)
-+            {
-+               /* Limit the AT_HWCAP to just those features we explicitly
-+		  support in VEX.  */
-+#define ARM64_SUPPORTED_HWCAP (VKI_HWCAP_AES	        \
-+                               | VKI_HWCAP_PMULL        \
-+                               | VKI_HWCAP_SHA1         \
-+                               | VKI_HWCAP_SHA2         \
-+                               | VKI_HWCAP_CRC32        \
-+                               | VKI_HWCAP_FP           \
-+                               | VKI_HWCAP_ASIMD)
-+               auxv->u.a_val &= ARM64_SUPPORTED_HWCAP;
-+            }
- #           endif
-             break;
- #        if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
-diff --git a/include/vki/vki-arm64-linux.h b/include/vki/vki-arm64-linux.h
-index af6b435..54b0428 100644
---- a/include/vki/vki-arm64-linux.h
-+++ b/include/vki/vki-arm64-linux.h
-@@ -692,6 +692,39 @@ struct vki_shminfo64 {
- #define VKI_TIOCSSERIAL     0x541F
- 
- //----------------------------------------------------------------------
-+// From linux-4.17/include/uapi/asm-generic/ioctls.h
-+//----------------------------------------------------------------------
-+
-+#define VKI_HWCAP_FP                (1 << 0)
-+#define VKI_HWCAP_ASIMD             (1 << 1)
-+#define VKI_HWCAP_EVTSTRM           (1 << 2)
-+#define VKI_HWCAP_AES               (1 << 3)
-+#define VKI_HWCAP_PMULL             (1 << 4)
-+#define VKI_HWCAP_SHA1              (1 << 5)
-+#define VKI_HWCAP_SHA2              (1 << 6)
-+#define VKI_HWCAP_CRC32             (1 << 7)
-+#define VKI_HWCAP_ATOMICS           (1 << 8)
-+#define VKI_HWCAP_FPHP              (1 << 9)
-+#define VKI_HWCAP_ASIMDHP           (1 << 10)
-+#define VKI_HWCAP_CPUID             (1 << 11)
-+#define VKI_HWCAP_ASIMDRDM          (1 << 12)
-+#define VKI_HWCAP_JSCVT             (1 << 13)
-+#define VKI_HWCAP_FCMA              (1 << 14)
-+#define VKI_HWCAP_LRCPC             (1 << 15)
-+#define VKI_HWCAP_DCPOP             (1 << 16)
-+#define VKI_HWCAP_SHA3              (1 << 17)
-+#define VKI_HWCAP_SM3               (1 << 18)
-+#define VKI_HWCAP_SM4               (1 << 19)
-+#define VKI_HWCAP_ASIMDDP           (1 << 20)
-+#define VKI_HWCAP_SHA512            (1 << 21)
-+#define VKI_HWCAP_SVE               (1 << 22)
-+#define VKI_HWCAP_ASIMDFHM          (1 << 23)
-+#define VKI_HWCAP_DIT               (1 << 24)
-+#define VKI_HWCAP_USCAT             (1 << 25)
-+#define VKI_HWCAP_ILRCPC            (1 << 26)
-+#define VKI_HWCAP_FLAGM             (1 << 27)
-+
-+//----------------------------------------------------------------------
- // And that's it!
- //----------------------------------------------------------------------
-  
diff --git a/SOURCES/valgrind-3.13.0-arm64-ptrace.patch b/SOURCES/valgrind-3.13.0-arm64-ptrace.patch
deleted file mode 100644
index 6ac1a44..0000000
--- a/SOURCES/valgrind-3.13.0-arm64-ptrace.patch
+++ /dev/null
@@ -1,235 +0,0 @@
-commit 122225d7ed260f6bd9de4472e5260ec768ce972d
-Author: Mark Wielaard <mark@klomp.org>
-Date:   Tue Jun 19 18:26:43 2018 +0200
-
-    Implement ptrace syscall wrapper for arm64-linux.
-    
-    With this valgrind is able to run gdb on arm64.
-    Also fixes the memcheck/tests/linux/getregset testcase.
-    
-    https://bugs.kde.org/show_bug.cgi?id=368913
-
-diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
-index 32b87bf..24a6493 100644
---- a/coregrind/m_syswrap/syswrap-arm64-linux.c
-+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
-@@ -265,7 +265,7 @@ DECL_TEMPLATE(arm64_linux, sys_rt_sigreturn);
- //ZZ DECL_TEMPLATE(arm_linux, sys_sigsuspend);
- //ZZ DECL_TEMPLATE(arm_linux, sys_set_tls);
- //ZZ DECL_TEMPLATE(arm_linux, sys_cacheflush);
--//ZZ DECL_TEMPLATE(arm_linux, sys_ptrace);
-+DECL_TEMPLATE(arm64_linux, sys_ptrace);
- 
- //ZZ PRE(sys_mmap2)
- //ZZ {
-@@ -459,137 +459,70 @@ PRE(sys_rt_sigreturn)
- //ZZ                               "PRE(sys_cacheflush)" );
- //ZZ    SET_STATUS_Success(0);
- //ZZ }
--//ZZ 
--//ZZ // ARG3 is only used for pointers into the traced process's address
--//ZZ // space and for offsets into the traced process's struct
--//ZZ // user_regs_struct. It is never a pointer into this process's memory
--//ZZ // space, and we should therefore not check anything it points to.
--//ZZ PRE(sys_ptrace)
--//ZZ {
--//ZZ    PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4);
--//ZZ    PRE_REG_READ4(int, "ptrace", 
--//ZZ                  long, request, long, pid, long, addr, long, data);
--//ZZ    switch (ARG1) {
--//ZZ    case VKI_PTRACE_PEEKTEXT:
--//ZZ    case VKI_PTRACE_PEEKDATA:
--//ZZ    case VKI_PTRACE_PEEKUSR:
--//ZZ       PRE_MEM_WRITE( "ptrace(peek)", ARG4, 
--//ZZ 		     sizeof (long));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETREGS:
--//ZZ       PRE_MEM_WRITE( "ptrace(getregs)", ARG4, 
--//ZZ 		     sizeof (struct vki_user_regs_struct));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETFPREGS:
--//ZZ       PRE_MEM_WRITE( "ptrace(getfpregs)", ARG4, 
--//ZZ 		     sizeof (struct vki_user_fp));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETWMMXREGS:
--//ZZ       PRE_MEM_WRITE( "ptrace(getwmmxregs)", ARG4, 
--//ZZ 		     VKI_IWMMXT_SIZE);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETCRUNCHREGS:
--//ZZ       PRE_MEM_WRITE( "ptrace(getcrunchregs)", ARG4, 
--//ZZ 		     VKI_CRUNCH_SIZE);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETVFPREGS:
--//ZZ       PRE_MEM_WRITE( "ptrace(getvfpregs)", ARG4, 
--//ZZ                      sizeof (struct vki_user_vfp) );
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETHBPREGS:
--//ZZ       PRE_MEM_WRITE( "ptrace(gethbpregs)", ARG4, 
--//ZZ                      sizeof (unsigned long) );
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETREGS:
--//ZZ       PRE_MEM_READ( "ptrace(setregs)", ARG4, 
--//ZZ 		     sizeof (struct vki_user_regs_struct));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETFPREGS:
--//ZZ       PRE_MEM_READ( "ptrace(setfpregs)", ARG4, 
--//ZZ 		     sizeof (struct vki_user_fp));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETWMMXREGS:
--//ZZ       PRE_MEM_READ( "ptrace(setwmmxregs)", ARG4, 
--//ZZ 		     VKI_IWMMXT_SIZE);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETCRUNCHREGS:
--//ZZ       PRE_MEM_READ( "ptrace(setcrunchregs)", ARG4, 
--//ZZ 		     VKI_CRUNCH_SIZE);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETVFPREGS:
--//ZZ       PRE_MEM_READ( "ptrace(setvfpregs)", ARG4, 
--//ZZ                      sizeof (struct vki_user_vfp));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETHBPREGS:
--//ZZ       PRE_MEM_READ( "ptrace(sethbpregs)", ARG4, sizeof(unsigned long));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GET_THREAD_AREA:
--//ZZ       PRE_MEM_WRITE( "ptrace(get_thread_area)", ARG4, sizeof(unsigned long));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETEVENTMSG:
--//ZZ       PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETSIGINFO:
--//ZZ       PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETSIGINFO:
--//ZZ       PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETREGSET:
--//ZZ       ML_(linux_PRE_getregset)(tid, ARG3, ARG4);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_SETREGSET:
--//ZZ       ML_(linux_PRE_setregset)(tid, ARG3, ARG4);
--//ZZ       break;
--//ZZ    default:
--//ZZ       break;
--//ZZ    }
--//ZZ }
--//ZZ 
--//ZZ POST(sys_ptrace)
--//ZZ {
--//ZZ    switch (ARG1) {
--//ZZ    case VKI_PTRACE_PEEKTEXT:
--//ZZ    case VKI_PTRACE_PEEKDATA:
--//ZZ    case VKI_PTRACE_PEEKUSR:
--//ZZ       POST_MEM_WRITE( ARG4, sizeof (long));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETREGS:
--//ZZ       POST_MEM_WRITE( ARG4, sizeof (struct vki_user_regs_struct));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETFPREGS:
--//ZZ       POST_MEM_WRITE( ARG4, sizeof (struct vki_user_fp));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETWMMXREGS:
--//ZZ       POST_MEM_WRITE( ARG4, VKI_IWMMXT_SIZE);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETCRUNCHREGS:
--//ZZ       POST_MEM_WRITE( ARG4, VKI_CRUNCH_SIZE);
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETVFPREGS:
--//ZZ       POST_MEM_WRITE( ARG4, sizeof(struct vki_user_vfp));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GET_THREAD_AREA:
--//ZZ    case VKI_PTRACE_GETHBPREGS:
--//ZZ    case VKI_PTRACE_GETEVENTMSG:
--//ZZ       POST_MEM_WRITE( ARG4, sizeof(unsigned long));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETSIGINFO:
--//ZZ       /* XXX: This is a simplification. Different parts of the
--//ZZ        * siginfo_t are valid depending on the type of signal.
--//ZZ        */
--//ZZ       POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t));
--//ZZ       break;
--//ZZ    case VKI_PTRACE_GETREGSET:
--//ZZ       ML_(linux_POST_getregset)(tid, ARG3, ARG4);
--//ZZ       break;
--//ZZ    default:
--//ZZ       break;
--//ZZ    }
--//ZZ }
--//ZZ 
--//ZZ #undef PRE
--//ZZ #undef POST
-+
-+// ARG3 is only used for pointers into the traced process's address
-+// space and for offsets into the traced process's struct
-+// user_regs_struct. It is never a pointer into this process's memory
-+// space, and we should therefore not check anything it points to.
-+PRE(sys_ptrace)
-+{
-+   PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4);
-+   PRE_REG_READ4(int, "ptrace",
-+                 long, request, long, pid, long, addr, long, data);
-+   switch (ARG1) {
-+   case VKI_PTRACE_PEEKTEXT:
-+   case VKI_PTRACE_PEEKDATA:
-+   case VKI_PTRACE_PEEKUSR:
-+      PRE_MEM_WRITE( "ptrace(peek)", ARG4,
-+		     sizeof (long));
-+      break;
-+   case VKI_PTRACE_GETEVENTMSG:
-+      PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long));
-+      break;
-+   case VKI_PTRACE_GETSIGINFO:
-+      PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t));
-+      break;
-+   case VKI_PTRACE_SETSIGINFO:
-+      PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t));
-+      break;
-+   case VKI_PTRACE_GETREGSET:
-+      ML_(linux_PRE_getregset)(tid, ARG3, ARG4);
-+      break;
-+   case VKI_PTRACE_SETREGSET:
-+      ML_(linux_PRE_setregset)(tid, ARG3, ARG4);
-+      break;
-+   default:
-+      break;
-+   }
-+}
-+
-+POST(sys_ptrace)
-+{
-+   switch (ARG1) {
-+   case VKI_PTRACE_PEEKTEXT:
-+   case VKI_PTRACE_PEEKDATA:
-+   case VKI_PTRACE_PEEKUSR:
-+      POST_MEM_WRITE( ARG4, sizeof (long));
-+      break;
-+   case VKI_PTRACE_GETEVENTMSG:
-+      POST_MEM_WRITE( ARG4, sizeof(unsigned long));
-+      break;
-+   case VKI_PTRACE_GETSIGINFO:
-+      /* XXX: This is a simplification. Different parts of the
-+       * siginfo_t are valid depending on the type of signal.
-+       */
-+      POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t));
-+      break;
-+   case VKI_PTRACE_GETREGSET:
-+      ML_(linux_POST_getregset)(tid, ARG3, ARG4);
-+      break;
-+   default:
-+      break;
-+   }
-+}
-+
-+#undef PRE
-+#undef POST
- 
- /* ---------------------------------------------------------------------
-    The arm64/Linux syscall table
-@@ -730,7 +663,7 @@ static SyscallTableEntry syscall_main_table[] = {
-    LINXY(__NR_clock_getres,      sys_clock_getres),      // 114
-    LINXY(__NR_clock_nanosleep,   sys_clock_nanosleep),   // 115
-    LINXY(__NR_syslog,            sys_syslog),            // 116
--   //   (__NR_ptrace,            sys_ptrace),            // 117
-+   PLAXY(__NR_ptrace,            sys_ptrace),            // 117
-    LINXY(__NR_sched_setparam,    sys_sched_setparam),    // 118
-    LINX_(__NR_sched_setscheduler,sys_sched_setscheduler),// 119
-    LINX_(__NR_sched_getscheduler,sys_sched_getscheduler),// 120
diff --git a/SOURCES/valgrind-3.13.0-build-id-phdrs.patch b/SOURCES/valgrind-3.13.0-build-id-phdrs.patch
deleted file mode 100644
index 6a0a9df..0000000
--- a/SOURCES/valgrind-3.13.0-build-id-phdrs.patch
+++ /dev/null
@@ -1,17 +0,0 @@
-diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c
-index 70c28e629..8bd3e049c 100644
---- a/coregrind/m_debuginfo/readelf.c
-+++ b/coregrind/m_debuginfo/readelf.c
-@@ -1137,7 +1137,11 @@ HChar* find_buildid(DiImage* img, Bool rel_ok, Bool search_shdrs)
- 
-       ElfXX_Ehdr ehdr;
-       ML_(img_get)(&ehdr, img, 0, sizeof(ehdr));
--      for (i = 0; i < ehdr.e_phnum; i++) {
-+      /* Skip the phdrs when we have to search the shdrs. In separate
-+         .debug files the phdrs might not be valid (they are a copy of
-+         the main ELF file) and might trigger assertions when getting
-+	 image notes based on them. */
-+      for (i = 0; !search_shdrs && i < ehdr.e_phnum; i++) {
-          ElfXX_Phdr phdr;
-          ML_(img_get)(&phdr, img,
-                       ehdr.e_phoff + i * ehdr.e_phentsize, sizeof(phdr));
diff --git a/SOURCES/valgrind-3.13.0-debug-alt-file.patch b/SOURCES/valgrind-3.13.0-debug-alt-file.patch
deleted file mode 100644
index 9176bb1..0000000
--- a/SOURCES/valgrind-3.13.0-debug-alt-file.patch
+++ /dev/null
@@ -1,160 +0,0 @@
-commit be82bb5f9dfecd854c53eda321d1914f28f19790
-Author: Mark Wielaard <mark@klomp.org>
-Date:   Sat Dec 9 23:01:29 2017 +0100
-
-    Fix gnu debug alt file resolving.
-    
-    https://bugs.kde.org/show_bug.cgi?id=387773
-    
-    The path to the alt file is relative to the actual debug file.
-    Make sure that we got the real file, not a (build-id) symlink.
-    Also handle the case where a debug or alt file is an absolute path.
-
-diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c
-index e612250..c19ff21 100644
---- a/coregrind/m_debuginfo/readelf.c
-+++ b/coregrind/m_debuginfo/readelf.c
-@@ -33,6 +33,7 @@
- 
- #include "pub_core_basics.h"
- #include "pub_core_vki.h"
-+#include "pub_core_vkiscnums.h"
- #include "pub_core_debuginfo.h"
- #include "pub_core_libcbase.h"
- #include "pub_core_libcprint.h"
-@@ -40,6 +41,7 @@
- #include "pub_core_machine.h"      /* VG_ELF_CLASS */
- #include "pub_core_options.h"
- #include "pub_core_oset.h"
-+#include "pub_core_syscall.h"
- #include "pub_core_tooliface.h"    /* VG_(needs) */
- #include "pub_core_xarray.h"
- #include "priv_misc.h"             /* dinfo_zalloc/free/strdup */
-@@ -1323,6 +1325,12 @@ DiImage* find_debug_file( struct _DebugInfo* di,
-                      + (extrapath ? VG_(strlen)(extrapath) : 0)
-                      + (serverpath ? VG_(strlen)(serverpath) : 0));
- 
-+      if (debugname[0] == '/') {
-+         VG_(sprintf)(debugpath, "%s", debugname);
-+         dimg = open_debug_file(debugpath, buildid, crc, rel_ok, NULL);
-+         if (dimg != NULL) goto dimg_ok;
-+      }
-+
-       VG_(sprintf)(debugpath, "%s/%s", objdir, debugname);
-       dimg = open_debug_file(debugpath, buildid, crc, rel_ok, NULL);
-       if (dimg != NULL) goto dimg_ok;
-@@ -1527,6 +1535,56 @@ static Bool check_compression(ElfXX_Shdr* h, DiSlice* s) {
-     return True;
- }
- 
-+/* Helper function to get the readlink path. Returns a copy of path if the
-+   file wasn't a symbolic link. Returns NULL on error. Unless NULL is
-+   returned the result needs to be released with dinfo_free.
-+*/
-+static HChar* readlink_path (const HChar *path)
-+{
-+   SizeT bufsiz = VG_(strlen)(path);
-+   HChar *buf = ML_(dinfo_strdup)("readlink_path.strdup", path);
-+   UInt   tries = 6;
-+
-+   while (tries > 0) {
-+      SysRes res;
-+#if defined(VGP_arm64_linux)
-+      res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD,
-+                                              (UWord)path, (UWord)buf, bufsiz);
-+#elif defined(VGO_linux) || defined(VGO_darwin)
-+      res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz);
-+#elif defined(VGO_solaris)
-+      res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)path,
-+                             (UWord)buf, bufsiz);
-+#else
-+#       error Unknown OS
-+#endif
-+      if (sr_isError(res)) {
-+         if (sr_Err(res) == VKI_EINVAL)
-+            return buf; // It wasn't a symbolic link, return the strdup result.
-+         ML_(dinfo_free)(buf);
-+         return NULL;
-+      }
-+
-+      SSizeT r = sr_Res(res);
-+      if (r < 0) break;
-+      if (r == bufsiz) {  // buffer too small; increase and retry
-+         bufsiz *= 2 + 16;
-+         buf = ML_(dinfo_realloc)("readlink_path.realloc", buf, bufsiz);
-+         tries--;
-+         continue;
-+      }
-+      buf[r] = '\0';
-+      break;
-+   }
-+
-+   if (tries == 0) { // We tried, but weird long path?
-+      ML_(dinfo_free)(buf);
-+      return NULL;
-+   }
-+
-+  return buf;
-+}
-+
- /* The central function for reading ELF debug info.  For the
-    object/exe specified by the DebugInfo, find ELF sections, then read
-    the symbols, line number info, file name info, CFA (stack-unwind
-@@ -2926,8 +2984,12 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
-                                 (debugaltlink_escn.szB - buildid_offset)
-                                 * 2 + 1);
- 
--         /* The altfile might be relative to the debug file or main file. */
-+         /* The altfile might be relative to the debug file or main file.
-+	    Make sure that we got the real file, not a symlink.  */
-          HChar *dbgname = di->fsm.dbgname ? di->fsm.dbgname : di->fsm.filename;
-+         HChar* rdbgname = readlink_path (dbgname);
-+         if (rdbgname == NULL)
-+            rdbgname = ML_(dinfo_strdup)("rdbgname", dbgname);
- 
-          for (j = 0; j < debugaltlink_escn.szB - buildid_offset; j++)
-             VG_(sprintf)(
-@@ -2937,9 +2999,11 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
-                                         + buildid_offset + j));
- 
-          /* See if we can find a matching debug file */
--         aimg = find_debug_file( di, dbgname, altbuildid,
-+         aimg = find_debug_file( di, rdbgname, altbuildid,
-                                  altfile_str_m, 0, True );
- 
-+         ML_(dinfo_free)(rdbgname);
-+
-          if (altfile_str_m)
-             ML_(dinfo_free)(altfile_str_m);
-          ML_(dinfo_free)(altbuildid);
-
-diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c
-index c19ff212b..70c28e629 100644
---- a/coregrind/m_debuginfo/readelf.c
-+++ b/coregrind/m_debuginfo/readelf.c
-@@ -1582,6 +1582,24 @@ static HChar* readlink_path (const HChar *path)
-       return NULL;
-    }
- 
-+  if (buf[0] == '/')
-+    return buf;
-+
-+  /* Relative path, add link dir.  */
-+  HChar *linkdirptr;
-+  SizeT linkdir_len = VG_(strlen)(path);
-+  if ((linkdirptr = VG_(strrchr)(path, '/')) != NULL)
-+    linkdir_len -= VG_(strlen)(linkdirptr + 1);
-+
-+  SizeT buflen = VG_(strlen)(buf);
-+  SizeT needed = linkdir_len + buflen + 1;
-+  if (bufsiz < needed)
-+    buf = ML_(dinfo_realloc)("readlink_path.linkdir", buf, needed);
-+
-+  VG_(memmove)(buf + linkdir_len, buf, buflen);
-+  VG_(memcpy)(buf, path, linkdir_len);
-+  buf[needed - 1] = '\0';
-+
-   return buf;
- }
- 
-
diff --git a/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch b/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch
deleted file mode 100644
index 4f9537a..0000000
--- a/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-commit 59af5db9c15d8ea03c1521736fb1f107d66bce08
-Author: philippe <philippe@a5019735-40e9-0310-863c-91ae7b9d1cf9>
-Date:   Sun Jun 25 20:25:50 2017 +0000
-
-    After fork, vgdb activity is polled according to the nr of bbs done :
-    once the nr of bbs done reaches the next vgdb poll, a check for vgdb
-    activity is done.
-    This might lead to the activation of gdbserver after fork.
-    Such poll is however not expected, unless the children is
-    to be trace.
-    This spurious poll in the forked child can cause failures
-    depending on the nr of bbs done before the fork, and the
-    nr of bbs done between the fork and the exec.
-    
-    => disable vgdb poll in the child in the cleanup after fork
-    in the child, unless the children have to be traced.
-    
-    
-    
-    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16454 a5019735-40e9-0310-863c-91ae7b9d1cf9
-
-diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c
-index 87fbce2..648d543 100644
---- a/coregrind/m_gdbserver/m_gdbserver.c
-+++ b/coregrind/m_gdbserver/m_gdbserver.c
-@@ -646,6 +646,10 @@ static void gdbserver_cleanup_in_child_after_fork(ThreadId me)
-    
-    if (VG_(clo_trace_children)) {
-       VG_(gdbserver_prerun_action) (me);
-+   } else {
-+      /* After fork, if we do not trace the children, disable vgdb
-+         poll to avoid gdbserver being called unexpectedly. */
-+      VG_(disable_vgdb_poll) ();
-    }
- }
- 
diff --git a/SOURCES/valgrind-3.13.0-epoll_pwait.patch b/SOURCES/valgrind-3.13.0-epoll_pwait.patch
deleted file mode 100644
index 8a7516b..0000000
--- a/SOURCES/valgrind-3.13.0-epoll_pwait.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-commit 79865f0eed7cf0e0ad687ee0a59d59a1d505b514
-Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
-Date:   Sat Jun 17 13:49:22 2017 +0000
-
-    epoll_pwait can have a NULL sigmask.
-    
-    According to the epoll_pwait(2) man page:
-    
-           The  sigmask  argument  may  be  specified  as  NULL,  in  which  case
-           epoll_pwait() is equivalent to epoll_wait().
-    
-    But doing that under valgrind gives:
-    
-    ==13887== Syscall param epoll_pwait(sigmask) points to unaddressable byte(s)
-    ==13887==    at 0x4F2B940: epoll_pwait (epoll_pwait.c:43)
-    ==13887==    by 0x400ADE: main (syscalls-2007.c:89)
-    ==13887==  Address 0x0 is not stack'd, malloc'd or (recently) free'd
-    
-    This is because the sys_epoll_pwait wrapper has:
-    
-       if (ARG4)
-          PRE_MEM_READ( "epoll_pwait(sigmask)", ARG5, sizeof(vki_sigset_t) );
-    
-    Which looks like a typo (ARG4 is timeout and ARG5 is sigmask).
-    
-    This shows up with newer glibc which translates an epoll_wait call into
-    an epoll_pwait call with NULL sigmask.
-    
-    Fix typo and add a testcase.
-    
-    https://bugs.kde.org/show_bug.cgi?id=381289
-    
-    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16451 a5019735-40e9-0310-863c-91ae7b9d1cf9
-
-diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c
-index 26e02fd..4120c1d 100644
---- a/coregrind/m_syswrap/syswrap-linux.c
-+++ b/coregrind/m_syswrap/syswrap-linux.c
-@@ -1901,7 +1901,7 @@ PRE(sys_epoll_pwait)
-                  int, maxevents, int, timeout, vki_sigset_t *, sigmask,
-                  vki_size_t, sigsetsize);
-    PRE_MEM_WRITE( "epoll_pwait(events)", ARG2, sizeof(struct vki_epoll_event)*ARG3);
--   if (ARG4)
-+   if (ARG5)
-       PRE_MEM_READ( "epoll_pwait(sigmask)", ARG5, sizeof(vki_sigset_t) );
- }
- POST(sys_epoll_pwait)
-diff --git a/memcheck/tests/linux/syscalls-2007.c b/memcheck/tests/linux/syscalls-2007.c
-index b61c6d5..5494623 100644
---- a/memcheck/tests/linux/syscalls-2007.c
-+++ b/memcheck/tests/linux/syscalls-2007.c
-@@ -79,5 +79,16 @@ int main (void)
-   }
- #endif
- 
-+#if defined(HAVE_EPOLL_CREATE) && defined(HAVE_EPOLL_PWAIT)
-+  {
-+    int fd3;
-+    struct epoll_event evs[10];
-+
-+    fd3 = epoll_create (10);
-+    /* epoll_pwait can take a NULL sigmask. */
-+    epoll_pwait (fd3, evs, 10, 1, NULL);
-+  }
-+#endif
-+
-   return 0;
- }
diff --git a/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch b/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch
deleted file mode 100644
index f34da04..0000000
--- a/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch
+++ /dev/null
@@ -1,183 +0,0 @@
-commit 21788250c945713fa25c16f2683e1f9cd0bb6ccf
-Author: philippe <philippe@a5019735-40e9-0310-863c-91ae7b9d1cf9>
-Date:   Sun Jun 25 12:40:53 2017 +0000
-
-    Fix some tests failure with GDB 8.0
-    
-    At the beginning of a Valgrind gdbserver test,
-    2 messages are produced when launching the command
-       target remote | vgdb
-    
-    A message output by vgdb:
-       relaying data between gdb and process <pid>
-    (this message is read by GDB from the vgdb pipe, and re-output
-    on stderr)
-    and a message produced by GDB:
-       Remote debugging using | ./vgdb
-    
-    GDB 8.0 changes the order in which the above messages are output.
-    This causes 2 tests to fail, as the 'relaying' line appears
-    then in a part of the output deleted by a filter script.
-    
-    To avoid this, change the filter scripts to always remove
-    this 'relaying line', which is not particularly interesting to check.
-    All the .exp files containining such a 'relaying' line are updated
-    accordingly.
-    
-    This has been tested with various gdb versions (7.5, 7.7, 7.12, 8.0)
-    on amd64 and/or ppc64.
-    
-    Thanks to Mark Wielaard, which helped to investigate this problem
-    by bisecting the GDB patches in GDB 8.0 causing this change of
-    behaviour.
-    
-    
-    
-    
-    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16453 a5019735-40e9-0310-863c-91ae7b9d1cf9
-
-diff --git a/gdbserver_tests/filter_gdb b/gdbserver_tests/filter_gdb
-index 7177720..ed78cfe 100755
---- a/gdbserver_tests/filter_gdb
-+++ b/gdbserver_tests/filter_gdb
-@@ -72,7 +72,7 @@ sed -e '/Remote debugging using/,/vgdb launched process attached/d'
-     -e '/^Missing separate debuginfo/d'                                                               \
-     -e '/\/_exit.c: No such file or directory/d'                                                      \
-     -e '/^Try: zypper install -C/d'                                                                   \
--    -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../'                              \
-+    -e '/relaying data between gdb and process/d'                                                     \
-     -e 's/pid [0-9][0-9]*/pid ..../g'                                                                 \
-     -e 's/Thread [0-9][0-9]*/Thread ..../g'                                                           \
-     -e '/\[Switching to Thread ....\]/d'                                                              \
-diff --git a/gdbserver_tests/filter_vgdb b/gdbserver_tests/filter_vgdb
-index 2442ec5..f8028a3 100755
---- a/gdbserver_tests/filter_vgdb
-+++ b/gdbserver_tests/filter_vgdb
-@@ -11,7 +11,7 @@ $dir/../tests/filter_addresses                  |
- #             pid
- # gdb 7.2 sometimes tries to access address 0x0 (same as with standard gdbserver)
- # filter a debian 6.0/ppc32 line
--sed -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../' \
-+sed -e '/relaying data between gdb and process/d'                        \
-     -e 's/\(sending command .* to pid \)[0-9][0-9]*/\1..../'             \
-     -e '/Cannot access memory at address 0x......../d'                   \
-     -e '/^[1-9][0-9]*	\.\.\/sysdeps\/powerpc\/powerpc32\/dl-start\.S: No such file or directory\./d' |
-diff --git a/gdbserver_tests/hginfo.stderrB.exp b/gdbserver_tests/hginfo.stderrB.exp
-index df47f11..669ff92 100644
---- a/gdbserver_tests/hginfo.stderrB.exp
-+++ b/gdbserver_tests/hginfo.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- Lock ga 0x........ {
-  Address 0x........ is 0 bytes inside data symbol "mx"
-diff --git a/gdbserver_tests/mcblocklistsearch.stderrB.exp b/gdbserver_tests/mcblocklistsearch.stderrB.exp
-index 312d776..1313321 100644
---- a/gdbserver_tests/mcblocklistsearch.stderrB.exp
-+++ b/gdbserver_tests/mcblocklistsearch.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- Breakpoint 1 at 0x........: file leak-tree.c, line 42.
- Breakpoint 2 at 0x........: file leak-tree.c, line 67.
-diff --git a/gdbserver_tests/mcbreak.stderrB.exp b/gdbserver_tests/mcbreak.stderrB.exp
-index 65281d2..0f051d1 100644
---- a/gdbserver_tests/mcbreak.stderrB.exp
-+++ b/gdbserver_tests/mcbreak.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- vgdb-error value changed from 999999 to 0
- n_errs_found 1 n_errs_shown 1 (vgdb-error 0) 
-diff --git a/gdbserver_tests/mcclean_after_fork.stderrB.exp b/gdbserver_tests/mcclean_after_fork.stderrB.exp
-index 995b42f..e812b8e 100644
---- a/gdbserver_tests/mcclean_after_fork.stderrB.exp
-+++ b/gdbserver_tests/mcclean_after_fork.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- monitor command request to kill this process
- Remote connection closed
-diff --git a/gdbserver_tests/mcinfcallWSRU.stderrB.exp b/gdbserver_tests/mcinfcallWSRU.stderrB.exp
-index 7789123..a2f2b87 100644
---- a/gdbserver_tests/mcinfcallWSRU.stderrB.exp
-+++ b/gdbserver_tests/mcinfcallWSRU.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- Breakpoint 1 at 0x........: file sleepers.c, line 74.
- Continuing.
-diff --git a/gdbserver_tests/mcleak.stderrB.exp b/gdbserver_tests/mcleak.stderrB.exp
-index 7782119..7ed3920 100644
---- a/gdbserver_tests/mcleak.stderrB.exp
-+++ b/gdbserver_tests/mcleak.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- 10 bytes in 1 blocks are still reachable in loss record ... of ...
-    at 0x........: malloc (vg_replace_malloc.c:...)
-diff --git a/gdbserver_tests/mcmain_pic.stderrB.exp b/gdbserver_tests/mcmain_pic.stderrB.exp
-index c90e1fa..53ec0ce 100644
---- a/gdbserver_tests/mcmain_pic.stderrB.exp
-+++ b/gdbserver_tests/mcmain_pic.stderrB.exp
-@@ -1,2 +1 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
-diff --git a/gdbserver_tests/mcvabits.stderrB.exp b/gdbserver_tests/mcvabits.stderrB.exp
-index bdabb1e..f9ced7a 100644
---- a/gdbserver_tests/mcvabits.stderrB.exp
-+++ b/gdbserver_tests/mcvabits.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- Address 0x........ len 10 addressable
-  Address 0x........ is 0 bytes inside data symbol "undefined"
-diff --git a/gdbserver_tests/mssnapshot.stderrB.exp b/gdbserver_tests/mssnapshot.stderrB.exp
-index 8bee8fc..e419ce6 100644
---- a/gdbserver_tests/mssnapshot.stderrB.exp
-+++ b/gdbserver_tests/mssnapshot.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- general valgrind monitor commands:
-   help [debug]            : monitor command help. With debug: + debugging commands
-diff --git a/gdbserver_tests/nlgone_abrt.stderrB.exp b/gdbserver_tests/nlgone_abrt.stderrB.exp
-index c8b2024..e69de29 100644
---- a/gdbserver_tests/nlgone_abrt.stderrB.exp
-+++ b/gdbserver_tests/nlgone_abrt.stderrB.exp
-@@ -1 +0,0 @@
--relaying data between gdb and process ....
-diff --git a/gdbserver_tests/nlgone_exit.stderrB.exp b/gdbserver_tests/nlgone_exit.stderrB.exp
-index c8b2024..e69de29 100644
---- a/gdbserver_tests/nlgone_exit.stderrB.exp
-+++ b/gdbserver_tests/nlgone_exit.stderrB.exp
-@@ -1 +0,0 @@
--relaying data between gdb and process ....
-diff --git a/gdbserver_tests/nlgone_return.stderrB.exp b/gdbserver_tests/nlgone_return.stderrB.exp
-index c8b2024..e69de29 100644
---- a/gdbserver_tests/nlgone_return.stderrB.exp
-+++ b/gdbserver_tests/nlgone_return.stderrB.exp
-@@ -1 +0,0 @@
--relaying data between gdb and process ....
-diff --git a/gdbserver_tests/nlpasssigalrm.stderrB.exp b/gdbserver_tests/nlpasssigalrm.stderrB.exp
-index c90e1fa..53ec0ce 100644
---- a/gdbserver_tests/nlpasssigalrm.stderrB.exp
-+++ b/gdbserver_tests/nlpasssigalrm.stderrB.exp
-@@ -1,2 +1 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
-diff --git a/gdbserver_tests/nlself_invalidate.stderrB.exp b/gdbserver_tests/nlself_invalidate.stderrB.exp
-index c8b2024..e69de29 100644
---- a/gdbserver_tests/nlself_invalidate.stderrB.exp
-+++ b/gdbserver_tests/nlself_invalidate.stderrB.exp
-@@ -1 +0,0 @@
--relaying data between gdb and process ....
-diff --git a/gdbserver_tests/nlsigvgdb.stderrB.exp b/gdbserver_tests/nlsigvgdb.stderrB.exp
-index 672fea5..ed5bb61 100644
---- a/gdbserver_tests/nlsigvgdb.stderrB.exp
-+++ b/gdbserver_tests/nlsigvgdb.stderrB.exp
-@@ -1,4 +1,3 @@
--relaying data between gdb and process ....
- vgdb-error value changed from 0 to 999999
- gdbserver: continuing in 5000 ms ...
- gdbserver: continuing after wait ...
diff --git a/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch b/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch
deleted file mode 100644
index 8356773..0000000
--- a/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-commit 326d53c8378984c50f29bd124d3f2b4a1242306c
-Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
-Date:   Fri Jun 16 09:33:35 2017 +0000
-
-    ppc64 doesn't compile test_isa_2_06_partx.c without VSX support
-    
-    The #ifdef HAS_VSX guard is wrongly placed. It makes the standard
-    include headers not be used. Causing a build failure. Fix by moving
-    the #ifdef HAS_VSX after the standard includes.
-    
-    https://bugs.kde.org/show_bug.cgi?id=381272
-    
-    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16450 a5019735-40e9-0310-863c-91ae7b9d1cf9
-
-diff --git a/none/tests/ppc32/test_isa_2_06_part1.c b/none/tests/ppc32/test_isa_2_06_part1.c
-index 7cd4930..7a14c6d 100644
---- a/none/tests/ppc32/test_isa_2_06_part1.c
-+++ b/none/tests/ppc32/test_isa_2_06_part1.c
-@@ -20,13 +20,14 @@
-  The GNU General Public License is contained in the file COPYING.
-  */
- 
--#ifdef HAS_VSX
--
- #include <stdio.h>
- #include <stdint.h>
- #include <stdlib.h>
- #include <string.h>
- #include <malloc.h>
-+
-+#ifdef HAS_VSX
-+
- #include <altivec.h>
- 
- #ifndef __powerpc64__
-diff --git a/none/tests/ppc32/test_isa_2_06_part2.c b/none/tests/ppc32/test_isa_2_06_part2.c
-index c7bf4fe..2ee7b53 100644
---- a/none/tests/ppc32/test_isa_2_06_part2.c
-+++ b/none/tests/ppc32/test_isa_2_06_part2.c
-@@ -20,17 +20,18 @@
-  The GNU General Public License is contained in the file COPYING.
-  */
- 
--#ifdef HAS_VSX
--
- #include <stdio.h>
- #include <stdint.h>
- #include <stdlib.h>
- #include <string.h>
- #include <malloc.h>
--#include <altivec.h>
- #include <math.h>
- #include <unistd.h>    // getopt
- 
-+#ifdef HAS_VSX
-+
-+#include <altivec.h>
-+
- #ifndef __powerpc64__
- typedef uint32_t HWord_t;
- #else
-diff --git a/none/tests/ppc32/test_isa_2_06_part3.c b/none/tests/ppc32/test_isa_2_06_part3.c
-index 8c74c09..5ebc1a5 100644
---- a/none/tests/ppc32/test_isa_2_06_part3.c
-+++ b/none/tests/ppc32/test_isa_2_06_part3.c
-@@ -20,17 +20,18 @@
-  The GNU General Public License is contained in the file COPYING.
-  */
- 
--#ifdef HAS_VSX
--
- #include <stdio.h>
- #include <stdint.h>
- #include <stdlib.h>
- #include <string.h>
- #include <malloc.h>
--#include <altivec.h>
- #include <math.h>
- #include <unistd.h>    // getopt
- 
-+#ifdef HAS_VSX
-+
-+#include <altivec.h>
-+
- #ifndef __powerpc64__
- typedef uint32_t HWord_t;
- #else
-
-diff --git a/none/tests/ppc64/test_isa_2_06_part1.c b/none/tests/ppc64/test_isa_2_06_part1.c
-index 7cd4930..7a14c6d 100644
---- a/none/tests/ppc64/test_isa_2_06_part1.c
-+++ b/none/tests/ppc64/test_isa_2_06_part1.c
-@@ -20,13 +20,14 @@
-  The GNU General Public License is contained in the file COPYING.
-  */
- 
--#ifdef HAS_VSX
--
- #include <stdio.h>
- #include <stdint.h>
- #include <stdlib.h>
- #include <string.h>
- #include <malloc.h>
-+
-+#ifdef HAS_VSX
-+
- #include <altivec.h>
- 
- #ifndef __powerpc64__
-diff --git a/none/tests/ppc64/test_isa_2_06_part2.c b/none/tests/ppc64/test_isa_2_06_part2.c
-index c7bf4fe..2ee7b53 100644
---- a/none/tests/ppc64/test_isa_2_06_part2.c
-+++ b/none/tests/ppc64/test_isa_2_06_part2.c
-@@ -20,17 +20,18 @@
-  The GNU General Public License is contained in the file COPYING.
-  */
- 
--#ifdef HAS_VSX
--
- #include <stdio.h>
- #include <stdint.h>
- #include <stdlib.h>
- #include <string.h>
- #include <malloc.h>
--#include <altivec.h>
- #include <math.h>
- #include <unistd.h>    // getopt
- 
-+#ifdef HAS_VSX
-+
-+#include <altivec.h>
-+
- #ifndef __powerpc64__
- typedef uint32_t HWord_t;
- #else
-diff --git a/none/tests/ppc64/test_isa_2_06_part3.c b/none/tests/ppc64/test_isa_2_06_part3.c
-index 8c74c09..5ebc1a5 100644
---- a/none/tests/ppc64/test_isa_2_06_part3.c
-+++ b/none/tests/ppc64/test_isa_2_06_part3.c
-@@ -20,17 +20,18 @@
-  The GNU General Public License is contained in the file COPYING.
-  */
- 
--#ifdef HAS_VSX
--
- #include <stdio.h>
- #include <stdint.h>
- #include <stdlib.h>
- #include <string.h>
- #include <malloc.h>
--#include <altivec.h>
- #include <math.h>
- #include <unistd.h>    // getopt
- 
-+#ifdef HAS_VSX
-+
-+#include <altivec.h>
-+
- #ifndef __powerpc64__
- typedef uint32_t HWord_t;
- #else
diff --git a/SOURCES/valgrind-3.13.0-ppc64-diag.patch b/SOURCES/valgrind-3.13.0-ppc64-diag.patch
deleted file mode 100644
index eba0acb..0000000
--- a/SOURCES/valgrind-3.13.0-ppc64-diag.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index e16e837..a8d4926 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -29356,62 +29356,70 @@ DisResult disInstr_PPC_WRK (
- 
-    decode_noF:
-       vassert(!allow_F);
--      vex_printf("disInstr(ppc): found the Floating Point instruction 0x%x that\n"
--		 "can't be handled by Valgrind on this host.  This instruction\n"
--		 "requires a host that supports Floating Point instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the Floating Point instruction 0x%x that\n"
-+		    "can't be handled by Valgrind on this host.  This instruction\n"
-+		    "requires a host that supports Floating Point instructions.\n",
-+		    theInstr);
-       goto not_supported;
-    decode_noV:
-       vassert(!allow_V);
--      vex_printf("disInstr(ppc): found an AltiVec or an e500 instruction 0x%x\n"
--		 "that can't be handled by Valgrind.  If this instruction is an\n"
--		 "Altivec instruction, Valgrind must be run on a host that supports"
--		 "AltiVec instructions.  If the application was compiled for e500, then\n"
--		 "unfortunately Valgrind does not yet support e500 instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found an AltiVec or an e500 instruction 0x%x\n"
-+		    "that can't be handled by Valgrind.  If this instruction is an\n"
-+		    "Altivec instruction, Valgrind must be run on a host that supports"
-+		    "AltiVec instructions.  If the application was compiled for e500, then\n"
-+		    "unfortunately Valgrind does not yet support e500 instructions.\n",
-+		    theInstr);
-       goto not_supported;
-    decode_noVX:
-       vassert(!allow_VX);
--      vex_printf("disInstr(ppc): found the instruction 0x%x that is defined in the\n"
--		 "Power ISA 2.06 ABI but can't be handled by Valgrind on this host.\n"
--		 "This instruction \nrequires a host that supports the ISA 2.06 ABI.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the instruction 0x%x that is defined in the\n"
-+		    "Power ISA 2.06 ABI but can't be handled by Valgrind on this host.\n"
-+		    "This instruction \nrequires a host that supports the ISA 2.06 ABI.\n",
-+		    theInstr);
-       goto not_supported;
-    decode_noFX:
-       vassert(!allow_FX);
--      vex_printf("disInstr(ppc): found the General Purpose-Optional instruction 0x%x\n"
--		 "that can't be handled by Valgrind on this host. This instruction\n"
--		 "requires a host that supports the General Purpose-Optional instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the General Purpose-Optional instruction 0x%x\n"
-+		    "that can't be handled by Valgrind on this host. This instruction\n"
-+		    "requires a host that supports the General Purpose-Optional instructions.\n",
-+		    theInstr);
-       goto not_supported;
-    decode_noGX:
-       vassert(!allow_GX);
--      vex_printf("disInstr(ppc): found the Graphics-Optional instruction 0x%x\n"
--		 "that can't be handled by Valgrind on this host. This instruction\n"
--		 "requires a host that supports the Graphic-Optional instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the Graphics-Optional instruction 0x%x\n"
-+		    "that can't be handled by Valgrind on this host. This instruction\n"
-+		    "requires a host that supports the Graphic-Optional instructions.\n",
-+		    theInstr);
-       goto not_supported;
-    decode_noDFP:
-       vassert(!allow_DFP);
--      vex_printf("disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x\n"
--		 "that can't be handled by Valgrind on this host.  This instruction\n"
--		 "requires a host that supports DFP instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x\n"
-+		    "that can't be handled by Valgrind on this host.  This instruction\n"
-+		    "requires a host that supports DFP instructions.\n",
-+		    theInstr);
-       goto not_supported;
-    decode_noP8:
-       vassert(!allow_isa_2_07);
--      vex_printf("disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled\n"
--		 "by Valgrind on this host.  This instruction requires a host that\n"
--		 "supports Power 8 instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled\n"
-+		    "by Valgrind on this host.  This instruction requires a host that\n"
-+		    "supports Power 8 instructions.\n",
-+		    theInstr);
-       goto not_supported;
- 
-    decode_noP9:
-       vassert(!allow_isa_3_0);
--      vex_printf("disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled\n"
--                 "by Valgrind on this host.  This instruction requires a host that\n"
--		 "supports Power 9 instructions.\n",
--		 theInstr);
-+      if (sigill_diag)
-+         vex_printf("disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled\n"
-+                    "by Valgrind on this host.  This instruction requires a host that\n"
-+		    "supports Power 9 instructions.\n",
-+		    theInstr);
-       goto not_supported;
- 
-    decode_failure:
diff --git a/SOURCES/valgrind-3.13.0-ppc64-mtfprwa-constraint.patch b/SOURCES/valgrind-3.13.0-ppc64-mtfprwa-constraint.patch
deleted file mode 100644
index 6b360e0..0000000
--- a/SOURCES/valgrind-3.13.0-ppc64-mtfprwa-constraint.patch
+++ /dev/null
@@ -1,13 +0,0 @@
-diff --git a/none/tests/ppc64/test_isa_2_07_part1.c b/none/tests/ppc64/test_isa_2_07_part1.c
-index 73a563c..201fa88 100644
---- a/none/tests/ppc64/test_isa_2_07_part1.c
-+++ b/none/tests/ppc64/test_isa_2_07_part1.c
-@@ -406,7 +406,7 @@ static void test_mtvsrwz (void)
- 
- static void test_mtfprwa (void)
- {
--   __asm__ __volatile__ ("mtfprwa %x0,%1" : "=ws" (vec_out) : "r" (r14));
-+   __asm__ __volatile__ ("mtfprwa %x0,%1" : "=d" (vec_out) : "r" (r14));
- };
- 
- static test_t tests_move_ops_spe[] = {
diff --git a/SOURCES/valgrind-3.13.0-ppc64-timebase.patch b/SOURCES/valgrind-3.13.0-ppc64-timebase.patch
deleted file mode 100644
index d862b81..0000000
--- a/SOURCES/valgrind-3.13.0-ppc64-timebase.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-commit 6a55b1e82ccda3f0d663d2cc89eb543ae2d096bf
-Author: Carl Love <carll@us.ibm.com>
-Date:   Tue Oct 31 13:45:28 2017 -0500
-
-    Fix access to time base register to return 64-bits.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index f63146e7e..4ec37f5f9 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -9419,26 +9419,60 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
-          putIReg( rD_addr, getGST( PPC_GST_SPRG3_RO ) );
-          break;
- 
--      /* Even a lowly PPC7400 can run the associated helper, so no
--         obvious need for feature testing at this point. */
--      case 268 /* 0x10C */:
--      case 269 /* 0x10D */: {
--         UInt     arg  = SPR==268 ? 0 : 1;
--         IRTemp   val  = newTemp(Ity_I32);
--         IRExpr** args = mkIRExprVec_1( mkU32(arg) );
-+      case 268 /* 0x10C  TB  - 64 bit time base register */:
-+      {
-+         IRTemp   val  = newTemp(Ity_I64);
-+         IRExpr** args = mkIRExprVec_0();
-          IRDirty* d    = unsafeIRDirty_1_N(
--                            val,
--                            0/*regparms*/,
--                            "ppc32g_dirtyhelper_MFSPR_268_269",
--                            fnptr_to_fnentry
--                               (vbi, &ppc32g_dirtyhelper_MFSPR_268_269),
--                            args
--                         );
-+                                           val,
-+                                           0/*regparms*/,
-+                                           "ppcg_dirtyhelper_MFTB",
-+                                           fnptr_to_fnentry(vbi,
-+                                                            &ppcg_dirtyhelper_MFTB),
-+                                           args );
-+         /* execute the dirty call, dumping the result in val. */
-+         stmt( IRStmt_Dirty(d) );
-+         putIReg( rD_addr, (mode64) ? mkexpr(val) :
-+                                      unop(Iop_64to32, mkexpr(val)) );
-+
-+         break;
-+      }
-+      case 269 /* 0x10D  TBU - upper 32-bits of time base register */:
-+      {
-+         DIP("mfspr r%u,%u", rD_addr, SPR);
-+         IRTemp   val  = newTemp(Ity_I64);
-+         IRExpr** args = mkIRExprVec_0();
-+         IRDirty* d    = unsafeIRDirty_1_N(
-+                                           val,
-+                                           0/*regparms*/,
-+                                           "ppcg_dirtyhelper_MFTB",
-+                                           fnptr_to_fnentry(vbi,
-+                                                            &ppcg_dirtyhelper_MFTB),
-+                                           args );
-          /* execute the dirty call, dumping the result in val. */
-          stmt( IRStmt_Dirty(d) );
-          putIReg( rD_addr,
--                  mkWidenFrom32(ty, mkexpr(val), False/*unsigned*/) );
-+                  mkWidenFrom32(ty, unop(Iop_64HIto32, mkexpr(val)),
-+                                /* Signed */False) );
-+         break;
-+      }
-+      case 284 /* 0x1  TBL - lower 32-bits of time base register */:
-+      {
-          DIP("mfspr r%u,%u", rD_addr, SPR);
-+         IRTemp   val  = newTemp(Ity_I64);
-+         IRExpr** args = mkIRExprVec_0();
-+         IRDirty* d    = unsafeIRDirty_1_N(
-+                                           val,
-+                                           0/*regparms*/,
-+                                           "ppcg_dirtyhelper_MFTB",
-+                                           fnptr_to_fnentry(vbi,
-+                                                            &ppcg_dirtyhelper_MFTB),
-+                                           args );
-+         /* execute the dirty call, dumping the result in val. */
-+         stmt( IRStmt_Dirty(d) );
-+         putIReg( rD_addr,
-+                  mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(val)),
-+                                /* Signed */False) );
-          break;
-       }
- 
-@@ -9493,6 +9527,12 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
-          putIReg( rD_addr, (mode64) ? mkexpr(val) :
-                                       unop(Iop_64to32, mkexpr(val)) );
-          break;
-+      case 284:
-+         DIP("mftbl r%u", rD_addr);
-+         putIReg( rD_addr,
-+                  mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(val)),
-+                                /* Signed */False) );
-+         break;
-       default:
-          return False; /* illegal instruction */
-       }
diff --git a/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch b/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch
deleted file mode 100644
index bc41de6..0000000
--- a/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch
+++ /dev/null
@@ -1,5703 +0,0 @@
-commit 7fce2c5269f82a7d063c87335a25de84fc9acc64
-Author: Carl Love <carll@us.ibm.com>
-Date:   Tue Oct 3 12:03:22 2017 -0500
-
-    PPC64, Add support for the Data Stream Control Register (DSCR)
-
-diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
-index 8230d65..34adf62 100644
---- a/VEX/priv/guest_ppc_helpers.c
-+++ b/VEX/priv/guest_ppc_helpers.c
-@@ -921,6 +921,7 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
-    vex_state->guest_TEXASR = 0;
-    vex_state->guest_PPR = 0x4ULL << 50;  // medium priority
-    vex_state->guest_PSPB = 0x100;  // an arbitrary non-zero value to start with
-+   vex_state->guest_DSCR = 0;
- }
- 
- 
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index a8d4926..2467f70 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -296,6 +296,7 @@ static Bool OV32_CA32_supported = False;
- #define OFFB_TFIAR       offsetofPPCGuestState(guest_TFIAR)
- #define OFFB_PPR         offsetofPPCGuestState(guest_PPR)
- #define OFFB_PSPB        offsetofPPCGuestState(guest_PSPB)
-+#define OFFB_DSCR        offsetofPPCGuestState(guest_DSCR)
- 
- 
- /*------------------------------------------------------------*/
-@@ -459,6 +460,7 @@ typedef enum {
-                       * automatically decrement. Could be added later if
-                       * needed.
-                       */
-+    PPC_GST_DSCR,     // Data Stream Control Register
-     PPC_GST_MAX
- } PPC_GST;
- 
-@@ -3068,6 +3070,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
-    case PPC_GST_PSPB:
-       return IRExpr_Get( OFFB_PSPB, ty );
- 
-+   case PPC_GST_DSCR:
-+      return IRExpr_Get( OFFB_DSCR, ty );
-+
-    default:
-       vex_printf("getGST(ppc): reg = %u", reg);
-       vpanic("getGST(ppc)");
-@@ -3344,6 +3349,11 @@ static void putGST ( PPC_GST reg, IRExpr* src )
-                                           mkU64( 0x1C000000000000) ) ) );
-       break;
-       }
-+   case PPC_GST_DSCR:
-+      vassert( ty_src == Ity_I64 );
-+      stmt( IRStmt_Put( OFFB_DSCR, src ) );
-+      break;
-+
-    default:
-       vex_printf("putGST(ppc): reg = %u", reg);
-       vpanic("putGST(ppc)");
-@@ -9407,6 +9417,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
-          putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ),
-                                          /* Signed */False) );
-          break;
-+      case 0x3:  // 131
-+         DIP("mfspr r%u (DSCR)\n", rD_addr);
-+         putIReg( rD_addr, getGST( PPC_GST_DSCR) );
-+         break;
-       case 0x8:
-          DIP("mflr r%u\n", rD_addr);
-          putIReg( rD_addr, getGST( PPC_GST_LR ) ); 
-@@ -9575,6 +9589,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
-          DIP("mtxer r%u\n", rS_addr);
-          putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) );
-          break;
-+      case 0x3:
-+         DIP("mtspr r%u (DSCR)\n", rS_addr);
-+         putGST( PPC_GST_DSCR, mkexpr(rS) );
-+         break;
-       case 0x8:
-          DIP("mtlr r%u\n", rS_addr);
-          putGST( PPC_GST_LR, mkexpr(rS) ); 
-diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
-index 816ef5a..bb48ac5 100644
---- a/VEX/pub/libvex_guest_ppc32.h
-+++ b/VEX/pub/libvex_guest_ppc32.h
-@@ -252,8 +252,8 @@ typedef
-       /* 1388 */ ULong guest_PPR;       // Program Priority register
-       /* 1396 */ UInt  guest_TEXASRU;   // Transaction EXception And Summary Register Upper
-       /* 1400 */ UInt  guest_PSPB;      // Problem State Priority Boost register
-+      /* 1404 */ ULong guest_DSCR;      // Data Stream Control register
-       /* Padding to make it have an 16-aligned size */
--      /* 1404 */ UInt  padding2;
-       /* 1408 */ UInt  padding3;
-       /* 1412 */ UInt  padding4;
-    }
-diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
-index 02c4020..8c01fa6 100644
---- a/VEX/pub/libvex_guest_ppc64.h
-+++ b/VEX/pub/libvex_guest_ppc64.h
-@@ -292,11 +292,12 @@ typedef
-       /* 1686 */ ULong guest_PPR;       // Program Priority register
-       /* 1694 */ UInt  guest_TEXASRU;   // Transaction EXception And Summary Register Upper
-       /* 1698 */ UInt  guest_PSPB;      // Problem State Priority Boost register
-+      /* 1702 */ ULong guest_DSCR;      // Data Stream Control register
- 
-       /* Padding to make it have an 16-aligned size */
--      /* 1698 */   UInt  padding1;
--   /* 1702    UInt  padding2; */
--   /* 1706    UInt  padding3; */
-+      /* 1710 */   UInt  padding1;
-+      /* 1714 */   UInt  padding2;
-+      /* 1718 */   UInt  padding3;
- 
-    }
-    VexGuestPPC64State;
-diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
-index 3ff7c44..1d57e0c 100644
---- a/memcheck/mc_machine.c
-+++ b/memcheck/mc_machine.c
-@@ -194,6 +194,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
-    if (o == GOF(TFIAR)     && sz == 8) return -1;
-    if (o == GOF(PPR)       && sz == 8) return -1;
-    if (o == GOF(PSPB)      && sz == 8) return -1;
-+   if (o == GOF(DSCR)      && sz == 8) return -1;
- 
-    // With ISA 2.06, the "Vector-Scalar Floating-point" category
-    // provides facilities to support vector and scalar binary floating-
-diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
-index a9a565b..892e503 100644
---- a/memcheck/mc_main.c
-+++ b/memcheck/mc_main.c
-@@ -4468,7 +4468,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid,
- static void mc_post_reg_write ( CorePart part, ThreadId tid, 
-                                 PtrdiffT offset, SizeT size)
- {
--#  define MAX_REG_WRITE_SIZE 1728
-+#  define MAX_REG_WRITE_SIZE 1744
-    UChar area[MAX_REG_WRITE_SIZE];
-    tl_assert(size <= MAX_REG_WRITE_SIZE);
-    VG_(memset)(area, V_BITS8_DEFINED, size);
-
-commit acdeb75d2a58f4f3910ddaf9b2bc2ec74378fa3a
-Author: Carl Love <carll@us.ibm.com>
-Date:   Tue Oct 3 12:08:09 2017 -0500
-
-    PPC64, Replace body of generate_store_FPRF with C helper function.
-    
-    The function calculates the floating point condition code values
-    and stores them into the floating point condition code register.
-    The function is used by a number of instructions. The calculation
-    generates a lot of Iops as it much check the operatds for NaN, SNaN,
-    zero, dnorm, norm and infinity. The large number of Iops exhausts
-    temporary memory.
-
-diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h
-index fe411f7..f3eb956 100644
---- a/VEX/priv/guest_ppc_defs.h
-+++ b/VEX/priv/guest_ppc_defs.h
-@@ -156,6 +156,7 @@ extern ULong convert_to_zoned_helper( ULong src_hi, ULong src_low,
- extern ULong convert_to_national_helper( ULong src, ULong return_upper );
- extern ULong convert_from_zoned_helper( ULong src_hi, ULong src_low );
- extern ULong convert_from_national_helper( ULong src_hi, ULong src_low );
-+extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src );
- 
- 
- /* --- DIRTY HELPERS --- */
-diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
-index 34adf62..bf2d071 100644
---- a/VEX/priv/guest_ppc_helpers.c
-+++ b/VEX/priv/guest_ppc_helpers.c
-@@ -216,6 +216,110 @@ IRExpr* guest_ppc64_spechelper ( const HChar* function_name,
- }
- 
- 
-+/* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */
-+#define I16_EXP_MASK       0x7C00
-+#define I16_FRACTION_MASK  0x03FF
-+#define I32_EXP_MASK       0x7F800000
-+#define I32_FRACTION_MASK  0x007FFFFF
-+#define I64_EXP_MASK       0x7FF0000000000000ULL
-+#define I64_FRACTION_MASK  0x000FFFFFFFFFFFFFULL
-+#define V128_EXP_MASK      0x7FFF000000000000ULL
-+#define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL  /* upper 64-bit fractional mask */
-+
-+ULong generate_C_FPCC_helper( ULong irType, ULong src_hi, ULong src )
-+{
-+   UInt NaN, inf, zero, norm, dnorm, pos;
-+   UInt bit0, bit1, bit2, bit3;
-+   UInt sign_bit = 0;
-+   ULong exp_mask = 0, exp_part = 0, frac_part = 0;
-+   ULong fpcc, c;
-+
-+   if ( irType == Ity_I16 ) {
-+      frac_part = I16_FRACTION_MASK & src;
-+      exp_mask = I16_EXP_MASK;
-+      exp_part = exp_mask & src;
-+      sign_bit = src >> 15;
-+
-+   } else if ( irType == Ity_I32 ) {
-+      frac_part = I32_FRACTION_MASK & src;
-+      exp_mask = I32_EXP_MASK;
-+      exp_part = exp_mask & src;
-+      sign_bit = src >> 31;
-+
-+   } else  if ( irType == Ity_I64 ) {
-+     frac_part = I64_FRACTION_MASK & src;
-+     exp_mask = I64_EXP_MASK;
-+     exp_part = exp_mask & src;
-+     sign_bit = src >> 63;
-+
-+   } else  if ( irType == Ity_F128 ) {
-+     /* only care if the frac part is zero or non-zero */
-+     frac_part = (V128_FRACTION_MASK & src_hi) | src;
-+     exp_mask = V128_EXP_MASK;
-+     exp_part = exp_mask & src_hi;
-+     sign_bit = src_hi >> 63;
-+   } else {
-+     vassert(0);  // Unknown value of irType
-+   }
-+
-+   /* NaN: exponene is all ones, fractional part not zero */
-+   if ((exp_part == exp_mask) && (frac_part != 0))
-+     NaN = 1;
-+   else
-+     NaN = 0;
-+
-+   /* inf: exponent all 1's, fraction part is zero */
-+   if ((exp_part == exp_mask) && (frac_part == 0))
-+     inf = 1;
-+   else
-+     inf = 0;
-+
-+   /* zero: exponent is 0, fraction part is zero */
-+   if ((exp_part == 0) && (frac_part == 0))
-+     zero = 1;
-+   else
-+     zero = 0;
-+
-+   /* norm: exponent is not 0, exponent is not all 1's */
-+   if ((exp_part != 0) && (exp_part != exp_mask))
-+     norm = 1;
-+   else
-+     norm = 0;
-+
-+   /* dnorm: exponent is all 0's, fraction is not 0 */
-+   if ((exp_part == 0) && (frac_part != 0))
-+     dnorm = 1;
-+   else
-+     dnorm = 0;
-+
-+   /* pos: MSB is 1 */
-+   if (sign_bit == 0)
-+     pos = 1;
-+   else
-+     pos = 0;
-+
-+   /* calculate FPCC */
-+   /* If the result is NaN then must force bits 1, 2 and 3 to zero
-+    * to get correct result.
-+    */
-+   bit0 = NaN | inf;
-+
-+   bit1 = (!NaN) & zero;
-+   bit2 =  (!NaN) & ((pos & dnorm) | (pos & norm) | (pos & inf))
-+      & ((!zero) & (!NaN));
-+   bit3 =  (!NaN) & (((!pos) & dnorm) |((!pos) & norm) | ((!pos) & inf))
-+      & ((!zero) & (!NaN));
-+
-+   fpcc = (bit3 << 3) | (bit2 << 2) | (bit1 << 1) | bit0;
-+
-+   /* calculate C */
-+   c = NaN | ((!pos) & dnorm) | ((!pos) & zero) | (pos & dnorm);
-+
-+   /* return C in the upper 32-bits and FPCC in the lower 32 bits */
-+   return (c <<32) | fpcc;
-+}
-+
-+
- /*---------------------------------------------------------------*/
- /*--- Misc BCD clean helpers.                                 ---*/
- /*---------------------------------------------------------------*/
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 2467f70..0dae368 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -3860,7 +3860,7 @@ static IRExpr * is_Denorm( IRType size, IRTemp src )
- 
-    setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
- 
--   /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
-+   /* check exponent is all zeros */
-    zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
- 
-    /* check fractional part is not zero */
-@@ -3871,8 +3871,11 @@ static IRExpr * is_Denorm( IRType size, IRTemp src )
-    return  mkAND1( zero_exp, not_zero_frac );
- }
- 
-+#if 0
- /* Normalized number has exponent between 1 and max_exp -1, or in other words
-    the exponent is not zero and not equal to the max exponent value. */
-+ Currently not needed since generate_C_FPCC is now done with a C helper.
-+ Keep it around, might be useful in the future.
- static IRExpr * is_Norm( IRType size, IRTemp src )
- {
-    IRExpr *not_zero_exp, *not_max_exp;
-@@ -3919,72 +3922,18 @@ static IRExpr * is_Norm( IRType size, IRTemp src )
- 
-    return  mkAND1( not_zero_exp, not_max_exp );
- }
-+#endif
- 
--
--static IRExpr * create_FPCC( IRTemp NaN,   IRTemp inf,
--                             IRTemp zero,  IRTemp norm,
--                             IRTemp dnorm, IRTemp pos,
--                             IRTemp neg ) {
--   IRExpr *bit0, *bit1, *bit2, *bit3;
--
--   /* If the result is NaN then must force bits 1, 2 and 3 to zero
--    * to get correct result.
--    */
--   bit0 = unop( Iop_1Uto32, mkOR1( mkexpr( NaN ), mkexpr( inf ) ) );
--   bit1 = unop( Iop_1Uto32, mkAND1( mkNOT1( mkexpr( NaN ) ), mkexpr( zero ) ) );
--   bit2 = unop( Iop_1Uto32,
--                mkAND1( mkNOT1( mkexpr( NaN ) ),
--                        mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( pos ),
--                                                      mkexpr( dnorm ) ),
--                                              mkAND1( mkexpr( pos ),
--                                                      mkexpr( norm ) ) ),
--                                       mkAND1( mkexpr( pos ),
--                                               mkexpr( inf ) ) ),
--                                mkAND1( mkNOT1 ( mkexpr( zero ) ),
--                                        mkNOT1( mkexpr( NaN ) ) ) ) ) );
--   bit3 = unop( Iop_1Uto32,
--                mkAND1( mkNOT1( mkexpr( NaN ) ),
--                        mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( neg ),
--                                                      mkexpr( dnorm ) ),
--                                              mkAND1( mkexpr( neg ),
--                                                      mkexpr( norm ) ) ),
--                                       mkAND1( mkexpr( neg ),
--                                               mkexpr( inf ) ) ),
--                                mkAND1( mkNOT1 ( mkexpr( zero ) ),
--                                        mkNOT1( mkexpr( NaN ) ) ) ) ) );
--
--   return binop( Iop_Or32,
--                 binop( Iop_Or32,
--                        bit0,
--                        binop( Iop_Shl32, bit1, mkU8( 1 ) ) ),
--                 binop( Iop_Or32,
--                        binop( Iop_Shl32, bit2, mkU8( 2 ) ),
--                        binop( Iop_Shl32, bit3, mkU8( 3 ) ) ) );
--}
--
--static IRExpr * create_C( IRTemp NaN,   IRTemp zero,
--                          IRTemp dnorm, IRTemp pos,
--                          IRTemp neg )
--{
--
--   return unop( Iop_1Uto32,
--                mkOR1( mkOR1( mkexpr( NaN ),
--                              mkAND1( mkexpr( neg ), mkexpr( dnorm ) ) ),
--                       mkOR1( mkAND1( mkexpr( neg ), mkexpr( zero ) ),
--                              mkAND1( mkexpr( pos ), mkexpr( dnorm ) ) ) ) );
--}
--
--static void generate_store_FPRF( IRType size, IRTemp src )
-+static void generate_store_FPRF( IRType size, IRTemp src,
-+				 const VexAbiInfo* vbi )
- {
--   IRExpr *FPCC, *C;
--   IRTemp NaN = newTemp( Ity_I1 ), inf = newTemp( Ity_I1 );
--   IRTemp dnorm = newTemp( Ity_I1 ), norm = newTemp( Ity_I1 );
--   IRTemp pos = newTemp( Ity_I1 ),  neg = newTemp( Ity_I1 );
--   IRTemp zero = newTemp( Ity_I1 );
- 
--   IRTemp sign_bit = newTemp( Ity_I1 );
--   IRTemp value;
-+  /* This function was originally written using IR code.  It has been
-+   * replaced with a clean helper due to the large amount of IR code
-+   * needed by this function.
-+   */
- 
-+   IRTemp tmp = newTemp( Ity_I64 );
-    vassert( ( size == Ity_I16 ) || ( size == Ity_I32 )
-             || ( size == Ity_I64 ) || ( size == Ity_F128 ) );
- 
-@@ -3993,82 +3942,45 @@ static void generate_store_FPRF( IRType size, IRTemp src )
-             || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_F128 ) );
- 
-    if( size == Ity_I16 ) {
--      /* The 16-bit floating point value is in the lower 16-bits of
--         the 32-bit input value */
--      value = newTemp( Ity_I32 );
--      assign( value, mkexpr( src ) );
--      assign( sign_bit,
--              unop ( Iop_32to1,
--                     binop( Iop_And32,
--                            binop( Iop_Shr32, mkexpr( value ), mkU8( 15 ) ),
--                            mkU32( 0x1 ) ) ) );
--
-+      assign( tmp,
-+              mkIRExprCCall( Ity_I64, 0 /*regparms*/,
-+                             "generate_store_C_FPCC_helper",
-+                             fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
-+                             mkIRExprVec_3( mkU64( size ), mkU64( 0 ),
-+                                            mkexpr( src ) ) ) );
-    } else if( size == Ity_I32 ) {
--      value = newTemp( size );
--      assign( value, mkexpr( src ) );
--      assign( sign_bit,
--              unop ( Iop_32to1,
--                     binop( Iop_And32,
--                            binop( Iop_Shr32, mkexpr( value ), mkU8( 31 ) ),
--                            mkU32( 0x1 ) ) ) );
--
-+      assign( tmp,
-+              mkIRExprCCall( Ity_I64, 0 /*regparms*/,
-+                             "generate_store_C_FPCC_helper",
-+                             fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
-+                             mkIRExprVec_3( mkU64( size ), mkU64( 0 ),
-+                                            mkexpr( src ) ) ) );
-    } else if( size == Ity_I64 ) {
--      value = newTemp( size );
--      assign( value, mkexpr( src ) );
--      assign( sign_bit,
--              unop ( Iop_64to1,
--                     binop( Iop_And64,
--                            binop( Iop_Shr64, mkexpr( value ), mkU8( 63 ) ),
--                            mkU64( 0x1 ) ) ) );
--
--   } else {
--   /* Move the F128 bit pattern to an integer V128 bit pattern */
--      value = newTemp( Ity_V128 );
--      assign( value,
--              binop( Iop_64HLtoV128,
--                     unop( Iop_ReinterpF64asI64,
--                           unop( Iop_F128HItoF64, mkexpr( src ) ) ),
--                     unop( Iop_ReinterpF64asI64,
--                           unop( Iop_F128LOtoF64, mkexpr( src ) ) ) ) );
--
--      size = Ity_V128;
--      assign( sign_bit,
--              unop ( Iop_64to1,
--                     binop( Iop_And64,
--                            binop( Iop_Shr64,
--                                   unop( Iop_V128HIto64, mkexpr( value ) ),
--                                   mkU8( 63 ) ),
--                            mkU64( 0x1 ) ) ) );
-+      assign( tmp,
-+              mkIRExprCCall( Ity_I64, 0 /*regparms*/,
-+                             "generate_store_C_FPCC_helper",
-+                             fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
-+                             mkIRExprVec_3( mkU64( size ), mkU64( 0 ),
-+                                            mkexpr( src ) ) ) );
-+   } else if( size == Ity_F128 ) {
-+      assign( tmp,
-+              mkIRExprCCall( Ity_I64, 0 /*regparms*/,
-+                             "generate_store_C_FPCC_helper",
-+                             fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
-+                             mkIRExprVec_3( mkU64( size ),
-+                                            unop( Iop_ReinterpF64asI64,
-+                                                  unop( Iop_F128HItoF64,
-+                                                        mkexpr( src ) ) ),
-+                                            unop( Iop_ReinterpF64asI64,
-+                                                  unop( Iop_F128LOtoF64,
-+                                                        mkexpr( src ) ) ) ) ) );
-    }
- 
--   /* Calculate the floating point result field FPRF */
--   assign( NaN, is_NaN( size, value ) );
--   assign( inf, is_Inf( size, value ) );
--   assign( zero, is_Zero( size, value ) );
--   assign( norm, is_Norm( size, value ) );
--   assign( dnorm, is_Denorm( size, value ) );
--   assign( pos, mkAND1( mkNOT1( mkexpr( sign_bit ) ), mkU1( 1 ) ) );
--   assign( neg, mkAND1( mkexpr( sign_bit ), mkU1( 1 ) ) );
--
--   /* create the FPRF bit field
--    *
--    *   FPRF field[4:0]   type of value
--    *      10001           QNaN
--    *      01001           - infininity
--    *      01000           - Normalized
--    *      11000           - Denormalized
--    *      10010           - zero
--    *      00010           + zero
--    *      10100           + Denormalized
--    *      00100           + Normalized
--    *      00101           + infinity
-+   /* C is in the upper 32-bits, FPCC is in the lower 32-bits of the
-+    * value returned by the helper function
-     */
--   FPCC = create_FPCC( NaN, inf, zero, norm, dnorm, pos, neg );
--   C = create_C( NaN, zero, dnorm, pos, neg );
--
--   /* Write the C and FPCC fields of the FPRF field */
--   putC( C );
--   putFPCC( FPCC );
-+   putC( unop(  Iop_64HIto32, mkexpr( tmp) ) );
-+   putFPCC( unop(  Iop_64to32, mkexpr( tmp) ) );
- }
- 
- /* This function takes an Ity_I32 input argument interpreted
-@@ -18538,7 +18450,8 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 )
-  * Miscellaneous VSX Scalar Instructions
-  */
- static Bool
--dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 )
-+dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
-+              int allow_isa_3_0 )
- {
- #define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL
-    /* XX3-Form and XX2-Form */
-@@ -18783,7 +18696,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 )
-             putVSReg( XT, mkexpr( result ) );
- 
-             assign( value, unop( Iop_V128HIto64, mkexpr( result ) ) );
--            generate_store_FPRF( Ity_I64, value );
-+            generate_store_FPRF( Ity_I64, value, vbi );
-             return True;
- 
-          } else if (inst_select == 17) {   // xscvdphp
-@@ -18798,7 +18711,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 )
-             assign( value, unop( Iop_64to32, unop( Iop_V128HIto64,
-                                                    mkexpr( result ) ) ) );
-             putVSReg( XT, mkexpr( result ) );
--            generate_store_FPRF( Ity_I16, value );
-+            generate_store_FPRF( Ity_I16, value, vbi );
-             return True;
- 
-          } else {
-@@ -21475,7 +21388,7 @@ dis_vx_store ( UInt theInstr )
- }
- 
- static Bool
--dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
-+dis_vx_Scalar_Round_to_quad_integer( UInt theInstr, const VexAbiInfo* vbi )
- {
-    /* The ISA 3.0 instructions supported in this function require
-     * the underlying hardware platform that supports the ISA3.0
-@@ -21514,7 +21427,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
-             DIP("xsrqpix %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC);
-             assign( vT, binop( Iop_F128toI128S, rm, mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-       }   /* case 0x005 */
-       break;
-    case 0x025:     // xsrqpxp  VSX Scalar Round Quad-Precision to
-@@ -21530,7 +21443,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
- 
-         DIP("xsrqpxp %d,v%d,v%d,%d\n",  R, vT_addr, vB_addr, RMC);
-          assign( vT, binop( Iop_RndF128, rm, mkexpr( vB ) ) );
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-       }   /* case 0x025 */
-      break;
-    default:
-@@ -21542,7 +21455,8 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
- }
- 
- static Bool
--dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-+dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr,
-+                                                 const VexAbiInfo* vbi )
- {
-    /* The ISA 3.0 instructions supported in this function require
-     * the underlying hardware platform that supports the ISA 3.0
-@@ -21582,7 +21496,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-             assign( vT, triop( Iop_AddF128, set_round_to_Oddmode(),
-                                mkexpr( vA ), mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-          break;
-       }
-    case 0x024:     // xsmulqp (VSX Scalar Multiply Quad-Precision[using round to Odd])
-@@ -21600,7 +21514,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-             assign( vT, triop( Iop_MulF128, set_round_to_Oddmode(), mkexpr( vA ),
-                                mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-          break;
-       }
-    case 0x184:   // xsmaddqp (VSX Scalar Multiply add Quad-Precision[using round to Odd])
-@@ -21625,7 +21539,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                qop( Iop_MAddF128, set_round_to_Oddmode(), mkexpr( vA ),
-                     mkexpr( vC ), mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-          break;
-       }
-    case 0x1A4:   // xsmsubqp (VSX Scalar Multiply Subtract Quad-Precision[using round to Odd])
-@@ -21649,7 +21563,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                     qop( Iop_MSubF128, set_round_to_Oddmode(),
-                          mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-          break;
-       }
-    case 0x1C4:   // xsnmaddqp (VSX Scalar Negative Multiply Add Quad-Precision[using round to Odd])
-@@ -21673,7 +21587,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                     qop( Iop_NegMAddF128, set_round_to_Oddmode(),
-                          mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-         break;
-       }
-    case 0x1E4:   // xsmsubqp (VSX Scalar Negatve Multiply Subtract Quad-Precision[using round to Odd])
-@@ -21697,7 +21611,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                     qop( Iop_NegMSubF128, set_round_to_Oddmode(),
-                          mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-          break;
-       }
-    case 0x204:     // xssubqp (VSX Scalar Subtract Quad-Precision[using round to Odd])
-@@ -21714,7 +21628,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-             assign( vT, triop( Iop_SubF128, set_round_to_Oddmode(), mkexpr( vA ),
-                                mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-         break;
-       }
-    case 0x224:     // xsdivqp (VSX Scalar Divide Quad-Precision[using round to Odd])
-@@ -21731,7 +21645,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-             assign( vT, triop( Iop_DivF128, set_round_to_Oddmode(), mkexpr( vA ),
-                                mkexpr( vB ) ) );
-          }
--         generate_store_FPRF( Ity_F128, vT );
-+         generate_store_FPRF( Ity_F128, vT, vbi );
-          break;
-       }
-    case 0x324:  // xssqrtqp (VSX Scalar Square root Quad-Precision[using round to Odd])
-@@ -21752,7 +21666,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                   assign( vT, binop( Iop_SqrtF128, set_round_to_Oddmode(),
-                                      mkexpr( vB ) ) );
-                }
--               generate_store_FPRF( Ity_F128, vT );
-+               generate_store_FPRF( Ity_F128, vT, vbi );
-                break;
-             }   /* end case 27 */
-          default:
-@@ -21783,7 +21697,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                assign( tmp, unop( Iop_ReinterpF64asI64,
-                                   unop( Iop_F128HItoF64, mkexpr( vB ) ) ) );
-                assign( vT, unop( Iop_I64UtoF128, mkexpr( tmp ) ) );
--               generate_store_FPRF( Ity_F128, vT );
-+               generate_store_FPRF( Ity_F128, vT, vbi );
-                break;
-             }
-          case 9:    // xsvqpswz  VSX Scalar Truncate & Convert Quad-Precision
-@@ -21803,7 +21717,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                assign( tmp, unop( Iop_ReinterpF64asI64,
-                                   unop( Iop_F128HItoF64, mkexpr( vB ) ) ) );
-                assign( vT, unop( Iop_I64StoF128, mkexpr( tmp ) ) );
--               generate_store_FPRF( Ity_F128, vT );
-+               generate_store_FPRF( Ity_F128, vT, vbi );
-                break;
-             }
-         case 17:    // xsvqpudz  VSX Scalar Truncate & Convert Quad-Precision
-@@ -21855,7 +21769,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                assign( tmp, unop( Iop_ReinterpF64asI64,
-                                   unop( Iop_F128HItoF64, mkexpr( vT ) ) ) );
- 
--               generate_store_FPRF( Ity_I64, tmp );
-+               generate_store_FPRF( Ity_I64, tmp, vbi );
-                break;
-             }
-          case 22:    // xscvdpqp VSX Scalar Convert from Double-Precision
-@@ -21866,7 +21780,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
-                assign( vT, unop( Iop_F64toF128,
-                                  unop( Iop_F128HItoF64, mkexpr( vB ) ) ) );
- 
--               generate_store_FPRF( Ity_F128, vT );
-+               generate_store_FPRF( Ity_F128, vT, vbi );
-                break;
-             }
-          case 25:    // xsvqpsdz  VSX Scalar Truncate & Convert Quad-Precision
-@@ -28199,13 +28113,13 @@ DisResult disInstr_PPC_WRK (
-       UInt vsxOpc2;
- 
-       if (( opc2hi == 13 ) && ( opc2lo == 5)) { //xvtstdcsp
--         if (dis_vxs_misc(theInstr, 0x354, allow_isa_3_0))
-+         if (dis_vxs_misc(theInstr, abiinfo, 0x354, allow_isa_3_0))
-             goto decode_success;
-          goto decode_failure;
-       }
- 
-       if (( opc2hi == 15 ) && ( opc2lo == 5)) { //xvtstdcdp
--         if (dis_vxs_misc(theInstr, 0x3D4, allow_isa_3_0))
-+         if (dis_vxs_misc(theInstr, abiinfo, 0x3D4, allow_isa_3_0))
-                goto decode_success;
-             goto decode_failure;
-       }
-@@ -28221,7 +28135,7 @@ DisResult disInstr_PPC_WRK (
-          /* This is a special case of the XX1 form where the  RA, RB
-           * fields hold an immediate value.
-           */
--         if (dis_vxs_misc(theInstr, opc2, allow_isa_3_0)) goto decode_success;
-+      if (dis_vxs_misc(theInstr, abiinfo, opc2, allow_isa_3_0)) goto decode_success;
-          goto decode_failure;
-       }
- 
-@@ -28231,7 +28145,8 @@ DisResult disInstr_PPC_WRK (
-          case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw
-          case 0x068: case 0xE8:  // xxperm, xxpermr
-          case 0x018: case 0x148: // xxsel, xxspltw
--            if (dis_vx_permute_misc(theInstr, vsxOpc2)) goto decode_success;
-+            if (dis_vx_permute_misc(theInstr, vsxOpc2 ))
-+	       goto decode_success;
-             goto decode_failure;
-          case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor,
-          case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc
-@@ -28255,7 +28170,7 @@ DisResult disInstr_PPC_WRK (
-          case 0x354:             // xvtstdcsp
-          case 0x360:case 0x396:  // xviexpsp, xsiexpdp
-          case 0x3D4: case 0x3E0: // xvtstdcdp, xviexpdp
--            if (dis_vxs_misc(theInstr, vsxOpc2, allow_isa_3_0))
-+            if (dis_vxs_misc(theInstr, abiinfo, vsxOpc2, allow_isa_3_0))
-                goto decode_success;
-             goto decode_failure;
-          case 0x08C: case 0x0AC: // xscmpudp, xscmpodp
-@@ -28409,7 +28324,7 @@ DisResult disInstr_PPC_WRK (
-       case 0x5: // xsrqpi, xsrqpix
-       case 0x25: // xsrqpxp
-          if ( !mode64 || !allow_isa_3_0 ) goto decode_failure;
--         if ( dis_vx_Scalar_Round_to_quad_integer( theInstr ) )
-+         if ( dis_vx_Scalar_Round_to_quad_integer( theInstr, abiinfo ) )
-             goto decode_success;
-          goto decode_failure;
-       default:
-@@ -28531,7 +28446,8 @@ DisResult disInstr_PPC_WRK (
- 
-       case 0x324: // xsabsqp, xsxexpqp,xsnabsqp, xsnegqp, xsxsigqp
-          if ( inst_select == 27 ) {    // xssqrtqp
--            if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) )
-+            if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr,
-+								  abiinfo ) )
-                goto decode_success;
-          }
- 
-@@ -28566,7 +28482,8 @@ DisResult disInstr_PPC_WRK (
-       case 0x344: // xscvudqp, xscvsdqp, xscvqpdp, xscvqpdpo, xsvqpdp
-                   // xscvqpswz, xscvqpuwz, xscvqpudz, xscvqpsdz
-          if ( !mode64 || !allow_isa_3_0 ) goto decode_failure;
--         if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) )
-+         if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr,
-+							       abiinfo ) )
-             goto decode_success;
-          goto decode_failure;
- 
-
-commit a1d03d0d11c0b31a6d9f57baa4d46317fdd5f6ef
-Author: Carl Love <carll@us.ibm.com>
-Date:   Tue Oct 3 15:09:22 2017 -0500
-
-    PPC64, Use the vperm code to implement the xxperm inst.
-    
-    The current xxperm instruction implementation generates a huge
-    number of Iops to explicitly do the permutation.  The code
-    was changed to use the Iop_Perm8x16 which is much more efficient
-    so temporary memory doesn't get exhausted.
-    
-    Bugzilla 385208
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 0dae368..1373d1c 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -22319,15 +22319,17 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
-       case 0x68: // xxperm  (VSX Permute )
-       case 0xE8: // xxpermr (VSX Permute right-index )
-       {
--         int i;
--         IRTemp new_Vt[17];
--         IRTemp perm_val[16];
--         IRTemp perm_val_gt16[16];
--         IRTemp tmp_val[16];
--         IRTemp perm_idx[16];
--         IRTemp perm_mask = newTemp( Ity_V128 );
--         IRTemp val_mask  = newTemp( Ity_V128 );
--         int    dest_shift_amount = 0;
-+
-+         /* The xxperm  instruction performs the same operation as
-+            the vperm except the xxperm operates on the VSR register
-+            file. while vperm operates on the VR register file.
-+            Lets borrow some code here from vperm. The mapping of
-+            the source registers is also a little different.
-+         */
-+         IRTemp a_perm  = newTemp(Ity_V128);
-+         IRTemp b_perm  = newTemp(Ity_V128);
-+         IRTemp mask    = newTemp(Ity_V128);
-+         IRTemp perm_val = newTemp(Ity_V128);
- 
-          if ( opc2 == 0x68 ) {
-             DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
-@@ -22337,119 +22339,40 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
-             DIP("xxpermr v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
-          }
- 
--         new_Vt[0] = newTemp( Ity_V128 );
--
-          assign( vT, getVSReg( XT ) );
- 
--         assign( new_Vt[0], binop( Iop_64HLtoV128,
--                                   mkU64( 0x0 ), mkU64( 0x0 ) ) );
--         assign( perm_mask, binop( Iop_64HLtoV128,
--                                   mkU64( 0x0 ), mkU64( 0x1F ) ) );
--         assign( val_mask, binop( Iop_64HLtoV128,
--                                  mkU64( 0x0 ), mkU64( 0xFF ) ) );
--
--         /* For each permute index in XB, the permute list, select the byte
--          * from XA indexed by the permute index if the permute index is less
--          * then 16.  Copy the selected byte to the destination location in
--          * the result.
--          */
--         for ( i = 0; i < 16; i++ ) {
--            perm_val_gt16[i] = newTemp( Ity_V128 );
--            perm_val[i] = newTemp( Ity_V128 );
--            perm_idx[i] = newTemp( Ity_I8 );
--            tmp_val[i]  = newTemp( Ity_V128 );
--            new_Vt[i+1]  = newTemp( Ity_V128 );
--
--            /* create mask to extract the permute index value from vB,
--             * store value in least significant bits of perm_val
--             */
--            if ( opc2 == 0x68 )
--               /* xxperm, the perm value is the index value in XB */
--               assign( perm_val[i], binop( Iop_ShrV128,
--                                           binop( Iop_AndV128,
--                                                  mkexpr(vB),
--                                                  binop( Iop_ShlV128,
--                                                         mkexpr( perm_mask ),
--                                                         mkU8( (15 - i) * 8 ) ) ),
--                                           mkU8( (15 - i) * 8 ) ) );
-+         if ( opc2 == 0x68 ) // xxperm
-+            assign( perm_val,
-+                    binop( Iop_AndV128, mkexpr( vB ),
-+                           unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) );
- 
--            else
--               /* xxpermr, the perm value is 31 - index value in XB */
--               assign( perm_val[i],
--                       binop( Iop_Sub8x16,
--                              binop( Iop_64HLtoV128,
--                                     mkU64( 0 ), mkU64( 31 ) ),
--                              binop( Iop_ShrV128,
--                                     binop( Iop_AndV128,
--                                            mkexpr( vB ),
--                                            binop( Iop_ShlV128,
--                                                   mkexpr( perm_mask ),
--                                                   mkU8( ( 15 - i ) * 8 ) ) ),
--                                     mkU8( ( 15 - i ) * 8 ) ) ) );
--
--            /* Determine if the perm_val[] > 16.  If it is, then the value
--             * will come from xT otherwise it comes from xA.  Either way,
--             * create the mask to get the value from the source using the
--             * lower 3 bits of perm_val[].  Create a 128 bit mask from the
--             * upper bit of perm_val[] to be used to select from xT or xA.
--             */
--            assign( perm_val_gt16[i],
--                    binop(Iop_64HLtoV128,
--                          unop( Iop_1Sto64,
--                                unop( Iop_64to1,
--                                      unop( Iop_V128to64,
--                                            binop( Iop_ShrV128,
--                                                   mkexpr( perm_val[i] ),
--                                                   mkU8( 4 ) ) ) ) ),
--                          unop( Iop_1Sto64,
--                                unop( Iop_64to1,
--                                      unop( Iop_V128to64,
--                                            binop( Iop_ShrV128,
--                                                   mkexpr( perm_val[i] ),
--                                                   mkU8( 4 ) ) ) ) ) ) );
--
--            assign( perm_idx[i],
--                    unop(Iop_32to8,
--                         binop( Iop_Mul32,
--                                binop( Iop_Sub32,
--                                       mkU32( 15 ),
--                                       unop( Iop_64to32,
--                                             binop( Iop_And64,
--                                                  unop( Iop_V128to64,
--                                                       mkexpr( perm_val[i] ) ),
--                                                  mkU64( 0xF ) ) ) ),
--                                mkU32( 8 ) ) ) );
--
--            dest_shift_amount = ( 15 - i )*8;
--
--            /* Use perm_val_gt16 to select value from vA or vT */
--            assign( tmp_val[i],
--                    binop( Iop_ShlV128,
--                           binop( Iop_ShrV128,
--                                  binop( Iop_OrV128,
--                                         binop( Iop_AndV128,
--                                                mkexpr( vA ),
--                                                binop( Iop_AndV128,
--                                                       unop( Iop_NotV128,
--                                                             mkexpr( perm_val_gt16[i] ) ),
--                                                       binop( Iop_ShlV128,
--                                                              mkexpr( val_mask ),
--                                                              mkexpr( perm_idx[i] ) ) ) ),
--                                         binop( Iop_AndV128,
--                                                mkexpr( vT ),
--                                                binop( Iop_AndV128,
--                                                       mkexpr( perm_val_gt16[i] ),
--                                                       binop( Iop_ShlV128,
--                                                              mkexpr( val_mask ),
--                                                              mkexpr( perm_idx[i] ) ) ) ) ),
--                                  mkexpr( perm_idx[i] ) ),
--                           mkU8( dest_shift_amount ) ) );
--
--            assign( new_Vt[i+1], binop( Iop_OrV128,
--                                       mkexpr( tmp_val[i] ),
--                                       mkexpr( new_Vt[i] ) ) );
--         }
--         putVSReg( XT, mkexpr( new_Vt[16] ) );
-+         else                // xxpermr
-+            assign( perm_val,
-+                    binop( Iop_Sub16x8,
-+                           binop( Iop_64HLtoV128,
-+                                  mkU64( 0x1F1F1F1F1F1F1F1F ),
-+                                  mkU64( 0x1F1F1F1F1F1F1F1F ) ),
-+                           binop( Iop_AndV128, mkexpr( vB ),
-+                                  unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
-+
-+         /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
-+            IR specifies, and also to hide irrelevant bits from
-+            memcheck.
-+         */
-+         assign( a_perm,
-+                 binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) );
-+         assign( b_perm,
-+                 binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) );
-+         assign( mask, binop( Iop_SarN8x16,
-+                              binop( Iop_ShlN8x16, mkexpr( perm_val ),
-+                                     mkU8( 3 ) ),
-+                              mkU8( 7 ) ) );
-+         // dst = (a & ~mask) | (b & mask)
-+         putVSReg( XT, binop( Iop_OrV128,
-+                              binop( Iop_AndV128, mkexpr( a_perm ),
-+                                     unop( Iop_NotV128, mkexpr( mask ) ) ),
-+                              binop( Iop_AndV128, mkexpr( b_perm ),
-+                                     mkexpr( mask ) ) ) );
-          break;
-       }
- 
-
-commit b0aef250a74804423341b3ce804355037211e330
-Author: Carl Love <carll@us.ibm.com>
-Date:   Tue Oct 3 15:18:09 2017 -0500
-
-    PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16.
-    
-    The current implementation will generate a lot of Iops.  The number
-    of generated Iops can lead to Valgrind running out of temporary space.
-    See bugzilla https://bugs.kde.org/show_bug.cgi?id=385208 as an example
-    of the issue.  Using Iop_Perm8x16 reduces the number of Iops significantly.
-    
-    bugzilla 385210
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 1373d1c..1785959 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -24107,107 +24107,40 @@ static Bool dis_av_permute ( UInt theInstr )
-    }
- 
-    case 0x3B: {  // vpermr (Vector Permute Right-indexed)
--      int i;
--      IRTemp new_Vt[17];
--      IRTemp tmp[16];
--      IRTemp index[16];
--      IRTemp index_gt16[16];
--      IRTemp mask[16];
--
--      DIP("vpermr v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr);
--
--      new_Vt[0] = newTemp( Ity_V128 );
--      assign( new_Vt[0], binop( Iop_64HLtoV128,
--                                mkU64( 0x0 ),
--                                mkU64( 0x0 ) ) );
--
--      for ( i = 0; i < 16; i++ ) {
--         index_gt16[i] = newTemp( Ity_V128 );
--         mask[i]  = newTemp( Ity_V128 );
--         index[i] = newTemp( Ity_I32 );
--         tmp[i]   = newTemp( Ity_V128 );
--         new_Vt[i+1] = newTemp( Ity_V128 );
--
--         assign( index[i],
--                 binop( Iop_Sub32,
--                        mkU32( 31 ),
--                        unop( Iop_64to32,
--                              unop( Iop_V128to64,
--                                    binop( Iop_ShrV128,
--                                           binop( Iop_AndV128,
--                                                  binop( Iop_ShlV128,
--                                                         binop( Iop_64HLtoV128,
--                                                                mkU64( 0x0 ),
--                                                                mkU64( 0x3F ) ),
--                                                         mkU8(  (15 - i) * 8 ) ),
--                                                  mkexpr( vC ) ),
--                                           mkU8( (15 - i) * 8 ) ) ) ) ) );
--
--         /* Determine if index < 16, src byte is vA[index], otherwise
--          * vB[31-index]. Check if msb of index is 1 or not.
--          */
--         assign( index_gt16[i],
--                 binop( Iop_64HLtoV128,
--                        unop( Iop_1Sto64,
--                              unop( Iop_32to1,
--                                    binop( Iop_Shr32,
--                                           mkexpr( index[i] ),
--                                           mkU8( 4 ) ) ) ),
--                        unop( Iop_1Sto64,
--                              unop( Iop_32to1,
--                                    binop( Iop_Shr32,
--                                           mkexpr( index[i] ),
--                                           mkU8( 4 ) ) ) ) ) );
--         assign( mask[i],
--                 binop( Iop_ShlV128,
--                        binop( Iop_64HLtoV128,
--                               mkU64( 0x0 ),
--                               mkU64( 0xFF ) ),
--                        unop( Iop_32to8,
--                              binop( Iop_Mul32,
--                                     binop( Iop_Sub32,
--                                            mkU32( 15 ),
--                                            binop( Iop_And32,
--                                                   mkexpr( index[i] ),
--                                                   mkU32( 0xF ) ) ),
--                                     mkU32( 8 ) ) ) ) );
--
--         /* Extract the indexed byte from vA and vB using the lower 4-bits
--          * of the index. Then use the index_gt16 mask to select vA if the
--          * index < 16 or vB if index > 15.  Put the selected byte in the
--          * least significant byte.
--          */
--         assign( tmp[i],
--                 binop( Iop_ShrV128,
--                        binop( Iop_OrV128,
--                               binop( Iop_AndV128,
--                                      binop( Iop_AndV128,
--                                             mkexpr( mask[i] ),
--                                             mkexpr( vA ) ),
--                                      unop( Iop_NotV128,
--                                            mkexpr( index_gt16[i] ) ) ),
--                               binop( Iop_AndV128,
--                                      binop( Iop_AndV128,
--                                             mkexpr( mask[i] ),
--                                             mkexpr( vB ) ),
--                                      mkexpr( index_gt16[i] ) ) ),
--                        unop( Iop_32to8,
--                              binop( Iop_Mul32,
--                                     binop( Iop_Sub32,
--                                            mkU32( 15 ),
--                                            binop( Iop_And32,
--                                                   mkexpr( index[i] ),
--                                                   mkU32( 0xF ) ) ),
--                                     mkU32( 8 ) ) ) ) );
--
--         /* Move the selected byte to the position to store in the result */
--         assign( new_Vt[i+1], binop( Iop_OrV128,
--                                     binop( Iop_ShlV128,
--                                            mkexpr( tmp[i] ),
--                                            mkU8(  (15 - i) * 8 ) ),
--                                     mkexpr( new_Vt[i] ) ) );
--         }
--      putVReg( vD_addr, mkexpr( new_Vt[16] ) );
-+      /* limited to two args for IR, so have to play games... */
-+      IRTemp a_perm  = newTemp( Ity_V128 );
-+      IRTemp b_perm  = newTemp( Ity_V128 );
-+      IRTemp mask    = newTemp( Ity_V128 );
-+      IRTemp vC_andF = newTemp( Ity_V128 );
-+
-+      DIP( "vpermr v%d,v%d,v%d,v%d\n",
-+           vD_addr, vA_addr, vB_addr, vC_addr);
-+      /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
-+         IR specifies, and also to hide irrelevant bits from
-+         memcheck.
-+      */
-+
-+      assign( vC_andF,
-+              binop( Iop_Sub16x8,
-+                     binop( Iop_64HLtoV128,
-+                            mkU64( 0x1F1F1F1F1F1F1F1F ),
-+                            mkU64( 0x1F1F1F1F1F1F1F1F ) ),
-+                     binop( Iop_AndV128, mkexpr( vC ),
-+                            unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
-+      assign( a_perm,
-+              binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) );
-+      assign( b_perm,
-+              binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) );
-+      // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0
-+      assign( mask, binop(Iop_SarN8x16,
-+                          binop( Iop_ShlN8x16, mkexpr( vC_andF ),
-+                                 mkU8( 3 ) ), mkU8( 7 ) ) );
-+      // dst = (a & ~mask) | (b & mask)
-+      putVReg( vD_addr, binop( Iop_OrV128,
-+                              binop( Iop_AndV128, mkexpr( a_perm ),
-+                                    unop( Iop_NotV128, mkexpr( mask ) ) ),
-+                              binop( Iop_AndV128, mkexpr( b_perm ),
-+                                    mkexpr( mask ) ) ) );
-       return True;
-    }
- 
-
-commit f0c4da68ca9e8c99f55965d8e074273a33ab916d
-Author: Carl Love <cel@us.ibm.com>
-Date:   Tue Oct 3 10:49:48 2017 -0500
-
-    PPC64, Fix bug in vperm instruction.
-    
-    The ISA says:
-    
-    Let the source vector be the concatenation of the
-    contents of VR[VRA] followed by the contents of
-    VR[VRB].
-    
-    For each integer value i from 0 to 15, do the following.
-      Let index be the value specified by bits 3:7 of byte
-      element i of VR[VRC].
-    
-    So, the index value is 5-bits wide ([3:7]), not 4-bits wide.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 1785959..97664c2 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -24047,12 +24047,12 @@ static Bool dis_av_permute ( UInt theInstr )
-       IRTemp vC_andF = newTemp(Ity_V128);
-       DIP("vperm v%d,v%d,v%d,v%d\n",
-           vD_addr, vA_addr, vB_addr, vC_addr);
--      /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
-+      /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
-          IR specifies, and also to hide irrelevant bits from
-          memcheck */
-       assign( vC_andF,
-               binop(Iop_AndV128, mkexpr(vC),
--                                 unop(Iop_Dup8x16, mkU8(0xF))) );
-+                                 unop(Iop_Dup8x16, mkU8(0x1F))) );
-       assign( a_perm,
-               binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) );
-       assign( b_perm,
-
-commit 5398a9f9cb9db6805df03e43258e65fa799a7caa
-Author: Carl Love <carll@us.ibm.com>
-Date:   Wed Oct 4 10:24:36 2017 -0500
-
-    PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions.
-    
-    These are Power 9 instructions.
-    
-    Add test cases for the new instructions to test_isa_3_0.c
-    
-    Bugzilla 385183.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 97664c2..6b2157d 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -3629,18 +3629,22 @@ static IRExpr * fp_exp_part( IRType size, IRTemp src )
- /* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */
- #define I16_EXP_MASK       0x7C00
- #define I16_FRACTION_MASK  0x03FF
-+#define I16_MSB_FRACTION_MASK  0x0200
- #define I32_EXP_MASK       0x7F800000
- #define I32_FRACTION_MASK  0x007FFFFF
-+#define I32_MSB_FRACTION_MASK  0x00400000
- #define I64_EXP_MASK       0x7FF0000000000000ULL
- #define I64_FRACTION_MASK  0x000FFFFFFFFFFFFFULL
-+#define I64_MSB_FRACTION_MASK  0x0008000000000000ULL
- #define V128_EXP_MASK      0x7FFF000000000000ULL
- #define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL  /* upper 64-bit fractional mask */
-+#define V128_MSB_FRACTION_MASK 0x0000800000000000ULL  /* upper 64-bit fractional mask */
- 
- void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
--                             IRTemp *zero );
-+                             IRTemp *msb_frac_mask, IRTemp *zero );
- 
- void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
--                             IRTemp *zero ) {
-+                             IRTemp *msb_frac_mask, IRTemp *zero ) {
- 
-    vassert( ( size == Ity_I16 ) || ( size == Ity_I32 )
-             || ( size == Ity_I64 ) || ( size == Ity_V128 ) );
-@@ -3649,37 +3653,45 @@ void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
-       /* The 16-bit floating point value is in the lower 16-bits of
-          the 32-bit input value */
-       *frac_mask = newTemp( Ity_I32 );
-+      *msb_frac_mask = newTemp( Ity_I32 );
-       *exp_mask  = newTemp( Ity_I32 );
-       *zero  = newTemp( Ity_I32 );
-       assign( *exp_mask, mkU32( I16_EXP_MASK ) );
-       assign( *frac_mask, mkU32( I16_FRACTION_MASK ) );
-+      assign( *msb_frac_mask, mkU32( I16_MSB_FRACTION_MASK ) );
-       assign( *zero, mkU32( 0 ) );
- 
-    } else if( size == Ity_I32 ) {
-       *frac_mask = newTemp( Ity_I32 );
-+      *msb_frac_mask = newTemp( Ity_I32 );
-       *exp_mask  = newTemp( Ity_I32 );
-       *zero  = newTemp( Ity_I32 );
-       assign( *exp_mask, mkU32( I32_EXP_MASK ) );
-       assign( *frac_mask, mkU32( I32_FRACTION_MASK ) );
-+      assign( *msb_frac_mask, mkU32( I32_MSB_FRACTION_MASK ) );
-       assign( *zero, mkU32( 0 ) );
- 
-    } else if( size == Ity_I64 ) {
-       *frac_mask = newTemp( Ity_I64 );
-+      *msb_frac_mask = newTemp( Ity_I64 );
-       *exp_mask  = newTemp( Ity_I64 );
-       *zero  = newTemp( Ity_I64 );
-       assign( *exp_mask, mkU64( I64_EXP_MASK ) );
-       assign( *frac_mask, mkU64( I64_FRACTION_MASK ) );
-+      assign( *msb_frac_mask, mkU64( I64_MSB_FRACTION_MASK ) );
-       assign( *zero, mkU64( 0 ) );
- 
-    } else {
-       /* V128 is converted to upper and lower 64 bit values, */
-       /* uses 64-bit operators and temps */
-       *frac_mask = newTemp( Ity_I64 );
-+      *msb_frac_mask = newTemp( Ity_I64 );
-       *exp_mask  = newTemp( Ity_I64 );
-       *zero  = newTemp( Ity_I64 );
-       assign( *exp_mask, mkU64( V128_EXP_MASK ) );
-       /* upper 64-bit fractional mask */
-       assign( *frac_mask, mkU64( V128_FRACTION_MASK ) );
-+      assign( *msb_frac_mask, mkU64( V128_MSB_FRACTION_MASK ) );
-       assign( *zero, mkU64( 0 ) );
-    }
- }
-@@ -3801,9 +3813,10 @@ static IRExpr *fractional_part_compare( IRType size, IRTemp src,
- static IRExpr * is_Inf( IRType size, IRTemp src )
- {
-    IRExpr *max_exp, *zero_frac;
--   IRTemp exp_mask, frac_mask, zero;
-+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- 
--   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
-+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
-+                           &zero );
- 
-    /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
-    max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
-@@ -3818,9 +3831,10 @@ static IRExpr * is_Inf( IRType size, IRTemp src )
- static IRExpr * is_Zero( IRType size, IRTemp src )
- {
-    IRExpr *zero_exp, *zero_frac;
--   IRTemp exp_mask, frac_mask, zero;
-+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- 
--   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
-+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
-+                           &zero );
- 
-    /* check the exponent is all zeros, i.e. (exp AND exp_mask) = zero */
-    zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
-@@ -3837,9 +3851,10 @@ static IRExpr * is_Zero( IRType size, IRTemp src )
- static IRExpr * is_NaN( IRType size, IRTemp src )
- {
-    IRExpr *max_exp, *not_zero_frac;
--   IRTemp exp_mask, frac_mask, zero;
-+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- 
--   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
-+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
-+                           &zero );
- 
-    /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
-    max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
-@@ -3852,13 +3867,37 @@ static IRExpr * is_NaN( IRType size, IRTemp src )
-    return  mkAND1( max_exp, not_zero_frac );
- }
- 
-+static IRExpr * is_sNaN( IRType size, IRTemp src )
-+{
-+   IRExpr *max_exp, *not_zero_frac, *msb_zero;
-+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
-+
-+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
-+                           &zero );
-+
-+   /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
-+   max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
-+
-+   /* Most significant fractional bit is zero for sNaN */
-+   msb_zero = fractional_part_compare ( size, src, msb_frac_mask,
-+                                        mkexpr( zero ) );
-+
-+   /* check fractional part is not zero */
-+   not_zero_frac = unop( Iop_Not1,
-+                         fractional_part_compare( size, src, frac_mask,
-+                                                  mkexpr( zero ) ) );
-+
-+   return  mkAND1( msb_zero, mkAND1( max_exp, not_zero_frac ) );
-+}
-+
- /* Denormalized number has a zero exponent and non zero fraction. */
- static IRExpr * is_Denorm( IRType size, IRTemp src )
- {
-    IRExpr *zero_exp, *not_zero_frac;
--   IRTemp exp_mask, frac_mask, zero;
-+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- 
--   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
-+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
-+                           &zero );
- 
-    /* check exponent is all zeros */
-    zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
-@@ -19712,6 +19751,216 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
- }
- 
- /*
-+ * VSX vector miscellaneous instructions
-+ */
-+
-+static Bool
-+dis_vx_misc ( UInt theInstr, UInt opc2 )
-+{
-+   /* XX3-Form */
-+   UChar XT = ifieldRegXT ( theInstr );
-+   UChar XA = ifieldRegXA ( theInstr );
-+   UChar XB = ifieldRegXB ( theInstr );
-+   IRTemp vA = newTemp( Ity_V128 );
-+   IRTemp vB = newTemp( Ity_V128 );
-+   IRTemp src1 = newTemp(Ity_I64);
-+   IRTemp src2 = newTemp(Ity_I64);
-+   IRTemp result_mask = newTemp(Ity_I64);
-+   IRTemp cmp_mask = newTemp(Ity_I64);
-+   IRTemp nan_mask = newTemp(Ity_I64);
-+   IRTemp snan_mask = newTemp(Ity_I64);
-+   IRTemp word_result = newTemp(Ity_I64);
-+   IRTemp check_result = newTemp(Ity_I64);
-+   IRTemp xT = newTemp( Ity_V128 );
-+   IRTemp nan_cmp_value = newTemp(Ity_I64);
-+   UInt trap_enabled = 0;  /* 0 - trap enabled is False */
-+
-+   assign( vA, getVSReg( XA ) );
-+   assign( vB, getVSReg( XB ) );
-+   assign( xT, getVSReg( XT ) );
-+
-+   assign(src1, unop( Iop_V128HIto64, mkexpr( vA ) ) );
-+   assign(src2, unop( Iop_V128HIto64, mkexpr( vB ) ) );
-+
-+   assign( nan_mask,
-+           binop( Iop_Or64,
-+                  unop( Iop_1Sto64, is_NaN( Ity_I64, src1 ) ),
-+                  unop( Iop_1Sto64, is_NaN( Ity_I64, src2 ) ) ) );
-+
-+   if ( trap_enabled == 0 )
-+      /* Traps on invalid operation are assumed not enabled, assign
-+         result of comparison to xT.
-+      */
-+      assign( snan_mask, mkU64( 0 ) );
-+
-+   else
-+      assign( snan_mask,
-+              binop( Iop_Or64,
-+                     unop( Iop_1Sto64, is_sNaN( Ity_I64, src1 ) ),
-+                     unop( Iop_1Sto64, is_sNaN( Ity_I64, src2 ) ) ) );
-+
-+   assign (result_mask, binop( Iop_Or64,
-+                               mkexpr( snan_mask ),
-+                               mkexpr( nan_mask ) ) );
-+
-+   switch (opc2) {
-+   case 0xC: //xscmpeqdp
-+      {
-+         DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB);
-+         /* extract double-precision floating point source values from
-+            double word 0 */
-+
-+         /* result of Iop_CmpF64 is 0x40 if operands are equal,
-+            mask is all 1's if equal. */
-+
-+         assign( cmp_mask,
-+                 unop( Iop_1Sto64,
-+                       unop(Iop_32to1,
-+                            binop(Iop_Shr32,
-+                                  binop( Iop_CmpF64,
-+                                         unop( Iop_ReinterpI64asF64,
-+                                               mkexpr( src1 ) ),
-+                                         unop( Iop_ReinterpI64asF64,
-+                                               mkexpr( src2 ) ) ),
-+                                  mkU8( 6 ) ) ) ) );
-+
-+         assign( word_result,
-+                 binop( Iop_Or64,
-+                        binop( Iop_And64, mkexpr( cmp_mask ),
-+                               mkU64( 0xFFFFFFFFFFFFFFFF ) ),
-+                        binop( Iop_And64,
-+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
-+                               mkU64( 0x0 ) ) ) );
-+         assign( nan_cmp_value, mkU64( 0 ) );
-+         break;
-+      }
-+
-+   case 0x2C: //xscmpgtdp
-+      {
-+         DIP("xscmpgtdp v%d,v%d,v%d\n", XT, XA, XB);
-+         /* Test for src1 > src2 */
-+
-+         /* Result of Iop_CmpF64 is 0x1 if op1 < op2, set mask to all 1's. */
-+         assign( cmp_mask,
-+                 unop( Iop_1Sto64,
-+                       unop(Iop_32to1,
-+                            binop(Iop_CmpF64,
-+                                  unop( Iop_ReinterpI64asF64,
-+                                        mkexpr( src2 ) ),
-+                                  unop( Iop_ReinterpI64asF64,
-+                                       mkexpr( src1 ) ) ) ) ) );
-+         assign( word_result,
-+                 binop( Iop_Or64,
-+                        binop( Iop_And64, mkexpr( cmp_mask ),
-+                               mkU64( 0xFFFFFFFFFFFFFFFF ) ),
-+                        binop( Iop_And64,
-+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
-+                               mkU64( 0x0 ) ) ) );
-+         assign( nan_cmp_value, mkU64( 0 ) );
-+         break;
-+      }
-+
-+   case 0x4C: //xscmpgedp
-+      {
-+         DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB);
-+         /* compare src 1 >= src 2 */
-+         /* result of Iop_CmpF64 is 0x40 if operands are equal,
-+            mask is all 1's if equal. */
-+         assign( cmp_mask,
-+                 unop( Iop_1Sto64,
-+                       unop(Iop_32to1,
-+                            binop( Iop_Or32,
-+                                   binop( Iop_Shr32,
-+                                          binop(Iop_CmpF64,   /* EQ test */
-+                                                unop( Iop_ReinterpI64asF64,
-+                                                      mkexpr( src1 ) ),
-+                                                unop( Iop_ReinterpI64asF64,
-+                                                      mkexpr( src2 ) ) ),
-+                                          mkU8( 6 ) ),
-+                                   binop(Iop_CmpF64,  /* src2 < src 1 test */
-+                                         unop( Iop_ReinterpI64asF64,
-+                                               mkexpr( src2 ) ),
-+                                         unop( Iop_ReinterpI64asF64,
-+                                               mkexpr( src1 ) ) ) ) ) ) );
-+         assign( word_result,
-+                 binop( Iop_Or64,
-+                        binop( Iop_And64, mkexpr( cmp_mask ),
-+                               mkU64( 0xFFFFFFFFFFFFFFFF ) ),
-+                        binop( Iop_And64,
-+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
-+                               mkU64( 0x0 ) ) ) );
-+         assign( nan_cmp_value, mkU64( 0 ) );
-+         break;
-+      }
-+
-+   case 0x220: //xsmincdp
-+      {
-+         DIP("xsmincdp v%d,v%d,v%d\n", XT, XA, XB);
-+         /* extract double-precision floating point source values from
-+            double word 0 */
-+
-+         /* result of Iop_CmpF64 is 0x1 if src1 less then src2, */
-+         assign( cmp_mask,
-+                 unop( Iop_1Sto64,
-+                       unop( Iop_32to1,
-+                             binop(Iop_CmpF64,
-+                                   unop( Iop_ReinterpI64asF64,
-+                                         mkexpr( src1 ) ),
-+                                   unop( Iop_ReinterpI64asF64,
-+                                         mkexpr( src2 ) ) ) ) ) );
-+         assign( word_result,
-+                 binop( Iop_Or64,
-+                        binop( Iop_And64, mkexpr( cmp_mask ), mkexpr( src1 ) ),
-+                        binop( Iop_And64,
-+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
-+                               mkexpr( src2 ) ) ) );
-+         assign( nan_cmp_value, mkexpr( src2 ) );
-+         break;
-+      }
-+
-+   default:
-+      vex_printf( "dis_vx_misc(ppc)(opc2)\n" );
-+      return False;
-+   }
-+
-+   /* If either argument is NaN, result is src2.  If either argument is
-+      SNaN, we are supposed to generate invalid operation exception.
-+      Currently don't support generating exceptions.  In case of an
-+      trap enabled invalid operation (SNaN) XT is not changed. The
-+      snan_mask is setup appropriately for trap enabled or not.
-+   */
-+   assign( check_result,
-+           binop( Iop_Or64,
-+                  binop( Iop_And64, mkexpr( snan_mask ),
-+                         unop( Iop_V128HIto64, mkexpr( xT ) ) ),
-+                  binop( Iop_And64, unop( Iop_Not64,
-+                                          mkexpr( snan_mask ) ),
-+                         binop( Iop_Or64,
-+                                binop( Iop_And64, mkexpr( nan_mask ),
-+                                       mkexpr( nan_cmp_value ) ),
-+                                binop( Iop_And64,
-+                                       unop( Iop_Not64,
-+                                             mkexpr( nan_mask ) ),
-+                                       mkU64( 0 ) ) ) ) ) );
-+
-+   /* If SNaN is true, then the result is unchanged if a trap-enabled
-+      Invalid Operation occurs.  Result mask already setup for trap-enabled
-+      case.
-+   */
-+   putVSReg( XT,
-+             binop( Iop_64HLtoV128,
-+                    binop( Iop_Or64,
-+                           binop( Iop_And64,
-+                                  unop( Iop_Not64, mkexpr( result_mask ) ),
-+                                  mkexpr( word_result ) ),
-+                           binop( Iop_And64,
-+                                  mkexpr( result_mask ),
-+                                  mkexpr( check_result ) ) ),
-+                    mkU64( 0 ) ) );
-+   return True;
-+}
-+
-+/*
-  * VSX Logical Instructions
-  */
- static Bool
-@@ -27319,12 +27568,15 @@ static struct vsx_insn vsx_xx3[] = {
-       { 0x0,  "xsaddsp" },
-       { 0x4,  "xsmaddasp" },
-       { 0x9,  "xsmaddmsp" },
-+      { 0xC,  "xscmpeqdp" },
-       { 0x20, "xssubsp" },
-       { 0x24, "xsmaddmsp" },
-+      { 0x2C, "xscmpgtdp" },
-       { 0x3A, "xxpermr" },
-       { 0x40, "xsmulsp" },
-       { 0x44, "xsmsubasp" },
-       { 0x48, "xxmrghw" },
-+      { 0x4C, "xscmpgedp" },
-       { 0x60, "xsdivsp" },
-       { 0x64, "xsmsubmsp" },
-       { 0x68, "xxperm" },
-@@ -27371,6 +27623,7 @@ static struct vsx_insn vsx_xx3[] = {
-       { 0x1f4, "xvtdivdp" },
-       { 0x204, "xsnmaddasp" },
-       { 0x208, "xxland" },
-+      { 0x220, "xsmincdp" },
-       { 0x224, "xsnmaddmsp" },
-       { 0x228, "xxlandc" },
-       { 0x244, "xsnmsubasp" },
-@@ -28004,9 +28257,13 @@ DisResult disInstr_PPC_WRK (
-             if (dis_vx_permute_misc(theInstr, vsxOpc2 ))
- 	       goto decode_success;
-             goto decode_failure;
-+         case 0xC: case 0x2C: case 0x4C: // xscmpeqdp, xscmpgtdp, xscmpgedp
-+         case 0x220: //xsmincdp
-+            if (dis_vx_misc(theInstr, vsxOpc2)) goto decode_success;
-+            goto decode_failure;
-          case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor,
--         case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc
--         case 0x2C8: case 0x2E8: // xxlnand, xxleqv
-+         case 0x208: case 0x228: // xxland, xxlandc
-+         case 0x2A8: case 0x2C8: case 0x2E8: //  xxlorc, xxlnand, xxleqv
-             if (dis_vx_logic(theInstr, vsxOpc2)) goto decode_success;
-             goto decode_failure;
-          case 0x0ec:             // xscmpexpdp
-diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
-index 6e4e7dc..4b07f8b 100644
---- a/none/tests/ppc64/test_isa_3_0.c
-+++ b/none/tests/ppc64/test_isa_3_0.c
-@@ -1172,8 +1172,28 @@ static void test_xscmpexpdp(void) {
-    };
- }
- 
--static test_list_t testgroup_vector_scalar_compare_exp_double[] = {
-+static void test_xscmpeqdp(void) {
-+   __asm__ __volatile__ ("xscmpeqdp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
-+}
-+
-+static void test_xscmpgtdp(void) {
-+   __asm__ __volatile__ ("xscmpgtdp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
-+}
-+
-+static void test_xscmpgedp(void) {
-+   __asm__ __volatile__ ("xscmpgedp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
-+}
-+
-+static void test_xsmincdp(void) {
-+   __asm__ __volatile__ ("xsmincdp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
-+}
-+
-+static test_list_t testgroup_vector_scalar_compare_double[] = {
-    { &test_xscmpexpdp , "xscmpexpdp " },
-+   { &test_xscmpeqdp , "xscmpeqdp " },
-+   { &test_xscmpgtdp , "xscmpgtdp " },
-+   { &test_xscmpgedp , "xscmpgedp " },
-+   { &test_xsmincdp , "xsmincdp " },
-    { NULL             , NULL          },
- };
- 
-@@ -2301,8 +2321,8 @@ static test_group_table_t all_tests[] = {
-       PPC_MISC | PPC_TWO_ARGS,
-    },
-    {
--      testgroup_vector_scalar_compare_exp_double,
--      "ppc vector scalar compare exponents doubles",
-+      testgroup_vector_scalar_compare_double,
-+      "ppc vector scalar compare doubles",
-       PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS,
-    },
-    {
-@@ -3125,8 +3145,16 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name,
-    }
- }
- 
-+/* helper macro.  Use below to limit output to only dword[0] for the inputs
-+ * to the instructions listed here.  */
-+#define instruction_only_uses_dword0_inputs(instruction_name) \
-+	((strncmp(instruction_name, "xscmpeqdp",9) == 0) || \
-+	 (strncmp(instruction_name, "xscmpgtdp",9) == 0) || \
-+	 (strncmp(instruction_name, "xscmpgedp",9) == 0) || \
-+	 (strncmp(instruction_name, "xsmincdp",8) == 0) )
-+
- static void
--testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
-+testfunction_vector_scalar_compare_double (const char* instruction_name,
-                                                test_func_t test_function,
-                                                unsigned int ignore_test_flags){
-    int i,j;
-@@ -3154,11 +3182,15 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
-              */
-             SET_CR_ZERO
-             SET_FPSCR_ZERO
--
--            printf("%s %016lx %016lx %016lx %016lx",
--                   instruction_name,
--                   vec_xa[0], vec_xa[1],
--                   vec_xb[0], vec_xb[1]);
-+            if (instruction_only_uses_dword0_inputs(instruction_name)) {
-+               printf("%s %016lx %016lx",
-+                      instruction_name, vec_xa[1], vec_xb[1]);
-+            } else {
-+               printf("%s %016lx %016lx %016lx %016lx",
-+                      instruction_name,
-+                      vec_xa[0], vec_xa[1],
-+                      vec_xb[0], vec_xb[1]);
-+            }
- 
-             if (verbose) printf(" cr#%d ", x_index);
- 
-@@ -3166,6 +3198,10 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
- 
-             (*test_function)();
- 
-+            if (instruction_only_uses_dword0_inputs(instruction_name)) {
-+               printf("%016lx %016lx", vec_xt[0], vec_xt[1]);
-+            }
-+
-             dissect_fpscr(local_fpscr);
-             dissect_fpscr_result_value_class(local_fpscr);
-             dissect_cr_rn(local_cr, x_index);
-@@ -4094,7 +4130,7 @@ static void do_tests ( insn_sel_flags_t seln_flags)
-                break;
- 
-             case PPC_COMPARE_ARGS:
--               group_function = &testfunction_vector_scalar_compare_exp_double;
-+               group_function = &testfunction_vector_scalar_compare_double;
-                break;
- 
-             default:
-diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
-index c4ad35f..7d3c94c 100644
---- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
-+++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
-@@ -53311,8 +53311,8 @@ stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0
-     00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ]
- 
- All done. Tested 135 different instructions
--ppc vector scalar compare exponents doubles:
--Test instruction group [ppc vector scalar compare exponents doubles]
-+ppc vector scalar compare doubles:
-+Test instruction group [ppc vector scalar compare doubles]
- xscmpexpdp  0000000000000000 0000000000000000 0000000000000000 0000000000000000 =>  FPCC-FE(EQ)
- xscmpexpdp  0000000000000000 0000000000000000 0000000000000000 00007fffffffffff =>  FPCC-FE(EQ)
- xscmpexpdp  0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff =>  FPCC-FE(EQ)
-@@ -54275,7 +54275,3855 @@ xscmpexpdp  fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000
- xscmpexpdp  fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff =>  FPCC-FU(SO)
- xscmpexpdp  fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff =>  FPCC-FU(SO)
- 
--All done. Tested 136 different instructions
-+xscmpeqdp  0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
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-+xsmincdp  8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
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-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
-+
-+All done. Tested 140 different instructions
- ppc vector scalar test data class tests:
- Test instruction group [ppc vector scalar test data class tests]
- xststdcqp  0000000000000000, 0000000000000000 =>  0505050505050505, 0a0a0a0a0a0a0a0a
-@@ -55453,7 +59301,7 @@ xvtstdcdp  0000000000000000, ffff7fffffffffff =>  0000000000000000, 000000000000
- xvtstdcdp  0000000000000000, ffff7fffffffffff =>  0000000000000000, 0000000000000000
- xvtstdcdp  0000000000000000, ffff7fffffffffff =>  0000000000000000, ffffffffffffffff
- 
--All done. Tested 141 different instructions
-+All done. Tested 145 different instructions
- ppc vector scalar tests against float double two args :
- Test instruction group [ppc vector scalar tests against float double two args ]
- xsiexpdp    r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff  =>  0000000000000000 0000000000000000
-@@ -56261,4 +60109,4 @@ xvcvsphp    vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f800
- xvcvsphp    vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff  =>  0000000000000000 0000ffff0000ffff
- xvcvsphp    vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff  =>  0000000000000000 0000ffff0000ffff
- 
--All done. Tested 146 different instructions
-+All done. Tested 150 different instructions
-
-commit c618e707d3e24853cd1e0b71deb981f2dc4ae8d4
-Author: Carl Love <carll@us.ibm.com>
-Date:   Wed Oct 4 10:54:07 2017 -0500
-
-    PPC64, revert the change to vperm instruction.
-    
-    The patch was in my git tree with the patch I intended to apply.
-    I didn't realize the patch was in the tree.  Git applied both
-    patches.  Still investigating the vperm change to see if it is
-    really needed.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 6b2157d..b5b0d03 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -24296,12 +24296,12 @@ static Bool dis_av_permute ( UInt theInstr )
-       IRTemp vC_andF = newTemp(Ity_V128);
-       DIP("vperm v%d,v%d,v%d,v%d\n",
-           vD_addr, vA_addr, vB_addr, vC_addr);
--      /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
-+      /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
-          IR specifies, and also to hide irrelevant bits from
-          memcheck */
-       assign( vC_andF,
-               binop(Iop_AndV128, mkexpr(vC),
--                                 unop(Iop_Dup8x16, mkU8(0x1F))) );
-+                                 unop(Iop_Dup8x16, mkU8(0xF))) );
-       assign( a_perm,
-               binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) );
-       assign( b_perm,
-
-commit 856d45eb7e3661a61ace32be2cfa10bf198620c8
-Author: Carl Love <carll@us.ibm.com>
-Date:   Thu Oct 5 12:19:59 2017 -0500
-
-    PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field
-    
-    The implementation of the vpermr, xxperm, xxpermr violate this by
-    using a mask of 0x1F.  Fix the code and the corresponding comments
-    to met the definition for Iop_Perm8x16.  Use Iop_Dup8x16 to generate
-    vector value for subtraction.
-    
-    Bugzilla 385334.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index b5b0d03..f63146e 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -22579,6 +22579,7 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
-          IRTemp b_perm  = newTemp(Ity_V128);
-          IRTemp mask    = newTemp(Ity_V128);
-          IRTemp perm_val = newTemp(Ity_V128);
-+         IRTemp vB_adj = newTemp( Ity_V128 );
- 
-          if ( opc2 == 0x68 ) {
-             DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
-@@ -22591,29 +22592,27 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
-          assign( vT, getVSReg( XT ) );
- 
-          if ( opc2 == 0x68 ) // xxperm
--            assign( perm_val,
--                    binop( Iop_AndV128, mkexpr( vB ),
--                           unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) );
-+            assign( vB_adj, mkexpr( vB ) );
- 
-          else                // xxpermr
--            assign( perm_val,
-+            assign( vB_adj,
-                     binop( Iop_Sub16x8,
--                           binop( Iop_64HLtoV128,
--                                  mkU64( 0x1F1F1F1F1F1F1F1F ),
--                                  mkU64( 0x1F1F1F1F1F1F1F1F ) ),
--                           binop( Iop_AndV128, mkexpr( vB ),
--                                  unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
-+                           unop( Iop_Dup8x16, mkU8( 0x1F ) ),
-+                           mkexpr( vB ) ) );
- 
--         /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
-+         /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
-             IR specifies, and also to hide irrelevant bits from
-             memcheck.
-          */
-+         assign( perm_val,
-+                 binop( Iop_AndV128, mkexpr( vB_adj ),
-+                        unop( Iop_Dup8x16, mkU8( 0xF ) ) ) );
-          assign( a_perm,
-                  binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) );
-          assign( b_perm,
-                  binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) );
-          assign( mask, binop( Iop_SarN8x16,
--                              binop( Iop_ShlN8x16, mkexpr( perm_val ),
-+                              binop( Iop_ShlN8x16, mkexpr( vB_adj ),
-                                      mkU8( 3 ) ),
-                               mkU8( 7 ) ) );
-          // dst = (a & ~mask) | (b & mask)
-@@ -24361,28 +24360,29 @@ static Bool dis_av_permute ( UInt theInstr )
-       IRTemp b_perm  = newTemp( Ity_V128 );
-       IRTemp mask    = newTemp( Ity_V128 );
-       IRTemp vC_andF = newTemp( Ity_V128 );
-+      IRTemp vC_adj = newTemp( Ity_V128 );
- 
-       DIP( "vpermr v%d,v%d,v%d,v%d\n",
-            vD_addr, vA_addr, vB_addr, vC_addr);
--      /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
-+      /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
-          IR specifies, and also to hide irrelevant bits from
-          memcheck.
-       */
- 
-+      assign( vC_adj,
-+                    binop( Iop_Sub16x8,
-+			   unop( Iop_Dup8x16, mkU8( 0x1F ) ),
-+			   mkexpr( vC ) ) );
-       assign( vC_andF,
--              binop( Iop_Sub16x8,
--                     binop( Iop_64HLtoV128,
--                            mkU64( 0x1F1F1F1F1F1F1F1F ),
--                            mkU64( 0x1F1F1F1F1F1F1F1F ) ),
--                     binop( Iop_AndV128, mkexpr( vC ),
--                            unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
-+              binop( Iop_AndV128, mkexpr( vC_adj),
-+                     unop( Iop_Dup8x16, mkU8( 0xF ) ) ) );
-       assign( a_perm,
-               binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) );
-       assign( b_perm,
-               binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) );
-       // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0
-       assign( mask, binop(Iop_SarN8x16,
--                          binop( Iop_ShlN8x16, mkexpr( vC_andF ),
-+                          binop( Iop_ShlN8x16, mkexpr( vC_adj ),
-                                  mkU8( 3 ) ), mkU8( 7 ) ) );
-       // dst = (a & ~mask) | (b & mask)
-       putVReg( vD_addr, binop( Iop_OrV128,
diff --git a/SOURCES/valgrind-3.13.0-s390-cgijnl.patch b/SOURCES/valgrind-3.13.0-s390-cgijnl.patch
deleted file mode 100644
index 776bed6..0000000
--- a/SOURCES/valgrind-3.13.0-s390-cgijnl.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-commit d6a810760ec61ddedf15445457edbbe288536a2f
-Author: Julian Seward <jseward@acm.org>
-Date:   Tue Dec 12 22:31:54 2017 +0100
-
-    Fix false positive with s390x cgijnl instruction testing against sign bit.
-    
-    https://bugs.kde.org/show_bug.cgi?id=387712
-    
-    When the cgij "compare immediate and branch relative" instruction
-    compares 0 <=signed dep1, that means dep1 >=signed 0, so it is a test
-    against the most significant bit of dep1. So only that bit needs
-    to be defined.
-
-diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c
-index 4cccdec..aacd833 100644
---- a/VEX/priv/guest_s390_helpers.c
-+++ b/VEX/priv/guest_s390_helpers.c
-@@ -1818,6 +1818,13 @@ isC64(const IRExpr *expr)
-    return expr->tag == Iex_Const && expr->Iex.Const.con->tag == Ico_U64;
- }
- 
-+static inline Bool
-+isC64_exactly(const IRExpr *expr, ULong n)
-+{
-+   return expr->tag == Iex_Const && expr->Iex.Const.con->tag == Ico_U64
-+          && expr->Iex.Const.con->Ico.U64 == n;
-+}
-+
- 
- /* The returned expression is NULL if no specialization was found. In that
-    case the helper function will be called. Otherwise, the expression has
-@@ -1895,9 +1902,25 @@ guest_s390x_spechelper(const HChar *function_name, IRExpr **args,
-          }
-          /* cc_dep1 > cc_dep2  ---->  cc_dep2 < cc_dep1 */
-          if (cond == 2 || cond == 2 + 1) {
-+            /* If we ever need the counterpart of the bug387712 fix just
-+               below, then here is the place.  We'll need to give an
-+               alternative expression for the case "cc_dep2 <s 0".  From a
-+               bit of simple testing, I've yet to see any such cases,
-+               however. */
-             return unop(Iop_1Uto32, binop(Iop_CmpLT64S, cc_dep2, cc_dep1));
-          }
-          if (cond == 8 + 2 || cond == 8 + 2 + 1) {
-+            if (isC64_exactly(cc_dep2, 0)) {
-+               /*     0    <=signed dep1
-+                  --> dep1 >=signed 0
-+                  --> m.s.bit of dep1 == 0 */
-+               /* See bug 387712.  This is an old trick from gcc to extract
-+                  the most significant bit of a word. */
-+               return unop(Iop_64to32,
-+                           binop(Iop_Xor64,
-+                                 binop(Iop_Shr64, cc_dep1, mkU8(63)),
-+                                 mkU64(1)));
-+            }
-             return unop(Iop_1Uto32, binop(Iop_CmpLE64S, cc_dep2, cc_dep1));
-          }
-          if (cond == 8 + 4 + 2 || cond == 8 + 4 + 2 + 1) {
diff --git a/SOURCES/valgrind-3.13.0-static-tls.patch b/SOURCES/valgrind-3.13.0-static-tls.patch
deleted file mode 100644
index 578a3c5..0000000
--- a/SOURCES/valgrind-3.13.0-static-tls.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-commit f1ff8597ef9c37ff1a853411b9e3be1696c36d92
-Author: Philippe Waroquiers <philippe.waroquiers@skynet.be>
-Date:   Tue Sep 19 23:17:48 2017 +0200
-
-    Implement static TLS code for more platforms
-    
-    gdbserver_tests/hgtls is failing on a number of platforms
-    as it looks like static tls handling is now needed.
-    So, omplement static tls for a few more platforms.
-    The formulas that are platform dependent are somewhat wild guesses
-    obtained with trial and errors.
-    Note that arm/arm64/ppc32 are not (yet) done
-
-diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c
-index 10e52fc..1f03c12 100644
---- a/coregrind/m_gdbserver/target.c
-+++ b/coregrind/m_gdbserver/target.c
-@@ -712,6 +712,7 @@ Bool valgrind_get_tls_addr (ThreadState *tst,
-    // Check we can read the modid
-    CHECK_DEREF(lm+lm_modid_offset, sizeof(unsigned long int), "link_map modid");
-    modid = *(unsigned long int *)(lm+lm_modid_offset);
-+   dlog (2, "tid %u modid %lu\n", tst->tid, modid);
- 
-    // Check we can access the dtv entry for modid
-    CHECK_DEREF(dtv + 2 * modid, sizeof(CORE_ADDR), "dtv[2*modid]");
-@@ -719,7 +720,6 @@ Bool valgrind_get_tls_addr (ThreadState *tst,
-    // Compute the base address of the tls block.
-    *tls_addr = *(dtv + 2 * modid);
- 
--#if defined(VGA_mips32) || defined(VGA_mips64)
-    if (*tls_addr & 1) {
-       /* This means that computed address is not valid, most probably
-          because given module uses Static TLS.
-@@ -731,17 +731,24 @@ Bool valgrind_get_tls_addr (ThreadState *tst,
-       CORE_ADDR tls_offset_addr;
-       PtrdiffT tls_offset;
- 
--      dlog(1, "computing tls_addr using static TLS\n");
-+      dlog(2, "tls_addr (%p & 1) => computing tls_addr using static TLS\n",
-+           (void*) *tls_addr);
- 
-       /* Assumes that tls_offset is placed right before tls_modid.
-          To check the assumption, start a gdb on none/tests/tls and do:
--         p &((struct link_map*)0x0)->l_tls_modid
--         p &((struct link_map*)0x0)->l_tls_offset */
-+           p &((struct link_map*)0x0)->l_tls_modid
-+           p &((struct link_map*)0x0)->l_tls_offset
-+         Instead of assuming this, we could calculate this similarly to
-+         lm_modid_offset, by extending getplatformoffset to support querying
-+         more than one offset.
-+      */
-       tls_offset_addr = lm + lm_modid_offset - sizeof(PtrdiffT);
- 
-       // Check we can read the tls_offset.
-       CHECK_DEREF(tls_offset_addr, sizeof(PtrdiffT), "link_map tls_offset");
-       tls_offset = *(PtrdiffT *)(tls_offset_addr);
-+      dlog(2, "tls_offset_addr %p tls_offset %ld\n",
-+           (void*)tls_offset_addr, (long)tls_offset);
- 
-       /* Following two values represent platform dependent constants
-          NO_TLS_OFFSET and FORCED_DYNAMIC_TLS_OFFSET, respectively. */
-@@ -751,9 +758,18 @@ Bool valgrind_get_tls_addr (ThreadState *tst,
-       }
- 
-       // This calculation is also platform dependent.
-+#if defined(VGA_mips32) || defined(VGA_mips64)
-       *tls_addr = ((CORE_ADDR)dtv_loc + 2 * sizeof(CORE_ADDR) + tls_offset);
--   }
-+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
-+      *tls_addr = ((CORE_ADDR)dtv_loc + sizeof(CORE_ADDR) + tls_offset);
-+#elif defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x)
-+      *tls_addr = (CORE_ADDR)dtv_loc - tls_offset - sizeof(CORE_ADDR);
-+#else
-+      // ppc32, arm, arm64
-+      dlog(0, "target.c is missing platform code for static TLS\n");
-+      return False;
- #endif
-+   }
- 
-    // Finally, add tls variable offset to tls block base address.
-    *tls_addr += offset;
diff --git a/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch b/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch
deleted file mode 100644
index 77405fc..0000000
--- a/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-commit 3c3aa1c62767c48ac8f2015df66f04f354dd897b
-Author: Mark Wielaard <mark@klomp.org>
-Date:   Tue Oct 17 17:49:26 2017 +0200
-
-    Suppress _dl_runtime_resolve_avx_slow for memcheck conditional.
-    
-    glibc ld.so has an optimization when resolving a symbol that checks
-    whether or not the upper 128 bits of the ymm registers are zero. If
-    so it uses "cheaper" instructions to save/restore them using the xmm
-    registers. If those upper 128 bits contain undefined values memcheck
-    will issue an Conditional jump or move depends on uninitialised value(s)
-    warning whenever trying to resolve a symbol.
-    
-    This triggers in our sh-mem-vecxxx test cases. Suppress the warning
-    by default.
-
-diff --git a/glibc-2.X.supp.in b/glibc-2.X.supp.in
-index 8edeb4a..126e8b3 100644
---- a/glibc-2.X.supp.in
-+++ b/glibc-2.X.supp.in
-@@ -236,3 +236,15 @@
-    Memcheck:Cond
-    fun:_dl_relocate_object
- }
-+
-+# glibc ld.so has an optimization when resolving a symbol that checks
-+# whether or not the upper 128 bits of the ymm registers are zero. If
-+# so it uses "cheaper" instructions to save/restore them using the xmm
-+# registers. If those upper 128 bits contain undefined values memcheck
-+# will issue an Conditional jump or move depends on uninitialised value(s)
-+# warning whenever trying to resolve a symbol.
-+{
-+   dl-trampoline-sse-avx
-+   Memcheck:Cond
-+   fun:_dl_runtime_resolve_avx_slow
-+}
diff --git a/SOURCES/valgrind-3.13.0-ucontext_t.patch b/SOURCES/valgrind-3.13.0-ucontext_t.patch
deleted file mode 100644
index 0abcef2..0000000
--- a/SOURCES/valgrind-3.13.0-ucontext_t.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-commit 9b37074f7609cd496c067e88ef8c436981aa7267
-Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
-Date:   Thu Jun 29 15:26:30 2017 +0000
-
-    memcheck/tests: Use ucontext_t instead of struct ucontext
-    
-    glibc 2.26 does not expose struct ucontext anymore.
-    
-    Signed-off-by: Khem Raj <raj.khem@gmail.com>
-    
-    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16457 a5019735-40e9-0310-863c-91ae7b9d1cf9
-
-diff --git a/memcheck/tests/linux/stack_changes.c b/memcheck/tests/linux/stack_changes.c
-index a978fc2..7f97b90 100644
---- a/memcheck/tests/linux/stack_changes.c
-+++ b/memcheck/tests/linux/stack_changes.c
-@@ -10,7 +10,7 @@
- // This test is checking the libc context calls (setcontext, etc.) and
- // checks that Valgrind notices their stack changes properly.
- 
--typedef  struct ucontext  mycontext;
-+typedef  ucontext_t  mycontext;
- 
- mycontext ctx1, ctx2, oldc;
- int count;
diff --git a/SOURCES/valgrind-3.13.0-xml-socket.patch b/SOURCES/valgrind-3.13.0-xml-socket.patch
deleted file mode 100644
index e1b79d3..0000000
--- a/SOURCES/valgrind-3.13.0-xml-socket.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-commit 34dd8493de39314033509bb7ad62673f33dcf3db
-Author: Ivo Raisr <ivosh@ivosh.net>
-Date:   Thu Aug 3 05:22:01 2017 +0000
-
-    Fix handling command line option --xml-socket.
-    Fixes BZ#382998
-    Patch by: Orgad Shaneh <orgads@gmail.com>
-    
-    
-    
-    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16467
-
-diff --git a/coregrind/m_libcprint.c b/coregrind/m_libcprint.c
-index d66c67d..f6ba202 100644
---- a/coregrind/m_libcprint.c
-+++ b/coregrind/m_libcprint.c
-@@ -526,7 +526,7 @@ void VG_(init_log_xml_sinks)(VgLogTo log_to, VgLogTo xml_to,
-          break;
- 
-       case VgLogTo_Socket:
--         log_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded),
-+         xml_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded),
-                                       &VG_(xml_output_sink), True);
-          break;
-    }
diff --git a/SOURCES/valgrind-3.14.0-arm64-ptrace-traceme.patch b/SOURCES/valgrind-3.14.0-arm64-ptrace-traceme.patch
new file mode 100644
index 0000000..726be00
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-arm64-ptrace-traceme.patch
@@ -0,0 +1,24 @@
+commit 43fe4bc236d667257eeebfb4f6bcbe2b92aea455
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Fri Dec 14 14:32:27 2018 +0100
+
+    arm64: Fix PTRACE_TRACEME memcheck/tests/linux/getregset.vgtest testcase.
+    
+    The sys_ptrace post didn't mark the thread as being in traceme mode.
+    This occassionally would make the memcheck/tests/linux/getregset.vgtest
+    testcase fail. With this patch it reliably passes.
+
+diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
+index 9ef54b4..650f5b9 100644
+--- a/coregrind/m_syswrap/syswrap-arm64-linux.c
++++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
+@@ -499,6 +499,9 @@ PRE(sys_ptrace)
+ POST(sys_ptrace)
+ {
+    switch (ARG1) {
++   case VKI_PTRACE_TRACEME:
++         ML_(linux_POST_traceme)(tid);
++         break;
+    case VKI_PTRACE_PEEKTEXT:
+    case VKI_PTRACE_PEEKDATA:
+    case VKI_PTRACE_PEEKUSR:
diff --git a/SOURCES/valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch b/SOURCES/valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch
new file mode 100644
index 0000000..8101f93
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch
@@ -0,0 +1,18 @@
+commit 27fe22378da38424102c5292b782cacdd9d7b9e4
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 12:09:03 2018 +0100
+
+    Add support for Iop_{Sar,Shr}8 on ppc.  --expensive-definedness-checks=yes needs them.
+
+diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
+index 5242176..750cf8d 100644
+--- a/VEX/priv/host_ppc_isel.c
++++ b/VEX/priv/host_ppc_isel.c
+@@ -1528,7 +1528,6 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
+                                            True/*32bit shift*/,
+                                            tmp, tmp,    amt));
+                r_srcL = tmp;
+-               vassert(0); /* AWAITING TEST CASE */
+             }
+          }
+          /* Only 64 expressions need 64bit shifts,
diff --git a/SOURCES/valgrind-3.14.0-final_tidyup.patch b/SOURCES/valgrind-3.14.0-final_tidyup.patch
new file mode 100644
index 0000000..f4e7698
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-final_tidyup.patch
@@ -0,0 +1,59 @@
+commit be7a73004583aab5d4c97cf55276ca58d5b3090b
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Wed Dec 12 14:15:28 2018 +0100
+
+    Mark helper regs defined in final_tidyup before freeres_wrapper call.
+    
+    In final_tidyup we setup the guest to call the freeres_wrapper, which
+    will (possibly) call __gnu_cxx::__freeres() and/or __libc_freeres().
+    
+    In a couple of cases (ppc64be, ppc64le and mips32) this involves setting
+    up one or more helper registers. Since we setup these guest registers
+    we should make sure to mark them as fully defined. Otherwise we might
+    see spurious warnings about undefined value usage if the guest register
+    happened to not be fully defined before.
+    
+    This fixes PR402006.
+
+diff --git a/coregrind/m_main.c b/coregrind/m_main.c
+index 00702fc..22872a2 100644
+--- a/coregrind/m_main.c
++++ b/coregrind/m_main.c
+@@ -2304,22 +2304,35 @@ static void final_tidyup(ThreadId tid)
+                    "Caught __NR_exit; running %s wrapper\n", msgs[to_run - 1]);
+    }
+       
+-   /* set thread context to point to freeres_wrapper */
+-   /* ppc64be-linux note: freeres_wrapper gives us the real
++   /* Set thread context to point to freeres_wrapper.
++      ppc64be-linux note: freeres_wrapper gives us the real
+       function entry point, not a fn descriptor, so can use it
+       directly.  However, we need to set R2 (the toc pointer)
+       appropriately. */
+    VG_(set_IP)(tid, freeres_wrapper);
++
+ #  if defined(VGP_ppc64be_linux)
+    VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
++   VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
++            offsetof(VexGuestPPC64State, guest_GPR2),
++            sizeof(VG_(threads)[tid].arch.vex.guest_GPR2));
+ #  elif  defined(VGP_ppc64le_linux)
+    /* setting GPR2 but not really needed, GPR12 is needed */
+    VG_(threads)[tid].arch.vex.guest_GPR2  = freeres_wrapper;
++   VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
++            offsetof(VexGuestPPC64State, guest_GPR2),
++            sizeof(VG_(threads)[tid].arch.vex.guest_GPR2));
+    VG_(threads)[tid].arch.vex.guest_GPR12 = freeres_wrapper;
++   VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
++            offsetof(VexGuestPPC64State, guest_GPR12),
++            sizeof(VG_(threads)[tid].arch.vex.guest_GPR12));
+ #  endif
+    /* mips-linux note: we need to set t9 */
+ #  if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
+    VG_(threads)[tid].arch.vex.guest_r25 = freeres_wrapper;
++   VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
++            offsetof(VexGuestMIPS32State, guest_r25),
++            sizeof(VG_(threads)[tid].arch.vex.guest_r25));
+ #  endif
+ 
+    /* Pass a parameter to freeres_wrapper(). */
diff --git a/SOURCES/valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch b/SOURCES/valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch
new file mode 100644
index 0000000..d9df0d9
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch
@@ -0,0 +1,81 @@
+commit 7f1dd9d5aec1f1fd4eb0ae3a311358a914f1d73f
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 10:18:29 2018 +0100
+
+    get_otrack_shadow_offset_wrk for ppc32 and ppc64: add missing cases for XER_OV32, XER_CA32 and C_FPCC.
+    
+    The missing cases were discovered whilst testing fixes for bug 386945, but are
+    otherwise unrelated to that bug.
+
+diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
+index 5ed101f..4ce746e 100644
+--- a/memcheck/mc_machine.c
++++ b/memcheck/mc_machine.c
+@@ -120,11 +120,11 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+    Int  o    = offset;
+    tl_assert(sz > 0);
+ 
+-#if defined(VGA_ppc64be)
++#  if defined(VGA_ppc64be)
+    tl_assert(host_is_big_endian());
+-#elif defined(VGA_ppc64le)
++#  elif defined(VGA_ppc64le)
+    tl_assert(host_is_little_endian());
+-#endif
++#  endif
+ 
+    if (sz == 8 || sz == 4) {
+       /* The point of this is to achieve
+@@ -132,11 +132,11 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+             return GOF(GPRn);
+          by testing ox instead of o, and setting ox back 4 bytes when sz == 4.
+       */
+-#if defined(VGA_ppc64le)
++#     if defined(VGA_ppc64le)
+       Int ox = o;
+-#else
++#     else
+       Int ox = sz == 8 ? o : (o - 4);
+-#endif
++#     endif
+       if (ox == GOF(GPR0)) return ox;
+       if (ox == GOF(GPR1)) return ox;
+       if (ox == GOF(GPR2)) return ox;
+@@ -240,11 +240,13 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+    if (o == GOF(VSR31) && sz == 8) return o;
+ 
+    /* For the various byte sized XER/CR pieces, use offset 8
+-      in VSR0 .. VSR19. */
++      in VSR0 .. VSR21. */
+    tl_assert(SZB(VSR0) == 16);
+    if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
+    if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
++   if (o == GOF(XER_OV32) && sz == 1) return 8 +GOF(VSR20);
+    if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
++   if (o == GOF(XER_CA32) && sz == 1) return 8 +GOF(VSR21);
+    if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
+ 
+    if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
+@@ -388,6 +390,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+    if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
+    if (o == GOF(FPROUND)   && sz == 1) return -1;
+    if (o == GOF(DFPROUND)  && sz == 1) return -1;
++   if (o == GOF(C_FPCC)    && sz == 1) return -1;
+    if (o == GOF(VRSAVE)    && sz == 4) return -1;
+    if (o == GOF(EMNOTE)    && sz == 4) return -1;
+    if (o == GOF(CMSTART)   && sz == 4) return -1;
+@@ -440,11 +443,13 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+    if (o == GOF(VSR31) && sz == 8) return o;
+ 
+    /* For the various byte sized XER/CR pieces, use offset 8
+-      in VSR0 .. VSR19. */
++      in VSR0 .. VSR21. */
+    tl_assert(SZB(VSR0) == 16);
+    if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
+    if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
++   if (o == GOF(XER_OV32) && sz == 1) return 8 +GOF(VSR20);
+    if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
++   if (o == GOF(XER_CA32) && sz == 1) return 8 +GOF(VSR21);
+    if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
+ 
+    if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
diff --git a/SOURCES/valgrind-3.14.0-gettid.patch b/SOURCES/valgrind-3.14.0-gettid.patch
new file mode 100644
index 0000000..ecdd209
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-gettid.patch
@@ -0,0 +1,55 @@
+commit b46023d525b6e38a096ff4fdf9e6a96c7d7b7d40
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Mon Mar 4 19:47:59 2019 +0100
+
+    Rename gettid() to gettid_sys() in gdbserver_tests.
+    
+    glibc might defined gettid() itself through unistd.h:
+    https://sourceware.org/bugzilla/show_bug.cgi?id=6399
+    
+    Rename to gettid_sys() so we don't clash with the glibc definition.
+
+diff --git a/gdbserver_tests/sleepers.c b/gdbserver_tests/sleepers.c
+index 5ffc6f8..dfda828 100644
+--- a/gdbserver_tests/sleepers.c
++++ b/gdbserver_tests/sleepers.c
+@@ -15,7 +15,7 @@ static int sleepms = 1000; // in each loop, will sleep "sleepms" milliseconds
+ static int burn = 0; // after each sleep, will burn cpu in a tight 'burn' loop 
+ static void setup_sigusr_handler(void); // sigusr1 and 2 sigaction setup.
+ 
+-static pid_t gettid()
++static pid_t gettid_sys()
+ {
+ #ifdef __NR_gettid
+    return syscall(__NR_gettid);
+@@ -27,7 +27,7 @@ static pid_t gettid()
+ static void whoami(char *msg) __attribute__((unused));
+ static void whoami(char *msg)
+ {
+-   fprintf(stderr, "pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid(),
++   fprintf(stderr, "pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid_sys(),
+            msg);
+    fflush(stderr);
+ }
+diff --git a/gdbserver_tests/t.c b/gdbserver_tests/t.c
+index 228d4a4..b3e7a28 100644
+--- a/gdbserver_tests/t.c
++++ b/gdbserver_tests/t.c
+@@ -16,7 +16,7 @@ static int loopmain, loopt1, loopt2;
+ 
+ static double pi = 3.14159265358979323846264338327950288;
+ 
+-static pid_t gettid()
++static pid_t gettid_sys()
+ {
+ #ifdef __NT_gettid
+    return syscall(__NR_gettid);
+@@ -26,7 +26,7 @@ static pid_t gettid()
+ }
+ static void whoami(char *msg)
+ {
+-   printf("pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid(), msg);
++   printf("pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid_sys(), msg);
+    fflush(stdout);
+ }
+ 
diff --git a/SOURCES/valgrind-3.14.0-jm-vmx-constraints.patch b/SOURCES/valgrind-3.14.0-jm-vmx-constraints.patch
new file mode 100644
index 0000000..cd6463b
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-jm-vmx-constraints.patch
@@ -0,0 +1,654 @@
+commit a0d97e88ec6d71239d30a5a4b2b129e094150873
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Thu Dec 6 20:52:22 2018 +0100
+
+    Bug 401822 Fix asm constraints for ppc64 jm-vmx jm-insns.c test.
+    
+    The mfvscr and vor instructions in jm-insns.c had a "=vr" constraint.
+    This should have been an "=v" constraint. This resolved assembler
+    warnings and the testcase failing on ppc64le with gcc 8.2 and
+    binutils 2.30.
+
+diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c
+index e1a7da9..be02425 100644
+--- a/none/tests/ppc32/jm-insns.c
++++ b/none/tests/ppc32/jm-insns.c
+@@ -6269,7 +6269,7 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
+    for (i=0; i<nb_viargs; i++) {
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+       vec_in  = (vector unsigned int)viargs[i];
+       vec_out = (vector unsigned int){ 0,0,0,0 };
+@@ -6287,11 +6287,11 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+ 
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6333,7 +6333,7 @@ static void test_av_int_two_args (const char* name, test_func_t func,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6349,11 +6349,11 @@ static void test_av_int_two_args (const char* name, test_func_t func,
+          (*func)();
+ 
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6401,7 +6401,7 @@ static void test_av_int_three_args (const char* name, test_func_t func,
+             
+             /* Save flags */
+             __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+             // reset VSCR and CR
+             vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6418,11 +6418,11 @@ static void test_av_int_three_args (const char* name, test_func_t func,
+             (*func)();
+             
+             // retrieve output <- r17
+-            __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++            __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+             
+             // get CR,VSCR flags
+             __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+             
+             /* Restore flags */
+             __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6475,7 +6475,7 @@ static void vs128_cb (const char* name, test_func_t func,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6491,11 +6491,11 @@ static void vs128_cb (const char* name, test_func_t func,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6548,7 +6548,7 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
+ 
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6563,11 +6563,11 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6615,7 +6615,7 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
+       
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+       
+       // reset VSCR and CR
+       vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6627,11 +6627,11 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+       
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6677,7 +6677,7 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
+             
+             /* Save flags */
+             __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+             
+             // reset VSCR and CR
+             vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6693,11 +6693,11 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
+             (*func)();
+          
+             // retrieve output <- r17
+-            __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++            __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+             
+             // get CR,VSCR flags
+             __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+             
+             /* Restore flags */
+             __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6750,7 +6750,7 @@ static void lvs_cb (const char *name, test_func_t func,
+ 
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+       
+       // reset VSCR and CR
+       vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6762,11 +6762,11 @@ static void lvs_cb (const char *name, test_func_t func,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6870,7 +6870,7 @@ static void test_av_int_ld_two_regs (const char *name,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+          
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6882,11 +6882,11 @@ static void test_av_int_ld_two_regs (const char *name,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6956,7 +6956,7 @@ static void test_av_int_st_three_regs (const char *name,
+ 
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+          
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6974,7 +6974,7 @@ static void test_av_int_st_three_regs (const char *name,
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7037,7 +7037,7 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
+       
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+       // reset VSCR and CR
+       vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7052,11 +7052,11 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+       
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7099,7 +7099,7 @@ static void test_av_float_two_args (const char* name, test_func_t func,
+ 
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7115,11 +7115,11 @@ static void test_av_float_two_args (const char* name, test_func_t func,
+          (*func)();
+ 
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+ 
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+ 
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7168,7 +7168,7 @@ static void test_av_float_three_args (const char* name, test_func_t func,
+             
+             /* Save flags */
+             __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+             // reset VSCR and CR
+             vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7185,11 +7185,11 @@ static void test_av_float_three_args (const char* name, test_func_t func,
+             (*func)();
+ 
+             // retrieve output <- r17
+-            __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++            __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+ 
+             // get CR,VSCR flags
+             __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+ 
+             /* Restore flags */
+             __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7276,7 +7276,7 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7291,11 +7291,11 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+
+diff --git a/none/tests/ppc64/jm-insns.c b/none/tests/ppc64/jm-insns.c
+index e1a7da9..be02425 100644
+--- a/none/tests/ppc64/jm-insns.c
++++ b/none/tests/ppc64/jm-insns.c
+@@ -6269,7 +6269,7 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
+    for (i=0; i<nb_viargs; i++) {
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+       vec_in  = (vector unsigned int)viargs[i];
+       vec_out = (vector unsigned int){ 0,0,0,0 };
+@@ -6287,11 +6287,11 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+ 
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6333,7 +6333,7 @@ static void test_av_int_two_args (const char* name, test_func_t func,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6349,11 +6349,11 @@ static void test_av_int_two_args (const char* name, test_func_t func,
+          (*func)();
+ 
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6401,7 +6401,7 @@ static void test_av_int_three_args (const char* name, test_func_t func,
+             
+             /* Save flags */
+             __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+             // reset VSCR and CR
+             vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6418,11 +6418,11 @@ static void test_av_int_three_args (const char* name, test_func_t func,
+             (*func)();
+             
+             // retrieve output <- r17
+-            __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++            __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+             
+             // get CR,VSCR flags
+             __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+             
+             /* Restore flags */
+             __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6475,7 +6475,7 @@ static void vs128_cb (const char* name, test_func_t func,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6491,11 +6491,11 @@ static void vs128_cb (const char* name, test_func_t func,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6548,7 +6548,7 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
+ 
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6563,11 +6563,11 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6615,7 +6615,7 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
+       
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+       
+       // reset VSCR and CR
+       vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6627,11 +6627,11 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+       
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6677,7 +6677,7 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
+             
+             /* Save flags */
+             __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+             
+             // reset VSCR and CR
+             vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6693,11 +6693,11 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
+             (*func)();
+          
+             // retrieve output <- r17
+-            __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++            __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+             
+             // get CR,VSCR flags
+             __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+             
+             /* Restore flags */
+             __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6750,7 +6750,7 @@ static void lvs_cb (const char *name, test_func_t func,
+ 
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+       
+       // reset VSCR and CR
+       vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6762,11 +6762,11 @@ static void lvs_cb (const char *name, test_func_t func,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6870,7 +6870,7 @@ static void test_av_int_ld_two_regs (const char *name,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+          
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6882,11 +6882,11 @@ static void test_av_int_ld_two_regs (const char *name,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -6956,7 +6956,7 @@ static void test_av_int_st_three_regs (const char *name,
+ 
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+          
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -6974,7 +6974,7 @@ static void test_av_int_st_three_regs (const char *name,
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7037,7 +7037,7 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
+       
+       /* Save flags */
+       __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+       // reset VSCR and CR
+       vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7052,11 +7052,11 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
+       (*func)();
+       
+       // retrieve output <- r17
+-      __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++      __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+       
+       // get CR,VSCR flags
+       __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-      __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++      __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+       
+       /* Restore flags */
+       __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7099,7 +7099,7 @@ static void test_av_float_two_args (const char* name, test_func_t func,
+ 
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7115,11 +7115,11 @@ static void test_av_float_two_args (const char* name, test_func_t func,
+          (*func)();
+ 
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+ 
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+ 
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7168,7 +7168,7 @@ static void test_av_float_three_args (const char* name, test_func_t func,
+             
+             /* Save flags */
+             __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+             // reset VSCR and CR
+             vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7185,11 +7185,11 @@ static void test_av_float_three_args (const char* name, test_func_t func,
+             (*func)();
+ 
+             // retrieve output <- r17
+-            __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++            __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+ 
+             // get CR,VSCR flags
+             __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-            __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++            __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+ 
+             /* Restore flags */
+             __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
+@@ -7276,7 +7276,7 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
+          
+          /* Save flags */
+          __asm__ __volatile__ ("mfcr   %0" : "=r"  (tmpcr));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
+ 
+          // reset VSCR and CR
+          vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+@@ -7291,11 +7291,11 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
+          (*func)();
+          
+          // retrieve output <- r17
+-         __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
++         __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
+          
+          // get CR,VSCR flags
+          __asm__ __volatile__ ("mfcr   %0" : "=r" (flags));
+-         __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
++         __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
+          
+          /* Restore flags */
+          __asm__ __volatile__ ("mtcr   %0" : : "r"  (tmpcr));
diff --git a/SOURCES/valgrind-3.14.0-mc_translate-vecret.patch b/SOURCES/valgrind-3.14.0-mc_translate-vecret.patch
new file mode 100644
index 0000000..487d328
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-mc_translate-vecret.patch
@@ -0,0 +1,12 @@
+diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
+index c24db91..1e770b3 100644
+--- a/memcheck/mc_translate.c
++++ b/memcheck/mc_translate.c
+@@ -8022,6 +8022,7 @@ static inline void noteTmpUsesIn ( /*MOD*/HowUsed* useEnv,
+       use info. */
+    switch (at->tag) {
+       case Iex_GSPTR:
++      case Iex_VECRET:
+       case Iex_Const:
+          return;
+       case Iex_RdTmp: {
diff --git a/SOURCES/valgrind-3.14.0-memcheck-new-IROps.patch b/SOURCES/valgrind-3.14.0-memcheck-new-IROps.patch
new file mode 100644
index 0000000..79e7113
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-memcheck-new-IROps.patch
@@ -0,0 +1,453 @@
+commit e221eca26be6b2396e3fcbf4117e630fc22e79f6
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 11:28:42 2018 +0100
+
+    Add Memcheck support for IROps added in 42719898.
+    
+    memcheck/mc_translate.c:
+    
+    Add mkRight{32,64} as right-travelling analogues to mkLeft{32,64}.
+    
+    doCmpORD: for the cases of a signed comparison against zero, compute
+    definedness of the 3 result bits (lt,gt,eq) separately, and, for the lt and eq
+    bits, do it exactly accurately.
+    
+    expensiveCountTrailingZeroes: no functional change.  Re-analyse/verify and add
+    comments.
+    
+    expensiveCountLeadingZeroes: add.  Very similar to
+    expensiveCountTrailingZeroes.
+    
+    Add some comments to mark unary ops which are self-shadowing.
+    
+    Route Iop_Ctz{,Nat}{32,64} through expensiveCountTrailingZeroes.
+    Route Iop_Clz{,Nat}{32,64} through expensiveCountLeadingZeroes.
+    
+    Add instrumentation for Iop_PopCount{32,64} and Iop_Reverse8sIn32_x1.
+    
+    memcheck/tests/vbit-test/irops.c
+    
+    Add dummy new entries for all new IROps, just enough to make it compile and
+    run.
+
+diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
+index 68a2ab3..c24db91 100644
+--- a/memcheck/mc_translate.c
++++ b/memcheck/mc_translate.c
+@@ -737,6 +737,34 @@ static IRAtom* mkLeft64 ( MCEnv* mce, IRAtom* a1 ) {
+    return assignNew('V', mce, Ity_I64, unop(Iop_Left64, a1));
+ }
+ 
++/* --------- The Right-family of operations. --------- */
++
++/* Unfortunately these are a lot more expensive then their Left
++   counterparts.  Fortunately they are only very rarely used -- only for
++   count-leading-zeroes instrumentation. */
++
++static IRAtom* mkRight32 ( MCEnv* mce, IRAtom* a1 )
++{
++   for (Int i = 1; i <= 16; i *= 2) {
++      // a1 |= (a1 >>u i)
++      IRAtom* tmp
++         = assignNew('V', mce, Ity_I32, binop(Iop_Shr32, a1, mkU8(i)));
++      a1 = assignNew('V', mce, Ity_I32, binop(Iop_Or32, a1, tmp));
++   }
++   return a1;
++}
++
++static IRAtom* mkRight64 ( MCEnv* mce, IRAtom* a1 )
++{
++   for (Int i = 1; i <= 32; i *= 2) {
++      // a1 |= (a1 >>u i)
++      IRAtom* tmp
++         = assignNew('V', mce, Ity_I64, binop(Iop_Shr64, a1, mkU8(i)));
++      a1 = assignNew('V', mce, Ity_I64, binop(Iop_Or64, a1, tmp));
++   }
++   return a1;
++}
++
+ /* --------- 'Improvement' functions for AND/OR. --------- */
+ 
+ /* ImproveAND(data, vbits) = data OR vbits.  Defined (0) data 0s give
+@@ -1280,20 +1308,18 @@ static IRAtom* doCmpORD ( MCEnv*  mce,
+                           IRAtom* xxhash, IRAtom* yyhash, 
+                           IRAtom* xx,     IRAtom* yy )
+ {
+-   Bool   m64    = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD64U;
+-   Bool   syned  = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD32S;
+-   IROp   opOR   = m64 ? Iop_Or64  : Iop_Or32;
+-   IROp   opAND  = m64 ? Iop_And64 : Iop_And32;
+-   IROp   opSHL  = m64 ? Iop_Shl64 : Iop_Shl32;
+-   IROp   opSHR  = m64 ? Iop_Shr64 : Iop_Shr32;
+-   IRType ty     = m64 ? Ity_I64   : Ity_I32;
+-   Int    width  = m64 ? 64        : 32;
++   Bool   m64      = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD64U;
++   Bool   syned    = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD32S;
++   IROp   opOR     = m64 ? Iop_Or64   : Iop_Or32;
++   IROp   opAND    = m64 ? Iop_And64  : Iop_And32;
++   IROp   opSHL    = m64 ? Iop_Shl64  : Iop_Shl32;
++   IROp   opSHR    = m64 ? Iop_Shr64  : Iop_Shr32;
++   IROp   op1UtoWS = m64 ? Iop_1Uto64 : Iop_1Uto32;
++   IRType ty       = m64 ? Ity_I64    : Ity_I32;
++   Int    width    = m64 ? 64         : 32;
+ 
+    Bool (*isZero)(IRAtom*) = m64 ? isZeroU64 : isZeroU32;
+ 
+-   IRAtom* threeLeft1 = NULL;
+-   IRAtom* sevenLeft1 = NULL;
+-
+    tl_assert(isShadowAtom(mce,xxhash));
+    tl_assert(isShadowAtom(mce,yyhash));
+    tl_assert(isOriginalAtom(mce,xx));
+@@ -1312,30 +1338,55 @@ static IRAtom* doCmpORD ( MCEnv*  mce,
+       /* fancy interpretation */
+       /* if yy is zero, then it must be fully defined (zero#). */
+       tl_assert(isZero(yyhash));
+-      threeLeft1 = m64 ? mkU64(3<<1) : mkU32(3<<1);
++      // This is still inaccurate, but I don't think it matters, since
++      // nobody writes code of the form
++      // "is <partially-undefined-value> signedly greater than zero?".
++      // We therefore simply declare "x >s 0" to be undefined if any bit in
++      // x is undefined.  That's clearly suboptimal in some cases.  Eg, if
++      // the highest order bit is a defined 1 then x is negative so it
++      // doesn't matter whether the remaining bits are defined or not.
++      IRAtom* t_0_gt_0_0
++         = assignNew(
++              'V', mce,ty,
++              binop(
++                 opAND,
++                 mkPCastTo(mce,ty, xxhash),
++                 m64 ? mkU64(1<<2) : mkU32(1<<2)
++              ));
++      // For "x <s 0", we can just copy the definedness of the top bit of x
++      // and we have a precise result.
++      IRAtom* t_lt_0_0_0
++         = assignNew(
++              'V', mce,ty,
++              binop(
++                 opSHL,
++                 assignNew(
++                    'V', mce,ty,
++                    binop(opSHR, xxhash, mkU8(width-1))),
++                 mkU8(3)
++              ));
++      // For "x == 0" we can hand the problem off to expensiveCmpEQorNE.
++      IRAtom* t_0_0_eq_0
++         = assignNew(
++              'V', mce,ty,
++              binop(
++                 opSHL,
++                 assignNew('V', mce,ty,
++                    unop(
++                    op1UtoWS,
++                    expensiveCmpEQorNE(mce, ty, xxhash, yyhash, xx, yy))
++                 ),
++                 mkU8(1)
++              ));
+       return
+          binop(
+             opOR,
+-            assignNew(
+-               'V', mce,ty,
+-               binop(
+-                  opAND,
+-                  mkPCastTo(mce,ty, xxhash), 
+-                  threeLeft1
+-               )),
+-            assignNew(
+-               'V', mce,ty,
+-               binop(
+-                  opSHL,
+-                  assignNew(
+-                     'V', mce,ty,
+-                     binop(opSHR, xxhash, mkU8(width-1))),
+-                  mkU8(3)
+-               ))
+-	 );
++            assignNew('V', mce,ty, binop(opOR, t_lt_0_0_0, t_0_gt_0_0)),
++            t_0_0_eq_0
++         );
+    } else {
+       /* standard interpretation */
+-      sevenLeft1 = m64 ? mkU64(7<<1) : mkU32(7<<1);
++      IRAtom* sevenLeft1 = m64 ? mkU64(7<<1) : mkU32(7<<1);
+       return 
+          binop( 
+             opAND, 
+@@ -2211,14 +2262,14 @@ IRAtom* expensiveCountTrailingZeroes ( MCEnv* mce, IROp czop,
+    tl_assert(sameKindedAtoms(atom,vatom));
+ 
+    switch (czop) {
+-      case Iop_Ctz32:
++      case Iop_Ctz32: case Iop_CtzNat32:
+          ty = Ity_I32;
+          xorOp = Iop_Xor32;
+          subOp = Iop_Sub32;
+          andOp = Iop_And32;
+          one = mkU32(1);
+          break;
+-      case Iop_Ctz64:
++      case Iop_Ctz64: case Iop_CtzNat64:
+          ty = Ity_I64;
+          xorOp = Iop_Xor64;
+          subOp = Iop_Sub64;
+@@ -2232,8 +2283,30 @@ IRAtom* expensiveCountTrailingZeroes ( MCEnv* mce, IROp czop,
+ 
+    // improver = atom ^ (atom - 1)
+    //
+-   // That is, improver has its low ctz(atom) bits equal to one;
+-   // higher bits (if any) equal to zero.
++   // That is, improver has its low ctz(atom)+1 bits equal to one;
++   // higher bits (if any) equal to zero.  So it's exactly the right
++   // mask to use to remove the irrelevant undefined input bits.
++   /* Here are some examples:
++         atom   = U...U 1 0...0
++         atom-1 = U...U 0 1...1
++         ^ed    = 0...0 1 11111, which correctly describes which bits of |atom|
++                                 actually influence the result
++      A boundary case
++         atom   = 0...0
++         atom-1 = 1...1
++         ^ed    = 11111, also a correct mask for the input: all input bits
++                         are relevant
++      Another boundary case
++         atom   = 1..1 1
++         atom-1 = 1..1 0
++         ^ed    = 0..0 1, also a correct mask: only the rightmost input bit
++                          is relevant
++      Now with misc U bits interspersed:
++         atom   = U...U 1 0 U...U 0 1 0...0
++         atom-1 = U...U 1 0 U...U 0 0 1...1
++         ^ed    = 0...0 0 0 0...0 0 1 1...1, also correct
++      (Per re-check/analysis of 14 Nov 2018)
++   */
+    improver = assignNew('V', mce,ty,
+                         binop(xorOp,
+                               atom,
+@@ -2242,8 +2315,96 @@ IRAtom* expensiveCountTrailingZeroes ( MCEnv* mce, IROp czop,
+ 
+    // improved = vatom & improver
+    //
+-   // That is, treat any V bits above the first ctz(atom) bits as
+-   // "defined".
++   // That is, treat any V bits to the left of the rightmost ctz(atom)+1
++   // bits as "defined".
++   improved = assignNew('V', mce, ty,
++                        binop(andOp, vatom, improver));
++
++   // Return pessimizing cast of improved.
++   return mkPCastTo(mce, ty, improved);
++}
++
++static
++IRAtom* expensiveCountLeadingZeroes ( MCEnv* mce, IROp czop,
++                                      IRAtom* atom, IRAtom* vatom )
++{
++   IRType ty;
++   IROp shrOp, notOp, andOp;
++   IRAtom* (*mkRight)(MCEnv*, IRAtom*);
++   IRAtom *improver, *improved;
++   tl_assert(isShadowAtom(mce,vatom));
++   tl_assert(isOriginalAtom(mce,atom));
++   tl_assert(sameKindedAtoms(atom,vatom));
++
++   switch (czop) {
++      case Iop_Clz32: case Iop_ClzNat32:
++         ty = Ity_I32;
++         shrOp = Iop_Shr32;
++         notOp = Iop_Not32;
++         andOp = Iop_And32;
++         mkRight = mkRight32;
++         break;
++      case Iop_Clz64: case Iop_ClzNat64:
++         ty = Ity_I64;
++         shrOp = Iop_Shr64;
++         notOp = Iop_Not64;
++         andOp = Iop_And64;
++         mkRight = mkRight64;
++         break;
++      default:
++         ppIROp(czop);
++         VG_(tool_panic)("memcheck:expensiveCountLeadingZeroes");
++   }
++
++   // This is in principle very similar to how expensiveCountTrailingZeroes
++   // works.  That function computed an "improver", which it used to mask
++   // off all but the rightmost 1-bit and the zeroes to the right of it,
++   // hence removing irrelevant bits from the input.  Here, we play the
++   // exact same game but with the left-vs-right roles interchanged.
++   // Unfortunately calculation of the improver in this case is
++   // significantly more expensive.
++   //
++   // improver = ~(RIGHT(atom) >>u 1)
++   //
++   // That is, improver has its upper clz(atom)+1 bits equal to one;
++   // lower bits (if any) equal to zero.  So it's exactly the right
++   // mask to use to remove the irrelevant undefined input bits.
++   /* Here are some examples:
++         atom             = 0...0 1 U...U
++         R(atom)          = 0...0 1 1...1
++         R(atom) >>u 1    = 0...0 0 1...1
++         ~(R(atom) >>u 1) = 1...1 1 0...0
++                            which correctly describes which bits of |atom|
++                            actually influence the result
++      A boundary case
++         atom             = 0...0
++         R(atom)          = 0...0
++         R(atom) >>u 1    = 0...0
++         ~(R(atom) >>u 1) = 1...1
++                            also a correct mask for the input: all input bits
++                            are relevant
++      Another boundary case
++         atom             = 1 1..1
++         R(atom)          = 1 1..1
++         R(atom) >>u 1    = 0 1..1
++         ~(R(atom) >>u 1) = 1 0..0
++                            also a correct mask: only the leftmost input bit
++                            is relevant
++      Now with misc U bits interspersed:
++         atom             = 0...0 1 U...U 0 1 U...U
++         R(atom)          = 0...0 1 1...1 1 1 1...1
++         R(atom) >>u 1    = 0...0 0 1...1 1 1 1...1
++         ~(R(atom) >>u 1) = 1...1 1 0...0 0 0 0...0, also correct
++      (Per initial implementation of 15 Nov 2018)
++   */
++   improver = mkRight(mce, atom);
++   improver = assignNew('V', mce, ty, binop(shrOp, improver, mkU8(1)));
++   improver = assignNew('V', mce, ty, unop(notOp, improver));
++
++   // improved = vatom & improver
++   //
++   // That is, treat any V bits to the right of the leftmost clz(atom)+1
++   // bits as "defined".
+    improved = assignNew('V', mce, ty,
+                         binop(andOp, vatom, improver));
+ 
+@@ -4705,6 +4866,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_RecipEst32F0x4:
+          return unary32F0x4(mce, vatom);
+ 
++      // These are self-shadowing.
+       case Iop_32UtoV128:
+       case Iop_64UtoV128:
+       case Iop_Dup8x16:
+@@ -4745,6 +4907,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_MulI128by10Carry:
+       case Iop_F16toF64x2:
+       case Iop_F64toF16x2:
++         // FIXME JRS 2018-Nov-15.  This is surely not correct!
+          return vatom;
+ 
+       case Iop_I32StoF128: /* signed I32 -> F128 */
+@@ -4770,7 +4933,6 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_RoundF64toF64_NegINF:
+       case Iop_RoundF64toF64_PosINF:
+       case Iop_RoundF64toF64_ZERO:
+-      case Iop_Clz64:
+       case Iop_D32toD64:
+       case Iop_I32StoD64:
+       case Iop_I32UtoD64:
+@@ -4785,17 +4947,32 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_D64toD128:
+          return mkPCastTo(mce, Ity_I128, vatom);
+ 
+-      case Iop_Clz32:
+       case Iop_TruncF64asF32:
+       case Iop_NegF32:
+       case Iop_AbsF32:
+       case Iop_F16toF32: 
+          return mkPCastTo(mce, Ity_I32, vatom);
+ 
+-      case Iop_Ctz32:
+-      case Iop_Ctz64:
++      case Iop_Ctz32: case Iop_CtzNat32:
++      case Iop_Ctz64: case Iop_CtzNat64:
+          return expensiveCountTrailingZeroes(mce, op, atom, vatom);
+ 
++      case Iop_Clz32: case Iop_ClzNat32:
++      case Iop_Clz64: case Iop_ClzNat64:
++         return expensiveCountLeadingZeroes(mce, op, atom, vatom);
++
++      // PopCount32: this is slightly pessimistic.  It is true that the
++      // result depends on all input bits, so that aspect of the PCast is
++      // correct.  However, regardless of the input, only the lowest 5 bits
++      // out of the output can ever be undefined.  So we could actually
++      // "improve" the results here by marking the top 27 bits of output as
++      // defined.  A similar comment applies for PopCount64.
++      case Iop_PopCount32:
++         return mkPCastTo(mce, Ity_I32, vatom);
++      case Iop_PopCount64:
++         return mkPCastTo(mce, Ity_I64, vatom);
++
++      // These are self-shadowing.
+       case Iop_1Uto64:
+       case Iop_1Sto64:
+       case Iop_8Uto64:
+@@ -4821,6 +4998,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_V256to64_2: case Iop_V256to64_3:
+          return assignNew('V', mce, Ity_I64, unop(op, vatom));
+ 
++      // These are self-shadowing.
+       case Iop_64to32:
+       case Iop_64HIto32:
+       case Iop_1Uto32:
+@@ -4830,8 +5008,10 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_16Sto32:
+       case Iop_8Sto32:
+       case Iop_V128to32:
++      case Iop_Reverse8sIn32_x1:
+          return assignNew('V', mce, Ity_I32, unop(op, vatom));
+ 
++      // These are self-shadowing.
+       case Iop_8Sto16:
+       case Iop_8Uto16:
+       case Iop_32to16:
+@@ -4840,6 +5020,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_GetMSBs8x16:
+          return assignNew('V', mce, Ity_I16, unop(op, vatom));
+ 
++      // These are self-shadowing.
+       case Iop_1Uto8:
+       case Iop_1Sto8:
+       case Iop_16to8:
+@@ -4868,6 +5049,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_Not16:
+       case Iop_Not8:
+       case Iop_Not1:
++         // FIXME JRS 2018-Nov-15.  This is surely not correct!
+          return vatom;
+ 
+       case Iop_CmpNEZ8x8:
+@@ -4929,6 +5111,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
+       case Iop_Ctz64x2:
+          return mkPCast64x2(mce, vatom);
+ 
++      // This is self-shadowing.
+       case Iop_PwBitMtxXpose64x2:
+          return assignNew('V', mce, Ity_V128, unop(op, vatom));
+ 
+diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
+index bfd82fc..e8bf67d 100644
+--- a/memcheck/tests/vbit-test/irops.c
++++ b/memcheck/tests/vbit-test/irops.c
+@@ -111,6 +111,12 @@ static irop_t irops[] = {
+   { DEFOP(Iop_Clz32,      UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+   { DEFOP(Iop_Ctz64,      UNDEF_ALL),  .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+   { DEFOP(Iop_Ctz32,      UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
++  { DEFOP(Iop_ClzNat64,   UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts
++  { DEFOP(Iop_ClzNat32,   UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
++  { DEFOP(Iop_CtzNat64,   UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
++  { DEFOP(Iop_CtzNat32,   UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
++  { DEFOP(Iop_PopCount64, UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
++  { DEFOP(Iop_PopCount32, UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
+   { DEFOP(Iop_CmpLT32S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+   { DEFOP(Iop_CmpLT64S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
+   { DEFOP(Iop_CmpLE32S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+@@ -336,6 +342,7 @@ static irop_t irops[] = {
+   { DEFOP(Iop_Sad8Ux4, UNDEF_UNKNOWN), },
+   { DEFOP(Iop_CmpNEZ16x2, UNDEF_UNKNOWN), },
+   { DEFOP(Iop_CmpNEZ8x4, UNDEF_UNKNOWN), },
++  { DEFOP(Iop_Reverse8sIn32_x1, UNDEF_UNKNOWN) },
+   /* ------------------ 64-bit SIMD FP ------------------------ */
+   { DEFOP(Iop_I32UtoFx2, UNDEF_UNKNOWN), },
+   { DEFOP(Iop_I32StoFx2, UNDEF_UNKNOWN), },
diff --git a/SOURCES/valgrind-3.14.0-new-strlen-IROps.patch b/SOURCES/valgrind-3.14.0-new-strlen-IROps.patch
new file mode 100644
index 0000000..d6587d8
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-new-strlen-IROps.patch
@@ -0,0 +1,124 @@
+commit 4271989815b5fc933c1e29bc75507c2726dc3738
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 10:52:33 2018 +0100
+
+    Add some new IROps to support improved Memcheck analysis of strlen etc.
+    
+    This is part of the fix for bug 386945.  It adds the following IROps, plus
+    their supporting type- and printing- fragments:
+    
+    Iop_Reverse8sIn32_x1: 32-bit byteswap.  A fancy name, but it is consistent
+    with naming for the other swapping IROps that already exist.
+    
+    Iop_PopCount64, Iop_PopCount32: population count
+    
+    Iop_ClzNat64, Iop_ClzNat32, Iop_CtzNat64, Iop_CtzNat32: counting leading and
+    trailing zeroes, with "natural" (Nat) semantics for a zero input, meaning, in
+    the case of zero input, return the number of bits in the word.  These
+    functionally overlap with the existing Iop_Clz64, Iop_Clz32, Iop_Ctz64,
+    Iop_Ctz32.  The existing operations are undefined in case of a zero input.
+    Adding these new variants avoids the complexity of having to change the
+    declared semantics of the existing operations.  Instead they are deprecated
+    but still available for use.
+
+diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c
+index 823b6be..3221033 100644
+--- a/VEX/priv/ir_defs.c
++++ b/VEX/priv/ir_defs.c
+@@ -194,6 +194,14 @@ void ppIROp ( IROp op )
+       case Iop_Ctz64:    vex_printf("Ctz64"); return;
+       case Iop_Ctz32:    vex_printf("Ctz32"); return;
+ 
++      case Iop_ClzNat64: vex_printf("ClzNat64"); return;
++      case Iop_ClzNat32: vex_printf("ClzNat32"); return;
++      case Iop_CtzNat64: vex_printf("CtzNat64"); return;
++      case Iop_CtzNat32: vex_printf("CtzNat32"); return;
++
++      case Iop_PopCount64: vex_printf("PopCount64"); return;
++      case Iop_PopCount32: vex_printf("PopCount32"); return;
++
+       case Iop_CmpLT32S: vex_printf("CmpLT32S"); return;
+       case Iop_CmpLE32S: vex_printf("CmpLE32S"); return;
+       case Iop_CmpLT32U: vex_printf("CmpLT32U"); return;
+@@ -395,6 +403,7 @@ void ppIROp ( IROp op )
+ 
+       case Iop_CmpNEZ16x2: vex_printf("CmpNEZ16x2"); return;
+       case Iop_CmpNEZ8x4:  vex_printf("CmpNEZ8x4"); return;
++      case Iop_Reverse8sIn32_x1: vex_printf("Reverse8sIn32_x1"); return;
+ 
+       case Iop_CmpF64:    vex_printf("CmpF64"); return;
+ 
+@@ -2719,6 +2728,7 @@ void typeOfPrimop ( IROp op,
+          UNARY(Ity_I16, Ity_I16);
+       case Iop_Not32:
+       case Iop_CmpNEZ16x2: case Iop_CmpNEZ8x4:
++      case Iop_Reverse8sIn32_x1:
+          UNARY(Ity_I32, Ity_I32);
+ 
+       case Iop_Not64:
+@@ -2782,9 +2792,13 @@ void typeOfPrimop ( IROp op,
+          BINARY(Ity_I64,Ity_I64, Ity_I128);
+ 
+       case Iop_Clz32: case Iop_Ctz32:
++      case Iop_ClzNat32: case Iop_CtzNat32:
++      case Iop_PopCount32:
+          UNARY(Ity_I32, Ity_I32);
+ 
+       case Iop_Clz64: case Iop_Ctz64:
++      case Iop_ClzNat64: case Iop_CtzNat64:
++      case Iop_PopCount64:
+          UNARY(Ity_I64, Ity_I64);
+ 
+       case Iop_DivU32: case Iop_DivS32: case Iop_DivU32E: case Iop_DivS32E:
+diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
+index 17bcb55..93fa5ac 100644
+--- a/VEX/pub/libvex_ir.h
++++ b/VEX/pub/libvex_ir.h
+@@ -452,12 +452,21 @@ typedef
+       Iop_MullS8, Iop_MullS16, Iop_MullS32, Iop_MullS64,
+       Iop_MullU8, Iop_MullU16, Iop_MullU32, Iop_MullU64,
+ 
+-      /* Wierdo integer stuff */
++      /* Counting bits */
++      /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of zero.
++         You must ensure they are never given a zero argument.  As of
++         2018-Nov-14 they are deprecated.  Try to use the Nat variants
++         immediately below, if you can.
++      */
+       Iop_Clz64, Iop_Clz32,   /* count leading zeroes */
+       Iop_Ctz64, Iop_Ctz32,   /* count trailing zeros */
+-      /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of
+-         zero.  You must ensure they are never given a zero argument.
+-      */
++      /* Count leading/trailing zeroes, with "natural" semantics for the
++         case where the input is zero: then the result is the number of bits
++         in the word. */
++      Iop_ClzNat64, Iop_ClzNat32,
++      Iop_CtzNat64, Iop_CtzNat32,
++      /* Population count -- compute the number of 1 bits in the argument. */
++      Iop_PopCount64, Iop_PopCount32,
+ 
+       /* Standard integer comparisons */
+       Iop_CmpLT32S, Iop_CmpLT64S,
+@@ -831,6 +840,9 @@ typedef
+       /* MISC (vector integer cmp != 0) */
+       Iop_CmpNEZ16x2, Iop_CmpNEZ8x4,
+ 
++      /* Byte swap in a 32-bit word */
++      Iop_Reverse8sIn32_x1,
++
+       /* ------------------ 64-bit SIMD FP ------------------------ */
+ 
+       /* Convertion to/from int */
+@@ -1034,8 +1046,9 @@ typedef
+       Iop_Slice64,  // (I64, I64, I8) -> I64
+ 
+       /* REVERSE the order of chunks in vector lanes.  Chunks must be
+-         smaller than the vector lanes (obviously) and so may be 8-,
+-         16- and 32-bit in size. */
++         smaller than the vector lanes (obviously) and so may be 8-, 16- and
++         32-bit in size.  Note that the degenerate case,
++         Iop_Reverse8sIn64_x1, is a simply a vanilla byte-swap. */
+       /* Examples:
+             Reverse8sIn16_x4([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
+             Reverse8sIn32_x2([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e]
diff --git a/SOURCES/valgrind-3.14.0-power9-addex.patch b/SOURCES/valgrind-3.14.0-power9-addex.patch
new file mode 100644
index 0000000..1b8d9f2
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-power9-addex.patch
@@ -0,0 +1,256 @@
+From 2c1f016e634bf79faf45e81c14c955c711bc202f Mon Sep 17 00:00:00 2001
+From: Mark Wielaard <mark@klomp.org>
+Date: Mon, 31 Dec 2018 22:26:31 +0100
+Subject: [PATCH] Bug 402519 - POWER 3.0 addex instruction incorrectly
+ implemented
+
+addex uses OV as carry in and carry out. For all other instructions
+OV is the signed overflow flag. And instructions like adde use CA
+as carry.
+
+Replace set_XER_OV_OV32 with set_XER_OV_OV32_ADDEX, which will
+call calculate_XER_CA_64 and calculate_XER_CA_32, but with OV
+as input, and sets OV and OV32.
+
+Enable test_addex in none/tests/ppc64/test_isa_3_0.c and update
+the expected output. test_addex would fail to match the expected
+output before this patch.
+---
+ NEWS                                              |  1 +
+ VEX/priv/guest_ppc_toIR.c                         | 52 ++++++++++++++---------
+ none/tests/ppc64/test_isa_3_0.c                   |  3 +-
+ none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE | 36 ++++++++++------
+ 4 files changed, 58 insertions(+), 34 deletions(-)
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index 18df822..d685383 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -2645,21 +2645,6 @@ static void copy_OV_to_OV32( void ) {
+    putXER_OV32( getXER_OV() );
+ }
+ 
+-static void set_XER_OV_OV32 ( IRType ty, UInt op, IRExpr* res,
+-                              IRExpr* argL, IRExpr* argR )
+-{
+-   if (ty == Ity_I32) {
+-      set_XER_OV_OV32_32( op, res, argL, argR );
+-   } else {
+-      IRExpr* xer_ov_32;
+-      set_XER_OV_64( op, res, argL, argR );
+-      xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
+-                                       unop(Iop_64to32, argL),
+-                                       unop(Iop_64to32, argR));
+-      putXER_OV32( unop(Iop_32to8, xer_ov_32) );
+-   }
+-}
+-
+ static void set_XER_OV_OV32_SO ( IRType ty, UInt op, IRExpr* res,
+                                  IRExpr* argL, IRExpr* argR )
+ {
+@@ -3005,6 +2990,33 @@ static void set_XER_CA_CA32 ( IRType ty, UInt op, IRExpr* res,
+    }
+ }
+ 
++/* Used only by addex instruction, which uses and sets OV as carry.  */
++static void set_XER_OV_OV32_ADDEX ( IRType ty, IRExpr* res,
++                                    IRExpr* argL, IRExpr* argR,
++                                    IRExpr* old_ov )
++{
++   if (ty == Ity_I32) {
++      IRTemp xer_ov = newTemp(Ity_I32);
++      assign ( xer_ov, unop(Iop_32to8,
++                            calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
++                                                 res, argL, argR, old_ov ) ) );
++      putXER_OV( mkexpr (xer_ov) );
++      putXER_OV32( mkexpr (xer_ov) );
++   } else {
++      IRExpr *xer_ov;
++      IRExpr* xer_ov_32;
++      xer_ov = calculate_XER_CA_64( PPCG_FLAG_OP_ADDE,
++                                    res, argL, argR, old_ov );
++      putXER_OV( unop(Iop_32to8, xer_ov) );
++      xer_ov_32 = calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
++                                       unop(Iop_64to32, res),
++                                       unop(Iop_64to32, argL),
++                                       unop(Iop_64to32, argR),
++                                       unop(Iop_64to32, old_ov) );
++      putXER_OV32( unop(Iop_32to8, xer_ov_32) );
++   }
++}
++
+ 
+ 
+ /*------------------------------------------------------------*/
+@@ -5094,16 +5106,18 @@ static Bool dis_int_arith ( UInt theInstr )
+       }
+ 
+       case 0xAA: {// addex (Add Extended alternate carry bit Z23-form)
++         IRTemp old_xer_ov = newTemp(ty);
+          DIP("addex r%u,r%u,r%u,%d\n", rD_addr, rA_addr, rB_addr, (Int)flag_OE);
++         assign( old_xer_ov, mkWidenFrom32(ty, getXER_OV_32(), False) );
+          assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
+                             binop( mkSzOp(ty, Iop_Add8), mkexpr(rB),
+-                                   mkWidenFrom8( ty, getXER_OV(), False ) ) ) );
++                                   mkexpr(old_xer_ov) ) ) );
+ 
+          /* CY bit is same as OE bit */
+          if (flag_OE == 0) {
+-            /* Exception, do not set SO bit */
+-            set_XER_OV_OV32( ty, PPCG_FLAG_OP_ADDE,
+-                             mkexpr(rD), mkexpr(rA), mkexpr(rB) );
++            /* Exception, do not set SO bit and set OV from carry. */
++            set_XER_OV_OV32_ADDEX( ty, mkexpr(rD), mkexpr(rA), mkexpr(rB),
++                                   mkexpr(old_xer_ov) );
+          } else {
+             /* CY=1, 2 and 3 (AKA flag_OE) are reserved */
+             vex_printf("addex instruction, CY = %d is reserved.\n", flag_OE);
+diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
+index 2d13505..1c2cda3 100644
+--- a/none/tests/ppc64/test_isa_3_0.c
++++ b/none/tests/ppc64/test_isa_3_0.c
+@@ -286,7 +286,7 @@ static test_list_t testgroup_ia_ops_two[] = {
+    { &test_moduw, "moduw" },
+    { &test_modsd, "modsd" },
+    { &test_modud, "modud" },
+-   //{ &test_addex, "addex" },
++   { &test_addex, "addex" },
+    { NULL       , NULL             },
+ };
+ 
+@@ -2741,7 +2741,6 @@ static void testfunction_gpr_vector_logical_one (const char* instruction_name,
+     *   rt, xa
+     */
+    int i;
+-   int t;
+    volatile HWord_t res;
+ 
+    VERBOSE_FUNCTION_CALLOUT
+diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
+index 152ff28..cc0e88e 100644
+--- a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
++++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
+@@ -40,7 +40,17 @@ modud ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+ modud ffffffffffffffff, 0000001cbe991def => 000000043eb0c0b2 (00000000)
+ modud ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+ 
+-All done. Tested 4 different instructions
++addex 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
++addex 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
++addex 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
++addex 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000)
++addex 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000) OV32
++addex 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000) OV OV32
++addex ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000) OV OV32
++addex ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000) OV OV32
++addex ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000) OV OV32
++
++All done. Tested 5 different instructions
+ ppc one argument plus shift:
+ Test instruction group [ppc one argument plus shift]
+ extswsli  aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
+@@ -85,7 +95,7 @@ extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaa
+ extswsli. 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
+ extswsli. 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+ 
+-All done. Tested 6 different instructions
++All done. Tested 7 different instructions
+ ppc three parameter ops:
+ Test instruction group [ppc three parameter ops]
+ maddhd  0000000000000000, 0000000000000000, 0000000000000000  => 0000000000000000 (00000000)
+@@ -172,7 +182,7 @@ maddld  ffffffffffffffff, ffffffffffffffff, 0000000000000000  => 000000000000000
+ maddld  ffffffffffffffff, ffffffffffffffff, 0000001cbe991def  => 0000001cbe991df0 (00000000)
+ maddld  ffffffffffffffff, ffffffffffffffff, ffffffffffffffff  => 0000000000000000 (00000000)
+ 
+-All done. Tested 9 different instructions
++All done. Tested 10 different instructions
+ ppc count zeros:
+ Test instruction group [ppc count zeros]
+ cnttzw 0000000000000000 => 0000000000000020
+@@ -197,7 +207,7 @@ cnttzd. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (200
+ cnttzd. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+ 
+ 
+-All done. Tested 13 different instructions
++All done. Tested 14 different instructions
+ ppc set boolean:
+ Test instruction group [ppc set boolean]
+ setb cr_field:0 cr_value::00000000 =>  0000000000000000
+@@ -265,7 +275,7 @@ setb cr_field:7 cr_value::00000005 =>  0000000000000001
+ setb cr_field:7 cr_value::00000006 =>  0000000000000001
+ setb cr_field:7 cr_value::00000007 =>  0000000000000001
+ 
+-All done. Tested 14 different instructions
++All done. Tested 15 different instructions
+ ppc char compare:
+ Test instruction group [ppc char compare]
+ cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+@@ -1711,7 +1721,7 @@ cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+ cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+ cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+ 
+-All done. Tested 17 different instructions
++All done. Tested 18 different instructions
+ ppc vector scalar move to/from:
+ Test instruction group [ppc vector scalar move to/from]
+ mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
+@@ -1777,7 +1787,7 @@ mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 113377cc113377cc
+ mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+ mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+ 
+-All done. Tested 20 different instructions
++All done. Tested 21 different instructions
+ ppc dfp significance:
+ Test instruction group [ppc dfp significance]
+ dtstsfi significance(0x00) +Finite                  0 * 10 ^ -12 (GT) (4)
+@@ -1862,7 +1872,7 @@ dtstsfiq significance(0x20) -inf      (GT) (4)
+ dtstsfiq significance(0x30) -inf      (GT) (4)
+ dtstsfiq significance(0x3f) -inf      (GT) (4)
+ 
+-All done. Tested 22 different instructions
++All done. Tested 23 different instructions
+ ppc bcd misc:
+ Test instruction group [ppc bcd misc]
+ bcdadd. p0 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000000000000c (+|0) => (EQ) (2) xt:0000000000000000 000000000000000c(+|0)
+@@ -33338,12 +33348,12 @@ bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:9999999999999999 99999
+ bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000001234567d ( - ) => (GT) (4) xt:0000000000000000 000000305419901f(+|0)
+ 
+ 
+-All done. Tested 51 different instructions
++All done. Tested 52 different instructions
+ ppc noop misc:
+ Test instruction group [ppc noop misc]
+ wait   =>
+ 
+-All done. Tested 52 different instructions
++All done. Tested 53 different instructions
+ ppc addpc_misc:
+ Test instruction group [ppc addpc_misc]
+ addpcis   0000000000000000  =>  0000000000000000
+@@ -33380,7 +33390,7 @@ subpcis   000000000000000d  =>  0000000000000000
+ subpcis   000000000000000e  =>  0000000000000000
+ subpcis   000000000000000f  =>  0000000000000000
+ 
+-All done. Tested 54 different instructions
++All done. Tested 55 different instructions
+ ppc mffpscr:
+ Test instruction group [ppc mffpscr]
+ mffsce  =>  000000000.000000
+@@ -33395,7 +33405,7 @@ mffs  =>  000000000.000000
+  fpscr: f14 
+  local_fpscr: 
+ 
+-All done. Tested 57 different instructions
++All done. Tested 58 different instructions
+ ppc mffpscr:
+ Test instruction group [ppc mffpscr]
+ mffscdrni  0  =>  0X0
+@@ -33426,4 +33436,4 @@ mffscrn  f15 0X1   =>  0X200000000
+ mffscrn  f15 0X2   =>  0X200000000
+  fpscr: f14  local_fpscr:  30-DRN1 RN-bit62
+ 
+-All done. Tested 61 different instructions
++All done. Tested 62 different instructions
+-- 
+1.8.3.1
+
diff --git a/SOURCES/valgrind-3.14.0-ppc-frontend-new-IROps.patch b/SOURCES/valgrind-3.14.0-ppc-frontend-new-IROps.patch
new file mode 100644
index 0000000..a550975
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc-frontend-new-IROps.patch
@@ -0,0 +1,381 @@
+commit 81d9832226d6e3d1ee78ee3133189d7b520e7eea
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 11:36:53 2018 +0100
+
+    ppc front end: use new IROps added in 42719898.
+    
+    This pertains to bug 386945.
+    
+    VEX/priv/guest_ppc_toIR.c:
+    
+    gen_POPCOUNT: use Iop_PopCount{32,64} where possible.
+    
+    gen_vpopcntd_mode32: use Iop_PopCount32.
+    
+    for cntlz{w,d}, use Iop_CtzNat{32,64}.
+    
+    gen_byterev32: use Iop_Reverse8sIn32_x1 instead of lengthy sequence.
+    
+    verbose_Clz32: remove (was unused anyway).
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index cb1cae1..8977d4f 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -1595,7 +1595,8 @@ typedef enum {
+ /* Generate an IR sequence to do a popcount operation on the supplied
+    IRTemp, and return a new IRTemp holding the result.  'ty' may be
+    Ity_I32 or Ity_I64 only. */
+-static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_type )
++static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src,
++                             _popcount_data_type data_type )
+ {
+   /* Do count across 2^data_type bits,
+      byte:        data_type = 3
+@@ -1611,6 +1612,22 @@ static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_typ
+ 
+    vassert(ty == Ity_I64 || ty == Ity_I32);
+ 
++   // Use a single IROp in cases where we can.
++
++   if (ty == Ity_I64 && data_type == DWORD) {
++      IRTemp res = newTemp(Ity_I64);
++      assign(res, unop(Iop_PopCount64, mkexpr(src)));
++      return res;
++   }
++
++   if (ty == Ity_I32 && data_type == WORD) {
++      IRTemp res = newTemp(Ity_I32);
++      assign(res, unop(Iop_PopCount32, mkexpr(src)));
++      return res;
++   }
++
++   // For the rest, we have to do it the slow way.
++
+    if (ty == Ity_I32) {
+ 
+       for (idx = 0; idx < WORD; idx++) {
+@@ -1638,7 +1655,7 @@ static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_typ
+       return nyu;
+    }
+ 
+-// else, ty == Ity_I64
++   // else, ty == Ity_I64
+    vassert(mode64);
+ 
+    for (i = 0; i < DWORD; i++) {
+@@ -1670,52 +1687,15 @@ static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_typ
+  */
+ static IRTemp gen_vpopcntd_mode32 ( IRTemp src1, IRTemp src2 )
+ {
+-   Int i, shift[6];
+-   IRTemp mask[6];
+-   IRTemp old = IRTemp_INVALID;
+-   IRTemp nyu1 = IRTemp_INVALID;
+-   IRTemp nyu2 = IRTemp_INVALID;
+    IRTemp retval = newTemp(Ity_I64);
+ 
+    vassert(!mode64);
+ 
+-   for (i = 0; i < WORD; i++) {
+-      mask[i]  = newTemp(Ity_I32);
+-      shift[i] = 1 << i;
+-   }
+-   assign(mask[0], mkU32(0x55555555));
+-   assign(mask[1], mkU32(0x33333333));
+-   assign(mask[2], mkU32(0x0F0F0F0F));
+-   assign(mask[3], mkU32(0x00FF00FF));
+-   assign(mask[4], mkU32(0x0000FFFF));
+-   old = src1;
+-   for (i = 0; i < WORD; i++) {
+-      nyu1 = newTemp(Ity_I32);
+-      assign(nyu1,
+-             binop(Iop_Add32,
+-                   binop(Iop_And32,
+-                         mkexpr(old),
+-                         mkexpr(mask[i])),
+-                   binop(Iop_And32,
+-                         binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
+-                         mkexpr(mask[i]))));
+-      old = nyu1;
+-   }
+-
+-   old = src2;
+-   for (i = 0; i < WORD; i++) {
+-      nyu2 = newTemp(Ity_I32);
+-      assign(nyu2,
+-             binop(Iop_Add32,
+-                   binop(Iop_And32,
+-                         mkexpr(old),
+-                         mkexpr(mask[i])),
+-                   binop(Iop_And32,
+-                         binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
+-                         mkexpr(mask[i]))));
+-      old = nyu2;
+-   }
+-   assign(retval, unop(Iop_32Uto64, binop(Iop_Add32, mkexpr(nyu1), mkexpr(nyu2))));
++   assign(retval,
++          unop(Iop_32Uto64,
++               binop(Iop_Add32,
++                     unop(Iop_PopCount32, mkexpr(src1)),
++                     unop(Iop_PopCount32, mkexpr(src2)))));
+    return retval;
+ }
+ 
+@@ -5715,7 +5695,7 @@ static Bool dis_modulo_int ( UInt theInstr )
+                 rA_address, rS_address);
+ 
+             assign( rS, getIReg( rS_address ) );
+-            assign( result, unop( Iop_Ctz32,
++            assign( result, unop( Iop_CtzNat32,
+                                   unop( Iop_64to32, mkexpr( rS ) ) ) );
+             assign( rA, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( result ) ) );
+ 
+@@ -5746,7 +5726,7 @@ static Bool dis_modulo_int ( UInt theInstr )
+                 rA_address, rS_address);
+ 
+             assign( rS, getIReg( rS_address ) );
+-            assign( rA, unop( Iop_Ctz64, mkexpr( rS ) ) );
++            assign( rA, unop( Iop_CtzNat64, mkexpr( rS ) ) );
+ 
+             if ( flag_rC == 1 )
+                set_CR0( mkexpr( rA ) );
+@@ -6307,7 +6287,6 @@ static Bool dis_int_logic ( UInt theInstr )
+    IRTemp rS     = newTemp(ty);
+    IRTemp rA     = newTemp(ty);
+    IRTemp rB     = newTemp(ty);
+-   IRExpr* irx;
+    Bool do_rc    = False;
+ 
+    assign( rS, getIReg(rS_addr) );
+@@ -6404,26 +6383,16 @@ static Bool dis_int_logic ( UInt theInstr )
+          break;
+          
+       case 0x01A: { // cntlzw (Count Leading Zeros Word, PPC32 p371)
+-         IRExpr* lo32;
+          if (rB_addr!=0) {
+             vex_printf("dis_int_logic(ppc)(cntlzw,rB_addr)\n");
+             return False;
+          }
+-         DIP("cntlzw%s r%u,r%u\n",
+-             flag_rC ? ".":"", rA_addr, rS_addr);
++         DIP("cntlzw%s r%u,r%u\n", flag_rC ? ".":"", rA_addr, rS_addr);
+          
+          // mode64: count in low word only
+-         lo32 = mode64 ? unop(Iop_64to32, mkexpr(rS)) : mkexpr(rS);
+-         
+-         // Iop_Clz32 undefined for arg==0, so deal with that case:
+-         irx =  binop(Iop_CmpNE32, lo32, mkU32(0));
+-         assign(rA, mkWidenFrom32(ty,
+-                         IRExpr_ITE( irx,
+-                                     unop(Iop_Clz32, lo32),
+-                                     mkU32(32)),
+-                         False));
+-
+-         // TODO: alternatively: assign(rA, verbose_Clz32(rS));
++         IRExpr* lo32 = mode64 ? unop(Iop_64to32, mkexpr(rS)) : mkexpr(rS);
++         IRExpr* res32 = unop(Iop_ClzNat32, lo32);
++         assign(rA, mode64 ? unop(Iop_32Uto64, res32) : res32);
+          break;
+       }
+          
+@@ -6521,14 +6490,8 @@ static Bool dis_int_logic ( UInt theInstr )
+             vex_printf("dis_int_logic(ppc)(cntlzd,rB_addr)\n");
+             return False;
+          }
+-         DIP("cntlzd%s r%u,r%u\n",
+-             flag_rC ? ".":"", rA_addr, rS_addr);
+-         // Iop_Clz64 undefined for arg==0, so deal with that case:
+-         irx =  binop(Iop_CmpNE64, mkexpr(rS), mkU64(0));
+-         assign(rA, IRExpr_ITE( irx,
+-                                unop(Iop_Clz64, mkexpr(rS)),
+-                                mkU64(64) ));
+-         // TODO: alternatively: assign(rA, verbose_Clz64(rS));
++         DIP("cntlzd%s r%u,r%u\n", flag_rC ? ".":"", rA_addr, rS_addr);
++         assign(rA, unop(Iop_ClzNat64, mkexpr(rS)));
+          break;
+ 
+       case 0x1FC: // cmpb (Power6: compare bytes)
+@@ -6574,8 +6537,9 @@ static Bool dis_int_logic ( UInt theInstr )
+          putFReg( rS_addr, mkexpr(frA));
+          return True;
+       }
+-      case 0x1FA: // popcntd (population count doubleword
++      case 0x1FA: // popcntd (population count doubleword)
+       {
++          vassert(mode64);
+     	  DIP("popcntd r%u,r%u\n", rA_addr, rS_addr);
+     	  IRTemp result = gen_POPCOUNT(ty, rS, DWORD);
+     	  putIReg( rA_addr, mkexpr(result) );
+@@ -9154,18 +9118,7 @@ static Bool dis_int_shift ( UInt theInstr )
+ static IRExpr* /* :: Ity_I32 */ gen_byterev32 ( IRTemp t )
+ {
+    vassert(typeOfIRTemp(irsb->tyenv, t) == Ity_I32);
+-   return
+-      binop(Iop_Or32,
+-         binop(Iop_Shl32, mkexpr(t), mkU8(24)),
+-      binop(Iop_Or32,
+-         binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)), 
+-                          mkU32(0x00FF0000)),
+-      binop(Iop_Or32,
+-         binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(8)),
+-                          mkU32(0x0000FF00)),
+-         binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(24)),
+-                          mkU32(0x000000FF) )
+-      )));
++   return unop(Iop_Reverse8sIn32_x1, mkexpr(t));
+ }
+ 
+ /* Generates code to swap the byte order in the lower half of an Ity_I32,
+@@ -9225,6 +9178,10 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ 
+       case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed)
+       {
++         // JRS FIXME:
++         // * is the host_endness conditional below actually necessary?
++         // * can we just do a 64-bit load followed by by Iop_Reverse8sIn64_x1?
++         //   That would be a lot more efficient.
+          IRExpr * nextAddr;
+          IRTemp w3 = newTemp( Ity_I32 );
+          IRTemp w4 = newTemp( Ity_I32 );
+@@ -17056,8 +17013,8 @@ dis_av_count_bitTranspose ( UInt theInstr, UInt opc2 )
+       case 0x7C3:    // vpopcntd
+       {
+          if (mode64) {
+-            /* Break vector into 64-bit double words and do the population count
+-             * on each double word.
++            /* Break vector into 64-bit double words and do the population
++               count on each double word.
+              */
+             IRType ty = Ity_I64;
+             IRTemp bits0_63   = newTemp(Ity_I64);
+@@ -17077,15 +17034,16 @@ dis_av_count_bitTranspose ( UInt theInstr, UInt opc2 )
+                                       mkexpr( cnt_bits0_63 ) ) );
+          } else {
+             /* Break vector into 32-bit words and do the population count
+-             * on each doubleword.
++               on each 32-bit word.
+              */
+             IRTemp bits0_31, bits32_63, bits64_95, bits96_127;
+             bits0_31 = bits32_63 = bits64_95 = bits96_127 = IRTemp_INVALID;
+-            IRTemp cnt_bits0_63   = newTemp(Ity_I64);
++            IRTemp cnt_bits0_63    = newTemp(Ity_I64);
+             IRTemp cnt_bits64_127  = newTemp(Ity_I64);
+ 
+             DIP("vpopcntd v%d,v%d\n", vRT_addr, vRB_addr);
+-            breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95, &bits32_63, &bits0_31 );
++            breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95,
++                                         &bits32_63, &bits0_31 );
+ 
+             cnt_bits0_63   = gen_vpopcntd_mode32(bits0_31, bits32_63);
+             cnt_bits64_127 = gen_vpopcntd_mode32(bits64_95, bits96_127);
+@@ -29103,10 +29061,12 @@ DisResult disInstr_PPC_WRK (
+ 
+       /* Miscellaneous ISA 2.06 instructions */
+       case 0x1FA: // popcntd
++         if (!mode64) goto decode_failure;
++         /* else fallthru */
+       case 0x17A: // popcntw
+       case 0x7A:  // popcntb
+-	  if (dis_int_logic( theInstr )) goto decode_success;
+-    	  goto decode_failure;
++         if (dis_int_logic( theInstr )) goto decode_success;
++         goto decode_failure;
+ 
+       case 0x0FC: // bpermd
+          if (!mode64) goto decode_failure;
+@@ -29669,94 +29629,6 @@ DisResult disInstr_PPC ( IRSB*        irsb_IN,
+    return dres;
+ }
+ 
+-
+-/*------------------------------------------------------------*/
+-/*--- Unused stuff                                         ---*/
+-/*------------------------------------------------------------*/
+-
+-///* A potentially more memcheck-friendly implementation of Clz32, with
+-//   the boundary case Clz32(0) = 32, which is what ppc requires. */
+-//
+-//static IRExpr* /* :: Ity_I32 */ verbose_Clz32 ( IRTemp arg )
+-//{
+-//   /* Welcome ... to SSA R Us. */
+-//   IRTemp n1  = newTemp(Ity_I32);
+-//   IRTemp n2  = newTemp(Ity_I32);
+-//   IRTemp n3  = newTemp(Ity_I32);
+-//   IRTemp n4  = newTemp(Ity_I32);
+-//   IRTemp n5  = newTemp(Ity_I32);
+-//   IRTemp n6  = newTemp(Ity_I32);
+-//   IRTemp n7  = newTemp(Ity_I32);
+-//   IRTemp n8  = newTemp(Ity_I32);
+-//   IRTemp n9  = newTemp(Ity_I32);
+-//   IRTemp n10 = newTemp(Ity_I32);
+-//   IRTemp n11 = newTemp(Ity_I32);
+-//   IRTemp n12 = newTemp(Ity_I32);
+-//
+-//   /* First, propagate the most significant 1-bit into all lower
+-//      positions in the word. */
+-//   /* unsigned int clz ( unsigned int n )
+-//      {
+-//         n |= (n >> 1);
+-//         n |= (n >> 2);
+-//         n |= (n >> 4);
+-//         n |= (n >> 8);
+-//         n |= (n >> 16);
+-//         return bitcount(~n);
+-//      }
+-//   */
+-//   assign(n1, mkexpr(arg));
+-//   assign(n2, binop(Iop_Or32, mkexpr(n1), binop(Iop_Shr32, mkexpr(n1), mkU8(1))));
+-//   assign(n3, binop(Iop_Or32, mkexpr(n2), binop(Iop_Shr32, mkexpr(n2), mkU8(2))));
+-//   assign(n4, binop(Iop_Or32, mkexpr(n3), binop(Iop_Shr32, mkexpr(n3), mkU8(4))));
+-//   assign(n5, binop(Iop_Or32, mkexpr(n4), binop(Iop_Shr32, mkexpr(n4), mkU8(8))));
+-//   assign(n6, binop(Iop_Or32, mkexpr(n5), binop(Iop_Shr32, mkexpr(n5), mkU8(16))));
+-//   /* This gives a word of the form 0---01---1.  Now invert it, giving
+-//      a word of the form 1---10---0, then do a population-count idiom
+-//      (to count the 1s, which is the number of leading zeroes, or 32
+-//      if the original word was 0. */
+-//   assign(n7, unop(Iop_Not32, mkexpr(n6)));
+-//
+-//   /* unsigned int bitcount ( unsigned int n )
+-//      {
+-//         n = n - ((n >> 1) & 0x55555555);
+-//         n = (n & 0x33333333) + ((n >> 2) & 0x33333333);
+-//         n = (n + (n >> 4)) & 0x0F0F0F0F;
+-//         n = n + (n >> 8);
+-//         n = (n + (n >> 16)) & 0x3F;
+-//         return n;
+-//      }
+-//   */
+-//   assign(n8, 
+-//          binop(Iop_Sub32, 
+-//                mkexpr(n7),  
+-//                binop(Iop_And32, 
+-//                      binop(Iop_Shr32, mkexpr(n7), mkU8(1)),
+-//                      mkU32(0x55555555))));
+-//   assign(n9,
+-//          binop(Iop_Add32,
+-//                binop(Iop_And32, mkexpr(n8), mkU32(0x33333333)),
+-//                binop(Iop_And32,
+-//                      binop(Iop_Shr32, mkexpr(n8), mkU8(2)),
+-//                      mkU32(0x33333333))));
+-//   assign(n10,
+-//          binop(Iop_And32,
+-//                binop(Iop_Add32, 
+-//                      mkexpr(n9), 
+-//                      binop(Iop_Shr32, mkexpr(n9), mkU8(4))),
+-//                mkU32(0x0F0F0F0F)));
+-//   assign(n11,
+-//          binop(Iop_Add32,
+-//                mkexpr(n10),
+-//                binop(Iop_Shr32, mkexpr(n10), mkU8(8))));
+-//   assign(n12,
+-//          binop(Iop_Add32,
+-//                mkexpr(n11),
+-//                binop(Iop_Shr32, mkexpr(n11), mkU8(16))));
+-//   return
+-//      binop(Iop_And32, mkexpr(n12), mkU32(0x3F));
+-//}
+-
+ /*--------------------------------------------------------------------*/
+ /*--- end                                         guest_ppc_toIR.c ---*/
+ /*--------------------------------------------------------------------*/
diff --git a/SOURCES/valgrind-3.14.0-ppc-instr-new-IROps.patch b/SOURCES/valgrind-3.14.0-ppc-instr-new-IROps.patch
new file mode 100644
index 0000000..4332736
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc-instr-new-IROps.patch
@@ -0,0 +1,257 @@
+commit 97d336b79e36f6c99d8b07f49ebc9b780e6df84e
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 11:07:37 2018 +0100
+
+    Add ppc host-side isel and instruction support for IROps added in previous commit.
+    
+    VEX/priv/host_ppc_defs.c, VEX/priv/host_ppc_defs.h:
+    
+    Dont emit cnttz{w,d}.  We may need them on a target which doesn't support
+    them.  Instead we can generate a fairly reasonable alternative sequence with
+    cntlz{w,d} instead.
+    
+    Add support for emitting popcnt{w,d}.
+    
+    VEX/priv/host_ppc_isel.c
+    
+    Add support for: Iop_ClzNat32 Iop_ClzNat64
+    
+    Redo support for: Iop_Ctz{32,64} and their Nat equivalents, so as to not use
+    cnttz{w,d}, as mentioned above.
+    
+    Add support for: Iop_PopCount64 Iop_PopCount32 Iop_Reverse8sIn32_x1
+
+diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
+index b073c1d..f4b52e4 100644
+--- a/VEX/priv/host_ppc_defs.c
++++ b/VEX/priv/host_ppc_defs.c
+@@ -501,9 +501,9 @@ const HChar* showPPCUnaryOp ( PPCUnaryOp op ) {
+    case Pun_NEG:   return "neg";
+    case Pun_CLZ32: return "cntlzw";
+    case Pun_CLZ64: return "cntlzd";
+-   case Pun_CTZ32: return "cnttzw";
+-   case Pun_CTZ64: return "cnttzd";
+    case Pun_EXTSW: return "extsw";
++   case Pun_POP32: return "popcntw";
++   case Pun_POP64: return "popcntd";
+    default: vpanic("showPPCUnaryOp");
+    }
+ }
+@@ -4265,20 +4265,19 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
+          vassert(mode64);
+          p = mkFormX(p, 31, r_src, r_dst, 0, 58, 0, endness_host);
+          break;
+-      case Pun_CTZ32:  // cnttzw r_dst, r_src
+-         /* Note oder of src and dst is backwards from normal */
+-         p = mkFormX(p, 31, r_src, r_dst, 0, 538, 0, endness_host);
+-         break;
+-      case Pun_CTZ64:  // cnttzd r_dst, r_src
+-         /* Note oder of src and dst is backwards from normal */
+-         vassert(mode64);
+-         p = mkFormX(p, 31, r_src, r_dst, 0, 570, 0, endness_host);
+-         break;
+       case Pun_EXTSW:  // extsw r_dst, r_src
+          vassert(mode64);
+          p = mkFormX(p, 31, r_src, r_dst, 0, 986, 0, endness_host);
+          break;
+-      default: goto bad;
++      case Pun_POP32:  // popcntw r_dst, r_src
++         p = mkFormX(p, 31, r_src, r_dst, 0, 378, 0, endness_host);
++         break;
++      case Pun_POP64:  // popcntd r_dst, r_src
++         vassert(mode64);
++         p = mkFormX(p, 31, r_src, r_dst, 0, 506, 0, endness_host);
++         break;
++      default:
++         goto bad;
+       }
+       goto done;
+    }
+diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h
+index 17baff5..321fba9 100644
+--- a/VEX/priv/host_ppc_defs.h
++++ b/VEX/priv/host_ppc_defs.h
+@@ -291,9 +291,9 @@ typedef
+       Pun_NOT,
+       Pun_CLZ32,
+       Pun_CLZ64,
+-      Pun_CTZ32,
+-      Pun_CTZ64,
+-      Pun_EXTSW
++      Pun_EXTSW,
++      Pun_POP32, // popcntw
++      Pun_POP64  // popcntd
+    }
+    PPCUnaryOp;
+ 
+diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
+index 6bdb5f7..5242176 100644
+--- a/VEX/priv/host_ppc_isel.c
++++ b/VEX/priv/host_ppc_isel.c
+@@ -2065,12 +2065,15 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
+             return r_dst;
+          }
+          break;
+-      case Iop_Clz32:
+-      case Iop_Clz64: {
++
++      case Iop_Clz32: case Iop_ClzNat32:
++      case Iop_Clz64: case Iop_ClzNat64: {
++         // cntlz is available even in the most basic (earliest) ppc
++         // variants, so it's safe to generate it unconditionally.
+          HReg r_src, r_dst;
+-         PPCUnaryOp op_clz = (op_unop == Iop_Clz32) ? Pun_CLZ32 :
+-                                                      Pun_CLZ64;
+-         if (op_unop == Iop_Clz64 && !mode64)
++         PPCUnaryOp op_clz = (op_unop == Iop_Clz32 || op_unop == Iop_ClzNat32)
++                                ? Pun_CLZ32 : Pun_CLZ64;
++         if ((op_unop == Iop_Clz64 || op_unop == Iop_ClzNat64) && !mode64)
+             goto irreducible;
+          /* Count leading zeroes. */
+          r_dst = newVRegI(env);
+@@ -2079,18 +2082,133 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
+          return r_dst;
+       }
+ 
+-      case Iop_Ctz32:
+-      case Iop_Ctz64: {
+-         HReg r_src, r_dst;
+-         PPCUnaryOp op_clz = (op_unop == Iop_Ctz32) ? Pun_CTZ32 :
+-                                                      Pun_CTZ64;
+-         if (op_unop == Iop_Ctz64 && !mode64)
+-            goto irreducible;
+-         /* Count trailing zeroes. */
+-         r_dst = newVRegI(env);
+-         r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
+-         addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
+-         return r_dst;
++      //case Iop_Ctz32:
++      case Iop_CtzNat32:
++      //case Iop_Ctz64:
++      case Iop_CtzNat64:
++      {
++         // Generate code using Clz, because we can't assume the host has
++         // Ctz.  In particular, part of the fix for bug 386945 involves
++         // creating a Ctz in ir_opt.c from smaller fragments.
++         PPCUnaryOp op_clz = Pun_CLZ64;
++         Int WS = 64;
++         if (op_unop == Iop_Ctz32 || op_unop == Iop_CtzNat32) {
++            op_clz = Pun_CLZ32;
++            WS = 32;
++         }
++         /* Compute ctz(arg) = wordsize - clz(~arg & (arg - 1)), thusly:
++            t1 = arg - 1
++            t2 = not arg
++            t2 = t2 & t1
++            t2 = clz t2
++            t1 = WS
++            t2 = t1 - t2
++            // result in t2
++         */
++         HReg arg = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
++         HReg t1 = newVRegI(env);
++         HReg t2 = newVRegI(env);
++         addInstr(env, PPCInstr_Alu(Palu_SUB, t1, arg, PPCRH_Imm(True, 1)));
++         addInstr(env, PPCInstr_Unary(Pun_NOT, t2, arg));
++         addInstr(env, PPCInstr_Alu(Palu_AND, t2, t2, PPCRH_Reg(t1)));
++         addInstr(env, PPCInstr_Unary(op_clz, t2, t2));
++         addInstr(env, PPCInstr_LI(t1, WS, False/*!64-bit imm*/));
++         addInstr(env, PPCInstr_Alu(Palu_SUB, t2, t1, PPCRH_Reg(t2)));
++         return t2;
++      }
++
++      case Iop_PopCount64: {
++         // popcnt{x,d} is only available in later arch revs (ISA 3.0,
++         // maybe) so it's not really correct to emit it here without a caps
++         // check for the host.
++         if (mode64) {
++            HReg r_dst = newVRegI(env);
++            HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
++            addInstr(env, PPCInstr_Unary(Pun_POP64, r_dst, r_src));
++            return r_dst;
++         }
++         // We don't expect to be required to handle this in 32-bit mode.
++         break;
++      }
++
++      case Iop_PopCount32: {
++         // Similar comment as for Ctz just above applies -- we really
++         // should have a caps check here.
++
++        HReg r_dst = newVRegI(env);
++        // This actually generates popcntw, which in 64 bit mode does a
++        // 32-bit count individually for both low and high halves of the
++        // word.  Per the comment at the top of iselIntExpr_R, in the 64
++        // bit mode case, the user of this result is required to ignore
++        // the upper 32 bits of the result.  In 32 bit mode this is all
++        // moot.  It is however unclear from the PowerISA 3.0 docs that
++        // the instruction exists in 32 bit mode; however our own front
++        // end (guest_ppc_toIR.c) accepts it, so I guess it does exist.
++        HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
++        addInstr(env, PPCInstr_Unary(Pun_POP32, r_dst, r_src));
++        return r_dst;
++      }
++
++      case Iop_Reverse8sIn32_x1: {
++         // A bit of a mouthful, but simply .. 32-bit byte swap.
++         // This is pretty rubbish code.  We could do vastly better if
++         // rotates, and better, rotate-inserts, were allowed.  Note that
++         // even on a 64 bit target, the right shifts must be done as 32-bit
++         // so as to introduce zero bits in the right places.  So it seems
++         // simplest to do the whole sequence in 32-bit insns.
++         /*
++            r     = <argument>  // working temporary, initial byte order ABCD
++            Mask  = 00FF00FF
++            nMask = not Mask
++            tHi   = and r, Mask
++            tHi   = shl tHi, 8
++            tLo   = and r, nMask
++            tLo   = shr tLo, 8
++            r     = or tHi, tLo  // now r has order BADC
++            and repeat for 16 bit chunks ..
++            Mask  = 0000FFFF
++            nMask = not Mask
++            tHi   = and r, Mask
++            tHi   = shl tHi, 16
++            tLo   = and r, nMask
++            tLo   = shr tLo, 16
++            r     = or tHi, tLo  // now r has order DCBA
++         */
++         HReg r_src  = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
++         HReg rr     = newVRegI(env);
++         HReg rMask  = newVRegI(env);
++         HReg rnMask = newVRegI(env);
++         HReg rtHi   = newVRegI(env);
++         HReg rtLo   = newVRegI(env);
++         // Copy r_src since we need to modify it
++         addInstr(env, mk_iMOVds_RR(rr, r_src));
++         // Swap within 16-bit lanes
++         addInstr(env, PPCInstr_LI(rMask, 0x00FF00FFULL,
++                                   False/* !64bit imm*/));
++         addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32 bit shift*/,
++                                     rtHi, rtHi,
++                                     PPCRH_Imm(False/*!signed imm*/, 8)));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32 bit shift*/,
++                                     rtLo, rtLo,
++                                     PPCRH_Imm(False/*!signed imm*/, 8)));
++         addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
++         // And now swap the two 16-bit chunks
++         addInstr(env, PPCInstr_LI(rMask, 0x0000FFFFULL,
++                                   False/* !64bit imm*/));
++         addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32 bit shift*/,
++                                     rtHi, rtHi,
++                                     PPCRH_Imm(False/*!signed imm*/, 16)));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32 bit shift*/,
++                                     rtLo, rtLo,
++                                     PPCRH_Imm(False/*!signed imm*/, 16)));
++         addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
++         return rr;
+       }
+ 
+       case Iop_Left8:
diff --git a/SOURCES/valgrind-3.14.0-ppc-subfe.patch b/SOURCES/valgrind-3.14.0-ppc-subfe.patch
new file mode 100644
index 0000000..301dd8c
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc-subfe.patch
@@ -0,0 +1,43 @@
+commit 256cf43c5eadb28edb45436aca6fda8ee55eb10e
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Thu Feb 21 17:21:53 2019 +0100
+
+    memcheck powerpc subfe x, x, x initializes x to 0 or -1 based on CA
+    
+    GCC might use subfe x, x, x to initialize x to 0 or -1, based on
+    whether the carry flag is set. This happens in some cases when g++
+    compiles resetting a unique_ptr. The "trick" used by the compiler is
+    that it can AND a pointer with the register x (now 0x0 or 0xffffffff)
+    to set something to NULL or to the given pointer.
+    
+    subfe is implemented as rD = (log not)rA + rB + XER[CA]
+    if we instead implement it as rD = rB - rA - (XER[CA] ^ 1)
+    then memcheck can see that rB and Ra cancel each other out if they
+    are the same.
+    
+    https://bugs.kde.org/show_bug.cgi?id=404054
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index e207642..00ae6df 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -5361,11 +5361,15 @@ static Bool dis_int_arith ( UInt theInstr )
+              flag_OE ? "o" : "", flag_rC ? ".":"",
+              rD_addr, rA_addr, rB_addr);
+          // rD = (log not)rA + rB + XER[CA]
++         //    ==>
++         // rD = rB - rA - (XER[CA] ^ 1)
+          assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
+-         assign( rD, binop( mkSzOp(ty, Iop_Add8),
+-                            unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)),
+-                            binop( mkSzOp(ty, Iop_Add8),
+-                                   mkexpr(rB), mkexpr(old_xer_ca))) );
++         assign( rD, binop( mkSzOp(ty, Iop_Sub8),
++                            binop( mkSzOp(ty, Iop_Sub8),
++                                   mkexpr(rB), mkexpr(rA)),
++                            binop(mkSzOp(ty, Iop_Xor8),
++                                  mkexpr(old_xer_ca),
++                                  mkSzImm(ty, 1))) );
+          set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+                           mkexpr(rD), mkexpr(rA), mkexpr(rB),
+                           mkexpr(old_xer_ca) );
diff --git a/SOURCES/valgrind-3.14.0-ppc64-ldbrx.patch b/SOURCES/valgrind-3.14.0-ppc64-ldbrx.patch
new file mode 100644
index 0000000..d4f5ab8
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-ldbrx.patch
@@ -0,0 +1,130 @@
+commit 7bdd6731f8337fd57bf91772aa1917e44239d7c2
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Fri Dec 7 10:42:22 2018 -0500
+
+    Implement ppc64 ldbrx as 64-bit load and Iop_Reverse8sIn64_x1.
+    
+    This makes it possible for memcheck to analyse the new gcc strcmp
+    inlined code correctly even if the ldbrx load is partly beyond an
+    addressable block.
+    
+    Partially resolves bug 386945.
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index 8977d4f..a81dace 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -9178,24 +9178,28 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ 
+       case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed)
+       {
+-         // JRS FIXME:
+-         // * is the host_endness conditional below actually necessary?
+-         // * can we just do a 64-bit load followed by by Iop_Reverse8sIn64_x1?
+-         //   That would be a lot more efficient.
+-         IRExpr * nextAddr;
+-         IRTemp w3 = newTemp( Ity_I32 );
+-         IRTemp w4 = newTemp( Ity_I32 );
+-         DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+-         assign( w1, load( Ity_I32, mkexpr( EA ) ) );
+-         assign( w2, gen_byterev32( w1 ) );
+-         nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+-                           ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );
+-         assign( w3, load( Ity_I32, nextAddr ) );
+-         assign( w4, gen_byterev32( w3 ) );
+-         if (host_endness == VexEndnessLE)
+-            putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) );
++         /* Caller makes sure we are only called in mode64. */
++
++         /* If we supported swapping LE/BE loads in the backend then we could
++            just load the value with the bytes reversed by doing a BE load
++            on an LE machine and a LE load on a BE machine.
++
++         IRTemp dw1 = newTemp(Ity_I64);
++         if (host_endness == VexEndnessBE)
++            assign( dw1, IRExpr_Load(Iend_LE, Ity_I64, mkexpr(EA)));
+          else
+-            putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
++            assign( dw1, IRExpr_Load(Iend_BE, Ity_I64, mkexpr(EA)));
++         putIReg( rD_addr, mkexpr(dw1) );
++
++         But since we currently don't we load the value as is and then
++         switch it around with Iop_Reverse8sIn64_x1. */
++
++         IRTemp dw1 = newTemp(Ity_I64);
++         IRTemp dw2 = newTemp(Ity_I64);
++         DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
++         assign( dw1, load(Ity_I64, mkexpr(EA)) );
++         assign( dw2, unop(Iop_Reverse8sIn64_x1, mkexpr(dw1)) );
++         putIReg( rD_addr, mkexpr(dw2) );
+          break;
+       }
+ 
+diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
+index 750cf8d..4fc3eb5 100644
+--- a/VEX/priv/host_ppc_isel.c
++++ b/VEX/priv/host_ppc_isel.c
+@@ -2210,6 +2210,63 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
+          return rr;
+       }
+ 
++      case Iop_Reverse8sIn64_x1: {
++	 /* See Iop_Reverse8sIn32_x1, but extended to 64bit.
++            Can only be used in 64bit mode.  */
++         vassert (mode64);
++
++         HReg r_src  = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
++         HReg rr     = newVRegI(env);
++         HReg rMask  = newVRegI(env);
++         HReg rnMask = newVRegI(env);
++         HReg rtHi   = newVRegI(env);
++         HReg rtLo   = newVRegI(env);
++
++         // Copy r_src since we need to modify it
++         addInstr(env, mk_iMOVds_RR(rr, r_src));
++
++         // r = (r & 0x00FF00FF00FF00FF) << 8 | (r & 0xFF00FF00FF00FF00) >> 8
++         addInstr(env, PPCInstr_LI(rMask, 0x00FF00FF00FF00FFULL,
++                                   True/* 64bit imm*/));
++         addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
++                                     rtHi, rtHi,
++                                     PPCRH_Imm(False/*!signed imm*/, 8)));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
++                                     rtLo, rtLo,
++                                     PPCRH_Imm(False/*!signed imm*/, 8)));
++         addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
++
++         // r = (r & 0x0000FFFF0000FFFF) << 16 | (r & 0xFFFF0000FFFF0000) >> 16
++         addInstr(env, PPCInstr_LI(rMask, 0x0000FFFF0000FFFFULL,
++                                   True/* !64bit imm*/));
++         addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
++                                     rtHi, rtHi,
++                                     PPCRH_Imm(False/*!signed imm*/, 16)));
++         addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
++                                     rtLo, rtLo,
++                                     PPCRH_Imm(False/*!signed imm*/, 16)));
++         addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
++
++         // r = (r & 0x00000000FFFFFFFF) << 32 | (r & 0xFFFFFFFF00000000) >> 32
++         /* We don't need to mask anymore, just two more shifts and an or.  */
++         addInstr(env, mk_iMOVds_RR(rtLo, rr));
++         addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
++                                     rtLo, rtLo,
++                                     PPCRH_Imm(False/*!signed imm*/, 32)));
++         addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
++                                     rr, rr,
++                                     PPCRH_Imm(False/*!signed imm*/, 32)));
++         addInstr(env, PPCInstr_Alu(Palu_OR, rr, rr, PPCRH_Reg(rtLo)));
++
++         return rr;
++      }
++
+       case Iop_Left8:
+       case Iop_Left16:
+       case Iop_Left32: 
diff --git a/SOURCES/valgrind-3.14.0-ppc64-lxvb16x.patch b/SOURCES/valgrind-3.14.0-ppc64-lxvb16x.patch
new file mode 100644
index 0000000..e821d81
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-lxvb16x.patch
@@ -0,0 +1,88 @@
+commit 5c00e04a1b61475a7f731f8cfede114201815e0a
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Sun Dec 9 23:25:05 2018 +0100
+
+    Implement ppc64 lxvb16x as 128-bit vector load with reversed double words.
+    
+    This makes it possible for memcheck to know which part of the 128bit
+    vector is defined, even if the load is partly beyond an addressable block.
+    
+    Partially resolves bug 386945.
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index 7af4973..ec2f90a 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -20702,54 +20702,29 @@ dis_vx_load ( UInt theInstr )
+    {
+       DIP("lxvb16x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+ 
+-      IRTemp byte[16];
+-      int i;
+-      UInt ea_off = 0;
+-      IRExpr* irx_addr;
+-      IRTemp tmp_low[9];
+-      IRTemp tmp_hi[9];
++      /* The result of lxvb16x should be the same on big and little
++         endian systems. We do a host load, then reverse the bytes in
++         the double words. If the host load was little endian we swap
++         them around again. */
+ 
+-      tmp_low[0] = newTemp( Ity_I64 );
+-      tmp_hi[0] = newTemp( Ity_I64 );
+-      assign( tmp_low[0], mkU64( 0 ) );
+-      assign( tmp_hi[0], mkU64( 0 ) );
+-
+-      for ( i = 0; i < 8; i++ ) {
+-         byte[i] = newTemp( Ity_I64 );
+-         tmp_low[i+1] = newTemp( Ity_I64 );
+-
+-         irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+-                           ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+-         ea_off += 1;
+-
+-         assign( byte[i], binop( Iop_Shl64,
+-                                 unop( Iop_8Uto64,
+-                                       load( Ity_I8, irx_addr ) ),
+-                                 mkU8( 8 * ( 7 - i ) ) ) );
++      IRTemp high = newTemp(Ity_I64);
++      IRTemp high_rev = newTemp(Ity_I64);
++      IRTemp low = newTemp(Ity_I64);
++      IRTemp low_rev = newTemp(Ity_I64);
+ 
+-         assign( tmp_low[i+1],
+-                 binop( Iop_Or64,
+-                        mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
+-      }
++      IRExpr *t128 = load( Ity_V128, mkexpr( EA ) );
+ 
+-      for ( i = 0; i < 8; i++ ) {
+-         byte[i + 8] = newTemp( Ity_I64 );
+-         tmp_hi[i+1] = newTemp( Ity_I64 );
++      assign( high, unop(Iop_V128HIto64, t128) );
++      assign( high_rev, unop(Iop_Reverse8sIn64_x1, mkexpr(high)) );
++      assign( low, unop(Iop_V128to64, t128) );
++      assign( low_rev, unop(Iop_Reverse8sIn64_x1, mkexpr(low)) );
+ 
+-         irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+-                           ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+-         ea_off += 1;
++      if (host_endness == VexEndnessLE)
++         t128 = binop( Iop_64HLtoV128, mkexpr (low_rev), mkexpr (high_rev) );
++      else
++         t128 = binop( Iop_64HLtoV128, mkexpr (high_rev), mkexpr (low_rev) );
+ 
+-         assign( byte[i+8], binop( Iop_Shl64,
+-                                   unop( Iop_8Uto64,
+-                                         load( Ity_I8, irx_addr ) ),
+-                                   mkU8( 8 * ( 7 - i ) ) ) );
+-         assign( tmp_hi[i+1], binop( Iop_Or64,
+-                                     mkexpr( byte[i+8] ),
+-                                     mkexpr( tmp_hi[i] ) ) );
+-      }
+-      putVSReg( XT, binop( Iop_64HLtoV128,
+-                           mkexpr( tmp_low[8] ), mkexpr( tmp_hi[8] ) ) );
++      putVSReg( XT, t128 );
+       break;
+    }
+ 
diff --git a/SOURCES/valgrind-3.14.0-ppc64-lxvd2x.patch b/SOURCES/valgrind-3.14.0-ppc64-lxvd2x.patch
new file mode 100644
index 0000000..cf2aa0c
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-lxvd2x.patch
@@ -0,0 +1,47 @@
+commit b7d65cab4f3e9a6f66a496e723e53ed736c4d2e7
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Sun Dec 9 00:55:42 2018 +0100
+
+    Implement ppc64 lxvd2x as 128-bit load with double word swap for ppc64le.
+    
+    This makes it possible for memcheck to know which part of the 128bit
+    vector is defined, even if the load is partly beyond an addressable block.
+    
+    Partially resolves bug 386945.
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index a81dace..7af4973 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -20590,16 +20590,22 @@ dis_vx_load ( UInt theInstr )
+    }
+    case 0x34C: // lxvd2x
+    {
+-      IROp addOp = ty == Ity_I64 ? Iop_Add64 : Iop_Add32;
+-      IRExpr * high, *low;
+-      ULong ea_off = 8;
+-      IRExpr* high_addr;
++      IRExpr *t128;
+       DIP("lxvd2x %d,r%u,r%u\n", XT, rA_addr, rB_addr);
+-      high = load( Ity_I64, mkexpr( EA ) );
+-      high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off )
+-            : mkU32( ea_off ) );
+-      low = load( Ity_I64, high_addr );
+-      putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
++      t128 = load( Ity_V128, mkexpr( EA ) );
++
++      /* The data in the vec register should be in big endian order.
++         So if we just did a little endian load then swap around the
++         high and low double words. */
++      if (host_endness == VexEndnessLE) {
++         IRTemp high = newTemp(Ity_I64);
++         IRTemp low = newTemp(Ity_I64);
++         assign( high, unop(Iop_V128HIto64, t128) );
++         assign( low, unop(Iop_V128to64, t128) );
++         t128 = binop( Iop_64HLtoV128, mkexpr (low), mkexpr (high) );
++      }
++
++      putVSReg( XT, t128 );
+       break;
+    }
+    case 0x14C: // lxvdsx
diff --git a/SOURCES/valgrind-3.14.0-ppc64-ptrace.patch b/SOURCES/valgrind-3.14.0-ppc64-ptrace.patch
new file mode 100644
index 0000000..5ce2a7e
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-ptrace.patch
@@ -0,0 +1,111 @@
+commit 3967a99c26e8b314634a6b1fd8927cbb2bb5d060
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Wed Dec 12 14:11:29 2018 +0100
+
+    Implement minimal ptrace support for ppc64[le]-linux.
+
+diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+index 6549dd1..0fdcc8e 100644
+--- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
++++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+@@ -388,6 +388,7 @@ DECL_TEMPLATE(ppc64_linux, sys_mmap);
+ //zz DECL_TEMPLATE(ppc64_linux, sys_sigreturn);
+ DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn);
+ DECL_TEMPLATE(ppc64_linux, sys_fadvise64);
++DECL_TEMPLATE(ppc64_linux, sys_ptrace);
+ 
+ PRE(sys_mmap)
+ {
+@@ -511,6 +512,72 @@ PRE(sys_rt_sigreturn)
+    *flags |= SfPollAfter;
+ }
+ 
++// ARG3 is only used for pointers into the traced process's address
++// space and for offsets into the traced process's struct
++// user_regs_struct. It is never a pointer into this process's memory
++// space, and we should therefore not check anything it points to.
++// powerpc does have other ways to get/set registers, we only support
++// GET/SETREGSET for now.
++PRE(sys_ptrace)
++{
++   PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4);
++   PRE_REG_READ4(int, "ptrace",
++                 long, request, long, pid, long, addr, long, data);
++   switch (ARG1) {
++   case VKI_PTRACE_PEEKTEXT:
++   case VKI_PTRACE_PEEKDATA:
++   case VKI_PTRACE_PEEKUSR:
++      PRE_MEM_WRITE( "ptrace(peek)", ARG4,
++                     sizeof (long));
++      break;
++   case VKI_PTRACE_GETEVENTMSG:
++      PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long));
++      break;
++   case VKI_PTRACE_GETSIGINFO:
++      PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t));
++      break;
++   case VKI_PTRACE_SETSIGINFO:
++      PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t));
++      break;
++   case VKI_PTRACE_GETREGSET:
++      ML_(linux_PRE_getregset)(tid, ARG3, ARG4);
++      break;
++   case VKI_PTRACE_SETREGSET:
++      ML_(linux_PRE_setregset)(tid, ARG3, ARG4);
++      break;
++   default:
++      break;
++   }
++}
++
++POST(sys_ptrace)
++{
++   switch (ARG1) {
++   case VKI_PTRACE_TRACEME:
++      ML_(linux_POST_traceme)(tid);
++      break;
++   case VKI_PTRACE_PEEKTEXT:
++   case VKI_PTRACE_PEEKDATA:
++   case VKI_PTRACE_PEEKUSR:
++      POST_MEM_WRITE( ARG4, sizeof (long));
++      break;
++   case VKI_PTRACE_GETEVENTMSG:
++      POST_MEM_WRITE( ARG4, sizeof(unsigned long));
++      break;
++   case VKI_PTRACE_GETSIGINFO:
++      /* XXX: This is a simplification. Different parts of the
++       * siginfo_t are valid depending on the type of signal.
++       */
++      POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t));
++      break;
++   case VKI_PTRACE_GETREGSET:
++      ML_(linux_POST_getregset)(tid, ARG3, ARG4);
++      break;
++   default:
++      break;
++   }
++}
++
+ #undef PRE
+ #undef POST
+ 
+@@ -562,8 +629,7 @@ static SyscallTableEntry syscall_table[] = {
+    GENX_(__NR_getuid,            sys_getuid),             //  24
+ 
+ // _____(__NR_stime,             sys_stime),              //  25
+-// When ptrace is supported, memcheck/tests/linux/getregset should be enabled
+-// _____(__NR_ptrace,            sys_ptrace),             //  26
++   PLAXY(__NR_ptrace,            sys_ptrace),             //  26
+    GENX_(__NR_alarm,             sys_alarm),              //  27
+ // _____(__NR_oldfstat,          sys_oldfstat),           //  28
+    GENX_(__NR_pause,             sys_pause),              //  29
+diff --git a/memcheck/tests/linux/getregset.vgtest b/memcheck/tests/linux/getregset.vgtest
+index 4c66108..c35be4c 100644
+--- a/memcheck/tests/linux/getregset.vgtest
++++ b/memcheck/tests/linux/getregset.vgtest
+@@ -1,4 +1,4 @@
+ prog: getregset
+ vgopts: -q
+-prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 ) && ! ../../../tests/arch_test ppc64
++prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 )
+ 
diff --git a/SOURCES/valgrind-3.14.0-ppc64-quotactl.patch b/SOURCES/valgrind-3.14.0-ppc64-quotactl.patch
new file mode 100644
index 0000000..87b4033
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-quotactl.patch
@@ -0,0 +1,22 @@
+commit 7f74ba249ead48f351676c37d498b17305212123
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Mon Mar 4 17:22:56 2019 +0100
+
+    Bug 405079 - unhandled ppc64le-linux syscall: 131 (quotactl)
+    
+    quotactl is really a "generic" linux syscall that just happened to not
+    have been hooked up for ppc64le. Add it to syswrap-ppc64-linux.c.
+
+diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+index 0fdcc8e..eada099 100644
+--- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
++++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+@@ -755,7 +755,7 @@ static SyscallTableEntry syscall_table[] = {
+    LINX_(__NR_delete_module,     sys_delete_module),      // 129
+ 
+ // _____(__NR_get_kernel_syms,   sys_get_kernel_syms),    // 130
+-// _____(__NR_quotactl,          sys_quotactl),           // 131
++   LINX_(__NR_quotactl,          sys_quotactl),           // 131
+    GENX_(__NR_getpgid,           sys_getpgid),            // 132
+    GENX_(__NR_fchdir,            sys_fchdir),             // 133
+ // _____(__NR_bdflush,           sys_bdflush),            // 134
diff --git a/SOURCES/valgrind-3.14.0-ppc64-unaligned-vecs.patch b/SOURCES/valgrind-3.14.0-ppc64-unaligned-vecs.patch
new file mode 100644
index 0000000..00c64fc
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-unaligned-vecs.patch
@@ -0,0 +1,28 @@
+commit 321771ee63740333ad355244e0764295218843b8
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Sun Dec 9 14:26:39 2018 +0100
+
+    memcheck: Allow unaligned loads of 128bit vectors on ppc64[le].
+    
+    On powerpc partial unaligned loads of vectors from partially invalid
+    addresses are OK and could be generated by our translation of lxvd2x.
+    
+    Adjust partial_load memcheck tests to allow partial loads of 16 byte
+    vectors on powerpc64.
+    
+    Part of resolving bug #386945.
+
+diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
+index 737f79d..101916b 100644
+--- a/memcheck/mc_main.c
++++ b/memcheck/mc_main.c
+@@ -1354,6 +1354,9 @@ void mc_LOADV_128_or_256_slow ( /*OUT*/ULong* res,
+    tl_assert(szB == 16); // s390 doesn't have > 128 bit SIMD
+    /* OK if all loaded bytes are from the same page. */
+    Bool alignedOK = ((a & 0xfff) <= 0x1000 - szB);
++#  elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
++   /* lxvd2x might generate an unaligned 128 bit vector load.  */
++   Bool alignedOK = (szB == 16);
+ #  else
+    /* OK if the address is aligned by the load size. */
+    Bool alignedOK = (0 == (a & (szB - 1)));
diff --git a/SOURCES/valgrind-3.14.0-ppc64-unaligned-words.patch b/SOURCES/valgrind-3.14.0-ppc64-unaligned-words.patch
new file mode 100644
index 0000000..75c8bf6
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-ppc64-unaligned-words.patch
@@ -0,0 +1,148 @@
+commit c5a5bea00af75f6ac50da10967d956f117b956f1
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Sat Dec 8 13:47:43 2018 -0500
+
+    memcheck: Allow unaligned loads of words on ppc64[le].
+    
+    On powerpc partial unaligned loads of words from partially invalid
+    addresses are OK and could be generated by our translation of ldbrx.
+    
+    Adjust partial_load memcheck tests to allow partial loads of words
+    on powerpc64.
+    
+    Part of resolving bug #386945.
+
+diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
+index 3ef7cb9..737f79d 100644
+--- a/memcheck/mc_main.c
++++ b/memcheck/mc_main.c
+@@ -1508,6 +1508,9 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian )
+ #  if defined(VGA_mips64) && defined(VGABI_N32)
+    if (szB == VG_WORDSIZE * 2 && VG_IS_WORD_ALIGNED(a)
+        && n_addrs_bad < VG_WORDSIZE * 2)
++#  elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
++   /* On power unaligned loads of words are OK. */
++   if (szB == VG_WORDSIZE && n_addrs_bad < VG_WORDSIZE)
+ #  else
+    if (szB == VG_WORDSIZE && VG_IS_WORD_ALIGNED(a)
+        && n_addrs_bad < VG_WORDSIZE)
+diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
+index 2af4dd1..70b8ada 100644
+--- a/memcheck/tests/Makefile.am
++++ b/memcheck/tests/Makefile.am
+@@ -235,8 +235,10 @@ EXTRA_DIST = \
+ 	partiallydefinedeq.stdout.exp \
+ 	partial_load_ok.vgtest partial_load_ok.stderr.exp \
+ 		partial_load_ok.stderr.exp64 \
++		partial_load_ok.stderr.exp-ppc64 \
+ 	partial_load_dflt.vgtest partial_load_dflt.stderr.exp \
+ 		partial_load_dflt.stderr.exp64 \
++		partial_load_dflt.stderr.exp-ppc64 \
+ 	partial_load_dflt.stderr.expr-s390x-mvc \
+ 	pdb-realloc.stderr.exp pdb-realloc.vgtest \
+ 	pdb-realloc2.stderr.exp pdb-realloc2.stdout.exp pdb-realloc2.vgtest \
+diff --git a/memcheck/tests/partial_load.c b/memcheck/tests/partial_load.c
+index 0b2f10b..685ca8d 100644
+--- a/memcheck/tests/partial_load.c
++++ b/memcheck/tests/partial_load.c
+@@ -1,14 +1,14 @@
+-
++#include <stdio.h>
+ #include <stdlib.h>
+ #include <assert.h>
+ 
+ int main ( void )
+ {
+-  long  w;
+-  int   i;
+-  char* p;
+-
++  long  w; int   i; char* p;
+   assert(sizeof(long) == sizeof(void*));
++#if defined(__powerpc64__)
++  fprintf (stderr, "powerpc64\n"); /* Used to select correct .exp file.  */
++#endif
+ 
+   /* partial load, which --partial-loads-ok=yes should suppress */
+   p = calloc( sizeof(long)-1, 1 );
+@@ -16,7 +16,7 @@ int main ( void )
+   w = *(long*)p;
+   free(p);
+ 
+-  /* partial but misaligned, cannot be suppressed */
++  /* partial but misaligned, ppc64[le] ok, but otherwise cannot be suppressed */
+   p = calloc( sizeof(long), 1 );
+   assert(p);
+   p++;
+diff --git a/memcheck/tests/partial_load_dflt.stderr.exp-ppc64 b/memcheck/tests/partial_load_dflt.stderr.exp-ppc64
+new file mode 100644
+index 0000000..cf32bcf
+--- /dev/null
++++ b/memcheck/tests/partial_load_dflt.stderr.exp-ppc64
+@@ -0,0 +1,23 @@
++
++powerpc64
++Invalid read of size 2
++   at 0x........: main (partial_load.c:30)
++ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
++   at 0x........: calloc (vg_replace_malloc.c:...)
++   by 0x........: main (partial_load.c:28)
++
++Invalid read of size 8
++   at 0x........: main (partial_load.c:37)
++ Address 0x........ is 0 bytes inside a block of size 8 free'd
++   at 0x........: free (vg_replace_malloc.c:...)
++   by 0x........: main (partial_load.c:36)
++
++
++HEAP SUMMARY:
++    in use at exit: ... bytes in ... blocks
++  total heap usage: ... allocs, ... frees, ... bytes allocated
++
++For a detailed leak analysis, rerun with: --leak-check=full
++
++For counts of detected and suppressed errors, rerun with: -v
++ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
+diff --git a/memcheck/tests/partial_load_ok.stderr.exp-ppc64 b/memcheck/tests/partial_load_ok.stderr.exp-ppc64
+new file mode 100644
+index 0000000..cf32bcf
+--- /dev/null
++++ b/memcheck/tests/partial_load_ok.stderr.exp-ppc64
+@@ -0,0 +1,23 @@
++
++powerpc64
++Invalid read of size 2
++   at 0x........: main (partial_load.c:30)
++ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
++   at 0x........: calloc (vg_replace_malloc.c:...)
++   by 0x........: main (partial_load.c:28)
++
++Invalid read of size 8
++   at 0x........: main (partial_load.c:37)
++ Address 0x........ is 0 bytes inside a block of size 8 free'd
++   at 0x........: free (vg_replace_malloc.c:...)
++   by 0x........: main (partial_load.c:36)
++
++
++HEAP SUMMARY:
++    in use at exit: ... bytes in ... blocks
++  total heap usage: ... allocs, ... frees, ... bytes allocated
++
++For a detailed leak analysis, rerun with: --leak-check=full
++
++For counts of detected and suppressed errors, rerun with: -v
++ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
+diff -ur valgrind-3.14.0.orig/memcheck/tests/Makefile.in valgrind-3.14.0/memcheck/tests/Makefile.in
+--- valgrind-3.14.0.orig/memcheck/tests/Makefile.in	2018-12-12 23:17:07.525501080 +0100
++++ valgrind-3.14.0/memcheck/tests/Makefile.in	2018-12-12 23:18:13.404014757 +0100
+@@ -1546,8 +1546,10 @@
+ 	partiallydefinedeq.stdout.exp \
+ 	partial_load_ok.vgtest partial_load_ok.stderr.exp \
+ 		partial_load_ok.stderr.exp64 \
++		partial_load_ok.stderr.exp-ppc64 \
+ 	partial_load_dflt.vgtest partial_load_dflt.stderr.exp \
+ 		partial_load_dflt.stderr.exp64 \
++		partial_load_dflt.stderr.exp-ppc64 \
+ 	partial_load_dflt.stderr.expr-s390x-mvc \
+ 	pdb-realloc.stderr.exp pdb-realloc.vgtest \
+ 	pdb-realloc2.stderr.exp pdb-realloc2.stdout.exp pdb-realloc2.vgtest \
diff --git a/SOURCES/valgrind-3.14.0-rsp-clobber.patch b/SOURCES/valgrind-3.14.0-rsp-clobber.patch
new file mode 100644
index 0000000..1400f0b
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-rsp-clobber.patch
@@ -0,0 +1,35 @@
+commit 022f5af61bc3cbfa2b74ab355b0d2d30b3dab027
+Author: Khem Raj <raj.khem@gmail.com>
+Date:   Sat Dec 22 15:28:40 2018 -0800
+
+    tests/amd64: Do not clobber %rsp register
+    
+    This is seen with gcc-9.0 compiler now which is fix that gcc community
+    did recently
+    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52813
+    
+    Signed-off-by: Khem Raj <raj.khem@gmail.com>
+
+diff --git a/none/tests/amd64-linux/bug345887.c b/none/tests/amd64-linux/bug345887.c
+index 0f9237d..269bd70 100644
+--- a/none/tests/amd64-linux/bug345887.c
++++ b/none/tests/amd64-linux/bug345887.c
+@@ -20,13 +20,17 @@ static void inner(void)
+       "movq $0x10d, %%r14\n"
+       "movq $0x10e, %%r15\n"
+       // not %rbp as mdb is then not able to reconstruct stack trace
++      // Do change %rsp (to test a bogus stack pointer),
++      // but don't add %rsp to the clobber list since gcc ignores it
++      // and since gcc >= 9.0 errors about it
++      // see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52813
+       "movq $0x10f, %%rsp\n"
+       "movq $0x1234, (%%rax)\n"  // should cause SEGV here
+       "ud2"                      // should never get here
+       : // no output registers
+       : // no input registers
+       : "memory", "%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi",
+-        "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", "%rsp");
++        "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15");
+ }
+ 
+ __attribute__((noinline))
diff --git a/SOURCES/valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch b/SOURCES/valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch
new file mode 100644
index 0000000..b5c8282
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch
@@ -0,0 +1,84 @@
+commit 71002d8a5111d02ce8049c55017a8d948c820e35
+Author: Andreas Arnez <arnez@linux.ibm.com>
+Date:   Thu Oct 25 13:47:12 2018 +0200
+
+    Bug 400490 s390x: Fix register allocation for VRs vs FPRs
+    
+    On s390x, if vector registers are available, they are fed to the register
+    allocator as if they were separate from the floating-point registers.  But
+    in fact the FPRs are embedded in the VRs.  So for instance, if both f3 and
+    v3 are allocated and used at the same time, corruption will result.
+    
+    This is fixed by offering only the non-overlapping VRs, v16 to v31, to the
+    register allocator instead.
+
+diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
+index 6c22ac8..98ac938 100644
+--- a/VEX/priv/host_s390_defs.c
++++ b/VEX/priv/host_s390_defs.c
+@@ -59,7 +59,6 @@ static UInt s390_tchain_load64_len(void);
+ 
+ /* A mapping from register number to register index */
+ static Int gpr_index[16];  // GPR regno -> register index
+-static Int fpr_index[16];  // FPR regno -> register index
+ static Int vr_index[32];   // VR regno -> register index
+ 
+ HReg
+@@ -73,7 +72,7 @@ s390_hreg_gpr(UInt regno)
+ HReg
+ s390_hreg_fpr(UInt regno)
+ {
+-   Int ix = fpr_index[regno];
++   Int ix = vr_index[regno];
+    vassert(ix >= 0);
+    return mkHReg(/*virtual*/False, HRcFlt64, regno, ix);
+ }
+@@ -463,11 +462,9 @@ getRRegUniverse_S390(void)
+ 
+    RRegUniverse__init(ru);
+ 
+-   /* Assign invalid values to the gpr/fpr/vr_index */
++   /* Assign invalid values to the gpr/vr_index */
+    for (UInt i = 0; i < sizeof gpr_index / sizeof gpr_index[0]; ++i)
+       gpr_index[i] = -1;
+-   for (UInt i = 0; i < sizeof fpr_index / sizeof fpr_index[0]; ++i)
+-      fpr_index[i] = -1;
+    for (UInt i = 0; i < sizeof vr_index / sizeof vr_index[0]; ++i)
+       vr_index[i] = -1;
+ 
+@@ -494,17 +491,17 @@ getRRegUniverse_S390(void)
+ 
+    ru->allocable_start[HRcFlt64] = ru->size;
+    for (UInt regno = 8; regno <= 15; ++regno) {
+-      fpr_index[regno] = ru->size;
++      vr_index[regno] = ru->size;
+       ru->regs[ru->size++] = s390_hreg_fpr(regno);
+    }
+    for (UInt regno = 0; regno <= 7; ++regno) {
+-      fpr_index[regno] = ru->size;
++      vr_index[regno] = ru->size;
+       ru->regs[ru->size++] = s390_hreg_fpr(regno);
+    }
+    ru->allocable_end[HRcFlt64] = ru->size - 1;
+ 
+    ru->allocable_start[HRcVec128] = ru->size;
+-   for (UInt regno = 0; regno <= 31; ++regno) {
++   for (UInt regno = 16; regno <= 31; ++regno) {
+       vr_index[regno] = ru->size;
+       ru->regs[ru->size++] = s390_hreg_vr(regno);
+    }
+@@ -527,12 +524,12 @@ getRRegUniverse_S390(void)
+    /* Sanity checking */
+    for (UInt i = 0; i < sizeof gpr_index / sizeof gpr_index[0]; ++i)
+       vassert(gpr_index[i] >= 0);
+-   for (UInt i = 0; i < sizeof fpr_index / sizeof fpr_index[0]; ++i)
+-      vassert(fpr_index[i] >= 0);
+    for (UInt i = 0; i < sizeof vr_index / sizeof vr_index[0]; ++i)
+       vassert(vr_index[i] >= 0);
+                  
+    initialised = True;
++
++   RRegUniverse__check_is_sane(ru);
+    return ru;
+ }
+ 
diff --git a/SOURCES/valgrind-3.14.0-s390x-sign-extend-lochi.patch b/SOURCES/valgrind-3.14.0-s390x-sign-extend-lochi.patch
new file mode 100644
index 0000000..318012f
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390x-sign-extend-lochi.patch
@@ -0,0 +1,41 @@
+commit 9545e9f96beda6e9f2205bdb3c3e96edaf8d9e2b
+Author: Andreas Arnez <arnez@linux.ibm.com>
+Date:   Tue Oct 30 17:06:38 2018 +0100
+
+    Bug 400491 s390x: Sign-extend immediate operand of LOCHI and friends
+    
+    The VEX implementation of each of the z/Architecture instructions LOCHI,
+    LOCHHI, and LOCGHI treats the immediate 16-bit operand as an unsigned
+    integer instead of a signed integer.  This is fixed.
+
+diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
+index 60b6081..9c4d79b 100644
+--- a/VEX/priv/guest_s390_toIR.c
++++ b/VEX/priv/guest_s390_toIR.c
+@@ -16307,7 +16307,7 @@ static const HChar *
+ s390_irgen_LOCHHI(UChar r1, UChar m3, UShort i2, UChar unused)
+ {
+    next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
+-   put_gpr_w0(r1, mkU32(i2));
++   put_gpr_w0(r1, mkU32((UInt)(Int)(Short)i2));
+ 
+    return "lochhi";
+ }
+@@ -16316,7 +16316,7 @@ static const HChar *
+ s390_irgen_LOCHI(UChar r1, UChar m3, UShort i2, UChar unused)
+ {
+    next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
+-   put_gpr_w1(r1, mkU32(i2));
++   put_gpr_w1(r1, mkU32((UInt)(Int)(Short)i2));
+ 
+    return "lochi";
+ }
+@@ -16325,7 +16325,7 @@ static const HChar *
+ s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2, UChar unused)
+ {
+    next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
+-   put_gpr_dw0(r1, mkU64(i2));
++   put_gpr_dw0(r1, mkU64((UInt)(Int)(Short)i2));
+ 
+    return "locghi";
+ }
diff --git a/SOURCES/valgrind-3.14.0-s390x-vec-facility-bit.patch b/SOURCES/valgrind-3.14.0-s390x-vec-facility-bit.patch
new file mode 100644
index 0000000..c00ed62
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390x-vec-facility-bit.patch
@@ -0,0 +1,32 @@
+commit 467c7c4c9665c0f8b41a4416722a027ebc05df2b
+Author: Andreas Arnez <arnez@linux.ibm.com>
+Date:   Mon Jan 21 14:10:00 2019 +0100
+
+    Bug 403552 s390x: Fix vector facility bit number
+    
+    The wrong bit number was used when checking for the vector facility.  This
+    can result in a fatal emulation error: "Encountered an instruction that
+    requires the vector facility.  That facility is not available on this
+    host."
+    
+    In many cases the wrong facility bit was usually set as well, hence
+    nothing bad happened.  But when running Valgrind within a Qemu/KVM guest,
+    the wrong bit was not (always?) set and the emulation error occurred.
+    
+    This fix simply corrects the vector facility bit number, changing it from
+    128 to 129.
+
+ 
+diff --git a/VEX/pub/libvex_s390x_common.h b/VEX/pub/libvex_s390x_common.h
+index a8a66b96b..8723ee21d 100644
+--- a/VEX/pub/libvex_s390x_common.h
++++ b/VEX/pub/libvex_s390x_common.h
+@@ -103,7 +103,7 @@
+ #define S390_FAC_MSA5    57  // message-security-assist 5
+ #define S390_FAC_TREXE   73  // transactional execution
+ #define S390_FAC_MSA4    77  // message-security-assist 4
+-#define S390_FAC_VX      128 // vector facility
++#define S390_FAC_VX      129 // vector facility
+ 
+ 
+ /*--------------------------------------------------------------*/
diff --git a/SOURCES/valgrind-3.14.0-s390x-vec-float-point-code.patch b/SOURCES/valgrind-3.14.0-s390x-vec-float-point-code.patch
new file mode 100644
index 0000000..1e73a6f
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390x-vec-float-point-code.patch
@@ -0,0 +1,1618 @@
+commit 600a0099a1eb2335a3f9563534c112e11817002b
+Author: Vadim Barkov <vbrkov@gmail.com>
+Date:   Fri Oct 5 13:51:49 2018 +0300
+
+    Bug 385411 s390x: Add z13 vector floating point support
+    
+    This adds support for the z/Architecture vector FP instructions that were
+    introduced with z13.
+    
+    The patch was contributed by Vadim Barkov, with some clean-up and minor
+    adjustments by Andreas Arnez.
+
+diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h
+index 3bfecbe..d72cc9f 100644
+--- a/VEX/priv/guest_s390_defs.h
++++ b/VEX/priv/guest_s390_defs.h
+@@ -281,7 +281,11 @@ enum {
+    S390_VEC_OP_VMALH = 13,
+    S390_VEC_OP_VCH = 14,
+    S390_VEC_OP_VCHL = 15,
+-   S390_VEC_OP_LAST = 16 // supposed to be the last element in enum
++   S390_VEC_OP_VFCE = 16,
++   S390_VEC_OP_VFCH = 17,
++   S390_VEC_OP_VFCHE = 18,
++   S390_VEC_OP_VFTCI = 19,
++   S390_VEC_OP_LAST = 20 // supposed to be the last element in enum
+ } s390x_vec_op_t;
+ 
+ /* Arguments of s390x_dirtyhelper_vec_op(...) which are packed into one
+@@ -300,8 +304,10 @@ typedef union {
+ 
+       unsigned int m4 : 4;        // field m4 of insn or zero if it's missing
+       unsigned int m5 : 4;        // field m5 of insn or zero if it's missing
++      unsigned int m6 : 4;        // field m6 of insn or zero if it's missing
++      unsigned int i3 : 12;       // field i3 of insn or zero if it's missing
+       unsigned int read_only: 1;  // don't write result to Guest State
+-      unsigned int reserved : 27; // reserved for future
++      unsigned int reserved : 11; // reserved for future
+    };
+    ULong serialized;
+ } s390x_vec_op_details_t;
+diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c
+index d9773e7..5877743 100644
+--- a/VEX/priv/guest_s390_helpers.c
++++ b/VEX/priv/guest_s390_helpers.c
+@@ -2498,6 +2498,10 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
+       {0xe7, 0xa9}, /* VMALH */
+       {0xe7, 0xfb}, /* VCH */
+       {0xe7, 0xf9}, /* VCHL */
++      {0xe7, 0xe8}, /* VFCE */
++      {0xe7, 0xeb}, /* VFCH */
++      {0xe7, 0xea}, /* VFCHE */
++      {0xe7, 0x4a}  /* VFTCI */
+    };
+ 
+    union {
+@@ -2525,6 +2529,28 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
+         unsigned int rxb : 4;
+         unsigned int op2 : 8;
+       } VRRd;
++      struct {
++         UInt op1 : 8;
++         UInt v1  : 4;
++         UInt v2  : 4;
++         UInt v3  : 4;
++         UInt     : 4;
++         UInt m6  : 4;
++         UInt m5  : 4;
++         UInt m4  : 4;
++         UInt rxb : 4;
++         UInt op2 : 8;
++      } VRRc;
++      struct {
++         UInt op1 : 8;
++         UInt v1  : 4;
++         UInt v2  : 4;
++         UInt i3  : 12;
++         UInt m5  : 4;
++         UInt m4  : 4;
++         UInt rxb : 4;
++         UInt op2 : 8;
++      } VRIe;
+       UChar bytes[6];
+    } the_insn;
+ 
+@@ -2578,6 +2604,27 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
+       the_insn.VRRd.m6 = d->m5;
+       break;
+ 
++   case S390_VEC_OP_VFCE:
++   case S390_VEC_OP_VFCH:
++   case S390_VEC_OP_VFCHE:
++      the_insn.VRRc.v1 = 1;
++      the_insn.VRRc.v2 = 2;
++      the_insn.VRRc.v3 = 3;
++      the_insn.VRRc.rxb = 0b1110;
++      the_insn.VRRc.m4 = d->m4;
++      the_insn.VRRc.m5 = d->m5;
++      the_insn.VRRc.m6 = d->m6;
++      break;
++
++   case S390_VEC_OP_VFTCI:
++      the_insn.VRIe.v1 = 1;
++      the_insn.VRIe.v2 = 2;
++      the_insn.VRIe.rxb = 0b1100;
++      the_insn.VRIe.i3 = d->i3;
++      the_insn.VRIe.m4 = d->m4;
++      the_insn.VRIe.m5 = d->m5;
++      break;
++
+    default:
+       vex_printf("operation = %d\n", d->op);
+       vpanic("s390x_dirtyhelper_vec_op: unknown operation");
+diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
+index 50a5a41..1c4ac39 100644
+--- a/VEX/priv/guest_s390_toIR.c
++++ b/VEX/priv/guest_s390_toIR.c
+@@ -86,6 +86,7 @@ typedef enum {
+    S390_DECODE_UNKNOWN_INSN,
+    S390_DECODE_UNIMPLEMENTED_INSN,
+    S390_DECODE_UNKNOWN_SPECIAL_INSN,
++   S390_DECODE_SPECIFICATION_EXCEPTION,
+    S390_DECODE_ERROR
+ } s390_decode_t;
+ 
+@@ -421,6 +422,26 @@ yield_if(IRExpr *condition)
+                     S390X_GUEST_OFFSET(guest_IA)));
+ }
+ 
++/* Convenience macro to yield a specification exception if the given condition
++   is not met.  Used to pass this type of decoding error up through the call
++   chain. */
++#define s390_insn_assert(mnm, cond)             \
++   do {                                         \
++      if (!(cond)) {                            \
++         dis_res->whatNext = Dis_StopHere;      \
++         dis_res->jk_StopHere = Ijk_NoDecode;   \
++         return (mnm);                          \
++      }                                         \
++   } while (0)
++
++/* Convenience function to check for a specification exception. */
++static Bool
++is_specification_exception(void)
++{
++   return (dis_res->whatNext == Dis_StopHere &&
++           dis_res->jk_StopHere == Ijk_NoDecode);
++}
++
+ static __inline__ IRExpr *get_fpr_dw0(UInt);
+ static __inline__ void    put_fpr_dw0(UInt, IRExpr *);
+ static __inline__ IRExpr *get_dpr_dw0(UInt);
+@@ -1770,6 +1791,11 @@ s390_vr_get_type(const UChar m)
+ /* Determine if Zero Search (ZS) flag is set in m field */
+ #define s390_vr_is_zs_set(m) (((m) & 0b0010) != 0)
+ 
++/* Check if the "Single-Element-Control" bit is set.
++   Used in vector FP instructions.
++ */
++#define s390_vr_is_single_element_control_set(m) (((m) & 0x8) != 0)
++
+ /* Generates arg1 < arg2 (or arg1 <= arg2 if allow_equal == True) expression.
+    Arguments must have V128 type and are treated as unsigned 128-bit numbers.
+ */
+@@ -2001,12 +2027,14 @@ s390_vr_offset_by_index(UInt archreg,IRType type, UChar index)
+       return vr_offset(archreg) + sizeof(UShort) * index;
+ 
+    case Ity_I32:
++   case Ity_F32:
+       if(index > 3) {
+          goto invalidIndex;
+       }
+       return vr_offset(archreg) + sizeof(UInt) * index;
+ 
+    case Ity_I64:
++   case Ity_F64:
+       if(index > 1) {
+          goto invalidIndex;
+       }
+@@ -2237,8 +2265,8 @@ encode_bfp_rounding_mode(UChar mode)
+    case S390_BFP_ROUND_PER_FPC:
+       rm = get_bfp_rounding_mode_from_fpc();
+       break;
+-   case S390_BFP_ROUND_NEAREST_AWAY:  /* not supported */
+-   case S390_BFP_ROUND_PREPARE_SHORT: /* not supported */
++   case S390_BFP_ROUND_NEAREST_AWAY:  rm = mkU32(Irrm_NEAREST_TIE_AWAY_0); break;
++   case S390_BFP_ROUND_PREPARE_SHORT: rm = mkU32(Irrm_PREPARE_SHORTER); break;
+    case S390_BFP_ROUND_NEAREST_EVEN:  rm = mkU32(Irrm_NEAREST); break;
+    case S390_BFP_ROUND_ZERO:          rm = mkU32(Irrm_ZERO);    break;
+    case S390_BFP_ROUND_POSINF:        rm = mkU32(Irrm_PosINF);  break;
+@@ -3524,6 +3552,26 @@ s390_format_VRI_VVIM(const HChar *(*irgen)(UChar v1, UChar v3, UShort i2, UChar
+       s390_disasm(ENC5(MNM, VR, VR, UINT, UINT), mnm, v1, v3, i2, m4);
+ }
+ 
++static void
++s390_format_VRI_VVIMM(const HChar *(*irgen)(UChar v1, UChar v2, UShort i3,
++                                            UChar m4, UChar m5),
++                      UChar v1, UChar v2, UShort i3, UChar m4, UChar m5,
++                      UChar rxb)
++{
++   const HChar *mnm;
++
++   if (!s390_host_has_vx) {
++      emulation_failure(EmFail_S390X_vx);
++      return;
++   }
++
++   v1 = s390_vr_getVRindex(v1, 1, rxb);
++   v2 = s390_vr_getVRindex(v2, 2, rxb);
++   mnm = irgen(v1, v2, i3, m4, m5);
++
++   if (vex_traceflags & VEX_TRACE_FE)
++      s390_disasm(ENC6(MNM, VR, VR, UINT, UINT, UINT), mnm, v1, v2, i3, m4, m5);
++}
+ 
+ static void
+ s390_format_VRS_RRDVM(const HChar *(*irgen)(UChar r1, IRTemp op2addr, UChar v3,
+@@ -3680,7 +3728,7 @@ s390_format_VRV_VVRDMT(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar m3)
+ 
+ 
+ static void
+-s390_format_VRRd_VVVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
++s390_format_VRR_VVVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
+                                               UChar v4, UChar m5, UChar m6),
+                         UChar v1, UChar v2, UChar v3, UChar v4, UChar m5,
+                         UChar m6, UChar rxb)
+@@ -3794,6 +3842,92 @@ s390_format_VRRd_VVVVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
+ }
+ 
+ 
++static void
++s390_format_VRRa_VVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3,
++                                             UChar m4, UChar m5),
++                       UChar v1, UChar v2, UChar m3, UChar m4, UChar m5,
++                       UChar rxb)
++{
++   const HChar *mnm;
++
++   if (!s390_host_has_vx) {
++      emulation_failure(EmFail_S390X_vx);
++      return;
++   }
++
++   v1 = s390_vr_getVRindex(v1, 1, rxb);
++   v2 = s390_vr_getVRindex(v2, 2, rxb);
++   mnm = irgen(v1, v2, m3, m4, m5);
++
++   if (vex_traceflags & VEX_TRACE_FE)
++      s390_disasm(ENC6(MNM, VR, VR, UINT, UINT, UINT), mnm, v1, v2, m3, m4, m5);
++}
++
++static void
++s390_format_VRRa_VVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
++                                             UChar m4, UChar m5),
++                       UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
++                       UChar rxb)
++{
++   const HChar *mnm;
++
++   if (!s390_host_has_vx) {
++      emulation_failure(EmFail_S390X_vx);
++      return;
++   }
++
++   v1 = s390_vr_getVRindex(v1, 1, rxb);
++   v2 = s390_vr_getVRindex(v2, 2, rxb);
++   v3 = s390_vr_getVRindex(v3, 3, rxb);
++   mnm = irgen(v1, v2, v3, m4, m5);
++
++   if (vex_traceflags & VEX_TRACE_FE)
++      s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), mnm, v1, v2, v3, m4, m5);
++}
++
++static void
++s390_format_VRRa_VVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3,
++                                            UChar m4),
++                       UChar v1, UChar v2, UChar m3, UChar m4, UChar rxb)
++{
++   const HChar *mnm;
++
++   if (!s390_host_has_vx) {
++      emulation_failure(EmFail_S390X_vx);
++      return;
++   }
++
++   v1 = s390_vr_getVRindex(v1, 1, rxb);
++   v2 = s390_vr_getVRindex(v2, 2, rxb);
++   mnm = irgen(v1, v2, m3, m4);
++
++   if (vex_traceflags & VEX_TRACE_FE)
++      s390_disasm(ENC5(MNM, VR, VR, UINT, UINT), mnm, v1, v2, m3, m4);
++}
++
++static void
++s390_format_VRRa_VVVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
++                                              UChar m4, UChar m5, UChar m6),
++                        UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
++                        UChar m6, UChar rxb)
++{
++   const HChar *mnm;
++
++   if (!s390_host_has_vx) {
++      emulation_failure(EmFail_S390X_vx);
++      return;
++   }
++
++   v1 = s390_vr_getVRindex(v1, 1, rxb);
++   v2 = s390_vr_getVRindex(v2, 2, rxb);
++   v3 = s390_vr_getVRindex(v3, 3, rxb);
++   mnm = irgen(v1, v2, v3, m4, m5, m6);
++
++   if (vex_traceflags & VEX_TRACE_FE)
++      s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT),
++                  mnm, v1, v2, v3, m4, m5, m6);
++}
++
+ /*------------------------------------------------------------*/
+ /*--- Build IR for opcodes                                 ---*/
+ /*------------------------------------------------------------*/
+@@ -17895,6 +18029,575 @@ s390_irgen_VMALH(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5)
+    return "vmalh";
+ }
+ 
++static void
++s390_vector_fp_convert(IROp op, IRType fromType, IRType toType,
++                       UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   Bool isSingleElementOp = s390_vr_is_single_element_control_set(m4);
++   UChar maxIndex = isSingleElementOp ? 0 : 1;
++
++   /* For Iop_F32toF64 we do this:
++      f32[0] -> f64[0]
++      f32[2] -> f64[1]
++
++      For Iop_F64toF32 we do this:
++      f64[0] -> f32[0]
++      f64[1] -> f32[2]
++
++      The magic below with scaling factors is used to achieve the logic
++      described above.
++   */
++   const UChar sourceIndexScaleFactor = (op == Iop_F32toF64) ? 2 : 1;
++   const UChar destinationIndexScaleFactor = (op == Iop_F64toF32) ? 2 : 1;
++
++   const Bool isUnary = (op == Iop_F32toF64);
++   for (UChar i = 0; i <= maxIndex; i++) {
++      IRExpr* argument = get_vr(v2, fromType, i * sourceIndexScaleFactor);
++      IRExpr* result;
++      if (!isUnary) {
++         result = binop(op,
++                        mkexpr(encode_bfp_rounding_mode(m5)),
++                        argument);
++      } else {
++         result = unop(op, argument);
++      }
++      put_vr(v1, toType, i * destinationIndexScaleFactor, result);
++   }
++
++   if (isSingleElementOp) {
++      put_vr_dw1(v1, mkU64(0));
++   }
++}
++
++static const HChar *
++s390_irgen_VCDG(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vcdg", m3 == 3);
++
++   if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
++      emulation_warning(EmWarn_S390X_fpext_rounding);
++      m5 = S390_BFP_ROUND_PER_FPC;
++   }
++
++   s390_vector_fp_convert(Iop_I64StoF64, Ity_I64, Ity_F64, v1, v2, m3, m4, m5);
++
++   return "vcdg";
++}
++
++static const HChar *
++s390_irgen_VCDLG(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vcdlg", m3 == 3);
++
++   if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
++      emulation_warning(EmWarn_S390X_fpext_rounding);
++      m5 = S390_BFP_ROUND_PER_FPC;
++   }
++
++   s390_vector_fp_convert(Iop_I64UtoF64, Ity_I64, Ity_F64, v1, v2, m3, m4, m5);
++
++   return "vcdlg";
++}
++
++static const HChar *
++s390_irgen_VCGD(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vcgd", m3 == 3);
++
++   if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
++      emulation_warning(EmWarn_S390X_fpext_rounding);
++      m5 = S390_BFP_ROUND_PER_FPC;
++   }
++
++   s390_vector_fp_convert(Iop_F64toI64S, Ity_F64, Ity_I64, v1, v2, m3, m4, m5);
++
++   return "vcgd";
++}
++
++static const HChar *
++s390_irgen_VCLGD(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vclgd", m3 == 3);
++
++   if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
++      emulation_warning(EmWarn_S390X_fpext_rounding);
++      m5 = S390_BFP_ROUND_PER_FPC;
++   }
++
++   s390_vector_fp_convert(Iop_F64toI64U, Ity_F64, Ity_I64, v1, v2, m3, m4, m5);
++
++   return "vclgd";
++}
++
++static const HChar *
++s390_irgen_VFI(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vfi", m3 == 3);
++
++   if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
++      emulation_warning(EmWarn_S390X_fpext_rounding);
++      m5 = S390_BFP_ROUND_PER_FPC;
++   }
++
++   s390_vector_fp_convert(Iop_RoundF64toInt, Ity_F64, Ity_F64,
++                          v1, v2, m3, m4, m5);
++
++   return "vcgld";
++}
++
++static const HChar *
++s390_irgen_VLDE(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vlde", m3 == 2);
++
++   s390_vector_fp_convert(Iop_F32toF64, Ity_F32, Ity_F64, v1, v2, m3, m4, m5);
++
++   return "vlde";
++}
++
++static const HChar *
++s390_irgen_VLED(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vled", m3 == 3);
++
++   if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
++      m5 = S390_BFP_ROUND_PER_FPC;
++   }
++
++   s390_vector_fp_convert(Iop_F64toF32, Ity_F64, Ity_F32, v1, v2, m3, m4, m5);
++
++   return "vled";
++}
++
++static const HChar *
++s390_irgen_VFPSO(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vfpso", m3 == 3);
++
++   IRExpr* result;
++   switch (m5) {
++   case 0: {
++      /* Invert sign */
++      if (!s390_vr_is_single_element_control_set(m4)) {
++         result = unop(Iop_Neg64Fx2, get_vr_qw(v2));
++      }
++      else {
++         result = binop(Iop_64HLtoV128,
++                        unop(Iop_ReinterpF64asI64,
++                             unop(Iop_NegF64, get_vr(v2, Ity_F64, 0))),
++                        mkU64(0));
++      }
++      break;
++   }
++
++   case 1: {
++      /* Set sign to negative */
++      IRExpr* highHalf = mkU64(0x8000000000000000ULL);
++      if (!s390_vr_is_single_element_control_set(m4)) {
++         IRExpr* lowHalf = highHalf;
++         IRExpr* mask = binop(Iop_64HLtoV128, highHalf, lowHalf);
++         result = binop(Iop_OrV128, get_vr_qw(v2), mask);
++      }
++      else {
++         result = binop(Iop_64HLtoV128,
++                        binop(Iop_Or64, get_vr_dw0(v2), highHalf),
++                        mkU64(0ULL));
++      }
++
++      break;
++   }
++
++   case 2: {
++      /* Set sign to positive */
++      if (!s390_vr_is_single_element_control_set(m4)) {
++         result = unop(Iop_Abs64Fx2, get_vr_qw(v2));
++      }
++      else {
++         result = binop(Iop_64HLtoV128,
++                        unop(Iop_ReinterpF64asI64,
++                             unop(Iop_AbsF64, get_vr(v2, Ity_F64, 0))),
++                        mkU64(0));
++      }
++
++      break;
++   }
++
++   default:
++      vpanic("s390_irgen_VFPSO: Invalid m5 value");
++   }
++
++   put_vr_qw(v1, result);
++   if (s390_vr_is_single_element_control_set(m4)) {
++      put_vr_dw1(v1, mkU64(0ULL));
++   }
++
++   return "vfpso";
++}
++
++static void s390x_vec_fp_binary_op(IROp generalOp, IROp singleElementOp,
++                                   UChar v1, UChar v2, UChar v3, UChar m4,
++                                   UChar m5)
++{
++   IRExpr* result;
++   if (!s390_vr_is_single_element_control_set(m5)) {
++      result = triop(generalOp, get_bfp_rounding_mode_from_fpc(),
++                     get_vr_qw(v2), get_vr_qw(v3));
++   } else {
++      IRExpr* highHalf = triop(singleElementOp,
++                               get_bfp_rounding_mode_from_fpc(),
++                               get_vr(v2, Ity_F64, 0),
++                               get_vr(v3, Ity_F64, 0));
++      result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
++                     mkU64(0ULL));
++   }
++
++   put_vr_qw(v1, result);
++}
++
++static void s390x_vec_fp_unary_op(IROp generalOp, IROp singleElementOp,
++                                  UChar v1, UChar v2, UChar m3, UChar m4)
++{
++   IRExpr* result;
++   if (!s390_vr_is_single_element_control_set(m4)) {
++      result = binop(generalOp, get_bfp_rounding_mode_from_fpc(),
++                     get_vr_qw(v2));
++   }
++   else {
++      IRExpr* highHalf = binop(singleElementOp,
++                               get_bfp_rounding_mode_from_fpc(),
++                               get_vr(v2, Ity_F64, 0));
++      result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
++                     mkU64(0ULL));
++   }
++
++   put_vr_qw(v1, result);
++}
++
++
++static void
++s390_vector_fp_mulAddOrSub(IROp singleElementOp,
++                           UChar v1, UChar v2, UChar v3, UChar v4,
++                           UChar m5, UChar m6)
++{
++   Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
++   IRTemp irrm_temp = newTemp(Ity_I32);
++   assign(irrm_temp, get_bfp_rounding_mode_from_fpc());
++   IRExpr* irrm = mkexpr(irrm_temp);
++   IRExpr* result;
++   IRExpr* highHalf = qop(singleElementOp,
++                          irrm,
++                          get_vr(v2, Ity_F64, 0),
++                          get_vr(v3, Ity_F64, 0),
++                          get_vr(v4, Ity_F64, 0));
++
++   if (isSingleElementOp) {
++      result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
++                     mkU64(0ULL));
++   } else {
++      IRExpr* lowHalf = qop(singleElementOp,
++                            irrm,
++                            get_vr(v2, Ity_F64, 1),
++                            get_vr(v3, Ity_F64, 1),
++                            get_vr(v4, Ity_F64, 1));
++      result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
++                     unop(Iop_ReinterpF64asI64, lowHalf));
++   }
++
++   put_vr_qw(v1, result);
++}
++
++static const HChar *
++s390_irgen_VFA(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vfa", m4 == 3);
++   s390x_vec_fp_binary_op(Iop_Add64Fx2, Iop_AddF64, v1, v2, v3, m4, m5);
++   return "vfa";
++}
++
++static const HChar *
++s390_irgen_VFS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vfs", m4 == 3);
++   s390x_vec_fp_binary_op(Iop_Sub64Fx2, Iop_SubF64, v1, v2, v3, m4, m5);
++   return "vfs";
++}
++
++static const HChar *
++s390_irgen_VFM(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vfm", m4 == 3);
++   s390x_vec_fp_binary_op(Iop_Mul64Fx2, Iop_MulF64, v1, v2, v3, m4, m5);
++   return "vfm";
++}
++
++static const HChar *
++s390_irgen_VFD(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vfd", m4 == 3);
++   s390x_vec_fp_binary_op(Iop_Div64Fx2, Iop_DivF64, v1, v2, v3, m4, m5);
++   return "vfd";
++}
++
++static const HChar *
++s390_irgen_VFSQ(UChar v1, UChar v2, UChar m3, UChar m4)
++{
++   s390_insn_assert("vfsq", m3 == 3);
++   s390x_vec_fp_unary_op(Iop_Sqrt64Fx2, Iop_SqrtF64, v1, v2, m3, m4);
++
++   return "vfsq";
++}
++
++static const HChar *
++s390_irgen_VFMA(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6)
++{
++   s390_insn_assert("vfma", m6 == 3);
++   s390_vector_fp_mulAddOrSub(Iop_MAddF64, v1, v2, v3, v4, m5, m6);
++   return "vfma";
++}
++
++static const HChar *
++s390_irgen_VFMS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6)
++{
++   s390_insn_assert("vfms", m6 == 3);
++   s390_vector_fp_mulAddOrSub(Iop_MSubF64, v1, v2, v3, v4, m5, m6);
++   return "vfms";
++}
++
++static const HChar *
++s390_irgen_WFC(UChar v1, UChar v2, UChar m3, UChar m4)
++{
++   s390_insn_assert("wfc", m3 == 3);
++   s390_insn_assert("wfc", m4 == 0);
++
++   IRTemp cc_vex = newTemp(Ity_I32);
++   assign(cc_vex, binop(Iop_CmpF64,
++                        get_vr(v1, Ity_F64, 0), get_vr(v2, Ity_F64, 0)));
++
++   IRTemp cc_s390 = newTemp(Ity_I32);
++   assign(cc_s390, convert_vex_bfpcc_to_s390(cc_vex));
++   s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False);
++
++   return "wfc";
++}
++
++static const HChar *
++s390_irgen_WFK(UChar v1, UChar v2, UChar m3, UChar m4)
++{
++   s390_irgen_WFC(v1, v2, m3, m4);
++
++   return "wfk";
++}
++
++static const HChar *
++s390_irgen_VFCE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6)
++{
++   s390_insn_assert("vfce", m4 == 3);
++
++   Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
++   if (!s390_vr_is_cs_set(m6)) {
++      if (!isSingleElementOp) {
++         put_vr_qw(v1, binop(Iop_CmpEQ64Fx2, get_vr_qw(v2), get_vr_qw(v3)));
++      } else {
++         IRExpr* comparisonResult = binop(Iop_CmpF64, get_vr(v2, Ity_F64, 0),
++                                          get_vr(v3, Ity_F64, 0));
++         IRExpr* result = mkite(binop(Iop_CmpEQ32, comparisonResult,
++                                      mkU32(Ircr_EQ)),
++                                mkU64(0xffffffffffffffffULL),
++                                mkU64(0ULL));
++         put_vr_qw(v1, binop(Iop_64HLtoV128, result, mkU64(0ULL)));
++      }
++   } else {
++      IRDirty* d;
++      IRTemp cc = newTemp(Ity_I64);
++
++      s390x_vec_op_details_t details = { .serialized = 0ULL };
++      details.op = S390_VEC_OP_VFCE;
++      details.v1 = v1;
++      details.v2 = v2;
++      details.v3 = v3;
++      details.m4 = m4;
++      details.m5 = m5;
++      details.m6 = m6;
++
++      d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
++                            &s390x_dirtyhelper_vec_op,
++                            mkIRExprVec_2(IRExpr_GSPTR(),
++                                          mkU64(details.serialized)));
++
++      const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
++      d->nFxState = 3;
++      vex_bzero(&d->fxState, sizeof(d->fxState));
++      d->fxState[0].fx = Ifx_Read;
++      d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
++      d->fxState[0].size = elementSize;
++      d->fxState[1].fx = Ifx_Read;
++      d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v3 * sizeof(V128);
++      d->fxState[1].size = elementSize;
++      d->fxState[2].fx = Ifx_Write;
++      d->fxState[2].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
++      d->fxState[2].size = sizeof(V128);
++
++      stmt(IRStmt_Dirty(d));
++      s390_cc_set(cc);
++   }
++
++   return "vfce";
++}
++
++static const HChar *
++s390_irgen_VFCH(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6)
++{
++   vassert(m4 == 3);
++
++   Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
++   if (!s390_vr_is_cs_set(m6)) {
++      if (!isSingleElementOp) {
++         put_vr_qw(v1, binop(Iop_CmpLE64Fx2, get_vr_qw(v3), get_vr_qw(v2)));
++      } else {
++         IRExpr* comparisonResult = binop(Iop_CmpF64, get_vr(v2, Ity_F64, 0),
++                                          get_vr(v3, Ity_F64, 0));
++         IRExpr* result = mkite(binop(Iop_CmpEQ32, comparisonResult,
++                                      mkU32(Ircr_GT)),
++                                mkU64(0xffffffffffffffffULL),
++                                mkU64(0ULL));
++         put_vr_qw(v1, binop(Iop_64HLtoV128, result, mkU64(0ULL)));
++      }
++   }
++   else {
++      IRDirty* d;
++      IRTemp cc = newTemp(Ity_I64);
++
++      s390x_vec_op_details_t details = { .serialized = 0ULL };
++      details.op = S390_VEC_OP_VFCH;
++      details.v1 = v1;
++      details.v2 = v2;
++      details.v3 = v3;
++      details.m4 = m4;
++      details.m5 = m5;
++      details.m6 = m6;
++
++      d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
++                            &s390x_dirtyhelper_vec_op,
++                            mkIRExprVec_2(IRExpr_GSPTR(),
++                                          mkU64(details.serialized)));
++
++      const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
++      d->nFxState = 3;
++      vex_bzero(&d->fxState, sizeof(d->fxState));
++      d->fxState[0].fx = Ifx_Read;
++      d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
++      d->fxState[0].size = elementSize;
++      d->fxState[1].fx = Ifx_Read;
++      d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v3 * sizeof(V128);
++      d->fxState[1].size = elementSize;
++      d->fxState[2].fx = Ifx_Write;
++      d->fxState[2].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
++      d->fxState[2].size = sizeof(V128);
++
++      stmt(IRStmt_Dirty(d));
++      s390_cc_set(cc);
++   }
++
++   return "vfch";
++}
++
++static const HChar *
++s390_irgen_VFCHE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6)
++{
++   s390_insn_assert("vfche", m4 == 3);
++
++   Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
++   if (!s390_vr_is_cs_set(m6)) {
++      if (!isSingleElementOp) {
++         put_vr_qw(v1, binop(Iop_CmpLT64Fx2, get_vr_qw(v3), get_vr_qw(v2)));
++      }
++      else {
++         IRExpr* comparisonResult = binop(Iop_CmpF64, get_vr(v3, Ity_F64, 0),
++                                          get_vr(v2, Ity_F64, 0));
++         IRExpr* result = mkite(binop(Iop_CmpEQ32, comparisonResult,
++                                      mkU32(Ircr_LT)),
++                                mkU64(0xffffffffffffffffULL),
++                                mkU64(0ULL));
++         put_vr_qw(v1, binop(Iop_64HLtoV128, result, mkU64(0ULL)));
++      }
++   }
++   else {
++      IRDirty* d;
++      IRTemp cc = newTemp(Ity_I64);
++
++      s390x_vec_op_details_t details = { .serialized = 0ULL };
++      details.op = S390_VEC_OP_VFCHE;
++      details.v1 = v1;
++      details.v2 = v2;
++      details.v3 = v3;
++      details.m4 = m4;
++      details.m5 = m5;
++      details.m6 = m6;
++
++      d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
++                            &s390x_dirtyhelper_vec_op,
++                            mkIRExprVec_2(IRExpr_GSPTR(),
++                                          mkU64(details.serialized)));
++
++      const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
++      d->nFxState = 3;
++      vex_bzero(&d->fxState, sizeof(d->fxState));
++      d->fxState[0].fx = Ifx_Read;
++      d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
++      d->fxState[0].size = elementSize;
++      d->fxState[1].fx = Ifx_Read;
++      d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v3 * sizeof(V128);
++      d->fxState[1].size = elementSize;
++      d->fxState[2].fx = Ifx_Write;
++      d->fxState[2].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
++      d->fxState[2].size = sizeof(V128);
++
++      stmt(IRStmt_Dirty(d));
++      s390_cc_set(cc);
++   }
++
++   return "vfche";
++}
++
++static const HChar *
++s390_irgen_VFTCI(UChar v1, UChar v2, UShort i3, UChar m4, UChar m5)
++{
++   s390_insn_assert("vftci", m4 == 3);
++
++   Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
++
++   IRDirty* d;
++   IRTemp cc = newTemp(Ity_I64);
++
++   s390x_vec_op_details_t details = { .serialized = 0ULL };
++   details.op = S390_VEC_OP_VFTCI;
++   details.v1 = v1;
++   details.v2 = v2;
++   details.i3 = i3;
++   details.m4 = m4;
++   details.m5 = m5;
++
++   d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
++                         &s390x_dirtyhelper_vec_op,
++                         mkIRExprVec_2(IRExpr_GSPTR(),
++                                       mkU64(details.serialized)));
++
++   const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
++   d->nFxState = 2;
++   vex_bzero(&d->fxState, sizeof(d->fxState));
++   d->fxState[0].fx = Ifx_Read;
++   d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
++   d->fxState[0].size = elementSize;
++   d->fxState[1].fx = Ifx_Write;
++   d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
++   d->fxState[1].size = sizeof(V128);
++
++   stmt(IRStmt_Dirty(d));
++   s390_cc_set(cc);
++
++   return "vftci";
++}
++
+ /* New insns are added here.
+    If an insn is contingent on a facility being installed also
+    check whether the list of supported facilities in function
+@@ -19358,6 +20061,18 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+         unsigned int op2 : 8;
+       } VRR;
+       struct {
++         UInt op1 : 8;
++         UInt v1  : 4;
++         UInt v2  : 4;
++         UInt v3  : 4;
++         UInt     : 4;
++         UInt m5  : 4;
++         UInt m4  : 4;
++         UInt m3  : 4;
++         UInt rxb : 4;
++         UInt op2 : 8;
++      } VRRa;
++      struct {
+         unsigned int op1 : 8;
+         unsigned int v1  : 4;
+         unsigned int v2  : 4;
+@@ -19370,6 +20085,18 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+         unsigned int op2 : 8;
+       } VRRd;
+       struct {
++         unsigned int op1 : 8;
++         unsigned int v1  : 4;
++         unsigned int v2  : 4;
++         unsigned int v3  : 4;
++         unsigned int m6  : 4;
++         unsigned int     : 4;
++         unsigned int m5  : 4;
++         unsigned int v4  : 4;
++         unsigned int rxb : 4;
++         unsigned int op2 : 8;
++      } VRRe;
++      struct {
+         unsigned int op1 : 8;
+         unsigned int v1  : 4;
+         unsigned int v3  : 4;
+@@ -19390,6 +20117,16 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+         unsigned int op2 : 8;
+       } VRId;
+       struct {
++         UInt op1 : 8;
++         UInt v1  : 4;
++         UInt v2  : 4;
++         UInt i3  : 12;
++         UInt m5  : 4;
++         UInt m4  : 4;
++         UInt rxb : 4;
++         UInt op2 : 8;
++      } VRIe;
++      struct {
+         unsigned int op1 : 8;
+         unsigned int v1  : 4;
+         unsigned int v3  : 4;
+@@ -19974,7 +20711,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+    case 0xe70000000046ULL: s390_format_VRI_VIM(s390_irgen_VGM, ovl.fmt.VRI.v1,
+                                                ovl.fmt.VRI.i2, ovl.fmt.VRI.m3,
+                                                ovl.fmt.VRI.rxb);  goto ok;
+-   case 0xe7000000004aULL: /* VFTCI */ goto unimplemented;
++   case 0xe7000000004aULL: s390_format_VRI_VVIMM(s390_irgen_VFTCI, ovl.fmt.VRIe.v1,
++                                                 ovl.fmt.VRIe.v2, ovl.fmt.VRIe.i3,
++                                                 ovl.fmt.VRIe.m4, ovl.fmt.VRIe.m5,
++                                                 ovl.fmt.VRIe.rxb);  goto ok;
+    case 0xe7000000004dULL: s390_format_VRI_VVIM(s390_irgen_VREP, ovl.fmt.VRI.v1,
+                                                ovl.fmt.VRI.v3, ovl.fmt.VRI.i2,
+                                                ovl.fmt.VRI.m3, ovl.fmt.VRI.rxb);  goto ok;
+@@ -20087,19 +20827,27 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+                                                ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
+                                                ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb);  goto ok;
+    case 0xe70000000085ULL: /* VBPERM */ goto unimplemented;
+-   case 0xe7000000008aULL: s390_format_VRRd_VVVVMM(s390_irgen_VSTRC, ovl.fmt.VRRd.v1,
+-                                                   ovl.fmt.VRRd.v2, ovl.fmt.VRRd.v3,
+-                                                   ovl.fmt.VRRd.v4, ovl.fmt.VRRd.m5,
+-                                                   ovl.fmt.VRRd.m6,
+-                                                   ovl.fmt.VRRd.rxb);  goto ok;
++   case 0xe7000000008aULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRC, ovl.fmt.VRRd.v1,
++                                                  ovl.fmt.VRRd.v2, ovl.fmt.VRRd.v3,
++                                                  ovl.fmt.VRRd.v4, ovl.fmt.VRRd.m5,
++                                                  ovl.fmt.VRRd.m6,
++                                                  ovl.fmt.VRRd.rxb);  goto ok;
+    case 0xe7000000008cULL: s390_format_VRR_VVVV(s390_irgen_VPERM, ovl.fmt.VRR.v1,
+                                                ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
+                                                ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb);  goto ok;
+    case 0xe7000000008dULL: s390_format_VRR_VVVV(s390_irgen_VSEL, ovl.fmt.VRR.v1,
+                                                ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
+                                                ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb);  goto ok;
+-   case 0xe7000000008eULL: /* VFMS */ goto unimplemented;
+-   case 0xe7000000008fULL: /* VFMA */ goto unimplemented;
++   case 0xe7000000008eULL: s390_format_VRR_VVVVMM(s390_irgen_VFMS, ovl.fmt.VRRe.v1,
++                                                  ovl.fmt.VRRe.v2, ovl.fmt.VRRe.v3,
++                                                  ovl.fmt.VRRe.v4, ovl.fmt.VRRe.m5,
++                                                  ovl.fmt.VRRe.m6,
++                                                  ovl.fmt.VRRe.rxb);  goto ok;
++   case 0xe7000000008fULL: s390_format_VRR_VVVVMM(s390_irgen_VFMA, ovl.fmt.VRRe.v1,
++                                                  ovl.fmt.VRRe.v2, ovl.fmt.VRRe.v3,
++                                                  ovl.fmt.VRRe.v4, ovl.fmt.VRRe.m5,
++                                                  ovl.fmt.VRRe.m6,
++                                                  ovl.fmt.VRRe.rxb);  goto ok;
+    case 0xe70000000094ULL: s390_format_VRR_VVVM(s390_irgen_VPK, ovl.fmt.VRR.v1,
+                                                ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
+                                                ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb);  goto ok;
+@@ -20184,17 +20932,50 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+                                                   ovl.fmt.VRRd.v2, ovl.fmt.VRRd.v3,
+                                                   ovl.fmt.VRRd.v4, ovl.fmt.VRRd.m5,
+                                                   ovl.fmt.VRRd.rxb);  goto ok;
+-   case 0xe700000000c0ULL: /* VCLGD */ goto unimplemented;
+-   case 0xe700000000c1ULL: /* VCDLG */ goto unimplemented;
+-   case 0xe700000000c2ULL: /* VCGD */ goto unimplemented;
+-   case 0xe700000000c3ULL: /* VCDG */ goto unimplemented;
+-   case 0xe700000000c4ULL: /* VLDE */ goto unimplemented;
+-   case 0xe700000000c5ULL: /* VLED */ goto unimplemented;
+-   case 0xe700000000c7ULL: /* VFI */ goto unimplemented;
+-   case 0xe700000000caULL: /* WFK */ goto unimplemented;
+-   case 0xe700000000cbULL: /* WFC */ goto unimplemented;
+-   case 0xe700000000ccULL: /* VFPSO */ goto unimplemented;
+-   case 0xe700000000ceULL: /* VFSQ */ goto unimplemented;
++   case 0xe700000000c0ULL: s390_format_VRRa_VVMMM(s390_irgen_VCLGD, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000c1ULL: s390_format_VRRa_VVMMM(s390_irgen_VCDLG, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000c2ULL: s390_format_VRRa_VVMMM(s390_irgen_VCGD, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000c3ULL: s390_format_VRRa_VVMMM(s390_irgen_VCDG, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000c4ULL: s390_format_VRRa_VVMMM(s390_irgen_VLDE, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000c5ULL: s390_format_VRRa_VVMMM(s390_irgen_VLED, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000c7ULL: s390_format_VRRa_VVMMM(s390_irgen_VFI, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000caULL: s390_format_VRRa_VVMM(s390_irgen_WFK, ovl.fmt.VRRa.v1,
++                                                 ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                 ovl.fmt.VRRa.m4,
++                                                 ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000cbULL: s390_format_VRRa_VVMM(s390_irgen_WFC, ovl.fmt.VRRa.v1,
++                                                 ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                 ovl.fmt.VRRa.m4,
++                                                 ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000ccULL: s390_format_VRRa_VVMMM(s390_irgen_VFPSO, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                  ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000ceULL: s390_format_VRRa_VVMM(s390_irgen_VFSQ, ovl.fmt.VRRa.v1,
++                                                 ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
++                                                 ovl.fmt.VRRa.m4,
++                                                 ovl.fmt.VRRa.rxb); goto ok;
+    case 0xe700000000d4ULL: s390_format_VRR_VVM(s390_irgen_VUPLL, ovl.fmt.VRR.v1,
+                                                ovl.fmt.VRR.v2, ovl.fmt.VRR.m4,
+                                                ovl.fmt.VRR.rxb);  goto ok;
+@@ -20221,13 +21002,37 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
+    case 0xe700000000dfULL: s390_format_VRR_VVM(s390_irgen_VLP, ovl.fmt.VRR.v1,
+                                                ovl.fmt.VRR.v2, ovl.fmt.VRR.m4,
+                                                ovl.fmt.VRR.rxb);  goto ok;
+-   case 0xe700000000e2ULL: /* VFS */ goto unimplemented;
+-   case 0xe700000000e3ULL: /* VFA */ goto unimplemented;
+-   case 0xe700000000e5ULL: /* VFD */ goto unimplemented;
+-   case 0xe700000000e7ULL: /* VFM */ goto unimplemented;
+-   case 0xe700000000e8ULL: /* VFCE */ goto unimplemented;
+-   case 0xe700000000eaULL: /* VFCHE */ goto unimplemented;
+-   case 0xe700000000ebULL: /* VFCH */ goto unimplemented;
++   case 0xe700000000e2ULL: s390_format_VRRa_VVVMM(s390_irgen_VFS, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                  ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000e3ULL: s390_format_VRRa_VVVMM(s390_irgen_VFA, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                  ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000e5ULL: s390_format_VRRa_VVVMM(s390_irgen_VFD, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                  ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000e7ULL: s390_format_VRRa_VVVMM(s390_irgen_VFM, ovl.fmt.VRRa.v1,
++                                                  ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                  ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                  ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000e8ULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCE, ovl.fmt.VRRa.v1,
++                                                   ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                   ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                   ovl.fmt.VRRa.m5,
++                                                   ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000eaULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCHE, ovl.fmt.VRRa.v1,
++                                                   ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                   ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                   ovl.fmt.VRRa.m5,
++                                                   ovl.fmt.VRRa.rxb); goto ok;
++   case 0xe700000000ebULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCH, ovl.fmt.VRRa.v1,
++                                                   ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
++                                                   ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
++                                                   ovl.fmt.VRRa.m5,
++                                                   ovl.fmt.VRRa.rxb); goto ok;
+    case 0xe700000000eeULL: /* VFMIN */ goto unimplemented;
+    case 0xe700000000efULL: /* VFMAX */ goto unimplemented;
+    case 0xe700000000f0ULL: s390_format_VRR_VVVM(s390_irgen_VAVGL, ovl.fmt.VRR.v1,
+@@ -21148,7 +21953,13 @@ s390_decode_and_irgen(const UChar *bytes, UInt insn_length, DisResult *dres)
+       dis_res->jk_StopHere = Ijk_Boring;
+    }
+ 
+-   if (status == S390_DECODE_OK) return insn_length;  /* OK */
++   if (status == S390_DECODE_OK) {
++      /* Adjust status if a specification exception was indicated. */
++      if (is_specification_exception())
++         status = S390_DECODE_SPECIFICATION_EXCEPTION;
++      else
++         return insn_length;  /* OK */
++   }
+ 
+    /* Decoding failed somehow */
+    if (sigill_diag) {
+@@ -21166,6 +21977,10 @@ s390_decode_and_irgen(const UChar *bytes, UInt insn_length, DisResult *dres)
+          vex_printf("unimplemented special insn: ");
+          break;
+ 
++      case S390_DECODE_SPECIFICATION_EXCEPTION:
++         vex_printf("specification exception: ");
++         break;
++
+       case S390_DECODE_ERROR:
+          vex_printf("decoding error: ");
+          break;
+diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
+index 98ac938..22cdd04 100644
+--- a/VEX/priv/host_s390_defs.c
++++ b/VEX/priv/host_s390_defs.c
+@@ -1711,6 +1711,23 @@ emit_VRR_VVM(UChar *p, ULong op, UChar v1, UChar v2, UChar m4)
+    return emit_6bytes(p, the_insn);
+ }
+ 
++static UChar *
++emit_VRR_VVMMM(UChar *p, ULong op, UChar v1, UChar v2, UChar m3, UChar m4,
++               UChar m5)
++{
++   ULong the_insn = op;
++   ULong rxb = s390_update_rxb(0, 1, &v1);
++   rxb = s390_update_rxb(rxb, 2, &v2);
++
++   the_insn |= ((ULong)v1) << 36;
++   the_insn |= ((ULong)v2) << 32;
++   the_insn |= ((ULong)m5) << 20;
++   the_insn |= ((ULong)m4) << 16;
++   the_insn |= ((ULong)m3) << 12;
++   the_insn |= ((ULong)rxb) << 8;
++
++   return emit_6bytes(p, the_insn);
++}
+ 
+ static UChar *
+ emit_VRR_VVVM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4)
+@@ -1762,6 +1779,26 @@ emit_VRR_VVVV(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar v4)
+    return emit_6bytes(p, the_insn);
+ }
+ 
++static UChar *
++emit_VRRe_VVVVMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar v4,
++                 UChar m5, UChar m6)
++{
++   ULong the_insn = op;
++   ULong rxb = s390_update_rxb(0, 1, &v1);
++   rxb = s390_update_rxb(rxb, 2, &v2);
++   rxb = s390_update_rxb(rxb, 3, &v3);
++   rxb = s390_update_rxb(rxb, 4, &v4);
++
++   the_insn |= ((ULong)v1) << 36;
++   the_insn |= ((ULong)v2) << 32;
++   the_insn |= ((ULong)v3) << 28;
++   the_insn |= ((ULong)m6) << 24;
++   the_insn |= ((ULong)m5) << 16;
++   the_insn |= ((ULong)v4) << 12;
++   the_insn |= ((ULong)rxb) << 8;
++
++   return emit_6bytes(p, the_insn);
++}
+ 
+ static UChar *
+ emit_VRR_VRR(UChar *p, ULong op, UChar v1, UChar r2, UChar r3)
+@@ -1777,6 +1814,33 @@ emit_VRR_VRR(UChar *p, ULong op, UChar v1, UChar r2, UChar r3)
+    return emit_6bytes(p, the_insn);
+ }
+ 
++static UChar *
++emit_VRR_VVVMMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4,
++                UChar m5, UChar m6)
++{
++   ULong the_insn = op;
++   ULong rxb = s390_update_rxb(0, 1, &v1);
++   rxb = s390_update_rxb(rxb, 2, &v2);
++   rxb = s390_update_rxb(rxb, 3, &v3);
++
++   the_insn |= ((ULong)v1) << 36;
++   the_insn |= ((ULong)v2) << 32;
++   the_insn |= ((ULong)v3) << 28;
++   the_insn |= ((ULong)m6) << 20;
++   the_insn |= ((ULong)m5) << 16;
++   the_insn |= ((ULong)m4) << 12;
++   the_insn |= ((ULong)rxb) << 8;
++
++   return emit_6bytes(p, the_insn);
++}
++
++static UChar*
++emit_VRR_VVVMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4,
++               UChar m5)
++{
++   return emit_VRR_VVVMMM(p, op, v1, v2, v3, m4, m5, 0);
++}
++
+ /*------------------------------------------------------------*/
+ /*--- Functions to emit particular instructions            ---*/
+ /*------------------------------------------------------------*/
+@@ -6057,6 +6121,116 @@ s390_emit_VLVGP(UChar *p, UChar v1, UChar r2, UChar r3)
+    return emit_VRR_VRR(p, 0xE70000000062ULL, v1, r2, r3);
+ }
+ 
++static UChar *
++s390_emit_VFPSO(UChar *p, UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC6(MNM, VR, VR, UINT, UINT, UINT), "vfpso", v1, v2, m3, m4,
++                  m5);
++
++   return emit_VRR_VVMMM(p, 0xE700000000CCULL, v1, v2, m3, m4, m5);
++}
++
++static UChar *
++s390_emit_VFA(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfa", v1, v2, v3, m4, m5);
++
++   return emit_VRR_VVVMM(p, 0xE700000000e3ULL, v1, v2, v3, m4, m5);
++}
++
++static UChar *
++s390_emit_VFS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfs", v1, v2, v3, m4, m5);
++
++   return emit_VRR_VVVMM(p, 0xE700000000e2ULL, v1, v2, v3, m4, m5);
++}
++
++static UChar *
++s390_emit_VFM(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfm", v1, v2, v3, m4, m5);
++
++   return emit_VRR_VVVMM(p, 0xE700000000e7ULL, v1, v2, v3, m4, m5);
++}
++
++static UChar *
++s390_emit_VFD(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfd", v1, v2, v3, m4, m5);
++
++   return emit_VRR_VVVMM(p, 0xE700000000e5ULL, v1, v2, v3, m4, m5);
++}
++
++static UChar *
++s390_emit_VFSQ(UChar *p, UChar v1, UChar v2, UChar m3, UChar m4)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC5(MNM, VR, VR, UINT, UINT), "vfsq", v1, v2, m3, m4);
++
++   return emit_VRR_VVMMM(p, 0xE700000000CEULL, v1, v2, m3, m4, 0);
++}
++
++static UChar *
++s390_emit_VFMA(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4, UChar m5,
++               UChar m6)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC7(MNM, VR, VR, VR, VR, UINT, UINT), "vfma",
++                  v1, v2, v3, v4, m5, m6);
++
++   return emit_VRRe_VVVVMM(p, 0xE7000000008fULL, v1, v2, v3, v4, m5, m6);
++}
++
++static UChar *
++s390_emit_VFMS(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4, UChar m5,
++               UChar m6)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC7(MNM, VR, VR, VR, VR, UINT, UINT), "vfms",
++                  v1, v2, v3, v4, m5, m6);
++
++   return emit_VRRe_VVVVMM(p, 0xE7000000008eULL, v1, v2, v3, v4, m5, m6);
++}
++
++static UChar *
++s390_emit_VFCE(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
++               UChar m6)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC7(MNM, VR, VR, VR, UINT, UINT, UINT), "vfce",
++                  v1, v2, v3, m4, m5, m6);
++
++   return emit_VRR_VVVMMM(p, 0xE700000000e8ULL, v1, v2, v3, m4, m5, m6);
++}
++
++static UChar *
++s390_emit_VFCH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
++               UChar m6)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC7(MNM, VR, VR, VR, UINT, UINT, UINT), "vfch",
++                  v1, v2, v3, m4, m5, m6);
++
++   return emit_VRR_VVVMMM(p, 0xE700000000ebULL, v1, v2, v3, m4, m5, m6);
++}
++
++static UChar *
++s390_emit_VFCHE(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
++                UChar m6)
++{
++   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
++      s390_disasm(ENC7(MNM, VR, VR, VR, UINT, UINT, UINT), "vfche",
++                  v1, v2, v3, m4, m5, m6);
++
++   return emit_VRR_VVVMMM(p, 0xE700000000eaULL, v1, v2, v3, m4, m5, m6);
++}
++
+ /*---------------------------------------------------------------*/
+ /*--- Constructors for the various s390_insn kinds            ---*/
+ /*---------------------------------------------------------------*/
+@@ -7201,7 +7375,6 @@ s390_insn *s390_insn_vec_triop(UChar size, s390_vec_triop_t tag, HReg dst,
+ {
+    s390_insn *insn = LibVEX_Alloc_inline(sizeof(s390_insn));
+ 
+-   vassert(size == 16);
+ 
+    insn->tag  = S390_INSN_VEC_TRIOP;
+    insn->size = size;
+@@ -7508,6 +7681,18 @@ s390_insn_as_string(const s390_insn *insn)
+          op = "v-vunpacku";
+          break;
+ 
++      case S390_VEC_FLOAT_NEG:
++         op = "v-vfloatneg";
++         break;
++
++      case S390_VEC_FLOAT_SQRT:
++         op = "v-vfloatsqrt";
++         break;
++
++      case S390_VEC_FLOAT_ABS:
++         op = "v-vfloatabs";
++         break;
++
+       default:
+          goto fail;
+       }
+@@ -7880,6 +8065,13 @@ s390_insn_as_string(const s390_insn *insn)
+       case S390_VEC_PWSUM_DW:         op = "v-vpwsumdw"; break;
+       case S390_VEC_PWSUM_QW:         op = "v-vpwsumqw"; break;
+       case S390_VEC_INIT_FROM_GPRS:   op = "v-vinitfromgprs"; break;
++      case S390_VEC_FLOAT_ADD:        op = "v-vfloatadd"; break;
++      case S390_VEC_FLOAT_SUB:        op = "v-vfloatsub"; break;
++      case S390_VEC_FLOAT_MUL:        op = "v-vfloatmul"; break;
++      case S390_VEC_FLOAT_DIV:        op = "v-vfloatdiv"; break;
++      case S390_VEC_FLOAT_COMPARE_EQUAL: op = "v-vfloatcmpeq"; break;
++      case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL:  op = "v-vfloatcmple"; break;
++      case S390_VEC_FLOAT_COMPARE_LESS: op = "v-vfloatcmpl"; break;
+       default: goto fail;
+       }
+       s390_sprintf(buf, "%M %R, %R, %R", op, insn->variant.vec_binop.dst,
+@@ -7889,6 +8081,8 @@ s390_insn_as_string(const s390_insn *insn)
+    case S390_INSN_VEC_TRIOP:
+       switch (insn->variant.vec_triop.tag) {
+       case S390_VEC_PERM:  op = "v-vperm";  break;
++      case S390_VEC_FLOAT_MADD: op = "v-vfloatmadd"; break;
++      case S390_VEC_FLOAT_MSUB: op = "v-vfloatmsub"; break;
+       default: goto fail;
+       }
+       s390_sprintf(buf, "%M %R, %R, %R, %R", op, insn->variant.vec_triop.dst,
+@@ -9036,6 +9230,27 @@ s390_insn_unop_emit(UChar *buf, const s390_insn *insn)
+       return s390_emit_VPOPCT(buf, v1, v2, s390_getM_from_size(insn->size));
+    }
+ 
++   case S390_VEC_FLOAT_NEG: {
++      vassert(insn->variant.unop.src.tag == S390_OPND_REG);
++      vassert(insn->size == 8);
++      UChar v1 = hregNumber(insn->variant.unop.dst);
++      UChar v2 = hregNumber(insn->variant.unop.src.variant.reg);
++      return s390_emit_VFPSO(buf, v1, v2, s390_getM_from_size(insn->size), 0, 0);
++   }
++   case S390_VEC_FLOAT_ABS: {
++      vassert(insn->variant.unop.src.tag == S390_OPND_REG);
++      vassert(insn->size == 8);
++      UChar v1 = hregNumber(insn->variant.unop.dst);
++      UChar v2 = hregNumber(insn->variant.unop.src.variant.reg);
++      return s390_emit_VFPSO(buf, v1, v2, s390_getM_from_size(insn->size), 0, 2);
++   }
++   case S390_VEC_FLOAT_SQRT: {
++      vassert(insn->variant.unop.src.tag == S390_OPND_REG);
++      vassert(insn->size == 8);
++      UChar v1 = hregNumber(insn->variant.unop.dst);
++      UChar v2 = hregNumber(insn->variant.unop.src.variant.reg);
++      return s390_emit_VFSQ(buf, v1, v2, s390_getM_from_size(insn->size), 0);
++   }
+    default:
+       vpanic("s390_insn_unop_emit");
+    }
+@@ -11049,6 +11264,21 @@ s390_insn_vec_binop_emit(UChar *buf, const s390_insn *insn)
+          return s390_emit_VSUMQ(buf, v1, v2, v3, s390_getM_from_size(size));
+       case S390_VEC_INIT_FROM_GPRS:
+          return s390_emit_VLVGP(buf, v1, v2, v3);
++      case S390_VEC_FLOAT_ADD:
++         return s390_emit_VFA(buf, v1, v2, v3, s390_getM_from_size(size), 0);
++      case S390_VEC_FLOAT_SUB:
++         return s390_emit_VFS(buf, v1, v2, v3, s390_getM_from_size(size), 0);
++      case S390_VEC_FLOAT_MUL:
++         return s390_emit_VFM(buf, v1, v2, v3, s390_getM_from_size(size), 0);
++      case S390_VEC_FLOAT_DIV:
++         return s390_emit_VFD(buf, v1, v2, v3, s390_getM_from_size(size), 0);
++      case S390_VEC_FLOAT_COMPARE_EQUAL:
++         return s390_emit_VFCE(buf, v1, v2, v3, s390_getM_from_size(size), 0, 0);
++      case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL:
++         return s390_emit_VFCH(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0);
++      case S390_VEC_FLOAT_COMPARE_LESS:
++         return s390_emit_VFCHE(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0);
++
+       default:
+          goto fail;
+    }
+@@ -11070,8 +11300,14 @@ s390_insn_vec_triop_emit(UChar *buf, const s390_insn *insn)
+    UChar v4 = hregNumber(insn->variant.vec_triop.op3);
+ 
+    switch (tag) {
+-      case S390_VEC_PERM:
++      case S390_VEC_PERM: {
++         vassert(insn->size == 16);
+          return s390_emit_VPERM(buf, v1, v2, v3, v4);
++      }
++      case S390_VEC_FLOAT_MADD:
++         return s390_emit_VFMA(buf, v1, v2, v3, v4, 0, 3);
++      case S390_VEC_FLOAT_MSUB:
++         return s390_emit_VFMS(buf, v1, v2, v3, v4, 0, 3);
+       default:
+          goto fail;
+    }
+diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h
+index 7ea0101..40f0472 100644
+--- a/VEX/priv/host_s390_defs.h
++++ b/VEX/priv/host_s390_defs.h
+@@ -202,7 +202,10 @@ typedef enum {
+    S390_VEC_ABS,
+    S390_VEC_COUNT_LEADING_ZEROES,
+    S390_VEC_COUNT_TRAILING_ZEROES,
+-   S390_VEC_COUNT_ONES
++   S390_VEC_COUNT_ONES,
++   S390_VEC_FLOAT_NEG,
++   S390_VEC_FLOAT_ABS,
++   S390_VEC_FLOAT_SQRT
+ } s390_unop_t;
+ 
+ /* The kind of ternary BFP operations */
+@@ -394,11 +397,20 @@ typedef enum {
+    S390_VEC_PWSUM_QW,
+ 
+    S390_VEC_INIT_FROM_GPRS,
++   S390_VEC_FLOAT_ADD,
++   S390_VEC_FLOAT_SUB,
++   S390_VEC_FLOAT_MUL,
++   S390_VEC_FLOAT_DIV,
++   S390_VEC_FLOAT_COMPARE_EQUAL,
++   S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL,
++   S390_VEC_FLOAT_COMPARE_LESS
+ } s390_vec_binop_t;
+ 
+ /* The vector operations with three operands */
+ typedef enum {
+-   S390_VEC_PERM
++   S390_VEC_PERM,
++   S390_VEC_FLOAT_MADD,
++   S390_VEC_FLOAT_MSUB
+ } s390_vec_triop_t;
+ 
+ /* The details of a CDAS insn. Carved out to keep the size of
+diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c
+index bc34f90..79581ff 100644
+--- a/VEX/priv/host_s390_isel.c
++++ b/VEX/priv/host_s390_isel.c
+@@ -787,10 +787,12 @@ get_bfp_rounding_mode(ISelEnv *env, IRExpr *irrm)
+       IRRoundingMode mode = irrm->Iex.Const.con->Ico.U32;
+ 
+       switch (mode) {
+-      case Irrm_NEAREST:  return S390_BFP_ROUND_NEAREST_EVEN;
+-      case Irrm_ZERO:     return S390_BFP_ROUND_ZERO;
+-      case Irrm_PosINF:   return S390_BFP_ROUND_POSINF;
+-      case Irrm_NegINF:   return S390_BFP_ROUND_NEGINF;
++      case Irrm_NEAREST_TIE_AWAY_0: return S390_BFP_ROUND_NEAREST_AWAY;
++      case Irrm_PREPARE_SHORTER:    return S390_BFP_ROUND_PREPARE_SHORT;
++      case Irrm_NEAREST:            return S390_BFP_ROUND_NEAREST_EVEN;
++      case Irrm_ZERO:               return S390_BFP_ROUND_ZERO;
++      case Irrm_PosINF:             return S390_BFP_ROUND_POSINF;
++      case Irrm_NegINF:             return S390_BFP_ROUND_NEGINF;
+       default:
+          vpanic("get_bfp_rounding_mode");
+       }
+@@ -3871,6 +3873,17 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
+          vec_op = S390_VEC_COUNT_ONES;
+          goto Iop_V_wrk;
+ 
++      case Iop_Neg64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_NEG;
++         goto Iop_V_wrk;
++
++      case Iop_Abs64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_ABS;
++         goto Iop_V_wrk;
++
++
+       Iop_V_wrk: {
+          dst = newVRegV(env);
+          reg1 = s390_isel_vec_expr(env, arg);
+@@ -4388,6 +4401,28 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
+          vec_op = S390_VEC_ELEM_ROLL_V;
+          goto Iop_VV_wrk;
+ 
++      case Iop_CmpEQ64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_COMPARE_EQUAL;
++         goto Iop_VV_wrk;
++
++      case Iop_CmpLE64Fx2: {
++         size = 8;
++         vec_op = S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL;
++         goto Iop_VV_wrk;
++      }
++
++      case Iop_CmpLT64Fx2: {
++         size = 8;
++         vec_op = S390_VEC_FLOAT_COMPARE_LESS;
++         goto Iop_VV_wrk;
++      }
++
++      case Iop_Sqrt64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_SQRT;
++         goto Iop_irrm_V_wrk;
++
+       case Iop_ShlN8x16:
+          size = 1;
+          shift_op = S390_VEC_ELEM_SHL_INT;
+@@ -4493,6 +4528,14 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
+          return dst;
+       }
+ 
++      Iop_irrm_V_wrk: {
++         set_bfp_rounding_mode_in_fpc(env, arg1);
++         reg1 = s390_isel_vec_expr(env, arg2);
++
++         addInstr(env, s390_insn_unop(size, vec_op, dst, s390_opnd_reg(reg1)));
++         return dst;
++      }
++
+       case Iop_64HLtoV128:
+          reg1 = s390_isel_int_expr(env, arg1);
+          reg2 = s390_isel_int_expr(env, arg2);
+@@ -4516,6 +4559,7 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
+       IRExpr* arg1 = expr->Iex.Triop.details->arg1;
+       IRExpr* arg2 = expr->Iex.Triop.details->arg2;
+       IRExpr* arg3 = expr->Iex.Triop.details->arg3;
++      IROp vec_op;
+       switch (op) {
+       case Iop_SetElem8x16:
+          size = 1;
+@@ -4551,6 +4595,36 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
+                                            dst, reg1, reg2, reg3));
+          return dst;
+ 
++      case Iop_Add64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_ADD;
++         goto Iop_irrm_VV_wrk;
++
++      case Iop_Sub64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_SUB;
++         goto Iop_irrm_VV_wrk;
++
++      case Iop_Mul64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_MUL;
++         goto Iop_irrm_VV_wrk;
++      case Iop_Div64Fx2:
++         size = 8;
++         vec_op = S390_VEC_FLOAT_DIV;
++         goto Iop_irrm_VV_wrk;
++
++      Iop_irrm_VV_wrk: {
++         set_bfp_rounding_mode_in_fpc(env, arg1);
++         reg1 = s390_isel_vec_expr(env, arg2);
++         reg2 = s390_isel_vec_expr(env, arg3);
++
++         addInstr(env, s390_insn_vec_binop(size, vec_op,
++                                           dst, reg1, reg2));
++
++         return dst;
++       }
++
+       default:
+          goto irreducible;
+       }
diff --git a/SOURCES/valgrind-3.14.0-s390x-vec-float-point-tests.patch b/SOURCES/valgrind-3.14.0-s390x-vec-float-point-tests.patch
new file mode 100644
index 0000000..79ba53b
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390x-vec-float-point-tests.patch
@@ -0,0 +1,2420 @@
+commit 86bd889458883295b73c36696ec64dea9338a7a3
+Author: Vadim Barkov <vbrkov@gmail.com>
+Date:   Fri Oct 5 13:46:44 2018 +0300
+
+    Bug 385411 s390x: Tests and internals for z13 vector FP support
+    
+    Add test cases for the z13 vector FP support.  Bring s390-opcodes.csv
+    up-to-date, reflecting that the z13 vector instructions are now supported.
+    Also remove the non-support disclaimer for the vector facility from
+    README.s390.
+    
+    The patch was contributed by Vadim Barkov, with some clean-up and minor
+    adjustments by Andreas Arnez.
+
+diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am
+index 77c00ba..097c85a 100644
+--- a/none/tests/s390x/Makefile.am
++++ b/none/tests/s390x/Makefile.am
+@@ -18,7 +18,8 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \
+ 	     spechelper-cr  spechelper-clr  \
+ 	     spechelper-ltr spechelper-or   \
+ 	     spechelper-icm-1  spechelper-icm-2 spechelper-tmll \
+-	     spechelper-tm laa vector lsc2 ppno vector_string vector_integer
++	     spechelper-tm laa vector lsc2 ppno vector_string vector_integer \
++	     vector_float
+ 
+ if BUILD_DFP_TESTS
+   INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo
+@@ -71,4 +72,4 @@ vector_CFLAGS    = $(AM_CFLAGS) -march=z13
+ lsc2_CFLAGS       = -march=z13 -DS390_TESTS_NOCOLOR
+ vector_string_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=5
+ vector_integer_CFLAGS    = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4
+-
++vector_float_CFLAGS    = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4
+diff --git a/none/tests/s390x/vector.h b/none/tests/s390x/vector.h
+index adefbcd..de23914 100644
+--- a/none/tests/s390x/vector.h
++++ b/none/tests/s390x/vector.h
+@@ -12,17 +12,21 @@
+ #endif
+ 
+ /* Test the instruction exactly one time. */
+-#define test_once(insn) test_##insn()
++#define test_once(insn) test_##insn ()
+ 
+ /* Test the instruction exactly S390_TEST_COUNT times.
+    "..." arguments specifies code which must be executed after each tests
+  */
+ #define test(insn, ...) \
+    for(iteration = 0; iteration < S390_TEST_COUNT; iteration++) \
+-     { test_##insn(); \
++     { test_once(insn); \
+         __VA_ARGS__; \
+      }
+ 
++#define test_with_selective_printing(insn, info) \
++   for(iteration = 0; iteration < S390_TEST_COUNT; iteration++) \
++     { test_ ## insn ## _selective(info); }
++
+ #ifdef __GNUC__
+ /* GCC complains about __int128 with -pedantic */
+ /* Hope that we will have int128_t in C standard someday. */
+@@ -38,18 +42,67 @@ typedef union {
+ 
+    uint32_t u32[4];
+    int32_t s32[4];
++   float   f32[4];
+ 
+    uint64_t u64[2];
+    int64_t s64[2];
++   double f64[2];
+ 
+    unsigned __int128 u128[1];
+    __int128 s128[1];
+ } V128;
+ 
++typedef enum {
++   V128_NO_PRINTING = 0,
++   V128_V_RES_AS_INT  = 1 << 0,
++   V128_V_ARG1_AS_INT = 1 << 1,
++   V128_V_ARG2_AS_INT = 1 << 2,
++   V128_V_ARG3_AS_INT = 1 << 3,
++   V128_V_RES_AS_FLOAT64 = 1 << 4,
++   V128_V_ARG1_AS_FLOAT64 = 1 << 5,
++   V128_V_ARG2_AS_FLOAT64 = 1 << 6,
++   V128_V_ARG3_AS_FLOAT64 = 1 << 7,
++   V128_V_RES_AS_FLOAT32 = 1 << 8,
++   V128_V_ARG1_AS_FLOAT32 = 1 << 9,
++   V128_V_ARG2_AS_FLOAT32 = 1 << 10,
++   V128_V_ARG3_AS_FLOAT32 = 1 << 11,
++   V128_R_RES = 1 << 12,
++   V128_R_ARG1 = 1 << 13,
++   V128_R_ARG2 = 1 << 14,
++   V128_R_ARG3 = 1 << 15,
++   V128_V_RES_EVEN_ONLY = 1 << 16,
++   V128_V_RES_ZERO_ONLY = 1 << 17,
++   V128_PRINT_ALL = (V128_V_RES_AS_INT |
++                     V128_V_ARG1_AS_INT |
++                     V128_V_ARG2_AS_INT |
++                     V128_V_ARG3_AS_INT |
++                     V128_R_RES |
++                     V128_R_ARG1 |
++                     V128_R_ARG2 |
++                     V128_R_ARG3),
++} s390x_test_usageInfo;
++
+ void print_hex(const V128 value) {
+    printf("%016lx | %016lx\n", value.u64[0], value.u64[1]);
+ }
+ 
++void print_f32(const V128 value, int even_only, int zero_only) {
++   if (zero_only)
++      printf("%a | -- | -- | --\n", value.f32[0]);
++   else if (even_only)
++      printf("%a | -- | %a | --\n", value.f32[0], value.f32[2]);
++   else
++      printf("%a | %a | %a | %a\n",
++             value.f32[0], value.f32[1], value.f32[2], value.f32[3]);
++}
++
++void print_f64(const V128 value, int zero_only) {
++   if (zero_only)
++      printf("%a | --\n", value.f64[0]);
++   else
++      printf("%a | %a\n", value.f64[0], value.f64[1]);
++}
++
+ void print_uint64_t(const uint64_t value) {
+    printf("%016lx\n", value);
+ }
+@@ -118,7 +171,7 @@ void randomize_memory_pool()
+ 
+ */
+ #define s390_test_generate(insn, asm_string) \
+-static void test_##insn() \
++static void test_##insn##_selective(const s390x_test_usageInfo info) \
+ { \
+    V128 v_result = { .u64 = {0ULL, 0ULL} }; \
+    V128 v_arg1; \
+@@ -138,6 +191,7 @@ static void test_##insn() \
+        "vl  %%v2, %[v_arg2]\n" \
+        "vl  %%v3, %[v_arg3]\n" \
+        "vone %%v5\n" \
++       "srnmb 1(0)\n " \
+        asm_string "\n"\
+        "vst %%v5, %[v_result]\n" \
+        "vst %%v1, %[v_arg1]\n" \
+@@ -162,14 +216,49 @@ static void test_##insn() \
+          "v1", "v2", "v3", "v5"); \
+     \
+    printf("insn %s:\n", #insn); \
+-   printf("  v_arg1   = "); print_hex(v_arg1); \
+-   printf("  v_arg2   = "); print_hex(v_arg2); \
+-   printf("  v_arg3   = "); print_hex(v_arg3); \
+-   printf("  v_result = "); print_hex(v_result); \
+-   printf("  r_arg1   = "); print_uint64_t(r_arg1); \
+-   printf("  r_arg2   = "); print_uint64_t(r_arg2); \
+-   printf("  r_arg3   = "); print_uint64_t(r_arg3); \
+-   printf("  r_result = "); print_uint64_t(r_result); \
++   if (info & V128_V_ARG1_AS_INT) \
++      {printf("  v_arg1   = "); print_hex(v_arg1);} \
++   if (info & V128_V_ARG2_AS_INT) \
++      {printf("  v_arg2   = "); print_hex(v_arg2);} \
++   if (info & V128_V_ARG3_AS_INT) \
++      {printf("  v_arg3   = "); print_hex(v_arg3);} \
++   if (info & V128_V_RES_AS_INT) \
++      {printf("  v_result = "); print_hex(v_result);} \
++   \
++   if (info & V128_V_ARG1_AS_FLOAT64) \
++      {printf("  v_arg1   = "); print_f64(v_arg1, 0);} \
++   if (info & V128_V_ARG2_AS_FLOAT64) \
++      {printf("  v_arg2   = "); print_f64(v_arg2, 0);} \
++   if (info & V128_V_ARG3_AS_FLOAT64) \
++      {printf("  v_arg3   = "); print_f64(v_arg3, 0);} \
++   if (info & V128_V_RES_AS_FLOAT64) { \
++      printf("  v_result = "); \
++      print_f64(v_result, info & V128_V_RES_ZERO_ONLY); \
++   } \
++   \
++   if (info & V128_V_ARG1_AS_FLOAT32) \
++      {printf("  v_arg1   = "); print_f32(v_arg1, 0, 0);} \
++   if (info & V128_V_ARG2_AS_FLOAT32) \
++      {printf("  v_arg2   = "); print_f32(v_arg2, 0, 0);} \
++   if (info & V128_V_ARG3_AS_FLOAT32) \
++      {printf("  v_arg3   = "); print_f32(v_arg3, 0, 0);} \
++   if (info & V128_V_RES_AS_FLOAT32) { \
++      printf("  v_result = "); \
++      print_f32(v_result, info & V128_V_RES_EVEN_ONLY, \
++                info & V128_V_RES_ZERO_ONLY); \
++   } \
++   if (info & V128_R_ARG1) \
++      {printf("  r_arg1   = "); print_uint64_t(r_arg1);} \
++   if (info & V128_R_ARG2) \
++      {printf("  r_arg2   = "); print_uint64_t(r_arg2);} \
++   if (info & V128_R_ARG3) \
++      {printf("  r_arg3   = "); print_uint64_t(r_arg3);} \
++   if (info & V128_R_RES) \
++      {printf("  r_result = "); print_uint64_t(r_result);} \
++} \
++__attribute__((unused)) static void test_##insn() \
++{ \
++   test_##insn##_selective (V128_PRINT_ALL); \
+ }
+ 
+ /* Stores CC to %[r_result].
+diff --git a/none/tests/s390x/vector_float.c b/none/tests/s390x/vector_float.c
+new file mode 100644
+index 0000000..52f3a29
+--- /dev/null
++++ b/none/tests/s390x/vector_float.c
+@@ -0,0 +1,275 @@
++#include "vector.h"
++
++#define s390_generate_float_test(insn, asm_string) \
++   s390_test_generate(v##insn##00,   "v" #insn " " asm_string ",0, 0") \
++   s390_test_generate(v##insn##01,   "v" #insn " " asm_string ",0, 1") \
++   s390_test_generate(v##insn##03,   "v" #insn " " asm_string ",0, 3") \
++   s390_test_generate(v##insn##04,   "v" #insn " " asm_string ",0, 4") \
++   s390_test_generate(v##insn##05,   "v" #insn " " asm_string ",0, 5") \
++   s390_test_generate(v##insn##06,   "v" #insn " " asm_string ",0, 6") \
++   s390_test_generate(v##insn##07,   "v" #insn " " asm_string ",0, 7") \
++   s390_test_generate(w##insn##00,   "w" #insn " " asm_string ",0, 0") \
++   s390_test_generate(w##insn##01,   "w" #insn " " asm_string ",0, 1") \
++   s390_test_generate(w##insn##03,   "w" #insn " " asm_string ",0, 3") \
++   s390_test_generate(w##insn##04,   "w" #insn " " asm_string ",0, 4") \
++   s390_test_generate(w##insn##05,   "w" #insn " " asm_string ",0, 5") \
++   s390_test_generate(w##insn##06,   "w" #insn " " asm_string ",0, 6") \
++   s390_test_generate(w##insn##07,   "w" #insn " " asm_string ",0, 7") \
++
++#define s390_call_float_test(insn, info) \
++   test_with_selective_printing(v ##insn ## 00, info); \
++   test_with_selective_printing(v ##insn ## 01, info); \
++   test_with_selective_printing(v ##insn ## 03, info); \
++   test_with_selective_printing(v ##insn ## 04, info); \
++   test_with_selective_printing(v ##insn ## 05, info); \
++   test_with_selective_printing(v ##insn ## 06, info); \
++   test_with_selective_printing(v ##insn ## 07, info); \
++   test_with_selective_printing(w ##insn ## 00, info | V128_V_RES_ZERO_ONLY); \
++   test_with_selective_printing(w ##insn ## 01, info | V128_V_RES_ZERO_ONLY); \
++   test_with_selective_printing(w ##insn ## 03, info | V128_V_RES_ZERO_ONLY); \
++   test_with_selective_printing(w ##insn ## 04, info | V128_V_RES_ZERO_ONLY); \
++   test_with_selective_printing(w ##insn ## 05, info | V128_V_RES_ZERO_ONLY); \
++   test_with_selective_printing(w ##insn ## 06, info | V128_V_RES_ZERO_ONLY); \
++   test_with_selective_printing(w ##insn ## 07, info | V128_V_RES_ZERO_ONLY); \
++
++s390_generate_float_test(cdgb, " %%v5, %%v1")
++s390_generate_float_test(cdlgb, " %%v5, %%v1")
++s390_generate_float_test(cgdb, " %%v5, %%v1")
++s390_generate_float_test(clgdb, " %%v5, %%v1")
++s390_generate_float_test(fidb, " %%v5, %%v1")
++s390_generate_float_test(ledb, " %%v5, %%v1")
++
++s390_test_generate(vldeb, "vldeb %%v5, %%v1")
++s390_test_generate(wldeb, "wldeb %%v5, %%v1")
++
++s390_test_generate(vflcdb, "vflcdb %%v5, %%v1")
++s390_test_generate(wflcdb, "wflcdb %%v5, %%v1")
++s390_test_generate(vflndb, "vflndb %%v5, %%v1")
++s390_test_generate(wflndb, "wflndb %%v5, %%v1")
++s390_test_generate(vflpdb, "vflpdb %%v5, %%v1")
++s390_test_generate(wflpdb, "wflpdb %%v5, %%v1")
++
++s390_test_generate(vfadb, "vfadb %%v5, %%v1, %%v2")
++s390_test_generate(wfadb, "wfadb %%v5, %%v1, %%v2")
++s390_test_generate(vfsdb, "vfsdb %%v5, %%v1, %%v2")
++s390_test_generate(wfsdb, "wfsdb %%v5, %%v1, %%v2")
++s390_test_generate(vfmdb, "vfmdb %%v5, %%v1, %%v2")
++s390_test_generate(wfmdb, "wfmdb %%v5, %%v1, %%v2")
++s390_test_generate(vfddb, "vfddb %%v5, %%v1, %%v2")
++s390_test_generate(wfddb, "wfddb %%v5, %%v1, %%v2")
++
++s390_test_generate(vfsqdb, "vfsqdb %%v5, %%v1")
++s390_test_generate(wfsqdb, "wfsqdb %%v5, %%v1")
++
++s390_test_generate(vfmadb, "vfmadb %%v5, %%v1, %%v2, %%v3")
++s390_test_generate(wfmadb, "wfmadb %%v5, %%v1, %%v2, %%v3")
++s390_test_generate(vfmsdb, "vfmsdb %%v5, %%v1, %%v2, %%v3")
++s390_test_generate(wfmsdb, "wfmsdb %%v5, %%v1, %%v2, %%v3")
++
++s390_test_generate(wfcdb, "wfcdb %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(wfkdb, "wfkdb %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++
++s390_test_generate(vfcedb,  "vfcedb  %%v5, %%v1, %%v2")
++s390_test_generate(wfcedb,  "wfcedb  %%v5, %%v1, %%v2")
++s390_test_generate(vfcedbs, "vfcedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(wfcedbs, "wfcedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++
++s390_test_generate(vfchdb,  "vfchdb  %%v5, %%v1, %%v2")
++s390_test_generate(wfchdb,  "wfchdb  %%v5, %%v1, %%v2")
++s390_test_generate(vfchdbs, "vfchdbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(wfchdbs, "wfchdbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++
++s390_test_generate(vfchedb,  "vfchedb  %%v5, %%v1, %%v2")
++s390_test_generate(wfchedb,  "wfchedb  %%v5, %%v1, %%v2")
++s390_test_generate(vfchedbs, "vfchedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(wfchedbs, "wfchedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
++
++s390_test_generate(vftcidb0,    "vftcidb %%v5, %%v1,  0  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb1,    "vftcidb %%v5, %%v1,  1  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb2,    "vftcidb %%v5, %%v1,  2  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb3,    "vftcidb %%v5, %%v1,  0  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb4,    "vftcidb %%v5, %%v1,  4  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb8,    "vftcidb %%v5, %%v1,  8  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb16,   "vftcidb %%v5, %%v1, 16  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb32,   "vftcidb %%v5, %%v1, 32  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb64,   "vftcidb %%v5, %%v1, 64  \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb128,  "vftcidb %%v5, %%v1, 128 \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb256,  "vftcidb %%v5, %%v1, 256 \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb512,  "vftcidb %%v5, %%v1, 512 \n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb1024, "vftcidb %%v5, %%v1, 1024\n" S390_TEST_PUT_CC_TO_RESULT)
++s390_test_generate(vftcidb2048, "vftcidb %%v5, %%v1, 2048\n" S390_TEST_PUT_CC_TO_RESULT)
++
++int main()
++{
++   size_t iteration = 0;
++
++   s390_call_float_test(cdgb, (V128_V_RES_AS_FLOAT64 | V128_V_ARG1_AS_INT));
++   s390_call_float_test(cdlgb, (V128_V_RES_AS_FLOAT64 | V128_V_ARG1_AS_INT));
++   s390_call_float_test(cgdb, (V128_V_RES_AS_INT | V128_V_ARG1_AS_FLOAT64));
++   s390_call_float_test(clgdb, (V128_V_RES_AS_INT | V128_V_ARG1_AS_FLOAT64));
++   s390_call_float_test(fidb, (V128_V_RES_AS_FLOAT64 | V128_V_ARG1_AS_FLOAT64));
++   s390_call_float_test(ledb, (V128_V_RES_AS_FLOAT32 | V128_V_RES_EVEN_ONLY |
++                               V128_V_ARG1_AS_FLOAT64));
++
++   test_with_selective_printing(vldeb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(wldeb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64));
++
++   test_with_selective_printing(vflcdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(wflcdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(vflndb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(wflndb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(vflpdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(wflpdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++
++   test_with_selective_printing(vfadb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfadb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(vfsdb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfsdb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(vfmdb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfmdb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(vfddb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfddb, (V128_V_RES_AS_FLOAT64 |
++                                        V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64));
++ 
++   test_with_selective_printing(vfsqdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++   test_with_selective_printing(wfsqdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64));
++
++   test_with_selective_printing(vfmadb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64 |
++                                         V128_V_ARG2_AS_FLOAT64 |
++                                         V128_V_ARG3_AS_FLOAT64));
++   test_with_selective_printing(wfmadb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64 |
++                                         V128_V_ARG2_AS_FLOAT64 |
++                                         V128_V_ARG3_AS_FLOAT64));
++   test_with_selective_printing(vfmsdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64 |
++                                         V128_V_ARG2_AS_FLOAT64 |
++                                         V128_V_ARG3_AS_FLOAT64));
++   test_with_selective_printing(wfmsdb, (V128_V_RES_AS_FLOAT64 |
++                                         V128_V_ARG1_AS_FLOAT64 |
++                                         V128_V_ARG2_AS_FLOAT64 |
++                                         V128_V_ARG3_AS_FLOAT64));
++
++   test_with_selective_printing(wfcdb, (V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64 |
++                                        V128_R_RES));
++   test_with_selective_printing(wfkdb, (V128_V_ARG1_AS_FLOAT64 |
++                                        V128_V_ARG2_AS_FLOAT64 |
++                                        V128_R_RES));
++
++   test_with_selective_printing(vfcedb,  (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfcedb,  (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(vfcedbs, (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64 |
++                                          V128_R_RES));
++   test_with_selective_printing(wfcedbs, (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64 |
++                                          V128_R_RES));
++
++   test_with_selective_printing(vfchdb,  (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfchdb,  (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(vfchdbs, (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64 |
++                                          V128_R_RES));
++   test_with_selective_printing(wfchdbs, (V128_V_RES_AS_INT |
++                                          V128_V_ARG1_AS_FLOAT64 |
++                                          V128_V_ARG2_AS_FLOAT64 |
++                                          V128_R_RES));
++
++   test_with_selective_printing(vfchedb,  (V128_V_RES_AS_INT |
++                                           V128_V_ARG1_AS_FLOAT64 |
++                                           V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(wfchedb,  (V128_V_RES_AS_INT |
++                                           V128_V_ARG1_AS_FLOAT64 |
++                                           V128_V_ARG2_AS_FLOAT64));
++   test_with_selective_printing(vfchedbs, (V128_V_RES_AS_INT |
++                                           V128_V_ARG1_AS_FLOAT64 |
++                                           V128_V_ARG2_AS_FLOAT64 |
++                                           V128_R_RES));
++   test_with_selective_printing(wfchedbs, (V128_V_RES_AS_INT |
++                                           V128_V_ARG1_AS_FLOAT64 |
++                                           V128_V_ARG2_AS_FLOAT64 |
++                                           V128_R_RES));
++
++   test_with_selective_printing(vftcidb0,    (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb1,    (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb2,    (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb3,    (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb4,    (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb8,    (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb16,   (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb32,   (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb64,   (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb128,  (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb256,  (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb512,  (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb1024, (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++   test_with_selective_printing(vftcidb2048, (V128_V_RES_AS_INT |
++                                              V128_V_ARG1_AS_FLOAT64 |
++                                              V128_R_RES));
++
++   return 0;
++}
+diff --git a/none/tests/s390x/vector_float.stderr.exp b/none/tests/s390x/vector_float.stderr.exp
+new file mode 100644
+index 0000000..139597f
+--- /dev/null
++++ b/none/tests/s390x/vector_float.stderr.exp
+@@ -0,0 +1,2 @@
++
++
+diff --git a/none/tests/s390x/vector_float.stdout.exp b/none/tests/s390x/vector_float.stdout.exp
+new file mode 100644
+index 0000000..eac5250
+--- /dev/null
++++ b/none/tests/s390x/vector_float.stdout.exp
+@@ -0,0 +1,1808 @@
++insn vcdgb00:
++  v_arg1   = 0d6a95fac528657d | 501eefeec0d8b847
++  v_result = 0x1.ad52bf58a50cap+59 | 0x1.407bbfbb0362ep+62
++insn vcdgb00:
++  v_arg1   = e540bc6839c44b4a | 36ed3550df9899d8
++  v_result = -0x1.abf4397c63bb4p+60 | 0x1.b769aa86fcc4cp+61
++insn vcdgb00:
++  v_arg1   = 979569ee6d5cbcd8 | 966cf73d98a42d54
++  v_result = -0x1.a1aa58464a8dp+62 | -0x1.a64c23099d6f4p+62
++insn vcdgb00:
++  v_arg1   = 10985cc9e2b9c255 | b2683bbf21432695
++  v_result = 0x1.0985cc9e2b9c2p+60 | -0x1.365f11037af36p+62
++insn vcdgb01:
++  v_arg1   = 4208cb757c0f3e0a | 91fe3de1d5e7ca54
++  v_result = 0x1.08232dd5f03dp+62 | -0x1.b8070878a860dp+62
++insn vcdgb01:
++  v_arg1   = e5f1216d47c3a621 | c1582e6bf6f3b5e9
++  v_result = -0x1.a0ede92b83c5ap+60 | -0x1.f53e8ca048625p+61
++insn vcdgb01:
++  v_arg1   = 376fbfe93425c861 | 1870f7a36a759b08
++  v_result = 0x1.bb7dff49a12e4p+61 | 0x1.870f7a36a759bp+60
++insn vcdgb01:
++  v_arg1   = bc68bf9dda3685ee | 6fcaf40c7feb0484
++  v_result = -0x1.0e5d01889725fp+62 | 0x1.bf2bd031ffac1p+62
++insn vcdgb03:
++  v_arg1   = ff55ac7f3661970c | 663cba29a8010f0e
++  v_result = -0x1.54a701933cd1fp+55 | 0x1.98f2e8a6a0043p+62
++insn vcdgb03:
++  v_arg1   = 50f94b806c444cdc | 23a9d13a3e4f30f5
++  v_result = 0x1.43e52e01b1113p+62 | 0x1.1d4e89d1f2799p+61
++insn vcdgb03:
++  v_arg1   = 8526565084674a1c | 13c07bfc401df2e6
++  v_result = -0x1.eb66a6bdee62dp+62 | 0x1.3c07bfc401df3p+60
++insn vcdgb03:
++  v_arg1   = bb7d3d1d2e024aea | a9bf6c6c1422b7ac
++  v_result = -0x1.120b0b8b47f6dp+62 | -0x1.59024e4faf753p+62
++insn vcdgb04:
++  v_arg1   = 122de4537ebadd80 | 1b359083443f73f0
++  v_result = 0x1.22de4537ebadep+60 | 0x1.b359083443f74p+60
++insn vcdgb04:
++  v_arg1   = 74b2685cb1632af8 | 28bac9f9424875f9
++  v_result = 0x1.d2c9a172c58cbp+62 | 0x1.45d64fca1243bp+61
++insn vcdgb04:
++  v_arg1   = 4f96da5fe8beae08 | d5b8af0426ba1f6b
++  v_result = 0x1.3e5b697fa2facp+62 | -0x1.523a87deca2fp+61
++insn vcdgb04:
++  v_arg1   = 57330304e93afcc5 | 2c244e196b83aa0a
++  v_result = 0x1.5ccc0c13a4ebfp+62 | 0x1.612270cb5c1d5p+61
++insn vcdgb05:
++  v_arg1   = 466d1f2de1b67b62 | fc44eca9b6c0e377
++  v_result = 0x1.19b47cb786d9ep+62 | -0x1.dd89ab249f8e4p+57
++insn vcdgb05:
++  v_arg1   = 9c7aa2bc253b2bf0 | 9c69c1e38f79f1f0
++  v_result = -0x1.8e15750f6b135p+62 | -0x1.8e58f871c2183p+62
++insn vcdgb05:
++  v_arg1   = 609cf752ecc5611e | a9b4be7727660d13
++  v_result = 0x1.8273dd4bb3158p+62 | -0x1.592d06236267cp+62
++insn vcdgb05:
++  v_arg1   = dde43c0d17fa87f9 | c4d4485011ac499a
++  v_result = -0x1.10de1f97402bcp+61 | -0x1.d95dbd7f729dbp+61
++insn vcdgb06:
++  v_arg1   = 67f00848ebf0ddad | 55c5fa58099e4a1e
++  v_result = 0x1.9fc02123afc38p+62 | 0x1.5717e96026793p+62
++insn vcdgb06:
++  v_arg1   = 14ac275ed2ea3c41 | 4c916736b17f0fd7
++  v_result = 0x1.4ac275ed2ea3dp+60 | 0x1.32459cdac5fc4p+62
++insn vcdgb06:
++  v_arg1   = 841359651e19ce5c | db11d6114f3da959
++  v_result = -0x1.efb29a6b8798cp+62 | -0x1.27714f758612bp+61
++insn vcdgb06:
++  v_arg1   = 9aee16f6c65ed705 | 3dab044d91370057
++  v_result = -0x1.9447a424e684ap+62 | 0x1.ed58226c89b81p+61
++insn vcdgb07:
++  v_arg1   = 41924de22705705d | 7314e64c4af69562
++  v_result = 0x1.064937889c15cp+62 | 0x1.cc5399312bda5p+62
++insn vcdgb07:
++  v_arg1   = 28a421fcc48a4766 | 020e652d33f63ba9
++  v_result = 0x1.45210fe624523p+61 | 0x1.07329699fb1ddp+57
++insn vcdgb07:
++  v_arg1   = 87d7abd5085662be | b72a218eab5dddb9
++  v_result = -0x1.e0a150abdea68p+62 | -0x1.235779c552889p+62
++insn vcdgb07:
++  v_arg1   = d9abbb790081d963 | 63852f4c78c03c3d
++  v_result = -0x1.32a22437fbf14p+61 | 0x1.8e14bd31e300fp+62
++insn wcdgb00:
++  v_arg1   = a02f983522909f6f | a08ddc4185e4afbe
++  v_result = -0x1.7f419f2b75bd8p+62 | --
++insn wcdgb00:
++  v_arg1   = 24bfbc5409373bdb | 8bbc6803a279e263
++  v_result = 0x1.25fde2a049b9dp+61 | --
++insn wcdgb00:
++  v_arg1   = 35c59adc3617873f | 895bccaa47e097b0
++  v_result = 0x1.ae2cd6e1b0bc3p+61 | --
++insn wcdgb00:
++  v_arg1   = e5795953d180798f | 033f758952e56949
++  v_result = -0x1.a86a6ac2e7f86p+60 | --
++insn wcdgb01:
++  v_arg1   = 50a3967f672fd7de | 2a8d07f3c58484af
++  v_result = 0x1.428e59fd9cbf6p+62 | --
++insn wcdgb01:
++  v_arg1   = 55572620ab0f011d | b4781cf689a66f00
++  v_result = 0x1.555c9882ac3cp+62 | --
++insn wcdgb01:
++  v_arg1   = 5ab7d2b735faacdb | 9d0003212fe3c3b9
++  v_result = 0x1.6adf4adcd7eabp+62 | --
++insn wcdgb01:
++  v_arg1   = 0cb41a414677a106 | e7b48241aa40f176
++  v_result = 0x1.96834828cef42p+59 | --
++insn wcdgb03:
++  v_arg1   = 1dcbf3fa837c83a7 | 5c6f941e16f101b0
++  v_result = 0x1.dcbf3fa837c83p+60 | --
++insn wcdgb03:
++  v_arg1   = 05ca8a1db62c87a8 | 471d2d4175174e7c
++  v_result = 0x1.72a2876d8b21fp+58 | --
++insn wcdgb03:
++  v_arg1   = c28bffa291993a8f | 3f76f2af6e814c51
++  v_result = -0x1.eba002eb73363p+61 | --
++insn wcdgb03:
++  v_arg1   = 99b62bfd6b813f43 | ddc001ae0d6e42c1
++  v_result = -0x1.9927500a51fb1p+62 | --
++insn wcdgb04:
++  v_arg1   = d3825be401140fc5 | 818fb07e8648113d
++  v_result = -0x1.63ed20dff75f8p+61 | --
++insn wcdgb04:
++  v_arg1   = 8273130837abb8f7 | 1287461ff268ecd4
++  v_result = -0x1.f633b3df21512p+62 | --
++insn wcdgb04:
++  v_arg1   = 3a1ccdd9d5909f57 | bc17c41010d81ef3
++  v_result = 0x1.d0e66eceac85p+61 | --
++insn wcdgb04:
++  v_arg1   = d8ddb8444bbc3ec3 | b03fa00d060ac825
++  v_result = -0x1.39123ddda21e1p+61 | --
++insn wcdgb05:
++  v_arg1   = 3fa47a776e92e735 | e74a85ce1fa4a0d3
++  v_result = 0x1.fd23d3bb74973p+61 | --
++insn wcdgb05:
++  v_arg1   = 16aeee9b39a78086 | e09214ce8b37b404
++  v_result = 0x1.6aeee9b39a78p+60 | --
++insn wcdgb05:
++  v_arg1   = 8c46e7988e7d462e | 5e41a7002202251c
++  v_result = -0x1.cee4619dc60aep+62 | --
++insn wcdgb05:
++  v_arg1   = 1584ecd3f3428b01 | 2c0d099a22b2ed9f
++  v_result = 0x1.584ecd3f3428bp+60 | --
++insn wcdgb06:
++  v_arg1   = 2b0dfbf1569378f2 | d9fa40cced239bee
++  v_result = 0x1.586fdf8ab49bdp+61 | --
++insn wcdgb06:
++  v_arg1   = 0fd84793ca3eccd2 | 7d1b4488cd1e1207
++  v_result = 0x1.fb08f27947d9ap+59 | --
++insn wcdgb06:
++  v_arg1   = 86e6fb1a47fa9c10 | 7350c53bb01b4e47
++  v_result = -0x1.e4641396e0158p+62 | --
++insn wcdgb06:
++  v_arg1   = 9c07f5646f2f1179 | 1d07e991ed001f2a
++  v_result = -0x1.8fe02a6e4343bp+62 | --
++insn wcdgb07:
++  v_arg1   = 659a8c8c44b32df8 | a3fd0c33fddfed09
++  v_result = 0x1.966a323112ccbp+62 | --
++insn wcdgb07:
++  v_arg1   = b84c4aadf38a8756 | b5fd808b43ba73d9
++  v_result = -0x1.1eced54831d5fp+62 | --
++insn wcdgb07:
++  v_arg1   = f2d6b39d8ea40bfa | 459e4b7dc64184f1
++  v_result = -0x1.a5298c4e2b7e9p+59 | --
++insn wcdgb07:
++  v_arg1   = bac2fdb4caa1bca9 | 4f08ec2df290cac3
++  v_result = -0x1.14f4092cd5791p+62 | --
++insn vcdlgb00:
++  v_arg1   = b826d785c58e7345 | 91ae17bf5bf582a0
++  v_result = 0x1.704daf0b8b1cep+63 | 0x1.235c2f7eb7ebp+63
++insn vcdlgb00:
++  v_arg1   = 5c6623a3c3a79e8f | 541375117aa74277
++  v_result = 0x1.71988e8f0e9e7p+62 | 0x1.504dd445ea9dp+62
++insn vcdlgb00:
++  v_arg1   = 9ef4bc5cec1602e7 | 228965816f8eb495
++  v_result = 0x1.3de978b9d82cp+63 | 0x1.144b2c0b7c75ap+61
++insn vcdlgb00:
++  v_arg1   = b912318010b2790a | 8eecbeacbe005865
++  v_result = 0x1.722463002164fp+63 | 0x1.1dd97d597c00bp+63
++insn vcdlgb01:
++  v_arg1   = f08d891964bfb5d2 | f0698b2c12804730
++  v_result = 0x1.e11b1232c97f7p+63 | 0x1.e0d3165825009p+63
++insn vcdlgb01:
++  v_arg1   = 4982fe3244b3fcf9 | 263cce57fe80ebdd
++  v_result = 0x1.260bf8c912cffp+62 | 0x1.31e672bff4076p+61
++insn vcdlgb01:
++  v_arg1   = 551bc293efedead4 | 556b3f05b71fc8b0
++  v_result = 0x1.546f0a4fbfb7bp+62 | 0x1.55acfc16dc7f2p+62
++insn vcdlgb01:
++  v_arg1   = e751bd824f7e331a | a68f0b49dcea370d
++  v_result = 0x1.cea37b049efc6p+63 | 0x1.4d1e1693b9d47p+63
++insn vcdlgb03:
++  v_arg1   = d8ab4e82afe45f9d | 0a8b96352f9d2734
++  v_result = 0x1.b1569d055fc8bp+63 | 0x1.5172c6a5f3a4fp+59
++insn vcdlgb03:
++  v_arg1   = cafc061682c88d0e | f751399a5ae2db05
++  v_result = 0x1.95f80c2d05911p+63 | 0x1.eea27334b5c5bp+63
++insn vcdlgb03:
++  v_arg1   = e328717e23c531bd | 2aa205c4ab0fafbd
++  v_result = 0x1.c650e2fc478a7p+63 | 0x1.55102e25587d7p+61
++insn vcdlgb03:
++  v_arg1   = 8eddcd779023d755 | 63cd7e40d9ebd3b6
++  v_result = 0x1.1dbb9aef2047bp+63 | 0x1.8f35f90367af5p+62
++insn vcdlgb04:
++  v_arg1   = 3e5cd1fd2f96dea2 | 2d6e6298be680e29
++  v_result = 0x1.f2e68fe97cb6fp+61 | 0x1.6b7314c5f3407p+61
++insn vcdlgb04:
++  v_arg1   = 2c31690b8a033d4d | 943061141b697dee
++  v_result = 0x1.618b485c5019fp+61 | 0x1.2860c22836d3p+63
++insn vcdlgb04:
++  v_arg1   = 14f57558143a429c | ed8ae27a577c5238
++  v_result = 0x1.4f57558143a43p+60 | 0x1.db15c4f4aef8ap+63
++insn vcdlgb04:
++  v_arg1   = fc128d1be2bb4f36 | 9283c5cd409f975c
++  v_result = 0x1.f8251a37c576ap+63 | 0x1.25078b9a813f3p+63
++insn vcdlgb05:
++  v_arg1   = ee7dc0c772749ddc | a3701c10cafde98a
++  v_result = 0x1.dcfb818ee4e93p+63 | 0x1.46e0382195fbdp+63
++insn vcdlgb05:
++  v_arg1   = b97c51cd687ff92f | c7b3f102ccb03d91
++  v_result = 0x1.72f8a39ad0fffp+63 | 0x1.8f67e20599607p+63
++insn vcdlgb05:
++  v_arg1   = b460795f4de78a6f | ea7d04e2c6809f9e
++  v_result = 0x1.68c0f2be9bcf1p+63 | 0x1.d4fa09c58d013p+63
++insn vcdlgb05:
++  v_arg1   = 7c4a292a4f638939 | fd8c8a2c9fa1effc
++  v_result = 0x1.f128a4a93d8e2p+62 | 0x1.fb1914593f43dp+63
++insn vcdlgb06:
++  v_arg1   = b2e9c51a04180847 | baecf0585f77a3d4
++  v_result = 0x1.65d38a3408302p+63 | 0x1.75d9e0b0beef5p+63
++insn vcdlgb06:
++  v_arg1   = be39eb18285aad32 | 5eb896a0fa5488ed
++  v_result = 0x1.7c73d63050b56p+63 | 0x1.7ae25a83e9523p+62
++insn vcdlgb06:
++  v_arg1   = 8f442ace5a6a7432 | 6dd995ba0537816b
++  v_result = 0x1.1e88559cb4d4fp+63 | 0x1.b76656e814de1p+62
++insn vcdlgb06:
++  v_arg1   = 5ae3cc60e43771db | 72c47a987f8e4792
++  v_result = 0x1.6b8f318390dddp+62 | 0x1.cb11ea61fe392p+62
++insn vcdlgb07:
++  v_arg1   = 577c8e33711f8ce0 | bc3f092e8bf32882
++  v_result = 0x1.5df238cdc47e3p+62 | 0x1.787e125d17e65p+63
++insn vcdlgb07:
++  v_arg1   = 88c462a8d4ae43d2 | 231bfc2b30f1c9fb
++  v_result = 0x1.1188c551a95c8p+63 | 0x1.18dfe159878e4p+61
++insn vcdlgb07:
++  v_arg1   = 727d35e1c85c6ce0 | c2f9c2bc20bfe51a
++  v_result = 0x1.c9f4d7872171bp+62 | 0x1.85f38578417fcp+63
++insn vcdlgb07:
++  v_arg1   = e238a379ac52f197 | bb08414f6f020c19
++  v_result = 0x1.c47146f358a5ep+63 | 0x1.7610829ede041p+63
++insn wcdlgb00:
++  v_arg1   = a912c54e442593a2 | f7c3954d578d6511
++  v_result = 0x1.52258a9c884b2p+63 | --
++insn wcdlgb00:
++  v_arg1   = 6179e4397b98a98a | e4b6cfddfb236dba
++  v_result = 0x1.85e790e5ee62ap+62 | --
++insn wcdlgb00:
++  v_arg1   = 27e744d3235cdf76 | 3539b7a62232b627
++  v_result = 0x1.3f3a26991ae6fp+61 | --
++insn wcdlgb00:
++  v_arg1   = 60a5da31b4d1f8ea | a6328b8cf898a98d
++  v_result = 0x1.829768c6d347ep+62 | --
++insn wcdlgb01:
++  v_arg1   = 758817a709c58c8a | b6d6be70d26145fc
++  v_result = 0x1.d6205e9c27163p+62 | --
++insn wcdlgb01:
++  v_arg1   = 97b59c872733cad7 | 6c67baf3e785de23
++  v_result = 0x1.2f6b390e4e679p+63 | --
++insn wcdlgb01:
++  v_arg1   = 7c5f03e2f70438ef | 13f5a03218ade00f
++  v_result = 0x1.f17c0f8bdc10ep+62 | --
++insn wcdlgb01:
++  v_arg1   = 20869d4407d06f50 | fe20038aa9ed8aeb
++  v_result = 0x1.0434ea203e838p+61 | --
++insn wcdlgb03:
++  v_arg1   = 85b92f7a4d9ce094 | 45d3b155068ab4c0
++  v_result = 0x1.0b725ef49b39dp+63 | --
++insn wcdlgb03:
++  v_arg1   = 74d3b54ee59c9334 | 87096ba97fb48a34
++  v_result = 0x1.d34ed53b96725p+62 | --
++insn wcdlgb03:
++  v_arg1   = 3bc02048cff1e348 | a78aa81e0d4c504e
++  v_result = 0x1.de0102467f8f1p+61 | --
++insn wcdlgb03:
++  v_arg1   = 6e38186eb26b4443 | 8fad57870c9d1c2e
++  v_result = 0x1.b8e061bac9ad1p+62 | --
++insn wcdlgb04:
++  v_arg1   = a781bb039c46fdba | f0169ab6ff259fd8
++  v_result = 0x1.4f037607388ep+63 | --
++insn wcdlgb04:
++  v_arg1   = 462f5c4ac0efef1d | 01788c3b504cdde9
++  v_result = 0x1.18bd712b03bfcp+62 | --
++insn wcdlgb04:
++  v_arg1   = 32e6464337bf4d7c | 3c53fd240e2af05e
++  v_result = 0x1.97323219bdfa7p+61 | --
++insn wcdlgb04:
++  v_arg1   = 9615776bc1bd6242 | 25b531bdae44ca53
++  v_result = 0x1.2c2aeed7837acp+63 | --
++insn wcdlgb05:
++  v_arg1   = a6bc667e825f4ffb | 04fca550cb4ef1c0
++  v_result = 0x1.4d78ccfd04be9p+63 | --
++insn wcdlgb05:
++  v_arg1   = 5826bd37c548ca0f | a690cbe5e6e9423d
++  v_result = 0x1.609af4df15232p+62 | --
++insn wcdlgb05:
++  v_arg1   = 2cad200dbc09e187 | 20acc9022764afbe
++  v_result = 0x1.6569006de04fp+61 | --
++insn wcdlgb05:
++  v_arg1   = e57be5f73fe3b5c6 | 8c153e6a1a7d0156
++  v_result = 0x1.caf7cbee7fc76p+63 | --
++insn wcdlgb06:
++  v_arg1   = 4e46db2789824050 | cbdffee0732097f5
++  v_result = 0x1.391b6c9e26091p+62 | --
++insn wcdlgb06:
++  v_arg1   = f61204d100c21186 | 422ed2e3cc26252c
++  v_result = 0x1.ec2409a201843p+63 | --
++insn wcdlgb06:
++  v_arg1   = f5f25be4ea6d0b66 | 9ef13972631676e7
++  v_result = 0x1.ebe4b7c9d4da2p+63 | --
++insn wcdlgb06:
++  v_arg1   = a5c590ce39f92a4e | 90a72ac9dde52c31
++  v_result = 0x1.4b8b219c73f26p+63 | --
++insn wcdlgb07:
++  v_arg1   = 6afcc73a404c3eb8 | 921dd02006b87bf3
++  v_result = 0x1.abf31ce90130fp+62 | --
++insn wcdlgb07:
++  v_arg1   = 6c515dd47c7aaffd | a12d4e718fa0f2b3
++  v_result = 0x1.b1457751f1eabp+62 | --
++insn wcdlgb07:
++  v_arg1   = 598fa3024d843814 | 027f7932ce5b3358
++  v_result = 0x1.663e8c093610ep+62 | --
++insn wcdlgb07:
++  v_arg1   = 2450a2abba1aac53 | fe49a1158218b7e3
++  v_result = 0x1.2285155dd0d56p+61 | --
++insn vcgdb00:
++  v_result = 8000000000000000 | 0000000000000000
++  v_arg1   = -0x1.9d6f33159b52cp+140 | -0x1.149ce8e328c35p-414
++insn vcgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.ef4fc458c90fp-924 | -0x1.9eacbbaf216cep-761
++insn vcgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.2a4a56fedd38ep-441 | -0x1.0b5fc7650d28ap-628
++insn vcgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.7484ccf632853p-296 | -0x1.64f8b96b20e65p-498
++insn vcgdb01:
++  v_result = 0000000000000000 | 7fffffffffffffff
++  v_arg1   = 0x1.9b48ee9440faap-186 | 0x1.793a417aab337p+274
++insn vcgdb01:
++  v_result = 0000000000000000 | 8000000000000000
++  v_arg1   = 0x1.5f4046914a1dcp-748 | -0x1.e542ddabafc78p+412
++insn vcgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.70a07df4248dp-475 | -0x1.2198d65113dfcp-305
++insn vcgdb01:
++  v_result = 0000000000000000 | 7fffffffffffffff
++  v_arg1   = -0x1.5ae6c84f089cap-838 | 0x1.bdf68a54e9eb5p+67
++insn vcgdb03:
++  v_result = 7fffffffffffffff | 8000000000000000
++  v_arg1   = 0x1.80d47f3abbb2ep+908 | -0x1.cdb5faf3bde76p+537
++insn vcgdb03:
++  v_result = 8000000000000000 | 7fffffffffffffff
++  v_arg1   = -0x1.38aaaf12dcd3cp+378 | 0x1.836d37a9211adp+161
++insn vcgdb03:
++  v_result = 0000000000000001 | ffffffffffffffff
++  v_arg1   = 0x1.88165272004d5p-526 | -0x1.0d0a1a7ba6227p-856
++insn vcgdb03:
++  v_result = 0000000000000001 | ffffffffffffffff
++  v_arg1   = 0x1.8ffc7e4ddbb33p-831 | -0x1.2ffe63a89d2cfp-189
++insn vcgdb04:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.28c5adc2722b3p+540 | -0x1.b4dbb5f02f86ep-483
++insn vcgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.2e2a9ecf4008dp-420 | -0x1.43ef92717c06ap-301
++insn vcgdb04:
++  v_result = 8000000000000000 | 7fffffffffffffff
++  v_arg1   = -0x1.3b4fcd4237299p+636 | 0x1.707f549662d89p+1004
++insn vcgdb04:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.c6918fb45aa0bp+947 | -0x1.95943e2ff17aep-22
++insn vcgdb05:
++  v_result = 0000000000000000 | 8000000000000000
++  v_arg1   = -0x1.4de033057b236p-61 | -0x1.01575361bed9ap+468
++insn vcgdb05:
++  v_result = 8000000000000000 | 8000000000000000
++  v_arg1   = -0x1.028bc6484274bp+144 | -0x1.d16db6de475aap+271
++insn vcgdb05:
++  v_result = 7fffffffffffffff | 8000000000000000
++  v_arg1   = 0x1.2500671e7fe19p+128 | -0x1.1eb435732889ep+338
++insn vcgdb05:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.b161dd74543cdp-442 | 0x1.b9ab9294bd84fp-297
++insn vcgdb06:
++  v_result = 7fffffffffffffff | 8000000000000000
++  v_arg1   = 0x1.9b07d7ad5d6b2p+319 | -0x1.75e473ea1aa76p+514
++insn vcgdb06:
++  v_result = 0000000000000000 | 7fffffffffffffff
++  v_arg1   = -0x1.888a166fb2dfp-837 | 0x1.f6bb5d7969d6ap+996
++insn vcgdb06:
++  v_result = 0000000000000001 | 8000000000000000
++  v_arg1   = 0x1.302c08b07155p-868 | -0x1.ca648dc3a61e1p+414
++insn vcgdb06:
++  v_result = 7fffffffffffffff | 8000000000000000
++  v_arg1   = 0x1.3349182f971f5p+336 | -0x1.46e859a0a81adp+216
++insn vcgdb07:
++  v_result = 8000000000000000 | 8000000000000000
++  v_arg1   = -0x1.dac06473efa23p+846 | -0x1.c56ee83b11b7fp+926
++insn vcgdb07:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = 0x1.72e13fd73fefbp-108 | -0x1.6e8c2f2c9a3a6p-960
++insn vcgdb07:
++  v_result = 8000000000000000 | 8000000000000000
++  v_arg1   = -0x1.27466ae20223bp+958 | -0x1.365c0e59aa4cep+392
++insn vcgdb07:
++  v_result = 7fffffffffffffff | 7fffffffffffffff
++  v_arg1   = 0x1.fed2f087c21p+341 | 0x1.180e4c1d87fc4p+682
++insn wcgdb00:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.d7fd9222e8b86p+670 | 0x1.c272612672a3p+798
++insn wcgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.745cd360987e5p-496 | -0x1.f3b404919f358p-321
++insn wcgdb00:
++  v_result = 8000000000000000 | 0000000000000000
++  v_arg1   = -0x1.9523565cd92d5p+643 | 0x1.253677d6d3be2p-556
++insn wcgdb00:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.b6eb576ec3e6ap+845 | -0x1.c7e102c503d91p+266
++insn wcgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.3d4319841f4d6p-1011 | -0x1.2feabf7dfc506p-680
++insn wcgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.6fb8d1cd8b32cp-843 | -0x1.50f6a6922f97ep+33
++insn wcgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.64a673daccf1ap-566 | -0x1.69ef9b1d01499p+824
++insn wcgdb01:
++  v_result = 8000000000000000 | 0000000000000000
++  v_arg1   = -0x1.3e2ddd862b4adp+1005 | -0x1.312466410271p+184
++insn wcgdb03:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.d594c3412a11p-953 | -0x1.a07393d34d77cp-224
++insn wcgdb03:
++  v_result = 8000000000000000 | 0000000000000000
++  v_arg1   = -0x1.f7a0dbcfd6e4cp+104 | -0x1.40f7cde7f2214p-702
++insn wcgdb03:
++  v_result = 8000000000000000 | 0000000000000000
++  v_arg1   = -0x1.40739c1574808p+560 | -0x1.970328ddf1b6ep-374
++insn wcgdb03:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.477653afd7048p-38 | 0x1.1eac2f8b2a93cp-384
++insn wcgdb04:
++  v_result = ffffffffe9479a7d | 0000000000000000
++  v_arg1   = -0x1.6b865833eff3p+28 | 0x1.06e8cf1834d0ep-722
++insn wcgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.eef0b2294a5cp-544 | -0x1.8e8b133ccda15p+752
++insn wcgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.f34e77e6b6698p-894 | -0x1.9f7ce1cb53bddp-896
++insn wcgdb04:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.95707a6d75db5p+1018 | -0x1.3b0c072d23011p-224
++insn wcgdb05:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.a9fb71160793p-968 | 0x1.05f601fe8123ap-986
++insn wcgdb05:
++  v_result = 8000000000000000 | 0000000000000000
++  v_arg1   = -0x1.0864159b94305p+451 | -0x1.d4647f5a78b7ep-599
++insn wcgdb05:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.37eadff8397c8p+432 | -0x1.15d896b6f6063p+464
++insn wcgdb05:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.eb0812b0d677p-781 | 0x1.3117c5e0e288cp-202
++insn wcgdb06:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.6b88069167c0fp-662 | -0x1.70571d27e1279p+254
++insn wcgdb06:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.f6a6d6e883596p+260 | 0x1.0d578afaaa34ap+604
++insn wcgdb06:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.d91c7d13c4694p-475 | -0x1.ecf1f8529767bp+830
++insn wcgdb06:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.fac8dd3bb7af6p-101 | 0x1.fb8324a00fba8p+959
++insn wcgdb07:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.4b0fa18fa73c7p+111 | -0x1.08e7b17633a49p+61
++insn wcgdb07:
++  v_result = e636b693e39a1100 | 0000000000000000
++  v_arg1   = -0x1.9c9496c1c65efp+60 | 0x1.c4182ee728d76p-572
++insn wcgdb07:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = -0x1.819718032dff7p-303 | 0x1.a784c77ff6aa2p-622
++insn wcgdb07:
++  v_result = 7fffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.978e8abfd83c2p+152 | 0x1.2531ebf451762p+315
++insn vclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.23363aaa9ca54p+517 | 0x1.7243af9b17426p-313
++insn vclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.9cd926092c28dp-961 | -0x1.d359f3e9bb6fdp-863
++insn vclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.0c2e79701cfedp+113 | -0x1.386cc4d0c2753p-639
++insn vclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.6404fbeee6e51p-833 | -0x1.88c7c4c78e8b5p-875
++insn vclgdb01:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = -0x1.becf5aabeedb2p-279 | 0x1.8f46a8584af8bp+339
++insn vclgdb01:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = -0x1.ba405560535ecp+419 | 0x1.f5f0d2ac089dbp+960
++insn vclgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.13765a3448273p-46 | -0x1.4245b126d990bp-32
++insn vclgdb01:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.42f7c19ab251ep+182 | -0x1.d11887b37d89ep+652
++insn vclgdb03:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.c89eea4d649dfp+1002 | -0x1.02ac7c6fad4f4p-857
++insn vclgdb03:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.c785c5992ac87p-658 | -0x1.e69063f7f720dp-81
++insn vclgdb03:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.7262730986284p+402 | -0x1.97db5d33ead45p+341
++insn vclgdb03:
++  v_result = 0000000000000000 | 0000000000000001
++  v_arg1   = -0x1.e732cc74f96a5p+338 | 0x1.e8c7ed81c5518p-50
++insn vclgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.fb488268d49d4p-603 | 0x1.af20dca2dd1dep-649
++insn vclgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.77654765512dap-986 | 0x1.700c80872de8ep-676
++insn vclgdb04:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.f3969c999dd1dp+671 | 0x1.ebe969b9a4e7ep-330
++insn vclgdb04:
++  v_result = ffffffffffffffff | ffffffffffffffff
++  v_arg1   = 0x1.1361bd5f8ad64p+859 | 0x1.6aa9af0c3cb2p+281
++insn vclgdb05:
++  v_result = ffffffffffffffff | ffffffffffffffff
++  v_arg1   = 0x1.21a00ba7f5a8fp+265 | 0x1.277f89a3992c5p+139
++insn vclgdb05:
++  v_result = ffffffffffffffff | ffffffffffffffff
++  v_arg1   = 0x1.8c9a9b86a5462p+672 | 0x1.5d08d1235385bp+372
++insn vclgdb05:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.41d67fae35e3ap-120 | 0x1.013ba779e6931p-854
++insn vclgdb05:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.7a5064fc054d4p+900 | -0x1.117184fcaa4b1p+826
++insn vclgdb06:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = -0x1.06793ec47e70cp+690 | 0x1.4e743453c0123p+679
++insn vclgdb06:
++  v_result = 0000000000000001 | ffffffffffffffff
++  v_arg1   = 0x1.b9f182ced5c9ap-622 | 0x1.48593e965ed7p+213
++insn vclgdb06:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.27e5c501152d5p-727 | -0x1.aa8dc7366e9dbp+4
++insn vclgdb06:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.eeca740c47973p-380 | -0x1.b7f3480cb4ec7p+750
++insn vclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.5477b49835c46p-130 | -0x1.d6cacd4500c77p+113
++insn vclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.c235bdef919ffp+466 | -0x1.1ca14189e67c8p+29
++insn vclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.5088657c024edp+64 | -0x1.8a9ba9a0ebaf7p-628
++insn vclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.137bbb51f08bdp+306 | 0x1.18d2a1063356p-795
++insn wclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.e66f55dcc2639p-1013 | -0x1.733ee56929f3bp-304
++insn wclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.8802fd9ab740cp-986 | -0x1.64d4d2c7c145fp-1015
++insn wclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.a67209b8c407bp-645 | -0x1.6410ff9b1c801p+487
++insn wclgdb00:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.cb2febaefeb2dp+49 | 0x1.dee368b2ec375p-502
++insn wclgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.5703db3c1b0e2p-728 | 0x1.068c4d51ea4ebp+617
++insn wclgdb01:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.ae350291e5b3ep+291 | 0x1.1b87bb09b6032p+376
++insn wclgdb01:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.c4666a710127ep+424 | -0x1.19e969b6c0076p+491
++insn wclgdb01:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.c892c5a4d103fp+105 | -0x1.d4f937cc76704p+749
++insn wclgdb03:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.81090d8fc663dp-111 | 0x1.337ec5e0f0904p+1
++insn wclgdb03:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.e787adc70b91p-593 | 0x1.db8d83196b53cp-762
++insn wclgdb03:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.6529307e907efp+389 | -0x1.3ea0d8d5b4dd2p+589
++insn wclgdb03:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.be701a158637p-385 | 0x1.c5a7f70cb8a09p+107
++insn wclgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.2f328571ab445p+21 | -0x1.dcc21fc82ba01p-930
++insn wclgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.06b69fcbb7bffp-415 | 0x1.6f9a13a0a827ap+915
++insn wclgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.738e549b38bcdp+479 | 0x1.a522edb999c9p-45
++insn wclgdb04:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.7f9399d2bcf3bp-215 | -0x1.7bc35f2d69a7fp+818
++insn wclgdb05:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.fc542bdb707f6p+880 | -0x1.8521ebc93a25fp-969
++insn wclgdb05:
++  v_result = 1ce8d9951b8c8600 | 0000000000000000
++  v_arg1   = 0x1.ce8d9951b8c86p+60 | 0x1.92712589230e7p+475
++insn wclgdb05:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.8a297f60a0811p-156 | 0x1.102b79043d82cp-204
++insn wclgdb05:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.beb9057e1401dp-196 | -0x1.820f18f830262p+15
++insn wclgdb06:
++  v_result = 0000000000000001 | 0000000000000000
++  v_arg1   = 0x1.c321a966ecb4dp-430 | -0x1.2f6a1a95ead99p-943
++insn wclgdb06:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.f1a86b4aed821p-56 | -0x1.1ee6717cc2d7fp-899
++insn wclgdb06:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.73ce49d89ecb9p-302 | 0x1.52663b975ed23p-716
++insn wclgdb06:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.3e9c2de97a292p+879 | 0x1.d34eed36f2eafp+960
++insn wclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.4e6ec6ddc6a45p-632 | -0x1.6e564d0fec72bp+369
++insn wclgdb07:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.42e2c658e4c4dp+459 | -0x1.9f9dc0252e44p+85
++insn wclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.fb40ac8cda3c1p-762 | 0x1.0e9ed614bc8f1p-342
++insn wclgdb07:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.c1f8b3c68e214p+118 | -0x1.1a26a49368b61p+756
++insn vfidb00:
++  v_arg1   = -0x1.38df4cf9d52dbp-545 | -0x1.049253d90dd92p+94
++  v_result = -0x0p+0 | -0x1.049253d90dd92p+94
++insn vfidb00:
++  v_arg1   = 0x1.75187b3d8d386p+793 | -0x1.0f5aea6c1c123p+547
++  v_result = 0x1.75187b3d8d386p+793 | -0x1.0f5aea6c1c123p+547
++insn vfidb00:
++  v_arg1   = 0x1.cb54303729724p-337 | -0x1.0791295e0541p+59
++  v_result = 0x0p+0 | -0x1.0791295e0541p+59
++insn vfidb00:
++  v_arg1   = -0x1.1b9a77d71eb22p+825 | -0x1.0189f7d748475p+647
++  v_result = -0x1.1b9a77d71eb22p+825 | -0x1.0189f7d748475p+647
++insn vfidb01:
++  v_arg1   = -0x1.5d26e474def0ap+1013 | -0x1.c4e9efb30da4ap-580
++  v_result = -0x1.5d26e474def0ap+1013 | -0x0p+0
++insn vfidb01:
++  v_arg1   = 0x1.4ad53aba85947p+105 | -0x1.f8f178fb43126p-350
++  v_result = 0x1.4ad53aba85947p+105 | -0x0p+0
++insn vfidb01:
++  v_arg1   = 0x1.aeacddb1336dep+106 | 0x1.0008f60517dffp-355
++  v_result = 0x1.aeacddb1336dep+106 | 0x0p+0
++insn vfidb01:
++  v_arg1   = -0x1.ee2d2afcea935p+75 | 0x1.740cbfdc486e6p-217
++  v_result = -0x1.ee2d2afcea935p+75 | 0x0p+0
++insn vfidb03:
++  v_arg1   = -0x1.662966287abcfp-856 | -0x1.7228d17f9aacep-413
++  v_result = -0x1p+0 | -0x1p+0
++insn vfidb03:
++  v_arg1   = 0x1.86f4c5919ca0cp-384 | -0x1.4715448c89f45p+675
++  v_result = 0x1p+0 | -0x1.4715448c89f45p+675
++insn vfidb03:
++  v_arg1   = -0x1.500e2dc4dececp-219 | -0x1.dab1ecfba3037p-347
++  v_result = -0x1p+0 | -0x1p+0
++insn vfidb03:
++  v_arg1   = -0x1.fc7c8db9b09ccp-892 | -0x1.1c72852c3fcb1p-605
++  v_result = -0x1p+0 | -0x1p+0
++insn vfidb04:
++  v_arg1   = 0x1.3eaa8ace8f425p-858 | 0x1.cf0ac9c083a9ap-249
++  v_result = 0x0p+0 | 0x0p+0
++insn vfidb04:
++  v_arg1   = 0x1.ec22dc8481352p+516 | 0x1.948a15e99787bp+705
++  v_result = 0x1.ec22dc8481352p+516 | 0x1.948a15e99787bp+705
++insn vfidb04:
++  v_arg1   = 0x1.aa3c092bc234ap-99 | -0x1.1a67dee375837p-741
++  v_result = 0x0p+0 | -0x0p+0
++insn vfidb04:
++  v_arg1   = -0x1.0954410f3f66p-870 | -0x1.959f40b0d52d1p+679
++  v_result = -0x0p+0 | -0x1.959f40b0d52d1p+679
++insn vfidb05:
++  v_arg1   = 0x1.714e0b00c3609p+188 | -0x1.7e3b89779752bp-897
++  v_result = 0x1.714e0b00c3609p+188 | -0x0p+0
++insn vfidb05:
++  v_arg1   = 0x1.2d4b405512095p-36 | -0x1.cbf3a5cc327c4p+987
++  v_result = 0x0p+0 | -0x1.cbf3a5cc327c4p+987
++insn vfidb05:
++  v_arg1   = -0x1.47fa188fc49f3p-399 | 0x1.a1d66c8e3e178p-350
++  v_result = -0x0p+0 | 0x0p+0
++insn vfidb05:
++  v_arg1   = 0x1.e760458f45d6fp-672 | -0x1.ea169b23ef443p+754
++  v_result = 0x0p+0 | -0x1.ea169b23ef443p+754
++insn vfidb06:
++  v_arg1   = 0x1.e8c7afa8edb76p-616 | -0x1.4286e146748fdp+864
++  v_result = 0x1p+0 | -0x1.4286e146748fdp+864
++insn vfidb06:
++  v_arg1   = 0x1.0cf9c1b4fdb5p-852 | 0x1.9845bcfe1181dp+687
++  v_result = 0x1p+0 | 0x1.9845bcfe1181dp+687
++insn vfidb06:
++  v_arg1   = -0x1.f40c24aa8cae3p+141 | -0x1.33b966adbb779p+18
++  v_result = -0x1.f40c24aa8cae3p+141 | -0x1.33b94p+18
++insn vfidb06:
++  v_arg1   = 0x1.497c3bfb72975p+895 | 0x1.94dc5d4f14f02p+866
++  v_result = 0x1.497c3bfb72975p+895 | 0x1.94dc5d4f14f02p+866
++insn vfidb07:
++  v_arg1   = 0x1.400b2180c5169p+9 | -0x1.0eb881ef09e8bp+144
++  v_result = 0x1.4p+9 | -0x1.0eb881ef09e8bp+144
++insn vfidb07:
++  v_arg1   = 0x1.5e1a1176032ffp-694 | 0x1.a413f4290b781p+986
++  v_result = 0x0p+0 | 0x1.a413f4290b781p+986
++insn vfidb07:
++  v_arg1   = 0x1.89260655d1017p+657 | -0x1.82ecae03ac7b3p-465
++  v_result = 0x1.89260655d1017p+657 | -0x1p+0
++insn vfidb07:
++  v_arg1   = -0x1.e233d525b46edp+954 | 0x1.70742fcc3ce0bp+148
++  v_result = -0x1.e233d525b46edp+954 | 0x1.70742fcc3ce0bp+148
++insn wfidb00:
++  v_arg1   = -0x1.61bc4941f04ddp-821 | 0x1.658c3c22e6351p+180
++  v_result = -0x0p+0 | --
++insn wfidb00:
++  v_arg1   = -0x1.b347e049e111fp-420 | 0x1.da424426c71edp-950
++  v_result = -0x0p+0 | --
++insn wfidb00:
++  v_arg1   = 0x1.920b565b7898ap+329 | 0x1.520bc351efda4p-592
++  v_result = 0x1.920b565b7898ap+329 | --
++insn wfidb00:
++  v_arg1   = -0x1.8482d1dfaa054p+729 | 0x1.57c1eb750de59p-154
++  v_result = -0x1.8482d1dfaa054p+729 | --
++insn wfidb01:
++  v_arg1   = -0x1.e88ebfa665fcep+172 | -0x1.29bdb0b3e83ccp+147
++  v_result = -0x1.e88ebfa665fcep+172 | --
++insn wfidb01:
++  v_arg1   = 0x1.0f5f1ef25622bp-839 | -0x1.d57455b11b25dp+173
++  v_result = 0x0p+0 | --
++insn wfidb01:
++  v_arg1   = 0x1.098fed551a139p+372 | 0x1.73f2976a143c8p+826
++  v_result = 0x1.098fed551a139p+372 | --
++insn wfidb01:
++  v_arg1   = -0x1.f30512cb12425p-608 | 0x1.e58939033eae8p-891
++  v_result = -0x0p+0 | --
++insn wfidb03:
++  v_arg1   = -0x1.af465d77bce39p+75 | -0x1.0e08c063beb77p-766
++  v_result = -0x1.af465d77bce39p+75 | --
++insn wfidb03:
++  v_arg1   = -0x1.f50b5e41314ap-764 | -0x1.607de181ae4ccp-591
++  v_result = -0x1p+0 | --
++insn wfidb03:
++  v_arg1   = 0x1.8a47842c8c31fp-50 | -0x1.8b5cdaee0879ap+947
++  v_result = 0x1p+0 | --
++insn wfidb03:
++  v_arg1   = 0x1.d08648a9cbedcp+182 | -0x1.e47de14095eb5p-832
++  v_result = 0x1.d08648a9cbedcp+182 | --
++insn wfidb04:
++  v_arg1   = 0x1.50b6db7fbbd1ap+133 | -0x1.c5293bf4286cfp+694
++  v_result = 0x1.50b6db7fbbd1ap+133 | --
++insn wfidb04:
++  v_arg1   = -0x1.57085ee8210f9p-986 | 0x1.45f2b06247536p+35
++  v_result = -0x0p+0 | --
++insn wfidb04:
++  v_arg1   = -0x1.df15d38b85b39p+278 | -0x1.6ae64eaf6b596p+961
++  v_result = -0x1.df15d38b85b39p+278 | --
++insn wfidb04:
++  v_arg1   = 0x1.0fc2143d758f6p+241 | -0x1.2f53bcf6ea7bcp-843
++  v_result = 0x1.0fc2143d758f6p+241 | --
++insn wfidb05:
++  v_arg1   = 0x1.c793f2582996cp-505 | 0x1.31faa416f414fp-393
++  v_result = 0x0p+0 | --
++insn wfidb05:
++  v_arg1   = 0x1.c831f1a8f44b3p-318 | -0x1.30d67b0cbd098p-799
++  v_result = 0x0p+0 | --
++insn wfidb05:
++  v_arg1   = -0x1.c2aea42bdd582p+522 | -0x1.d58aa3500b839p+73
++  v_result = -0x1.c2aea42bdd582p+522 | --
++insn wfidb05:
++  v_arg1   = -0x1.33846647de0efp+805 | -0x1.40ee74cfe2ff8p+336
++  v_result = -0x1.33846647de0efp+805 | --
++insn wfidb06:
++  v_arg1   = 0x1.9ea16aeaccd2bp-592 | -0x1.0718e98de0774p-791
++  v_result = 0x1p+0 | --
++insn wfidb06:
++  v_arg1   = -0x1.2b33d73559b49p+432 | 0x1.0bcd0a3aa62edp+137
++  v_result = -0x1.2b33d73559b49p+432 | --
++insn wfidb06:
++  v_arg1   = 0x1.0fd5bed729ef7p-136 | -0x1.7de5c9c1a7cffp-542
++  v_result = 0x1p+0 | --
++insn wfidb06:
++  v_arg1   = 0x1.3e88df9ab4141p+1001 | 0x1.23d1c18546565p-208
++  v_result = 0x1.3e88df9ab4141p+1001 | --
++insn wfidb07:
++  v_arg1   = 0x1.a0a30de14c554p-995 | 0x1.f75fbd2aac4b9p+721
++  v_result = 0x0p+0 | --
++insn wfidb07:
++  v_arg1   = -0x1.22d9d06f10138p+388 | 0x1.617a16b5e9631p-40
++  v_result = -0x1.22d9d06f10138p+388 | --
++insn wfidb07:
++  v_arg1   = -0x1.415ecc4742193p-484 | -0x1.26b342b60ed63p+353
++  v_result = -0x1p+0 | --
++insn wfidb07:
++  v_arg1   = 0x1.a38b40d7c686bp+18 | 0x1.72f17be0db2p+786
++  v_result = 0x1.a38b4p+18 | --
++insn vledb00:
++  v_arg1   = -0x1.a84c84057eee2p-484 | 0x1.c57adf9f0649bp-745
++  v_result = -0x0p+0 | -- | 0x0p+0 | --
++insn vledb00:
++  v_arg1   = 0x1.81df9df7f63fbp+804 | 0x1.1cb169383d862p-99
++  v_result = 0x1.fffffep+127 | -- | 0x1.1cb168p-99 | --
++insn vledb00:
++  v_arg1   = -0x1.71dd9545fca52p+677 | -0x1.92cefededf8e1p-117
++  v_result = -0x1.fffffep+127 | -- | -0x1.92cefep-117 | --
++insn vledb00:
++  v_arg1   = -0x1.65375ad0e40e7p-937 | 0x1.09014cbc484c5p+485
++  v_result = -0x0p+0 | -- | 0x1.fffffep+127 | --
++insn vledb01:
++  v_arg1   = -0x1.505196110b3d2p+107 | -0x1.3426019ccd495p+80
++  v_result = -0x1.505196p+107 | -- | -0x1.342602p+80 | --
++insn vledb01:
++  v_arg1   = -0x1.0af0f091bac0ep+839 | 0x1.e846aa8b59579p-876
++  v_result = -inf | -- | 0x0p+0 | --
++insn vledb01:
++  v_arg1   = -0x1.2c25e28cf0631p+481 | -0x1.84e49efdf88f6p-761
++  v_result = -inf | -- | -0x0p+0 | --
++insn vledb01:
++  v_arg1   = -0x1.2668ee57bb531p-627 | -0x1.70c4fcb1747afp+53
++  v_result = -0x0p+0 | -- | -0x1.70c4fcp+53 | --
++insn vledb03:
++  v_arg1   = 0x1.83961ccdd811fp-57 | -0x1.164d03f590024p+321
++  v_result = 0x1.83961ep-57 | -- | -0x1.fffffep+127 | --
++insn vledb03:
++  v_arg1   = -0x1.70f9991e0c8eep-335 | 0x1.7eedb358f3874p+893
++  v_result = -0x1p-149 | -- | 0x1.fffffep+127 | --
++insn vledb03:
++  v_arg1   = 0x1.2b0b7cd5f402cp+157 | -0x1.bfafe3c4f891dp-342
++  v_result = 0x1.fffffep+127 | -- | -0x1p-149 | --
++insn vledb03:
++  v_arg1   = -0x1.a9eb9c0dfb4c6p+89 | 0x1.a4f0449a065bap+737
++  v_result = -0x1.a9eb9ep+89 | -- | 0x1.fffffep+127 | --
++insn vledb04:
++  v_arg1   = -0x1.dccda0e58c3c6p+254 | -0x1.1e7b977b4d2c3p-832
++  v_result = -inf | -- | -0x0p+0 | --
++insn vledb04:
++  v_arg1   = -0x1.8685582eca417p+537 | 0x1.ab5a3c7ae2d4fp+276
++  v_result = -inf | -- | inf | --
++insn vledb04:
++  v_arg1   = -0x1.49320cface53ep+903 | 0x1.e5fc9e15ce8d3p+298
++  v_result = -inf | -- | inf | --
++insn vledb04:
++  v_arg1   = 0x1.b25b34a582821p+386 | 0x1.4056fd2fc4ce3p-361
++  v_result = inf | -- | 0x0p+0 | --
++insn vledb05:
++  v_arg1   = 0x1.26ac2b21ee5c2p+207 | 0x1.ff8d7ccf938eep-142
++  v_result = 0x1.fffffep+127 | -- | 0x1.fep-142 | --
++insn vledb05:
++  v_arg1   = -0x1.fe8fde9582b04p+564 | 0x1.28400eaaee105p+536
++  v_result = -0x1.fffffep+127 | -- | 0x1.fffffep+127 | --
++insn vledb05:
++  v_arg1   = -0x1.317d5b9516063p-163 | -0x1.ea868ea209093p+333
++  v_result = -0x0p+0 | -- | -0x1.fffffep+127 | --
++insn vledb05:
++  v_arg1   = -0x1.027399100fdbfp-546 | -0x1.1d9ccf1c66825p+36
++  v_result = -0x0p+0 | -- | -0x1.1d9ccep+36 | --
++insn vledb06:
++  v_arg1   = 0x1.2bf5345ca531p+982 | 0x1.7c3e64b441d22p-449
++  v_result = inf | -- | 0x1p-149 | --
++insn vledb06:
++  v_arg1   = -0x1.8b94ed2434a31p+1001 | 0x1.c092c292abf92p+853
++  v_result = -0x1.fffffep+127 | -- | inf | --
++insn vledb06:
++  v_arg1   = 0x1.ce81218ec1d98p+236 | 0x1.6009662b86edap+985
++  v_result = inf | -- | inf | --
++insn vledb06:
++  v_arg1   = -0x1.5d2059ff4201bp+513 | 0x1.d7857339c237dp-955
++  v_result = -0x1.fffffep+127 | -- | 0x1p-149 | --
++insn vledb07:
++  v_arg1   = 0x1.a76ca53f97aabp-255 | -0x1.674a200b06edbp-581
++  v_result = 0x0p+0 | -- | -0x1p-149 | --
++insn vledb07:
++  v_arg1   = 0x1.0080548c7ec1bp+989 | 0x1.2ee6511bf33f3p+395
++  v_result = 0x1.fffffep+127 | -- | 0x1.fffffep+127 | --
++insn vledb07:
++  v_arg1   = -0x1.9b113781789d9p-813 | -0x1.2950f56406c23p-653
++  v_result = -0x1p-149 | -- | -0x1p-149 | --
++insn vledb07:
++  v_arg1   = 0x1.651d480507cb1p+722 | -0x1.58f4c2418ebe6p-70
++  v_result = 0x1.fffffep+127 | -- | -0x1.58f4c4p-70 | --
++insn wledb00:
++  v_arg1   = 0x1.43d646747c59p-257 | -0x1.737c6f65a1694p+700
++  v_result = 0x0p+0 | -- | -- | --
++insn wledb00:
++  v_arg1   = -0x1.201dc5801fd3dp-331 | -0x1.2e0e52d09aa24p+358
++  v_result = -0x0p+0 | -- | -- | --
++insn wledb00:
++  v_arg1   = 0x1.81f14646f0e21p+15 | 0x1.f918fd1d379ebp+784
++  v_result = 0x1.81f146p+15 | -- | -- | --
++insn wledb00:
++  v_arg1   = -0x1.fcf63412ffdffp-746 | -0x1.4c8e74fd72c5cp-193
++  v_result = -0x0p+0 | -- | -- | --
++insn wledb01:
++  v_arg1   = 0x1.ebe5b0e50a1bap+140 | 0x1.638103a5e01c9p+504
++  v_result = inf | -- | -- | --
++insn wledb01:
++  v_arg1   = -0x1.9d0900d0d6914p+359 | -0x1.78bea0aa48f2p-76
++  v_result = -inf | -- | -- | --
++insn wledb01:
++  v_arg1   = 0x1.3de51688f1b6cp-210 | 0x1.721d2e08e7eadp+312
++  v_result = 0x0p+0 | -- | -- | --
++insn wledb01:
++  v_arg1   = -0x1.d796ceeae907ep-668 | -0x1.6cf64417450ddp-126
++  v_result = -0x0p+0 | -- | -- | --
++insn wledb03:
++  v_arg1   = 0x1.3a6edd4af7926p+104 | 0x1.fa23bd7d81cf7p+68
++  v_result = 0x1.3a6edep+104 | -- | -- | --
++insn wledb03:
++  v_arg1   = 0x1.4a0dd74061d1cp+154 | -0x1.d9bae342b4ee3p+307
++  v_result = 0x1.fffffep+127 | -- | -- | --
++insn wledb03:
++  v_arg1   = 0x1.99a06111419b7p-275 | -0x1.871938f8d69e6p-833
++  v_result = 0x1p-149 | -- | -- | --
++insn wledb03:
++  v_arg1   = -0x1.a7bac92e920acp+145 | -0x1.752ff858cc562p-671
++  v_result = -0x1.fffffep+127 | -- | -- | --
++insn wledb04:
++  v_arg1   = -0x1.fa1544402b9cfp+862 | -0x1.ea203dae35299p+583
++  v_result = -inf | -- | -- | --
++insn wledb04:
++  v_arg1   = 0x1.c9f7f990a04cfp+258 | -0x1.0bb6e363b546ap+690
++  v_result = inf | -- | -- | --
++insn wledb04:
++  v_arg1   = 0x1.3ff6eeb9a76fdp-981 | 0x1.dac90e9ec2511p+619
++  v_result = 0x0p+0 | -- | -- | --
++insn wledb04:
++  v_arg1   = 0x1.401df3afc9905p+883 | 0x1.4fcf4a8bbf7e9p-598
++  v_result = inf | -- | -- | --
++insn wledb05:
++  v_arg1   = 0x1.f5bcdeae2ceb1p-482 | -0x1.064234e9c8f2cp-825
++  v_result = 0x0p+0 | -- | -- | --
++insn wledb05:
++  v_arg1   = 0x1.ff73387320bacp-138 | -0x1.d99679d700cbp+220
++  v_result = 0x1.ff6p-138 | -- | -- | --
++insn wledb05:
++  v_arg1   = 0x1.eb9c782bd9d3bp+916 | 0x1.30084fbc69faap-269
++  v_result = 0x1.fffffep+127 | -- | -- | --
++insn wledb05:
++  v_arg1   = -0x1.737c1f102e804p+703 | 0x1.7787f359d506ep-790
++  v_result = -0x1.fffffep+127 | -- | -- | --
++insn wledb06:
++  v_arg1   = -0x1.d7f9453ee23c9p-667 | -0x1.01459401fc02bp-872
++  v_result = -0x0p+0 | -- | -- | --
++insn wledb06:
++  v_arg1   = 0x1.7d5b34b9d1d2cp+188 | 0x1.fdfd3f465e2b2p+97
++  v_result = inf | -- | -- | --
++insn wledb06:
++  v_arg1   = 0x1.7734c6119fb6cp+504 | 0x1.4972ad038c12ep-213
++  v_result = inf | -- | -- | --
++insn wledb06:
++  v_arg1   = 0x1.d480ec418f825p+795 | 0x1.e73dbbacd3fecp-1
++  v_result = inf | -- | -- | --
++insn wledb07:
++  v_arg1   = 0x1.7bbe60bc02413p-511 | 0x1.ade60bc87d013p-400
++  v_result = 0x0p+0 | -- | -- | --
++insn wledb07:
++  v_arg1   = -0x1.365bcf06526cdp+361 | 0x1.23aefc8b7436bp-449
++  v_result = -inf | -- | -- | --
++insn wledb07:
++  v_arg1   = -0x1.9db391449fb8dp-1005 | -0x1.e9f40755e7a19p-55
++  v_result = -0x1p-149 | -- | -- | --
++insn wledb07:
++  v_arg1   = 0x1.46282bf59b5e5p+334 | 0x1.59946c0e82d5fp+936
++  v_result = 0x1.fffffep+127 | -- | -- | --
++insn vldeb:
++  v_arg1   = -0x1.8b9fd9ef53d8ap-833 | -0x1.aeef3cdf1ac5fp-282
++  v_result = -0x1.d173fap-104 | -0x1.b5dde6p-35
++insn vldeb:
++  v_arg1   = 0x1.cd30a83a7130bp-430 | 0x1.256f7a4029ad8p-286
++  v_result = 0x1.39a614p-53 | 0x1.24adeep-35
++insn vldeb:
++  v_arg1   = -0x1.09bc929ea0999p-364 | 0x1.c4281f653b3e6p-652
++  v_result = -0x1.613792p-45 | 0x1.788502p-81
++insn vldeb:
++  v_arg1   = -0x1.7afd9ede30cbfp+556 | -0x1.696fbd68a88c4p-863
++  v_result = -0x1.6f5fb2p+70 | -0x1.0d2df6p-107
++insn wldeb:
++  v_arg1   = -0x1.d26169729db2ap-435 | 0x1.d6fd080793e8cp+767
++  v_result = -0x1.9a4c2cp-54 | 0x0p+0
++insn wldeb:
++  v_arg1   = -0x1.f4b59107fce61p-930 | 0x1.cdf2816e253f4p-168
++  v_result = -0x1.be96b2p-116 | 0x0p+0
++insn wldeb:
++  v_arg1   = -0x1.9603a2997928cp-441 | -0x1.aada85e355a11p-767
++  v_result = -0x1.d2c074p-55 | 0x0p+0
++insn wldeb:
++  v_arg1   = 0x1.25ccf5bd0e83p+620 | 0x1.e1635864ebb17p-88
++  v_result = 0x1.64b99ep+78 | 0x0p+0
++insn vflcdb:
++  v_arg1   = 0x1.0ae6d82f76afp-166 | -0x1.e8fb1e03a7415p-191
++  v_result = -0x1.0ae6d82f76afp-166 | 0x1.e8fb1e03a7415p-191
++insn vflcdb:
++  v_arg1   = 0x1.9f865a209464cp+19 | 0x1.a81bca7f2dbbcp-960
++  v_result = -0x1.9f865a209464cp+19 | -0x1.a81bca7f2dbbcp-960
++insn vflcdb:
++  v_arg1   = 0x1.ed6c6a3ed0163p-5 | 0x1.40b73b91e5a17p+838
++  v_result = -0x1.ed6c6a3ed0163p-5 | -0x1.40b73b91e5a17p+838
++insn vflcdb:
++  v_arg1   = 0x1.19520153d35b4p-301 | 0x1.ac5325cd23253p+396
++  v_result = -0x1.19520153d35b4p-301 | -0x1.ac5325cd23253p+396
++insn wflcdb:
++  v_arg1   = 0x1.ffd3eecfd54d7p-831 | -0x1.97854fa523a77p+146
++  v_result = -0x1.ffd3eecfd54d7p-831 | 0x0p+0
++insn wflcdb:
++  v_arg1   = -0x1.508ea45606447p-442 | 0x1.ae7f0e6cf9d2bp+583
++  v_result = 0x1.508ea45606447p-442 | 0x0p+0
++insn wflcdb:
++  v_arg1   = 0x1.da8ab2188c21ap+94 | 0x1.78a9c152aa074p-808
++  v_result = -0x1.da8ab2188c21ap+94 | 0x0p+0
++insn wflcdb:
++  v_arg1   = -0x1.086882645e0c5p-1001 | -0x1.54e2de5af5a74p-262
++  v_result = 0x1.086882645e0c5p-1001 | 0x0p+0
++insn vflndb:
++  v_arg1   = -0x1.5bec561d407dcp+819 | -0x1.a5773dadb7a2dp+935
++  v_result = -0x1.5bec561d407dcp+819 | -0x1.a5773dadb7a2dp+935
++insn vflndb:
++  v_arg1   = -0x1.fa5a407a116cep+972 | 0x1.7bf005c15063dp-437
++  v_result = -0x1.fa5a407a116cep+972 | -0x1.7bf005c15063dp-437
++insn vflndb:
++  v_arg1   = -0x1.184242f0442acp-994 | -0x1.e54e17c7617a2p-355
++  v_result = -0x1.184242f0442acp-994 | -0x1.e54e17c7617a2p-355
++insn vflndb:
++  v_arg1   = -0x1.c5bc39a06d4e2p-259 | 0x1.c5e61ad849e77p-833
++  v_result = -0x1.c5bc39a06d4e2p-259 | -0x1.c5e61ad849e77p-833
++insn wflndb:
++  v_arg1   = -0x1.e9f3e6d1beffap-117 | -0x1.d58cc8bf123b3p-714
++  v_result = -0x1.e9f3e6d1beffap-117 | 0x0p+0
++insn wflndb:
++  v_arg1   = -0x1.3fc4ef2e7485ep-691 | 0x1.eb328986081efp-775
++  v_result = -0x1.3fc4ef2e7485ep-691 | 0x0p+0
++insn wflndb:
++  v_arg1   = -0x1.7146c5afdec16p+23 | -0x1.597fcfa1fab2p-708
++  v_result = -0x1.7146c5afdec16p+23 | 0x0p+0
++insn wflndb:
++  v_arg1   = 0x1.03f8d7e9afe84p-947 | 0x1.9a10c3feb6b57p-118
++  v_result = -0x1.03f8d7e9afe84p-947 | 0x0p+0
++insn vflpdb:
++  v_arg1   = 0x1.64ae59b6c762ep-407 | -0x1.fa7191ab21e86p+533
++  v_result = 0x1.64ae59b6c762ep-407 | 0x1.fa7191ab21e86p+533
++insn vflpdb:
++  v_arg1   = -0x1.e39a61250e473p-116 | -0x1.970a4244b7a3dp+800
++  v_result = 0x1.e39a61250e473p-116 | 0x1.970a4244b7a3dp+800
++insn vflpdb:
++  v_arg1   = -0x1.905c12e0e2c53p+264 | 0x1.87daa9c3e4967p-647
++  v_result = 0x1.905c12e0e2c53p+264 | 0x1.87daa9c3e4967p-647
++insn vflpdb:
++  v_arg1   = -0x1.85fa2de1d492ap+170 | 0x1.ac36828822c11p-968
++  v_result = 0x1.85fa2de1d492ap+170 | 0x1.ac36828822c11p-968
++insn wflpdb:
++  v_arg1   = 0x1.a6cf677640a73p-871 | 0x1.b6f1792385922p-278
++  v_result = 0x1.a6cf677640a73p-871 | 0x0p+0
++insn wflpdb:
++  v_arg1   = -0x1.b886774f6d888p-191 | -0x1.6a2b08d735d22p-643
++  v_result = 0x1.b886774f6d888p-191 | 0x0p+0
++insn wflpdb:
++  v_arg1   = 0x1.5045d37d46f5fp+943 | -0x1.333a86ef2dcf6p-1013
++  v_result = 0x1.5045d37d46f5fp+943 | 0x0p+0
++insn wflpdb:
++  v_arg1   = 0x1.1e7bec6ada14dp+252 | 0x1.a70b3f3e24dap-153
++  v_result = 0x1.1e7bec6ada14dp+252 | 0x0p+0
++insn vfadb:
++  v_arg1   = 0x1.5b1ad8e9f17c6p-294 | -0x1.ddd8300a0bf02p+122
++  v_arg2   = -0x1.9b49c31ca8ac6p+926 | 0x1.fdbc992926268p+677
++  v_result = -0x1.9b49c31ca8ac5p+926 | 0x1.fdbc992926267p+677
++insn vfadb:
++  v_arg1   = -0x1.6144d24f60f19p+321 | -0x1.0f4885e73979ap+190
++  v_arg2   = 0x1.cf70ab6af95e5p-656 | -0x1.d2a10763bba9ep+317
++  v_result = -0x1.6144d24f60f18p+321 | -0x1.d2a10763bba9ep+317
++insn vfadb:
++  v_arg1   = -0x1.6ba7d00ea2037p-839 | 0x1.3e5b07b555046p-553
++  v_arg2   = -0x1.d400afb20401fp+608 | 0x1.600f85fbc2774p-86
++  v_result = -0x1.d400afb20401fp+608 | 0x1.600f85fbc2774p-86
++insn vfadb:
++  v_arg1   = -0x1.5039c4164f26bp+471 | -0x1.554272eaa3a01p-539
++  v_arg2   = 0x1.a3a594bc042dep+515 | 0x1.6d08aceb68682p+706
++  v_result = 0x1.a3a594bc0418dp+515 | 0x1.6d08aceb68681p+706
++insn wfadb:
++  v_arg1   = 0x1.3c5466cb80722p+489 | -0x1.11e1770053ca2p+924
++  v_arg2   = 0x1.d876cd721a726p-946 | 0x1.5c04ceb79c9bcp+1001
++  v_result = 0x1.3c5466cb80722p+489 | 0x0p+0
++insn wfadb:
++  v_arg1   = 0x1.b0b142d6b76a3p+577 | 0x1.3146824e993a2p+432
++  v_arg2   = -0x1.f7f3b7582925fp-684 | -0x1.9700143c2b935p-837
++  v_result = 0x1.b0b142d6b76a2p+577 | 0x0p+0
++insn wfadb:
++  v_arg1   = -0x1.8d65e15edabd6p+244 | 0x1.3be7fd08492d6p-141
++  v_arg2   = -0x1.5eef86490fb0ap+481 | 0x1.7b26c897cb6dfp+810
++  v_result = -0x1.5eef86490fb0ap+481 | 0x0p+0
++insn wfadb:
++  v_arg1   = -0x1.2dffa5b5f29p+34 | 0x1.71a026274602fp-881
++  v_arg2   = 0x1.4dad707287289p+756 | -0x1.1500d55807247p-616
++  v_result = 0x1.4dad707287288p+756 | 0x0p+0
++insn vfsdb:
++  v_arg1   = 0x1.054fd9c4d4883p+644 | 0x1.45c90ed85bd7fp-780
++  v_arg2   = 0x1.f3bc7a611dadap+494 | -0x1.7c9e1e858ba5bp-301
++  v_result = 0x1.054fd9c4d4882p+644 | 0x1.7c9e1e858ba5bp-301
++insn vfsdb:
++  v_arg1   = -0x1.697779c72f8a1p-232 | 0x1.cac8c6a6fbe36p-751
++  v_arg2   = 0x1.6c23630c5305bp-897 | 0x1.91525e7f72d26p+516
++  v_result = -0x1.697779c72f8a1p-232 | -0x1.91525e7f72d25p+516
++insn vfsdb:
++  v_arg1   = 0x1.7033a03797d39p-722 | 0x1.fecd2799b8d1fp-588
++  v_arg2   = -0x1.794d0fc274286p+204 | 0x1.25d121c810391p-344
++  v_result = 0x1.794d0fc274286p+204 | -0x1.25d121c81039p-344
++insn vfsdb:
++  v_arg1   = 0x1.3a79321b93187p+146 | 0x1.d707e1ddd2a26p-13
++  v_arg2   = -0x1.00c3f844d79b5p+354 | 0x1.dc5a03907c923p-869
++  v_result = 0x1.00c3f844d79b5p+354 | 0x1.d707e1ddd2a25p-13
++insn wfsdb:
++  v_arg1   = 0x1.9090dabf846e7p-648 | 0x1.1c4ab843a2d15p+329
++  v_arg2   = -0x1.a7ceb293690dep+316 | 0x1.22245954a20cp+42
++  v_result = 0x1.a7ceb293690dep+316 | 0x0p+0
++insn wfsdb:
++  v_arg1   = 0x1.4e5347c27819p-933 | -0x1.56a30bda28351p-64
++  v_arg2   = -0x1.dedb9f3935b56p-155 | 0x1.8c5b6ed76816cp-522
++  v_result = 0x1.dedb9f3935b56p-155 | 0x0p+0
++insn wfsdb:
++  v_arg1   = 0x1.0ec4e562a015bp-491 | 0x1.3996381b52d9fp-686
++  v_arg2   = 0x1.1dcce4e81819p+960 | -0x1.32fa425e8fc08p-263
++  v_result = -0x1.1dcce4e81818fp+960 | 0x0p+0
++insn wfsdb:
++  v_arg1   = -0x1.587229f90f77dp-19 | 0x1.100d8eb8105e4p-784
++  v_arg2   = -0x1.afb4cce4c43ddp+530 | -0x1.6da7f05e7f512p-869
++  v_result = 0x1.afb4cce4c43dcp+530 | 0x0p+0
++insn vfmdb:
++  v_arg1   = 0x1.892b425556c47p-124 | 0x1.38222404079dfp-656
++  v_arg2   = 0x1.af612ed2c342dp-267 | -0x1.1f735fd6ce768p-877
++  v_result = 0x1.4b428afda35a7p-390 | -0x0p+0
++insn vfmdb:
++  v_arg1   = -0x1.02106dba6feecp-272 | 0x1.cf890a91d4eefp-455
++  v_arg2   = -0x1.12c7fc909ffcbp+782 | -0x1.22bf2e2dd2204p-721
++  v_result = 0x1.14ff2ed0ce42bp+510 | -0x0p+0
++insn vfmdb:
++  v_arg1   = -0x1.e3fd7999ca339p+101 | 0x1.cf2eff4ef5fd2p+816
++  v_arg2   = -0x1.e722ee73a2523p-135 | 0x1.652dfb0cc8dbfp+179
++  v_result = 0x1.cc7c9e66fd70ap-33 | 0x1.431fddc319ee2p+996
++insn vfmdb:
++  v_arg1   = 0x1.2aa65e0fe665dp+729 | 0x1.1774d58fb5c62p+50
++  v_arg2   = -0x1.ed5baf340bd7ep+475 | -0x1.83de646bb6511p+564
++  v_result = -0x1.fffffffffffffp+1023 | -0x1.a76863c8aab11p+614
++insn wfmdb:
++  v_arg1   = -0x1.b992d950126a1p-683 | -0x1.9c1b22eb58c59p-497
++  v_arg2   = 0x1.b557a7d8e32c3p-25 | -0x1.f746b2ddafccep+227
++  v_result = -0x1.792f6fb13894ap-707 | 0x0p+0
++insn wfmdb:
++  v_arg1   = -0x1.677a8c20a5a2fp+876 | 0x1.c03e7b97e8c0dp-645
++  v_arg2   = 0x1.dab44be430937p-1011 | -0x1.3f51352c67be9p-916
++  v_result = -0x1.4d4b0a1827064p-134 | 0x0p+0
++insn wfmdb:
++  v_arg1   = -0x1.da60f596ad0cep+254 | 0x1.52332e0650e33p+966
++  v_arg2   = 0x1.a042c52ed993cp+215 | 0x1.8f380c84aa133p+204
++  v_result = -0x1.81aca4bbcbd24p+470 | 0x0p+0
++insn wfmdb:
++  v_arg1   = -0x1.83d17f11f6aa3p-469 | -0x1.98117efe89b9ep-361
++  v_arg2   = 0x1.8c445fd46d214p-701 | -0x1.f98118821821cp+596
++  v_result = -0x0p+0 | 0x0p+0
++insn vfddb:
++  v_arg1   = -0x1.ecbb48899e0f1p+969 | 0x1.caf175ab352p-20
++  v_arg2   = -0x1.9455d67f9f79dp+208 | 0x1.bc4a431b04a6fp+482
++  v_result = 0x1.37f78f2cbe546p+761 | 0x1.087170c12984cp-502
++insn vfddb:
++  v_arg1   = 0x1.213d83f7082d8p-330 | 0x1.237737a5fa7a6p+548
++  v_arg2   = 0x1.d96c3df5d6415p-214 | -0x1.8cd56c8cef818p+139
++  v_result = 0x1.38cf2a1e99e53p-117 | -0x1.780d86d7eff49p+408
++insn vfddb:
++  v_arg1   = 0x1.9ce332231f317p-915 | -0x1.a58e84e32263ep-1000
++  v_arg2   = 0x1.23d041c374ad6p-905 | -0x1.33e41797e24ep+986
++  v_result = 0x1.6a3702fbc252cp-10 | 0x0p+0
++insn vfddb:
++  v_arg1   = -0x1.26cf3de11efccp-342 | 0x1.3ca733ce42f94p-818
++  v_arg2   = -0x1.5f5a8f87a6e19p+319 | 0x1.8993c56b2ba2dp+426
++  v_result = 0x1.ad9a43954644bp-662 | 0x0p+0
++insn wfddb:
++  v_arg1   = 0x1.bd48489b60731p-114 | 0x1.a760dcf57b74fp-51
++  v_arg2   = -0x1.171f83409eeb6p-402 | -0x1.e159d1409bdc6p-972
++  v_result = -0x1.9864f1511f8cp+288 | 0x0p+0
++insn wfddb:
++  v_arg1   = -0x1.120505ef4606p-637 | -0x1.83f6f775c0eb7p+272
++  v_arg2   = -0x1.d18ba3872fde1p+298 | 0x1.c60f8d191068cp-454
++  v_result = 0x1.2d5cdb15a686cp-936 | 0x0p+0
++insn wfddb:
++  v_arg1   = 0x1.f637f7f8c790fp-97 | -0x1.7bdce4d74947p+189
++  v_arg2   = -0x1.1c8f2d1b3a2edp-218 | -0x1.55fdfd1840241p-350
++  v_result = -0x1.c3d0799c1420fp+121 | 0x0p+0
++insn wfddb:
++  v_arg1   = -0x1.c63b7b2eee253p+250 | 0x1.dfd9dcd8b823fp-125
++  v_arg2   = 0x1.094a1f1f87e0cp+629 | 0x1.eeaa23c0d7843p-814
++  v_result = -0x1.b653a10ebdeccp-379 | 0x0p+0
++insn vfsqdb:
++  v_arg1   = 0x1.f60db25f7066p-703 | -0x1.d43509abca8c3p+631
++  v_result = 0x1.fb009ab25ec11p-352 | nan
++insn vfsqdb:
++  v_arg1   = -0x1.ecbce2bb2e245p-872 | 0x1.cc9173d132a3bp-290
++  v_result = nan | 0x1.575fa6778042ep-145
++insn vfsqdb:
++  v_arg1   = 0x1.9102ffd19ccb3p-205 | -0x1.87e9ee7454345p-374
++  v_result = 0x1.c51ecb6cc318p-103 | nan
++insn vfsqdb:
++  v_arg1   = 0x1.24e1d7ad32eb5p+499 | -0x1.1c7d22b78039bp+918
++  v_result = 0x1.833dba0954bccp+249 | nan
++insn wfsqdb:
++  v_arg1   = 0x1.71af4e7f64978p+481 | -0x1.3429dc60011d7p-879
++  v_result = 0x1.b30fc65551133p+240 | 0x0p+0
++insn wfsqdb:
++  v_arg1   = 0x1.5410db1c5f403p+173 | 0x1.97fa6581e692fp+108
++  v_result = 0x1.a144f43a592c1p+86 | 0x0p+0
++insn wfsqdb:
++  v_arg1   = -0x1.5838027725afep+6 | 0x1.ac61529c11f38p+565
++  v_result = nan | 0x0p+0
++insn wfsqdb:
++  v_arg1   = -0x1.159e341dcc06ep-439 | 0x1.ed54ce5481ba5p-574
++  v_result = nan | 0x0p+0
++insn vfmadb:
++  v_arg1   = -0x1.eb00a5c503d75p+538 | 0x1.89fae603ddc07p+767
++  v_arg2   = -0x1.71c72712c3957p+715 | 0x1.1bd5773442feap+762
++  v_arg3   = 0x1.bd0daed56ada5p+355 | 0x1.618b7cfa37a8bp-935
++  v_result = 0x1.fffffffffffffp+1023 | 0x1.fffffffffffffp+1023
++insn vfmadb:
++  v_arg1   = 0x1.2acc8fc4a8115p-394 | -0x1.b0e5a531a368ep+599
++  v_arg2   = 0x1.7e7c008b06eb6p-26 | -0x1.a3368d351c861p+17
++  v_arg3   = 0x1.665fcd4adbb82p-991 | 0x1.b27284ea351eap+402
++  v_result = 0x1.be6dfa3f5b30dp-420 | 0x1.62720e4cb1583p+617
++insn vfmadb:
++  v_arg1   = -0x1.e66ac8a348fedp-315 | 0x1.8c2ef1e0615c5p+132
++  v_arg2   = 0x1.01397e671d7fdp+313 | -0x1.97c403198fa76p-750
++  v_arg3   = -0x1.1568273c73bf1p-843 | 0x1.8f0b6073eadccp+277
++  v_result = -0x1.e8be715f14671p-2 | 0x1.8f0b6073eadcbp+277
++insn vfmadb:
++  v_arg1   = -0x1.4afc3142483f9p+706 | 0x1.dd14885973858p+695
++  v_arg2   = 0x1.ebc6146439945p-726 | -0x1.77a97fce9117p-586
++  v_arg3   = 0x1.60a3231346326p+102 | -0x1.621f717816614p-653
++  v_result = 0x1.60a3231346325p+102 | -0x1.5e0a7a3b97e9bp+110
++insn wfmadb:
++  v_arg1   = 0x1.1cc5b10a14d54p+668 | -0x1.686407390f7d1p+616
++  v_arg2   = -0x1.bf34549e73246p+676 | -0x1.dc5a34cc470f3p+595
++  v_arg3   = -0x1.95e0fdcf13974p-811 | -0x1.79c7cc1a8ec83p-558
++  v_result = -0x1.fffffffffffffp+1023 | 0x0p+0
++insn wfmadb:
++  v_arg1   = 0x1.138bc1a5d75f8p+713 | -0x1.e226ebba2fe54p+381
++  v_arg2   = -0x1.081ebb7cc3414p-772 | 0x1.369d99e174fc3p+922
++  v_arg3   = -0x1.0671c682a5d0cp-1016 | 0x1.03c9530dd0377p+378
++  v_result = -0x1.1c4933e117d95p-59 | 0x0p+0
++insn wfmadb:
++  v_arg1   = -0x1.166f0b1fad67bp+64 | -0x1.e9ee8d32e1069p-452
++  v_arg2   = -0x1.4a235bdd109e2p-65 | 0x1.bacaa96fc7e81p-403
++  v_arg3   = -0x1.d2e19acf7c4bdp+99 | 0x1.f901130f685adp-963
++  v_result = -0x1.d2e19acf7c4bcp+99 | 0x0p+0
++insn wfmadb:
++  v_arg1   = -0x1.77d7bfec863d2p-988 | -0x1.b68029700c6b1p-206
++  v_arg2   = -0x1.aca05ad00aec1p+737 | 0x1.ac746bd7e216bp+51
++  v_arg3   = 0x1.17342292078b4p+188 | -0x1.49efaf9392301p+555
++  v_result = 0x1.17342292078b4p+188 | 0x0p+0
++insn vfmsdb:
++  v_arg1   = -0x1.a1b218e84e61p+34 | 0x1.b220f0d144daep-111
++  v_arg2   = 0x1.564fcc2527961p-265 | 0x1.ea85a4154721ep+733
++  v_arg3   = 0x1.a6c16c3dc593cp-1012 | -0x1.ba15ae51a252bp+979
++  v_result = -0x1.1743102949c9bp-230 | 0x1.ba15ae51a252bp+979
++insn vfmsdb:
++  v_arg1   = 0x1.f13a61419bc27p+603 | -0x1.f671d1b532c7fp+668
++  v_arg2   = -0x1.68f38da70d3cdp+145 | 0x1.7b7d4b8a38256p+87
++  v_arg3   = -0x1.4830d858cdf7dp-522 | -0x1.ecdfb36fb2682p+537
++  v_result = -0x1.5e89932819567p+749 | -0x1.746835a6a3d29p+756
++insn vfmsdb:
++  v_arg1   = -0x1.82f8829619ba4p+274 | -0x1.886bc5356fc9fp+4
++  v_arg2   = 0x1.ae0143a6fff31p-759 | 0x1.08e9ddebff9acp-192
++  v_arg3   = 0x1.a1c5f6283d74p+602 | 0x1.60722d2eadabcp+573
++  v_result = -0x1.a1c5f6283d74p+602 | -0x1.60722d2eadabcp+573
++insn vfmsdb:
++  v_arg1   = -0x1.6efc50de44d76p-235 | -0x1.546b6a9202facp+17
++  v_arg2   = 0x1.023eb4e92d296p-593 | 0x1.6c05c52e8d255p-408
++  v_arg3   = -0x1.54cc2efc022a8p+360 | 0x1.9ae520664c8abp+486
++  v_result = 0x1.54cc2efc022a7p+360 | -0x1.9ae520664c8abp+486
++insn wfmsdb:
++  v_arg1   = -0x1.7499a639673a6p-100 | -0x1.2a0d737e6cb1cp-207
++  v_arg2   = -0x1.01ad4670a7aa3p-911 | 0x1.f94385e1021e8p+317
++  v_arg3   = 0x1.aa42b2bb17af9p+982 | 0x1.c550e471711p+786
++  v_result = -0x1.aa42b2bb17af8p+982 | 0x0p+0
++insn wfmsdb:
++  v_arg1   = 0x1.76840f99b431ep+500 | -0x1.989a500c92c08p+594
++  v_arg2   = 0x1.33c657cb8385cp-84 | -0x1.2c795ad92ce17p+807
++  v_arg3   = -0x1.ee58a39f02d54p-351 | -0x1.18695ed9a280ap+48
++  v_result = 0x1.c242894a0068p+416 | 0x0p+0
++insn wfmsdb:
++  v_arg1   = -0x1.16db07e054a65p-469 | -0x1.3a627ab99c6e4p+689
++  v_arg2   = 0x1.17872eae826e5p-538 | 0x1.44ed513fb5873p-929
++  v_arg3   = 0x1.5ca912008e077p-217 | -0x1.982a6f7359876p-23
++  v_result = -0x1.5ca912008e077p-217 | 0x0p+0
++insn wfmsdb:
++  v_arg1   = -0x1.d315f4a932c6p+122 | 0x1.616a04493e143p+513
++  v_arg2   = -0x1.cf1cd3516f23fp+552 | 0x1.7121749c3932cp-750
++  v_arg3   = 0x1.dc26d92304d7fp-192 | -0x1.1fc3cca9ec20ep+371
++  v_result = 0x1.a67ca6ba395bcp+675 | 0x0p+0
++insn wfcdb:
++  v_arg1   = 0x1.302001b736011p-633 | -0x1.72d5300225c97p-468
++  v_arg2   = -0x1.8c007c5aba108p-17 | -0x1.bb3f9ae136acdp+569
++  r_result = 0000000000000002
++insn wfcdb:
++  v_arg1   = -0x1.56248d3fff55ap-440 | -0x1.83340f6a06bedp-612
++  v_arg2   = 0x1.5b62caabf4e3ep-302 | 0x1.0465808809e02p+199
++  r_result = 0000000000000001
++insn wfcdb:
++  v_arg1   = 0x1.7cca43b8250bap-969 | 0x1.a2ae4e71459b3p+792
++  v_arg2   = -0x1.2178959d8e9fbp-238 | -0x1.1180e41cc8654p+609
++  r_result = 0000000000000002
++insn wfcdb:
++  v_arg1   = 0x1.96f03c4f3ec0dp-774 | 0x1.a86fcf7f54875p+448
++  v_arg2   = -0x1.a61696da8f939p-732 | -0x1.969b12babcde9p+239
++  r_result = 0000000000000002
++insn wfkdb:
++  v_arg1   = -0x1.af19141b6194ep-304 | 0x1.6f34172e4ec9ap+281
++  v_arg2   = -0x1.903d268d15b8dp-496 | 0x1.132593e7a3848p+663
++  r_result = 0000000000000001
++insn wfkdb:
++  v_arg1   = -0x1.52e78ae61bf57p-979 | -0x1.8132c8874542ap+264
++  v_arg2   = -0x1.7274a70a201eep+729 | 0x1.ee05a55085e12p-508
++  r_result = 0000000000000002
++insn wfkdb:
++  v_arg1   = -0x1.6f8a0ed73189ep-27 | -0x1.93db112e3a289p-560
++  v_arg2   = -0x1.a699712dab56fp-677 | 0x1.5170475506fc8p-437
++  r_result = 0000000000000001
++insn wfkdb:
++  v_arg1   = -0x1.5d56e841d7af8p+346 | -0x1.e40064ce1ce3bp-1012
++  v_arg2   = 0x1.79e790363d4ffp+888 | 0x1.97168873bee8ap-323
++  r_result = 0000000000000001
++insn vfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.8c48762fd0b58p+38 | 0x1.c1f5c994768a1p-819
++  v_arg2   = -0x1.08f71db17132ep+914 | 0x1.a3d14196177d5p-229
++insn vfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.4f88d97dc8b9p+73 | 0x1.6d3a343e053bap+356
++  v_arg2   = -0x1.5bc7cd97d3ee9p+135 | 0x1.641d521c77b43p-114
++insn vfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.b9ce020750f0dp-494 | -0x1.c0d4939228ce1p-82
++  v_arg2   = -0x1.61ad6a28bf43bp-656 | 0x1.b7973bba1ff4dp-877
++insn vfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.d8e5c9930c19dp+623 | -0x1.cf1facff4e194p-605
++  v_arg2   = -0x1.ed6ba02646d0dp+441 | -0x1.2d677e710620bp+810
++insn wfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.a252009e1a12cp-442 | 0x1.4dc608268bb29p-513
++  v_arg2   = -0x1.81020aa1a36e6p-687 | -0x1.300e64ce414f1p-899
++insn wfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.cec439a8d4781p-175 | -0x1.d20e3b281d599p+893
++  v_arg2   = 0x1.ca17cf16cf0aap-879 | 0x1.61506f8596092p+545
++insn wfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.0659f5f24a004p+877 | 0x1.fc46867ed0338p-680
++  v_arg2   = -0x1.1d6849587155ep-1010 | -0x1.f68171edc235fp+575
++insn wfcedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.dc88a0d46ad79p-816 | 0x1.245140dcaed79p+851
++  v_arg2   = 0x1.b33e977c7b3ep-818 | -0x1.04319d7c69367p+787
++insn vfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.ac196c30148c5p-498 | -0x1.a58093963d1aep+355
++  v_arg2   = 0x1.d321b63762fb1p+28 | -0x1.9a68be31efa17p-143
++  r_result = 0000000000000003
++insn vfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.b3657c390dfa7p-452 | 0x1.8a62662f245c4p+1010
++  v_arg2   = -0x1.70208c68a03aep+974 | 0x1.a0729665a79fap+667
++  r_result = 0000000000000003
++insn vfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.3ff1b361c377ep-846 | -0x1.f8fcaa95ff309p+948
++  v_arg2   = 0x1.749db766981d1p-510 | -0x1.d11abab1dc779p+981
++  r_result = 0000000000000003
++insn vfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.2adb2ed7d2b08p-701 | -0x1.be89092fe5ce8p+472
++  v_arg2   = 0x1.ae2c06ea88ff4p+332 | -0x1.f668ce4f8ef9ap+821
++  r_result = 0000000000000003
++insn wfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.645261bf86b1fp-996 | 0x1.abd13c95397aap+992
++  v_arg2   = -0x1.ba09e8fc66a8cp+113 | 0x1.75dbfe92c16c4p-786
++  r_result = 0000000000000003
++insn wfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.d02831d003e7dp+415 | -0x1.611a9dfd10f36p-80
++  v_arg2   = -0x1.10bda62f4647p+723 | 0x1.cc47af6653378p-614
++  r_result = 0000000000000003
++insn wfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.f168f32f84178p-321 | -0x1.79a2a0b9549d1p-136
++  v_arg2   = 0x1.41e19d1cfa692p+11 | -0x1.2a0ed6e7fd517p-453
++  r_result = 0000000000000003
++insn wfcedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.76a9144ee26c5p+188 | -0x1.386aaea2d9cddp-542
++  v_arg2   = 0x1.810fcf222efc4p-999 | -0x1.ce90a9a43e2a1p+80
++  r_result = 0000000000000003
++insn vfchdb:
++  v_result = ffffffffffffffff | ffffffffffffffff
++  v_arg1   = -0x1.a5a0d9e617637p-707 | 0x1.039393f56f89cp+540
++  v_arg2   = -0x1.e08e4bda75373p+861 | -0x1.94f3e6b2a5373p+361
++insn vfchdb:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = 0x1.c7b84b4fa508p-448 | 0x1.00ca9b4b8a0ecp+837
++  v_arg2   = 0x1.9e7afd1c5fe6dp-379 | 0x1.af9353417f907p-20
++insn vfchdb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = -0x1.15637df5529edp-476 | -0x1.3104698aaf00bp-679
++  v_arg2   = -0x1.503783453ef9dp-282 | 0x1.94198721f3bb6p-491
++insn vfchdb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.82be31fb88a2dp+946 | -0x1.7ca9e9ff31953p-931
++  v_arg2   = 0x1.fe75a1052beccp+490 | 0x1.179d18543d678p-255
++insn wfchdb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.0af85d8d8d609p-464 | -0x1.9f639a686e0fep+203
++  v_arg2   = -0x1.3142b77b55761p-673 | 0x1.ca9c474339da1p+472
++insn wfchdb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = -0x1.6cf16959a022bp+213 | 0x1.445606e4363e1p+942
++  v_arg2   = -0x1.8c343201bbd2p+939 | -0x1.e5095ad0c37a4p-434
++insn wfchdb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.36b4fc9cf5bdap-52 | -0x1.f1fd95cbcd533p+540
++  v_arg2   = 0x1.5a2362891c9edp-175 | -0x1.e1f68c319e5d2p+58
++insn wfchdb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.11c6489f544bbp+811 | 0x1.262a740ec3d47p+456
++  v_arg2   = -0x1.d9394d354e989p-154 | 0x1.cc21b3094391ap-972
++insn vfchdbs:
++  v_result = ffffffffffffffff | ffffffffffffffff
++  v_arg1   = 0x1.6efcb54fbf69p+929 | 0x1.021ce0bff3c4cp-827
++  v_arg2   = 0x1.571ae4a8be152p+851 | -0x1.a970c1164e0c9p+737
++  r_result = 0000000000000000
++insn vfchdbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.528f5ccfc3efbp-445 | -0x1.c660b9810c512p-663
++  v_arg2   = -0x1.bcc535b108e06p-294 | 0x1.675d8eddf5a4ap-641
++  r_result = 0000000000000001
++insn vfchdbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.300127b01433ap+86 | -0x1.8f19f65e5e3c6p+633
++  v_arg2   = -0x1.0a88d3c279f7fp-502 | -0x1.d68196f88bde5p+368
++  r_result = 0000000000000003
++insn vfchdbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.e68d08fc23febp+955 | -0x1.0f80357b376b4p+800
++  v_arg2   = 0x1.e426748435a76p+370 | 0x1.8702527d17783p-871
++  r_result = 0000000000000003
++insn wfchdbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.6c51b9f6442c8p+639 | 0x1.1e6b37adff703p+702
++  v_arg2   = 0x1.0cba9c1c75e43p+520 | -0x1.145d44ed90967p+346
++  r_result = 0000000000000000
++insn wfchdbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.7b3dd643bf36bp+816 | -0x1.61ce7bfb9307ap-683
++  v_arg2   = -0x1.f2c998dc15c9ap-776 | 0x1.e16397f2dcdf5p+571
++  r_result = 0000000000000000
++insn wfchdbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.cc3be81884e0ap-865 | -0x1.8b353bd41064p+820
++  v_arg2   = -0x1.2c1bafaafdd4ep-34 | -0x1.24666808ab16ep-435
++  r_result = 0000000000000000
++insn wfchdbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.c3de33d3b673ap+554 | 0x1.d39ed71e53096p-798
++  v_arg2   = -0x1.c1e8f7b3c001p-828 | 0x1.22e2cf797fabp-787
++  r_result = 0000000000000000
++insn vfchedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.fdeb244b026aep-169 | 0x1.870a6fe40fd9ep-132
++  v_arg2   = 0x1.0ce586903392fp-469 | 0x1.cdfd736ae03f8p+471
++insn vfchedb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.89c8a6a740af8p-958 | 0x1.e132e6edb1316p+78
++  v_arg2   = -0x1.f10d2c3491358p+683 | 0x1.0def4f092fca2p+322
++insn vfchedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.a5e8e6900e845p+342 | 0x1.d92b370ee2a1cp+275
++  v_arg2   = 0x1.799f9efc6ef56p+379 | 0x1.ae60d0239ade7p+933
++insn vfchedb:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = -0x1.6c5599e7ba923p+829 | -0x1.5d1a1191ed6eap-994
++  v_arg2   = -0x1.555c8775bc4d2p-478 | -0x1.4aa6a2c82319cp+493
++insn wfchedb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.ae6cad07b0f3ep-232 | -0x1.2ed61a43f3b99p-74
++  v_arg2   = -0x1.226f7cddbde13p-902 | -0x1.790d1d6febbf8p+336
++insn wfchedb:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.20eb8eac3711dp-385 | 0x1.ef71d3312d7e1p+739
++  v_arg2   = 0x1.7a3ba08c5a0bdp-823 | -0x1.a7845ccaa544dp-129
++insn wfchedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.97ebdbc057be8p+824 | 0x1.2b7798b063cd6p+237
++  v_arg2   = 0x1.cdb87a6074294p-81 | -0x1.074c902b19bccp-416
++insn wfchedb:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.82deebf9ff023p+937 | 0x1.56c5adcf9d4abp-672
++  v_arg2   = -0x1.311ce49bc9439p+561 | 0x1.c8e1c512d8544p+103
++insn vfchedbs:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = -0x1.489a0cf606972p-417 | 0x1.a87a278f79c72p+64
++  v_arg2   = 0x1.17ec17aedbaeap+435 | -0x1.f867d39e61ce2p-919
++  r_result = 0000000000000001
++insn vfchedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.33723ef431356p-420 | -0x1.474f097f9ead8p+498
++  v_arg2   = 0x1.4130d6951ee45p+7 | 0x1.791689e1040f1p+354
++  r_result = 0000000000000003
++insn vfchedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.6cf89093275eep-237 | 0x1.451631aa628ebp-186
++  v_arg2   = 0x1.c349eac0f4204p-200 | 0x1.01c558c10699ap+770
++  r_result = 0000000000000003
++insn vfchedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.ea15eabc329b6p+52 | -0x1.7b556461496d6p-682
++  v_arg2   = -0x1.47f5dfc7a5bcp-569 | 0x1.5877ef33664a3p-758
++  r_result = 0000000000000003
++insn wfchedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.a7370ccfd9e49p+505 | 0x1.c6b2385850ca2p-591
++  v_arg2   = 0x1.984f4fcd338b1p+675 | -0x1.feb996c821232p-39
++  r_result = 0000000000000003
++insn wfchedbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.641878612dd2p+207 | 0x1.b35e3292db7f6p+567
++  v_arg2   = -0x1.18a87f209e96bp+299 | -0x1.3d598f3612d8ap+1016
++  r_result = 0000000000000000
++insn wfchedbs:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.cfc2cda244153p+404 | 0x1.d8b2b28e9d8d7p+276
++  v_arg2   = 0x1.3517b8c7a59a1p-828 | 0x1.6096fab7003ccp-415
++  r_result = 0000000000000000
++insn wfchedbs:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.54d656f033e56p-603 | -0x1.95ad0e2088967p+254
++  v_arg2   = 0x1.4cb319db206e4p-614 | 0x1.b41cd9e3739b6p-862
++  r_result = 0000000000000003
++insn vftcidb0:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.7507654eb1cbdp-363 | -0x1.4c5a2d70578a7p-769
++  r_result = 0000000000000003
++insn vftcidb0:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.759a0ba4abaf7p+638 | -0x1.fe832724aaa38p+97
++  r_result = 0000000000000003
++insn vftcidb0:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.7b3e4bb774c14p-102 | -0x1.b908fc2ed3a14p+766
++  r_result = 0000000000000003
++insn vftcidb0:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.85cbf177a1d82p+208 | -0x1.705033c741858p-794
++  r_result = 0000000000000003
++insn vftcidb1:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.7cbeef2c94fcap+288 | -0x1.ec1d97b93cbfdp+702
++  r_result = 0000000000000003
++insn vftcidb1:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.2ab2a98079656p+47 | -0x1.c371901eb3099p+334
++  r_result = 0000000000000003
++insn vftcidb1:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.39eeb39c6012dp-574 | 0x1.98e49f4cc3921p+457
++  r_result = 0000000000000003
++insn vftcidb1:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.3fc28ae45b2b3p-452 | -0x1.b632de2f2b0a8p-517
++  r_result = 0000000000000003
++insn vftcidb2:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.792143331a16dp-472 | 0x1.78b867d4bf21fp+966
++  r_result = 0000000000000003
++insn vftcidb2:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.463e12b675eb9p-361 | 0x1.fcfd460adb415p+411
++  r_result = 0000000000000003
++insn vftcidb2:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.d6b7fe0aecc99p+233 | -0x1.3af17c9a3c277p+571
++  r_result = 0000000000000003
++insn vftcidb2:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.2575c4180e868p+734 | -0x1.320885d20bb51p+204
++  r_result = 0000000000000003
++insn vftcidb3:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.14f24a3c080a1p+651 | -0x1.a4e63e948d889p-821
++  r_result = 0000000000000003
++insn vftcidb3:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.8ad818084fd9dp+652 | 0x1.35c9f1c2ca3a9p-489
++  r_result = 0000000000000003
++insn vftcidb3:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.0c4da3ccb1a54p-577 | -0x1.620b34e8dc095p+265
++  r_result = 0000000000000003
++insn vftcidb3:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.19a17db46ab1ap+844 | -0x1.ae8523c97a84fp+549
++  r_result = 0000000000000003
++insn vftcidb4:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.3af5acd125862p+758 | 0x1.3382dcaa769b8p+644
++  r_result = 0000000000000003
++insn vftcidb4:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.ab5c5a37a5f7ep+180 | -0x1.48ab6c0046851p+926
++  r_result = 0000000000000003
++insn vftcidb4:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.7563ad8b9565bp+255 | 0x1.d0cda8ea71ff4p+761
++  r_result = 0000000000000003
++insn vftcidb4:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.df11489b4e747p-917 | -0x1.c66c509f6e09ep-283
++  r_result = 0000000000000003
++insn vftcidb8:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.85ef23ec393aep-969 | 0x1.e73a12c839128p+469
++  r_result = 0000000000000003
++insn vftcidb8:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.6a66b9f6771d7p-539 | -0x1.e0455d9d06f08p-322
++  r_result = 0000000000000003
++insn vftcidb8:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.1ccd94013eda9p-151 | 0x1.3a149960dcc13p-830
++  r_result = 0000000000000003
++insn vftcidb8:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.1881157e6896bp+739 | -0x1.5481e51d7d13cp+938
++  r_result = 0000000000000003
++insn vftcidb16:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.c0728816e9f7ep+780 | -0x1.82c791cf93d54p-154
++  r_result = 0000000000000003
++insn vftcidb16:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.8ad2e81651e24p-284 | 0x1.d78b8f22e24cap-938
++  r_result = 0000000000000003
++insn vftcidb16:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.7d4f40176493bp-567 | -0x1.70aba71dbb26bp+824
++  r_result = 0000000000000003
++insn vftcidb16:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.98bc950f87c01p+903 | -0x1.2389a9fd7e622p-703
++  r_result = 0000000000000003
++insn vftcidb32:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.c583723b0e8dp-973 | -0x1.b8f72a62558b8p-21
++  r_result = 0000000000000003
++insn vftcidb32:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.df6ca559152e2p+87 | -0x1.e901b98b7f494p+275
++  r_result = 0000000000000003
++insn vftcidb32:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.718c8a77ed80dp+222 | 0x1.272ea2c2cbd7ap+786
++  r_result = 0000000000000003
++insn vftcidb32:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.125f88105ad86p+783 | 0x1.ee37380928c4ep+103
++  r_result = 0000000000000003
++insn vftcidb64:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.3fb5daf24d9ap-918 | -0x1.5c849d623cfd1p+59
++  r_result = 0000000000000003
++insn vftcidb64:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.0adfa2607fa8cp-235 | -0x1.cf9ba570a4a61p+467
++  r_result = 0000000000000003
++insn vftcidb64:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.b468fbdc60619p-667 | -0x1.10695d31ddabcp+261
++  r_result = 0000000000000003
++insn vftcidb64:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.58459f52a0775p-465 | -0x1.5f6e77fa32ebcp+492
++  r_result = 0000000000000003
++insn vftcidb128:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.d9dd5b268dee9p+109 | 0x1.202b8b70f8c1ap-757
++  r_result = 0000000000000003
++insn vftcidb128:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.dfe7c00e2019fp-63 | -0x1.35fd1bac1932ep+836
++  r_result = 0000000000000003
++insn vftcidb128:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.10886d0eb3e5ep+29 | 0x1.1f27771caf4acp+471
++  r_result = 0000000000000003
++insn vftcidb128:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.2d2aab983764ap+430 | 0x1.31a3029a73867p-388
++  r_result = 0000000000000003
++insn vftcidb256:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = 0x1.6eadbb81663a7p-756 | -0x1.c6b7c55047e1p+800
++  r_result = 0000000000000001
++insn vftcidb256:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = 0x1.0150bf13f5396p-188 | -0x1.f6e9b4e793af6p+546
++  r_result = 0000000000000001
++insn vftcidb256:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = -0x1.50be96c89ecd5p-574 | 0x1.d624d134ff7c6p+605
++  r_result = 0000000000000001
++insn vftcidb256:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = 0x1.33ca5d92be782p+577 | -0x1.4fe8b0a3a164bp+725
++  r_result = 0000000000000001
++insn vftcidb512:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.a8eaa4ccad5d7p-269 | -0x1.12d51bd1f8e2ep-222
++  r_result = 0000000000000003
++insn vftcidb512:
++  v_result = ffffffffffffffff | ffffffffffffffff
++  v_arg1   = 0x1.61d62033addeep+577 | 0x1.dd1569eceabb6p+829
++  r_result = 0000000000000000
++insn vftcidb512:
++  v_result = 0000000000000000 | ffffffffffffffff
++  v_arg1   = -0x1.1fbf51c3c7c7cp+803 | 0x1.182d1c5c7d087p-193
++  r_result = 0000000000000001
++insn vftcidb512:
++  v_result = ffffffffffffffff | 0000000000000000
++  v_arg1   = 0x1.4ee08603f4498p-802 | -0x1.54d34adf83565p+965
++  r_result = 0000000000000001
++insn vftcidb1024:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.63580fb229f75p+737 | -0x1.b75f3fb7baaf1p-508
++  r_result = 0000000000000003
++insn vftcidb1024:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.a443f42ef8a22p-625 | 0x1.8363d375b5369p+818
++  r_result = 0000000000000003
++insn vftcidb1024:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.383e46d9f5b4fp-771 | 0x1.a7dc0924f6a6bp-720
++  r_result = 0000000000000003
++insn vftcidb1024:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = -0x1.2148e5bdb7c09p-517 | 0x1.1b2689f7c01b1p-502
++  r_result = 0000000000000003
++insn vftcidb2048:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.48b9851b82d7cp-589 | 0x1.86f1e1a36bdd4p-930
++  r_result = 0000000000000003
++insn vftcidb2048:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.8b45cbb7947aep-572 | -0x1.c478ca5bd9d0cp-274
++  r_result = 0000000000000003
++insn vftcidb2048:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.651f3ea4ff449p-18 | 0x1.381d68603b1edp+264
++  r_result = 0000000000000003
++insn vftcidb2048:
++  v_result = 0000000000000000 | 0000000000000000
++  v_arg1   = 0x1.7d9f2d51b7851p+653 | 0x1.4da616b63e42ap-415
++  r_result = 0000000000000003
+diff --git a/none/tests/s390x/vector_float.vgtest b/none/tests/s390x/vector_float.vgtest
+new file mode 100644
+index 0000000..428d2a2
+--- /dev/null
++++ b/none/tests/s390x/vector_float.vgtest
+@@ -0,0 +1,2 @@
++prog: vector_float
++prereq: test -e vector_float && ../../../tests/s390x_features s390x-vx
+diff -ru valgrind-3.14.0.orig/none/tests/s390x/Makefile.in valgrind-3.14.0/none/tests/s390x/Makefile.in
+--- valgrind-3.14.0.orig/none/tests/s390x/Makefile.in	2018-11-20 17:55:21.383617322 +0100
++++ valgrind-3.14.0/none/tests/s390x/Makefile.in	2018-11-20 17:55:33.442353544 +0100
+@@ -179,8 +179,8 @@
+ 	spechelper-icm-1$(EXEEXT) spechelper-icm-2$(EXEEXT) \
+ 	spechelper-tmll$(EXEEXT) spechelper-tm$(EXEEXT) laa$(EXEEXT) \
+ 	vector$(EXEEXT) lsc2$(EXEEXT) ppno$(EXEEXT) \
+-	vector_string$(EXEEXT) vector_integer$(EXEEXT) $(am__EXEEXT_1) \
+-	$(am__EXEEXT_2)
++	vector_string$(EXEEXT) vector_integer$(EXEEXT) \
++	vector_float$(EXEEXT) $(am__EXEEXT_1) $(am__EXEEXT_2)
+ add_SOURCES = add.c
+ add_OBJECTS = add.$(OBJEXT)
+ add_LDADD = $(LDADD)
+@@ -574,6 +574,11 @@
+ vector_LDADD = $(LDADD)
+ vector_LINK = $(CCLD) $(vector_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ 	$(LDFLAGS) -o $@
++vector_float_SOURCES = vector_float.c
++vector_float_OBJECTS = vector_float-vector_float.$(OBJEXT)
++vector_float_LDADD = $(LDADD)
++vector_float_LINK = $(CCLD) $(vector_float_CFLAGS) $(CFLAGS) \
++	$(AM_LDFLAGS) $(LDFLAGS) -o $@
+ vector_integer_SOURCES = vector_integer.c
+ vector_integer_OBJECTS = vector_integer-vector_integer.$(OBJEXT)
+ vector_integer_LDADD = $(LDADD)
+@@ -646,7 +651,8 @@
+ 	srnmb.c srnmt.c srst.c stck.c stcke.c stckf.c stfle.c stmg.c \
+ 	sub.c sub_EI.c tcxb.c test_fork.c test_sig.c tm.c tmll.c tr.c \
+ 	traps.c tre.c troo.c trot.c trto.c trtt.c vector.c \
+-	vector_integer.c vector_string.c xc.c xor.c xor_EI.c
++	vector_float.c vector_integer.c vector_string.c xc.c xor.c \
++	xor_EI.c
+ DIST_SOURCES = add.c add_EI.c add_GE.c allexec.c and.c and_EI.c \
+ 	bfp-1.c bfp-2.c bfp-3.c bfp-4.c cds.c cdsg.c cgij.c cgrj.c \
+ 	cij.c cksm.c clc.c clcl.c clcle.c clgij.c clgrj.c clij.c \
+@@ -667,7 +673,8 @@
+ 	srnmb.c srnmt.c srst.c stck.c stcke.c stckf.c stfle.c stmg.c \
+ 	sub.c sub_EI.c tcxb.c test_fork.c test_sig.c tm.c tmll.c tr.c \
+ 	traps.c tre.c troo.c trot.c trto.c trtt.c vector.c \
+-	vector_integer.c vector_string.c xc.c xor.c xor_EI.c
++	vector_float.c vector_integer.c vector_string.c xc.c xor.c \
++	xor_EI.c
+ am__can_run_installinfo = \
+   case $$AM_UPDATE_INFO_DIR in \
+     n|no|NO) false;; \
+@@ -1080,7 +1087,8 @@
+ 	spechelper-slgr spechelper-cr spechelper-clr spechelper-ltr \
+ 	spechelper-or spechelper-icm-1 spechelper-icm-2 \
+ 	spechelper-tmll spechelper-tm laa vector lsc2 ppno \
+-	vector_string vector_integer $(am__append_11) $(am__append_12)
++	vector_string vector_integer vector_float $(am__append_11) \
++	$(am__append_12)
+ noinst_HEADERS = vector.h
+ EXTRA_DIST = \
+ 	$(addsuffix .stderr.exp,$(INSN_TESTS)) \
+@@ -1116,6 +1124,7 @@
+ lsc2_CFLAGS = -march=z13 -DS390_TESTS_NOCOLOR
+ vector_string_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=5
+ vector_integer_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4
++vector_float_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4
+ all: all-am
+ 
+ .SUFFIXES:
+@@ -1654,6 +1663,10 @@
+ 	@rm -f vector$(EXEEXT)
+ 	$(AM_V_CCLD)$(vector_LINK) $(vector_OBJECTS) $(vector_LDADD) $(LIBS)
+ 
++vector_float$(EXEEXT): $(vector_float_OBJECTS) $(vector_float_DEPENDENCIES) $(EXTRA_vector_float_DEPENDENCIES) 
++	@rm -f vector_float$(EXEEXT)
++	$(AM_V_CCLD)$(vector_float_LINK) $(vector_float_OBJECTS) $(vector_float_LDADD) $(LIBS)
++
+ vector_integer$(EXEEXT): $(vector_integer_OBJECTS) $(vector_integer_DEPENDENCIES) $(EXTRA_vector_integer_DEPENDENCIES) 
+ 	@rm -f vector_integer$(EXEEXT)
+ 	$(AM_V_CCLD)$(vector_integer_LINK) $(vector_integer_OBJECTS) $(vector_integer_LDADD) $(LIBS)
+@@ -1805,6 +1818,7 @@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trto.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trtt.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vector-vector.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vector_float-vector_float.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vector_integer-vector_integer.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vector_string-vector_string.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc.Po@am__quote@
+@@ -1953,6 +1967,20 @@
+ @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ @am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vector_CFLAGS) $(CFLAGS) -c -o vector-vector.obj `if test -f 'vector.c'; then $(CYGPATH_W) 'vector.c'; else $(CYGPATH_W) '$(srcdir)/vector.c'; fi`
+ 
++vector_float-vector_float.o: vector_float.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vector_float_CFLAGS) $(CFLAGS) -MT vector_float-vector_float.o -MD -MP -MF $(DEPDIR)/vector_float-vector_float.Tpo -c -o vector_float-vector_float.o `test -f 'vector_float.c' || echo '$(srcdir)/'`vector_float.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vector_float-vector_float.Tpo $(DEPDIR)/vector_float-vector_float.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='vector_float.c' object='vector_float-vector_float.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vector_float_CFLAGS) $(CFLAGS) -c -o vector_float-vector_float.o `test -f 'vector_float.c' || echo '$(srcdir)/'`vector_float.c
++
++vector_float-vector_float.obj: vector_float.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vector_float_CFLAGS) $(CFLAGS) -MT vector_float-vector_float.obj -MD -MP -MF $(DEPDIR)/vector_float-vector_float.Tpo -c -o vector_float-vector_float.obj `if test -f 'vector_float.c'; then $(CYGPATH_W) 'vector_float.c'; else $(CYGPATH_W) '$(srcdir)/vector_float.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vector_float-vector_float.Tpo $(DEPDIR)/vector_float-vector_float.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='vector_float.c' object='vector_float-vector_float.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vector_float_CFLAGS) $(CFLAGS) -c -o vector_float-vector_float.obj `if test -f 'vector_float.c'; then $(CYGPATH_W) 'vector_float.c'; else $(CYGPATH_W) '$(srcdir)/vector_float.c'; fi`
++
+ vector_integer-vector_integer.o: vector_integer.c
+ @am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vector_integer_CFLAGS) $(CFLAGS) -MT vector_integer-vector_integer.o -MD -MP -MF $(DEPDIR)/vector_integer-vector_integer.Tpo -c -o vector_integer-vector_integer.o `test -f 'vector_integer.c' || echo '$(srcdir)/'`vector_integer.c
+ @am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vector_integer-vector_integer.Tpo $(DEPDIR)/vector_integer-vector_integer.Po
diff --git a/SOURCES/valgrind-3.14.0-s390x-vec-reg-vgdb.patch b/SOURCES/valgrind-3.14.0-s390x-vec-reg-vgdb.patch
new file mode 100644
index 0000000..e9a2916
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390x-vec-reg-vgdb.patch
@@ -0,0 +1,408 @@
+commit 50bd2282bce101012a5668b670cb185375600d2d
+Author: Andreas Arnez <arnez@linux.ibm.com>
+Date:   Thu Oct 18 17:51:57 2018 +0200
+
+    Bug 397187 s390x: Add vector register support for vgdb
+    
+    On s390x machines with a vector facility, Valgrind's gdbserver didn't
+    represent the vector registers.  This is fixed.
+
+diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am
+index 8de1996..94030fd 100644
+--- a/coregrind/Makefile.am
++++ b/coregrind/Makefile.am
+@@ -685,6 +685,11 @@ GDBSERVER_XML_FILES = \
+ 	m_gdbserver/s390x-linux64-valgrind-s1.xml \
+ 	m_gdbserver/s390x-linux64-valgrind-s2.xml \
+ 	m_gdbserver/s390x-linux64.xml \
++	m_gdbserver/s390-vx-valgrind-s1.xml \
++	m_gdbserver/s390-vx-valgrind-s2.xml \
++	m_gdbserver/s390-vx.xml \
++	m_gdbserver/s390x-vx-linux-valgrind.xml \
++	m_gdbserver/s390x-vx-linux.xml \
+ 	m_gdbserver/mips-cp0-valgrind-s1.xml \
+ 	m_gdbserver/mips-cp0-valgrind-s2.xml \
+ 	m_gdbserver/mips-cp0.xml \
+diff --git a/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml b/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
+new file mode 100644
+index 0000000..ca461b3
+--- /dev/null
++++ b/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
+@@ -0,0 +1,43 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.s390.vx-valgrind-s1">
++  <reg name="v0ls1" bitsize="64" type="uint64"/>
++  <reg name="v1ls1" bitsize="64" type="uint64"/>
++  <reg name="v2ls1" bitsize="64" type="uint64"/>
++  <reg name="v3ls1" bitsize="64" type="uint64"/>
++  <reg name="v4ls1" bitsize="64" type="uint64"/>
++  <reg name="v5ls1" bitsize="64" type="uint64"/>
++  <reg name="v6ls1" bitsize="64" type="uint64"/>
++  <reg name="v7ls1" bitsize="64" type="uint64"/>
++  <reg name="v8ls1" bitsize="64" type="uint64"/>
++  <reg name="v9ls1" bitsize="64" type="uint64"/>
++  <reg name="v10ls1" bitsize="64" type="uint64"/>
++  <reg name="v11ls1" bitsize="64" type="uint64"/>
++  <reg name="v12ls1" bitsize="64" type="uint64"/>
++  <reg name="v13ls1" bitsize="64" type="uint64"/>
++  <reg name="v14ls1" bitsize="64" type="uint64"/>
++  <reg name="v15ls1" bitsize="64" type="uint64"/>
++
++  <reg name="v16s1" bitsize="128" type="uint128"/>
++  <reg name="v17s1" bitsize="128" type="uint128"/>
++  <reg name="v18s1" bitsize="128" type="uint128"/>
++  <reg name="v19s1" bitsize="128" type="uint128"/>
++  <reg name="v20s1" bitsize="128" type="uint128"/>
++  <reg name="v21s1" bitsize="128" type="uint128"/>
++  <reg name="v22s1" bitsize="128" type="uint128"/>
++  <reg name="v23s1" bitsize="128" type="uint128"/>
++  <reg name="v24s1" bitsize="128" type="uint128"/>
++  <reg name="v25s1" bitsize="128" type="uint128"/>
++  <reg name="v26s1" bitsize="128" type="uint128"/>
++  <reg name="v27s1" bitsize="128" type="uint128"/>
++  <reg name="v28s1" bitsize="128" type="uint128"/>
++  <reg name="v29s1" bitsize="128" type="uint128"/>
++  <reg name="v30s1" bitsize="128" type="uint128"/>
++  <reg name="v31s1" bitsize="128" type="uint128"/>
++</feature>
+diff --git a/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml b/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
+new file mode 100644
+index 0000000..eccbd8d
+--- /dev/null
++++ b/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
+@@ -0,0 +1,43 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.s390.vx-valgrind-s2">
++  <reg name="v0ls2" bitsize="64" type="uint64"/>
++  <reg name="v1ls2" bitsize="64" type="uint64"/>
++  <reg name="v2ls2" bitsize="64" type="uint64"/>
++  <reg name="v3ls2" bitsize="64" type="uint64"/>
++  <reg name="v4ls2" bitsize="64" type="uint64"/>
++  <reg name="v5ls2" bitsize="64" type="uint64"/>
++  <reg name="v6ls2" bitsize="64" type="uint64"/>
++  <reg name="v7ls2" bitsize="64" type="uint64"/>
++  <reg name="v8ls2" bitsize="64" type="uint64"/>
++  <reg name="v9ls2" bitsize="64" type="uint64"/>
++  <reg name="v10ls2" bitsize="64" type="uint64"/>
++  <reg name="v11ls2" bitsize="64" type="uint64"/>
++  <reg name="v12ls2" bitsize="64" type="uint64"/>
++  <reg name="v13ls2" bitsize="64" type="uint64"/>
++  <reg name="v14ls2" bitsize="64" type="uint64"/>
++  <reg name="v15ls2" bitsize="64" type="uint64"/>
++
++  <reg name="v16s2" bitsize="128" type="uint128"/>
++  <reg name="v17s2" bitsize="128" type="uint128"/>
++  <reg name="v18s2" bitsize="128" type="uint128"/>
++  <reg name="v19s2" bitsize="128" type="uint128"/>
++  <reg name="v20s2" bitsize="128" type="uint128"/>
++  <reg name="v21s2" bitsize="128" type="uint128"/>
++  <reg name="v22s2" bitsize="128" type="uint128"/>
++  <reg name="v23s2" bitsize="128" type="uint128"/>
++  <reg name="v24s2" bitsize="128" type="uint128"/>
++  <reg name="v25s2" bitsize="128" type="uint128"/>
++  <reg name="v26s2" bitsize="128" type="uint128"/>
++  <reg name="v27s2" bitsize="128" type="uint128"/>
++  <reg name="v28s2" bitsize="128" type="uint128"/>
++  <reg name="v29s2" bitsize="128" type="uint128"/>
++  <reg name="v30s2" bitsize="128" type="uint128"/>
++  <reg name="v31s2" bitsize="128" type="uint128"/>
++</feature>
+diff --git a/coregrind/m_gdbserver/s390-vx.xml b/coregrind/m_gdbserver/s390-vx.xml
+new file mode 100644
+index 0000000..2a16873
+--- /dev/null
++++ b/coregrind/m_gdbserver/s390-vx.xml
+@@ -0,0 +1,59 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.s390.vx">
++  <vector id="v4f" type="ieee_single" count="4"/>
++  <vector id="v2d" type="ieee_double" count="2"/>
++  <vector id="v16i8" type="int8" count="16"/>
++  <vector id="v8i16" type="int16" count="8"/>
++  <vector id="v4i32" type="int32" count="4"/>
++  <vector id="v2i64" type="int64" count="2"/>
++  <union id="vec128">
++    <field name="v4_float" type="v4f"/>
++    <field name="v2_double" type="v2d"/>
++    <field name="v16_int8" type="v16i8"/>
++    <field name="v8_int16" type="v8i16"/>
++    <field name="v4_int32" type="v4i32"/>
++    <field name="v2_int64" type="v2i64"/>
++    <field name="uint128" type="uint128"/>
++  </union>
++
++  <reg name="v0l" bitsize="64" type="uint64"/>
++  <reg name="v1l" bitsize="64" type="uint64"/>
++  <reg name="v2l" bitsize="64" type="uint64"/>
++  <reg name="v3l" bitsize="64" type="uint64"/>
++  <reg name="v4l" bitsize="64" type="uint64"/>
++  <reg name="v5l" bitsize="64" type="uint64"/>
++  <reg name="v6l" bitsize="64" type="uint64"/>
++  <reg name="v7l" bitsize="64" type="uint64"/>
++  <reg name="v8l" bitsize="64" type="uint64"/>
++  <reg name="v9l" bitsize="64" type="uint64"/>
++  <reg name="v10l" bitsize="64" type="uint64"/>
++  <reg name="v11l" bitsize="64" type="uint64"/>
++  <reg name="v12l" bitsize="64" type="uint64"/>
++  <reg name="v13l" bitsize="64" type="uint64"/>
++  <reg name="v14l" bitsize="64" type="uint64"/>
++  <reg name="v15l" bitsize="64" type="uint64"/>
++
++  <reg name="v16" bitsize="128" type="vec128"/>
++  <reg name="v17" bitsize="128" type="vec128"/>
++  <reg name="v18" bitsize="128" type="vec128"/>
++  <reg name="v19" bitsize="128" type="vec128"/>
++  <reg name="v20" bitsize="128" type="vec128"/>
++  <reg name="v21" bitsize="128" type="vec128"/>
++  <reg name="v22" bitsize="128" type="vec128"/>
++  <reg name="v23" bitsize="128" type="vec128"/>
++  <reg name="v24" bitsize="128" type="vec128"/>
++  <reg name="v25" bitsize="128" type="vec128"/>
++  <reg name="v26" bitsize="128" type="vec128"/>
++  <reg name="v27" bitsize="128" type="vec128"/>
++  <reg name="v28" bitsize="128" type="vec128"/>
++  <reg name="v29" bitsize="128" type="vec128"/>
++  <reg name="v30" bitsize="128" type="vec128"/>
++  <reg name="v31" bitsize="128" type="vec128"/>
++</feature>
+diff --git a/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml b/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
+new file mode 100644
+index 0000000..0237002
+--- /dev/null
++++ b/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
+@@ -0,0 +1,28 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2010-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!-- S/390 64-bit user-level code.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <architecture>s390:64-bit</architecture>
++  <xi:include href="s390x-core64.xml"/>
++  <xi:include href="s390-acr.xml"/>
++  <xi:include href="s390-fpr.xml"/>
++  <xi:include href="s390x-linux64.xml"/>
++  <xi:include href="s390-vx.xml"/>
++  <xi:include href="s390x-core64-valgrind-s1.xml"/>
++  <xi:include href="s390-acr-valgrind-s1.xml"/>
++  <xi:include href="s390-fpr-valgrind-s1.xml"/>
++  <xi:include href="s390x-linux64-valgrind-s1.xml"/>
++  <xi:include href="s390-vx-valgrind-s1.xml"/>
++  <xi:include href="s390x-core64-valgrind-s2.xml"/>
++  <xi:include href="s390-acr-valgrind-s2.xml"/>
++  <xi:include href="s390-fpr-valgrind-s2.xml"/>
++  <xi:include href="s390x-linux64-valgrind-s2.xml"/>
++  <xi:include href="s390-vx-valgrind-s2.xml"/>
++</target>
+diff --git a/coregrind/m_gdbserver/s390x-vx-linux.xml b/coregrind/m_gdbserver/s390x-vx-linux.xml
+new file mode 100644
+index 0000000..e431c5b
+--- /dev/null
++++ b/coregrind/m_gdbserver/s390x-vx-linux.xml
+@@ -0,0 +1,18 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2010-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!-- S/390 64-bit user-level code.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <architecture>s390:64-bit</architecture>
++  <xi:include href="s390x-core64.xml"/>
++  <xi:include href="s390-acr.xml"/>
++  <xi:include href="s390-fpr.xml"/>
++  <xi:include href="s390x-linux64.xml"/>
++  <xi:include href="s390-vx.xml"/>
++</target>
+diff --git a/coregrind/m_gdbserver/valgrind-low-s390x.c b/coregrind/m_gdbserver/valgrind-low-s390x.c
+index 7bbb2e3..a667f4b 100644
+--- a/coregrind/m_gdbserver/valgrind-low-s390x.c
++++ b/coregrind/m_gdbserver/valgrind-low-s390x.c
+@@ -88,9 +88,42 @@ static struct reg regs[] = {
+   { "f14", 2592, 64 },
+   { "f15", 2656, 64 },
+   { "orig_r2", 2720, 64 },
++  { "v0l", 2784, 64 },
++  { "v1l", 2848, 64 },
++  { "v2l", 2912, 64 },
++  { "v3l", 2976, 64 },
++  { "v4l", 3040, 64 },
++  { "v5l", 3104, 64 },
++  { "v6l", 3168, 64 },
++  { "v7l", 3232, 64 },
++  { "v8l", 3296, 64 },
++  { "v9l", 3360, 64 },
++  { "v10l", 3424, 64 },
++  { "v11l", 3488, 64 },
++  { "v12l", 3552, 64 },
++  { "v13l", 3616, 64 },
++  { "v14l", 3680, 64 },
++  { "v15l", 3744, 64 },
++  { "v16", 3808, 128 },
++  { "v17", 3936, 128 },
++  { "v18", 4064, 128 },
++  { "v19", 4192, 128 },
++  { "v20", 4320, 128 },
++  { "v21", 4448, 128 },
++  { "v22", 4576, 128 },
++  { "v23", 4704, 128 },
++  { "v24", 4832, 128 },
++  { "v25", 4960, 128 },
++  { "v26", 5088, 128 },
++  { "v27", 5216, 128 },
++  { "v28", 5344, 128 },
++  { "v29", 5472, 128 },
++  { "v30", 5600, 128 },
++  { "v31", 5728, 128 },
+ };
+ static const char *expedite_regs[] = { "r14", "r15", "pswa", 0 };
+-#define num_regs (sizeof (regs) / sizeof (regs[0]))
++#define num_regs_all (sizeof (regs) / sizeof (regs[0]))
++static int num_regs;
+ 
+ static
+ CORE_ADDR get_pc (void)
+@@ -165,7 +198,7 @@ void transfer_register (ThreadId tid, int abs_regno, void * buf,
+    case 32: VG_(transfer) (&s390x->guest_a14, buf, dir, size, mod); break;
+    case 33: VG_(transfer) (&s390x->guest_a15, buf, dir, size, mod); break;
+    case 34: VG_(transfer) (&s390x->guest_fpc, buf, dir, size, mod); break;
+-   case 35: VG_(transfer) (&s390x->guest_v0,  buf, dir, size, mod); break;
++   case 35: VG_(transfer) (&s390x->guest_v0.w64[0],  buf, dir, size, mod); break;
+    case 36: VG_(transfer) (&s390x->guest_v1.w64[0],  buf, dir, size, mod); break;
+    case 37: VG_(transfer) (&s390x->guest_v2.w64[0],  buf, dir, size, mod); break;
+    case 38: VG_(transfer) (&s390x->guest_v3.w64[0],  buf, dir, size, mod); break;
+@@ -182,18 +215,65 @@ void transfer_register (ThreadId tid, int abs_regno, void * buf,
+    case 49: VG_(transfer) (&s390x->guest_v14.w64[0], buf, dir, size, mod); break;
+    case 50: VG_(transfer) (&s390x->guest_v15.w64[0], buf, dir, size, mod); break;
+    case 51:  *mod = False; break; //GDBTD??? { "orig_r2", 0, 64 },
++   case 52: VG_(transfer) (&s390x->guest_v0.w64[1],  buf, dir, size, mod); break;
++   case 53: VG_(transfer) (&s390x->guest_v1.w64[1],  buf, dir, size, mod); break;
++   case 54: VG_(transfer) (&s390x->guest_v2.w64[1],  buf, dir, size, mod); break;
++   case 55: VG_(transfer) (&s390x->guest_v3.w64[1],  buf, dir, size, mod); break;
++   case 56: VG_(transfer) (&s390x->guest_v4.w64[1],  buf, dir, size, mod); break;
++   case 57: VG_(transfer) (&s390x->guest_v5.w64[1],  buf, dir, size, mod); break;
++   case 58: VG_(transfer) (&s390x->guest_v6.w64[1],  buf, dir, size, mod); break;
++   case 59: VG_(transfer) (&s390x->guest_v7.w64[1],  buf, dir, size, mod); break;
++   case 60: VG_(transfer) (&s390x->guest_v8.w64[1],  buf, dir, size, mod); break;
++   case 61: VG_(transfer) (&s390x->guest_v9.w64[1],  buf, dir, size, mod); break;
++   case 62: VG_(transfer) (&s390x->guest_v10.w64[1], buf, dir, size, mod); break;
++   case 63: VG_(transfer) (&s390x->guest_v11.w64[1], buf, dir, size, mod); break;
++   case 64: VG_(transfer) (&s390x->guest_v12.w64[1], buf, dir, size, mod); break;
++   case 65: VG_(transfer) (&s390x->guest_v13.w64[1], buf, dir, size, mod); break;
++   case 66: VG_(transfer) (&s390x->guest_v14.w64[1], buf, dir, size, mod); break;
++   case 67: VG_(transfer) (&s390x->guest_v15.w64[1], buf, dir, size, mod); break;
++   case 68: VG_(transfer) (&s390x->guest_v16, buf, dir, size, mod); break;
++   case 69: VG_(transfer) (&s390x->guest_v17, buf, dir, size, mod); break;
++   case 70: VG_(transfer) (&s390x->guest_v18, buf, dir, size, mod); break;
++   case 71: VG_(transfer) (&s390x->guest_v19, buf, dir, size, mod); break;
++   case 72: VG_(transfer) (&s390x->guest_v20, buf, dir, size, mod); break;
++   case 73: VG_(transfer) (&s390x->guest_v21, buf, dir, size, mod); break;
++   case 74: VG_(transfer) (&s390x->guest_v22, buf, dir, size, mod); break;
++   case 75: VG_(transfer) (&s390x->guest_v23, buf, dir, size, mod); break;
++   case 76: VG_(transfer) (&s390x->guest_v24, buf, dir, size, mod); break;
++   case 77: VG_(transfer) (&s390x->guest_v25, buf, dir, size, mod); break;
++   case 78: VG_(transfer) (&s390x->guest_v26, buf, dir, size, mod); break;
++   case 79: VG_(transfer) (&s390x->guest_v27, buf, dir, size, mod); break;
++   case 80: VG_(transfer) (&s390x->guest_v28, buf, dir, size, mod); break;
++   case 81: VG_(transfer) (&s390x->guest_v29, buf, dir, size, mod); break;
++   case 82: VG_(transfer) (&s390x->guest_v30, buf, dir, size, mod); break;
++   case 83: VG_(transfer) (&s390x->guest_v31, buf, dir, size, mod); break;
+    default: vg_assert(0);
+    }
+ }
+ 
+ static
++Bool have_vx (void)
++{
++   VexArch va;
++   VexArchInfo vai;
++   VG_(machine_get_VexArchInfo) (&va, &vai);
++   return (vai.hwcaps & VEX_HWCAPS_S390X_VX) != 0;
++}
++
++static
+ const char* target_xml (Bool shadow_mode)
+ {
+    if (shadow_mode) {
+-      return "s390x-generic-valgrind.xml";
++      if (have_vx())
++         return "s390x-vx-linux-valgrind.xml";
++      else
++         return "s390x-generic-valgrind.xml";
+    } else {
+-      return "s390x-generic.xml";
+-   }  
++      if (have_vx())
++         return "s390x-vx-linux.xml";
++      else
++         return "s390x-generic.xml";
++   }
+ }
+ 
+ static CORE_ADDR** target_get_dtv (ThreadState *tst)
+@@ -206,7 +286,7 @@ static CORE_ADDR** target_get_dtv (ThreadState *tst)
+ }
+ 
+ static struct valgrind_target_ops low_target = {
+-   num_regs,
++   -1, // Override at init time.
+    regs,
+    17, //sp = r15, which is register offset 17 in regs
+    transfer_register,
+@@ -220,6 +300,11 @@ static struct valgrind_target_ops low_target = {
+ void s390x_init_architecture (struct valgrind_target_ops *target)
+ {
+    *target = low_target;
++   if (have_vx())
++      num_regs = num_regs_all;
++   else
++      num_regs = num_regs_all - 32; // Remove all VX registers.
++   target->num_regs = num_regs;
+    set_register_cache (regs, num_regs);
+    gdbserver_expedite_regs = expedite_regs;
+ }
+diff -ru valgrind-3.14.0.orig/coregrind/Makefile.in valgrind-3.14.0/coregrind/Makefile.in
+--- valgrind-3.14.0.orig/coregrind/Makefile.in	2018-11-20 17:30:03.075888111 +0100
++++ valgrind-3.14.0/coregrind/Makefile.in	2018-11-20 17:31:14.999314275 +0100
+@@ -1869,6 +1869,11 @@
+ 	m_gdbserver/s390x-linux64-valgrind-s1.xml \
+ 	m_gdbserver/s390x-linux64-valgrind-s2.xml \
+ 	m_gdbserver/s390x-linux64.xml \
++	m_gdbserver/s390-vx-valgrind-s1.xml \
++	m_gdbserver/s390-vx-valgrind-s2.xml \
++	m_gdbserver/s390-vx.xml \
++	m_gdbserver/s390x-vx-linux-valgrind.xml \
++	m_gdbserver/s390x-vx-linux.xml \
+ 	m_gdbserver/mips-cp0-valgrind-s1.xml \
+ 	m_gdbserver/mips-cp0-valgrind-s2.xml \
+ 	m_gdbserver/mips-cp0.xml \
diff --git a/SOURCES/valgrind-3.14.0-s390z-more-z13-fixes.patch b/SOURCES/valgrind-3.14.0-s390z-more-z13-fixes.patch
new file mode 100644
index 0000000..82441b9
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-s390z-more-z13-fixes.patch
@@ -0,0 +1,51 @@
+From d10cd86ee32bf76495f79c02df62fc242adbcbe3 Mon Sep 17 00:00:00 2001
+From: Andreas Arnez <arnez@linux.vnet.ibm.com>
+Date: Thu, 26 Jul 2018 16:35:24 +0200
+Subject: [PATCH] s390x: More fixes for z13 support
+
+This patch addresses the following:
+
+* Fix the implementation of LOCGHI.  Previously Valgrind performed 32-bit
+  sign extension instead of 64-bit sign extension on the immediate value.
+
+* Advertise VXRS in HWCAP.  If no VXRS are advertised, but the program
+  uses vector registers, this could cause problems with a glibc built with
+  "-march=z13".
+---
+ VEX/priv/guest_s390_toIR.c          | 2 +-
+ coregrind/m_initimg/initimg-linux.c | 6 +++---
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
+index 9c4d79b87..50a5a4177 100644
+--- a/VEX/priv/guest_s390_toIR.c
++++ b/VEX/priv/guest_s390_toIR.c
+@@ -16325,7 +16325,7 @@ static const HChar *
+ s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2, UChar unused)
+ {
+    next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
+-   put_gpr_dw0(r1, mkU64((UInt)(Int)(Short)i2));
++   put_gpr_dw0(r1, mkU64((ULong)(Long)(Short)i2));
+ 
+    return "locghi";
+ }
+diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
+index 61cc458bc..8a7f0d024 100644
+--- a/coregrind/m_initimg/initimg-linux.c
++++ b/coregrind/m_initimg/initimg-linux.c
+@@ -699,9 +699,9 @@ Addr setup_client_stack( void*  init_sp,
+             }
+ #           elif defined(VGP_s390x_linux)
+             {
+-               /* Advertise hardware features "below" TE only.  TE and VXRS
+-                  (and anything above) are not supported by Valgrind. */
+-               auxv->u.a_val &= VKI_HWCAP_S390_TE - 1;
++               /* Advertise hardware features "below" TE and VXRS.  TE itself
++                  and anything above VXRS is not supported by Valgrind. */
++               auxv->u.a_val &= (VKI_HWCAP_S390_TE - 1) | VKI_HWCAP_S390_VXRS;
+             }
+ #           elif defined(VGP_arm64_linux)
+             {
+-- 
+2.17.0
+
diff --git a/SOURCES/valgrind-3.14.0-set_AV_CR6.patch b/SOURCES/valgrind-3.14.0-set_AV_CR6.patch
new file mode 100644
index 0000000..0dc67cd
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-set_AV_CR6.patch
@@ -0,0 +1,145 @@
+commit dc1523fb3550b4ed9dd4c178741626daaa474da7
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Mon Dec 10 17:18:20 2018 +0100
+
+    PR386945 set_AV_CR6 patch
+    
+    https://bugs.kde.org/show_bug.cgi?id=386945#c62
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index ec2f90a..c3cc6d0 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -2062,45 +2062,88 @@ static void set_CR0 ( IRExpr* result )
+ static void set_AV_CR6 ( IRExpr* result, Bool test_all_ones )
+ {
+    /* CR6[0:3] = {all_ones, 0, all_zeros, 0}
+-      all_ones  = (v[0] && v[1] && v[2] && v[3])
+-      all_zeros = ~(v[0] || v[1] || v[2] || v[3])
++      32 bit: all_zeros =  (v[0] || v[1] || v[2] || v[3]) == 0x0000'0000
++              all_ones  = ~(v[0] && v[1] && v[2] && v[3]) == 0x0000'0000
++              where v[] denotes 32-bit lanes
++      or
++      64 bit: all_zeros =  (v[0] || v[1]) == 0x0000'0000'0000'0000
++              all_ones  = ~(v[0] && v[1]) == 0x0000'0000'0000'0000
++              where v[] denotes 64-bit lanes
++
++      The 32- and 64-bit versions compute the same thing, but the 64-bit one
++      tries to be a bit more efficient.
+    */
+-   IRTemp v0 = newTemp(Ity_V128);
+-   IRTemp v1 = newTemp(Ity_V128);
+-   IRTemp v2 = newTemp(Ity_V128);
+-   IRTemp v3 = newTemp(Ity_V128);
+-   IRTemp rOnes  = newTemp(Ity_I8);
+-   IRTemp rZeros = newTemp(Ity_I8);
+-
+    vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_V128);
+ 
+-   assign( v0, result );
+-   assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
+-   assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
+-   assign( v3, binop(Iop_ShrV128, result, mkU8(96)) );
++   IRTemp overlappedOred  = newTemp(Ity_V128);
++   IRTemp overlappedAnded = newTemp(Ity_V128);
++
++   if (mode64) {
++      IRTemp v0 = newTemp(Ity_V128);
++      IRTemp v1 = newTemp(Ity_V128);
++      assign( v0, result );
++      assign( v1, binop(Iop_ShrV128, result, mkU8(64)) );
++      assign(overlappedOred,
++             binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)));
++      assign(overlappedAnded,
++             binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)));
++   } else {
++      IRTemp v0 = newTemp(Ity_V128);
++      IRTemp v1 = newTemp(Ity_V128);
++      IRTemp v2 = newTemp(Ity_V128);
++      IRTemp v3 = newTemp(Ity_V128);
++      assign( v0, result );
++      assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
++      assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
++      assign( v3, binop(Iop_ShrV128, result, mkU8(96)) );
++      assign(overlappedOred,
++             binop(Iop_OrV128,
++                   binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)),
++                   binop(Iop_OrV128, mkexpr(v2), mkexpr(v3))));
++      assign(overlappedAnded,
++             binop(Iop_AndV128,
++                   binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
++                   binop(Iop_AndV128, mkexpr(v2), mkexpr(v3))));
++   }
++
++   IRTemp rOnes   = newTemp(Ity_I8);
++   IRTemp rZeroes = newTemp(Ity_I8);
+ 
+-   assign( rZeros, unop(Iop_1Uto8,
+-       binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
+-             unop(Iop_Not32,
+-                  unop(Iop_V128to32,
+-                       binop(Iop_OrV128,
+-                             binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)),
+-                             binop(Iop_OrV128, mkexpr(v2), mkexpr(v3))))
+-                  ))) );
++   if (mode64) {
++      assign(rZeroes,
++             unop(Iop_1Uto8,
++                  binop(Iop_CmpEQ64,
++                        mkU64(0),
++                        unop(Iop_V128to64, mkexpr(overlappedOred)))));
++      assign(rOnes,
++             unop(Iop_1Uto8,
++                  binop(Iop_CmpEQ64,
++                        mkU64(0),
++                        unop(Iop_Not64,
++                             unop(Iop_V128to64, mkexpr(overlappedAnded))))));
++   } else {
++      assign(rZeroes,
++             unop(Iop_1Uto8,
++                  binop(Iop_CmpEQ32,
++                        mkU32(0),
++                        unop(Iop_V128to32, mkexpr(overlappedOred)))));
++      assign(rOnes,
++             unop(Iop_1Uto8,
++                  binop(Iop_CmpEQ32,
++                        mkU32(0),
++                        unop(Iop_Not32,
++                             unop(Iop_V128to32, mkexpr(overlappedAnded))))));
++   }
++
++   // rOnes might not be used below.  But iropt will remove it, so there's no
++   // inefficiency as a result.
+ 
+    if (test_all_ones) {
+-      assign( rOnes, unop(Iop_1Uto8,
+-         binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
+-               unop(Iop_V128to32,
+-                    binop(Iop_AndV128,
+-                          binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
+-                          binop(Iop_AndV128, mkexpr(v2), mkexpr(v3)))
+-                    ))) );
+       putCR321( 6, binop(Iop_Or8,
+                          binop(Iop_Shl8, mkexpr(rOnes),  mkU8(3)),
+-                         binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) );
++                         binop(Iop_Shl8, mkexpr(rZeroes), mkU8(1))) );
+    } else {
+-      putCR321( 6, binop(Iop_Shl8, mkexpr(rZeros), mkU8(1)) );
++      putCR321( 6, binop(Iop_Shl8, mkexpr(rZeroes), mkU8(1)) );
+    }
+    putCR0( 6, mkU8(0) );
+ } 
+diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
+index c24db91..7f69ee3 100644
+--- a/memcheck/mc_translate.c
++++ b/memcheck/mc_translate.c
+@@ -8322,6 +8322,9 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure,
+ #     elif defined(VGA_amd64)
+       mce.dlbo.dl_Add64           = DLauto;
+       mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive;
++#     elif defined(VGA_ppc64le)
++      // Needed by (at least) set_AV_CR6() in the front end.
++      mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive;
+ #     endif
+ 
+       /* preInstrumentationAnalysis() will allocate &mce.tmpHowUsed and then
diff --git a/SOURCES/valgrind-3.14.0-sigkill.patch b/SOURCES/valgrind-3.14.0-sigkill.patch
new file mode 100644
index 0000000..27ef411
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-sigkill.patch
@@ -0,0 +1,244 @@
+commit 0c701ba2a4b10a5f6f3fae31cb0ec6ca034d51d9
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Fri Dec 7 14:01:20 2018 +0100
+
+    Fix sigkill.stderr.exp for glibc-2.28.
+    
+    glibc 2.28 filters out some bad signal numbers and returns
+    Invalid argument instead of passing such bad signal numbers
+    the kernel sigaction syscall. So we won't see such bad signal
+    numbers and won't print "bad signal number" ourselves.
+    
+    Add a new memcheck/tests/sigkill.stderr.exp-glibc-2.28 to catch
+    this case.
+
+diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
+index 76e0e90..2af4dd1 100644
+--- a/memcheck/tests/Makefile.am
++++ b/memcheck/tests/Makefile.am
+@@ -260,7 +260,8 @@ EXTRA_DIST = \
+ 	sh-mem-random.stdout.exp sh-mem-random.vgtest \
+ 	sigaltstack.stderr.exp sigaltstack.vgtest \
+ 	sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-mips32 \
+-	    sigkill.stderr.exp-solaris sigkill.vgtest \
++	    sigkill.stderr.exp-solaris \
++	    sigkill.stderr.exp-glibc-2.28 sigkill.vgtest \
+ 	signal2.stderr.exp signal2.stdout.exp signal2.vgtest \
+ 	sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \
+ 	static_malloc.stderr.exp static_malloc.vgtest \
+diff --git a/memcheck/tests/sigkill.stderr.exp-glibc-2.28 b/memcheck/tests/sigkill.stderr.exp-glibc-2.28
+new file mode 100644
+index 0000000..0e5f0cb
+--- /dev/null
++++ b/memcheck/tests/sigkill.stderr.exp-glibc-2.28
+@@ -0,0 +1,197 @@
++
++setting signal 1: Success
++getting signal 1: Success
++
++setting signal 2: Success
++getting signal 2: Success
++
++setting signal 3: Success
++getting signal 3: Success
++
++setting signal 4: Success
++getting signal 4: Success
++
++setting signal 5: Success
++getting signal 5: Success
++
++setting signal 6: Success
++getting signal 6: Success
++
++setting signal 7: Success
++getting signal 7: Success
++
++setting signal 8: Success
++getting signal 8: Success
++
++setting signal 9: Warning: ignored attempt to set SIGKILL handler in sigaction();
++         the SIGKILL signal is uncatchable
++Invalid argument
++getting signal 9: Success
++
++setting signal 10: Success
++getting signal 10: Success
++
++setting signal 11: Success
++getting signal 11: Success
++
++setting signal 12: Success
++getting signal 12: Success
++
++setting signal 13: Success
++getting signal 13: Success
++
++setting signal 14: Success
++getting signal 14: Success
++
++setting signal 15: Success
++getting signal 15: Success
++
++setting signal 16: Success
++getting signal 16: Success
++
++setting signal 17: Success
++getting signal 17: Success
++
++setting signal 18: Success
++getting signal 18: Success
++
++setting signal 19: Warning: ignored attempt to set SIGSTOP handler in sigaction();
++         the SIGSTOP signal is uncatchable
++Invalid argument
++getting signal 19: Success
++
++setting signal 20: Success
++getting signal 20: Success
++
++setting signal 21: Success
++getting signal 21: Success
++
++setting signal 22: Success
++getting signal 22: Success
++
++setting signal 23: Success
++getting signal 23: Success
++
++setting signal 24: Success
++getting signal 24: Success
++
++setting signal 25: Success
++getting signal 25: Success
++
++setting signal 26: Success
++getting signal 26: Success
++
++setting signal 27: Success
++getting signal 27: Success
++
++setting signal 28: Success
++getting signal 28: Success
++
++setting signal 29: Success
++getting signal 29: Success
++
++setting signal 30: Success
++getting signal 30: Success
++
++setting signal 31: Success
++getting signal 31: Success
++
++setting signal 34: Success
++getting signal 34: Success
++
++setting signal 35: Success
++getting signal 35: Success
++
++setting signal 36: Success
++getting signal 36: Success
++
++setting signal 37: Success
++getting signal 37: Success
++
++setting signal 38: Success
++getting signal 38: Success
++
++setting signal 39: Success
++getting signal 39: Success
++
++setting signal 40: Success
++getting signal 40: Success
++
++setting signal 41: Success
++getting signal 41: Success
++
++setting signal 42: Success
++getting signal 42: Success
++
++setting signal 43: Success
++getting signal 43: Success
++
++setting signal 44: Success
++getting signal 44: Success
++
++setting signal 45: Success
++getting signal 45: Success
++
++setting signal 46: Success
++getting signal 46: Success
++
++setting signal 47: Success
++getting signal 47: Success
++
++setting signal 48: Success
++getting signal 48: Success
++
++setting signal 49: Success
++getting signal 49: Success
++
++setting signal 50: Success
++getting signal 50: Success
++
++setting signal 51: Success
++getting signal 51: Success
++
++setting signal 52: Success
++getting signal 52: Success
++
++setting signal 53: Success
++getting signal 53: Success
++
++setting signal 54: Success
++getting signal 54: Success
++
++setting signal 55: Success
++getting signal 55: Success
++
++setting signal 56: Success
++getting signal 56: Success
++
++setting signal 57: Success
++getting signal 57: Success
++
++setting signal 58: Success
++getting signal 58: Success
++
++setting signal 59: Success
++getting signal 59: Success
++
++setting signal 60: Success
++getting signal 60: Success
++
++setting signal 61: Success
++getting signal 61: Success
++
++setting signal 62: Success
++getting signal 62: Success
++
++setting signal 65: Invalid argument
++getting signal 65: Invalid argument
++
++
++HEAP SUMMARY:
++    in use at exit: ... bytes in ... blocks
++  total heap usage: ... allocs, ... frees, ... bytes allocated
++
++For a detailed leak analysis, rerun with: --leak-check=full
++
++For counts of detected and suppressed errors, rerun with: -v
++ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
+diff -ur valgrind-3.14.0.orig/memcheck/tests/Makefile.in valgrind-3.14.0/memcheck/tests/Makefile.in
+--- valgrind-3.14.0.orig/memcheck/tests/Makefile.in	2018-12-13 00:30:45.013839247 +0100
++++ valgrind-3.14.0/memcheck/tests/Makefile.in	2018-12-13 00:30:54.242636002 +0100
+@@ -1573,7 +1573,8 @@
+ 	sh-mem-random.stdout.exp sh-mem-random.vgtest \
+ 	sigaltstack.stderr.exp sigaltstack.vgtest \
+ 	sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-mips32 \
+-	    sigkill.stderr.exp-solaris sigkill.vgtest \
++	    sigkill.stderr.exp-solaris \
++	    sigkill.stderr.exp-glibc-2.28 sigkill.vgtest \
+ 	signal2.stderr.exp signal2.stdout.exp signal2.vgtest \
+ 	sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \
+ 	static_malloc.stderr.exp static_malloc.vgtest \
diff --git a/SOURCES/valgrind-3.14.0-subrange_type-count.patch b/SOURCES/valgrind-3.14.0-subrange_type-count.patch
new file mode 100644
index 0000000..817d749
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-subrange_type-count.patch
@@ -0,0 +1,43 @@
+commit 3528f84037833a799538a2fc48ed30dd09c77b5e
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Fri Jan 11 21:52:26 2019 +0100
+
+    readdwarf3.c (parse_type_DIE): Accept DW_TAG_subrange_type with DW_AT_count
+    
+    GCC9 generates a subrange_type with a lower_bound and count, but no
+    upper_bound attribute. This simply means the upper bound is lower
+    plus count.
+
+diff --git a/coregrind/m_debuginfo/readdwarf3.c b/coregrind/m_debuginfo/readdwarf3.c
+index e9a3816..1b49ba4 100644
+--- a/coregrind/m_debuginfo/readdwarf3.c
++++ b/coregrind/m_debuginfo/readdwarf3.c
+@@ -3610,6 +3610,7 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents,
+       Bool have_count = False;
+       Long lower = 0;
+       Long upper = 0;
++      Long count = 0;
+ 
+       switch (parser->language) {
+          case 'C': have_lower = True;  lower = 0; break;
+@@ -3641,7 +3642,7 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents,
+             have_upper = True;
+          }
+          if (attr == DW_AT_count && cts.szB > 0) {
+-            /*count    = (Long)cts.u.val;*/
++            count    = (Long)cts.u.val;
+             have_count = True;
+          }
+       }
+@@ -3680,6 +3681,11 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents,
+          boundE.Te.Bound.knownU = False;
+          boundE.Te.Bound.boundL = 0;
+          boundE.Te.Bound.boundU = 0;
++      } else if (have_lower && (!have_upper) && (have_count)) {
++         boundE.Te.Bound.knownL = True;
++         boundE.Te.Bound.knownU = True;
++         boundE.Te.Bound.boundL = lower;
++         boundE.Te.Bound.boundU = lower + count;
+       } else {
+          /* FIXME: handle more cases */
+          goto_bad_DIE;
diff --git a/SOURCES/valgrind-3.14.0-transform-popcount64-ctznat64.patch b/SOURCES/valgrind-3.14.0-transform-popcount64-ctznat64.patch
new file mode 100644
index 0000000..c8b2ac1
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-transform-popcount64-ctznat64.patch
@@ -0,0 +1,82 @@
+commit cb5d7e047598bff6d0f1d707a70d9fb1a1c7f0e2
+Author: Julian Seward <jseward@acm.org>
+Date:   Tue Nov 20 11:46:55 2018 +0100
+
+    VEX/priv/ir_opt.c
+    
+    fold_Expr: transform PopCount64(And64(Add64(x,-1),Not64(x))) into CtzNat64(x).
+    
+    This is part of the fix for bug 386945.
+
+diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c
+index f40870b..23964be 100644
+--- a/VEX/priv/ir_opt.c
++++ b/VEX/priv/ir_opt.c
+@@ -1377,6 +1377,8 @@ static IRExpr* fold_Expr ( IRExpr** env, IRExpr* e )
+    case Iex_Unop:
+       /* UNARY ops */
+       if (e->Iex.Unop.arg->tag == Iex_Const) {
++
++         /* cases where the arg is a const */
+          switch (e->Iex.Unop.op) {
+          case Iop_1Uto8:
+             e2 = IRExpr_Const(IRConst_U8(toUChar(
+@@ -1690,8 +1692,56 @@ static IRExpr* fold_Expr ( IRExpr** env, IRExpr* e )
+ 
+          default: 
+             goto unhandled;
+-      }
+-      }
++         } // switch (e->Iex.Unop.op)
++
++      } else {
++
++         /* other cases (identities, etc) */
++         switch (e->Iex.Unop.op) {
++         case Iop_PopCount64: {
++            // PopCount64( And64( Add64(x,-1), Not64(x) ) ) ==> CtzNat64(x)
++            // bindings:
++            //   a1:And64( a11:Add64(a111:x,a112:-1), a12:Not64(a121:x) )
++            IRExpr* a1 = chase(env, e->Iex.Unop.arg);
++            if (!a1)
++               goto nomatch;
++            if (a1->tag != Iex_Binop || a1->Iex.Binop.op != Iop_And64)
++               goto nomatch;
++            // a1 is established
++            IRExpr* a11 = chase(env, a1->Iex.Binop.arg1);
++            if (!a11)
++               goto nomatch;
++            if (a11->tag != Iex_Binop || a11->Iex.Binop.op != Iop_Add64)
++               goto nomatch;
++            // a11 is established
++            IRExpr* a12 = chase(env, a1->Iex.Binop.arg2);
++            if (!a12)
++               goto nomatch;
++            if (a12->tag != Iex_Unop || a12->Iex.Unop.op != Iop_Not64)
++               goto nomatch;
++            // a12 is established
++            IRExpr* a111 = a11->Iex.Binop.arg1;
++            IRExpr* a112 = chase(env, a11->Iex.Binop.arg2);
++            IRExpr* a121 = a12->Iex.Unop.arg;
++            if (!a111 || !a112 || !a121)
++               goto nomatch;
++            // a111 and a121 need to be the same temp.
++            if (!eqIRAtom(a111, a121))
++               goto nomatch;
++            // Finally, a112 must be a 64-bit version of -1.
++            if (!isOnesU(a112))
++               goto nomatch;
++            // Match established.  Transform.
++            e2 = IRExpr_Unop(Iop_CtzNat64, a111);
++            break;
++           nomatch:
++            break;
++         }
++         default:
++            break;
++         } // switch (e->Iex.Unop.op)
++
++      } // if (e->Iex.Unop.arg->tag == Iex_Const)
+       break;
+ 
+    case Iex_Binop:
diff --git a/SOURCES/valgrind-3.14.0-undef_malloc_args.patch b/SOURCES/valgrind-3.14.0-undef_malloc_args.patch
new file mode 100644
index 0000000..43db5ab
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-undef_malloc_args.patch
@@ -0,0 +1,98 @@
+commit 262275da43425ba2b8c240e47063e36b39167996
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Wed Dec 12 13:55:01 2018 +0100
+
+    Fix memcheck/tests/undef_malloc_args testcase.
+
+diff --git a/coregrind/m_replacemalloc/vg_replace_malloc.c b/coregrind/m_replacemalloc/vg_replace_malloc.c
+index 28bdb4a..564829a 100644
+--- a/coregrind/m_replacemalloc/vg_replace_malloc.c
++++ b/coregrind/m_replacemalloc/vg_replace_malloc.c
+@@ -216,9 +216,19 @@ static void init(void);
+    Apart of allowing memcheck to detect an error, the macro
+    TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED has no effect and
+    has a minimal cost for other tools replacing malloc functions.
++
++   Creating an "artificial" use of _x that works reliably is not entirely
++   straightforward.  Simply comparing it against zero often produces no
++   warning if _x contains at least one nonzero bit is defined, because
++   Memcheck knows that the result of the comparison will be defined (cf
++   expensiveCmpEQorNE).
++
++   Really we want to PCast _x, so as to create a value which is entirely
++   undefined if any bit of _x is undefined.  But there's no portable way to do
++   that.
+ */
+-#define TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED(x) \
+-   if ((ULong)x == 0) __asm__ __volatile__( "" ::: "memory" )
++#define TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED(_x) \
++   if ((UWord)(_x) == 0) __asm__ __volatile__( "" ::: "memory" )
+ 
+ /*---------------------- malloc ----------------------*/
+ 
+@@ -504,7 +514,7 @@ static void init(void);
+    void VG_REPLACE_FUNCTION_EZU(10040,soname,fnname) (void *zone, void *p)  \
+    { \
+       DO_INIT; \
+-      TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED((UWord) zone);	\
++      TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED((UWord)zone ^ (UWord)p); \
+       MALLOC_TRACE(#fnname "(%p, %p)\n", zone, p ); \
+       if (p == NULL)  \
+          return; \
+diff --git a/memcheck/tests/undef_malloc_args.c b/memcheck/tests/undef_malloc_args.c
+index 99e2799..654d70d 100644
+--- a/memcheck/tests/undef_malloc_args.c
++++ b/memcheck/tests/undef_malloc_args.c
+@@ -11,29 +11,29 @@ int main (int argc, char*argv[])
+ 
+    {
+       size_t size = def_size;
+-      (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1);
++      (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size));
+       p = malloc(size);
+    }
+ 
+-   (void) VALGRIND_MAKE_MEM_UNDEFINED(&p, 1);
++   (void) VALGRIND_MAKE_MEM_UNDEFINED(&p, sizeof(p));
+    new_p = realloc(p, def_size);
+ 
+-   (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, 1);
++   (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, sizeof(new_p));
+    new_p = realloc(new_p, def_size);
+ 
+-   (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, 1);
++   (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, sizeof(new_p));
+    free (new_p);
+ 
+    {
+       size_t nmemb = 1;
+-      (void) VALGRIND_MAKE_MEM_UNDEFINED(&nmemb, 1);
++      (void) VALGRIND_MAKE_MEM_UNDEFINED(&nmemb, sizeof(nmemb));
+       new_p = calloc(nmemb, def_size);
+       free (new_p);
+    }
+ #if 0
+    {
+       size_t alignment = 1;
+-      (void) VALGRIND_MAKE_MEM_UNDEFINED(&alignment, 1);
++      (void) VALGRIND_MAKE_MEM_UNDEFINED(&alignment, sizeof(alignment));
+       new_p = memalign(alignment, def_size);
+       free(new_p);
+    }
+@@ -41,14 +41,14 @@ int main (int argc, char*argv[])
+    {
+       size_t nmemb = 16;
+       size_t size = def_size;
+-      (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1);
++      (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size));
+       new_p = memalign(nmemb, size);
+       free(new_p);
+    }
+ 
+    {
+       size_t size = def_size;
+-      (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1);
++      (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size));
+       new_p = valloc(size);
+       free (new_p);
+    }
diff --git a/SOURCES/valgrind-3.14.0-vbit-test-sec.patch b/SOURCES/valgrind-3.14.0-vbit-test-sec.patch
new file mode 100644
index 0000000..01090b7
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-vbit-test-sec.patch
@@ -0,0 +1,299 @@
+From cee6817c2f4637f859829c7caeac168ccbb74850 Mon Sep 17 00:00:00 2001
+From: Mark Wielaard <mark@klomp.org>
+Date: Sun, 23 Dec 2018 13:29:27 +0100
+Subject: [PATCH] Also test memcheck/tests/vbit-test on any secondary arch.
+
+If we are building a secondary arch then also build and run ther
+memcheck vbit-test for that architecture.
+---
+ memcheck/tests/vbit-test/Makefile.am              | 20 ++++++++++++++++++++
+ memcheck/tests/vbit-test/vbit-test-sec.stderr.exp |  0
+ memcheck/tests/vbit-test/vbit-test-sec.vgtest     |  3 +++
+ 3 files changed, 23 insertions(+)
+ create mode 100644 memcheck/tests/vbit-test/vbit-test-sec.stderr.exp
+ create mode 100644 memcheck/tests/vbit-test/vbit-test-sec.vgtest
+
+diff --git a/memcheck/tests/vbit-test/Makefile.am b/memcheck/tests/vbit-test/Makefile.am
+index 371a71b..124e82e 100644
+--- a/memcheck/tests/vbit-test/Makefile.am
++++ b/memcheck/tests/vbit-test/Makefile.am
+@@ -17,6 +17,10 @@ noinst_HEADERS = vtest.h vbits.h
+ 
+ noinst_PROGRAMS = vbit-test
+ 
++if VGCONF_HAVE_PLATFORM_SEC
++noinst_PROGRAMS += vbit-test-sec
++endif
++
+ if VGCONF_OS_IS_DARWIN
+ noinst_DSYMS = $(noinst_PROGRAMS)
+ endif
+@@ -41,3 +45,19 @@ vbit_test_CFLAGS       = $(AM_CFLAGS_PRI)
+ vbit_test_DEPENDENCIES = 
+ vbit_test_LDADD        = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+ vbit_test_LDFLAGS      = $(AM_CFLAGS_PRI) @LIB_UBSAN@
++
++if VGCONF_HAVE_PLATFORM_SEC
++vbit_test_sec_SOURCES      = $(SOURCES)
++vbit_test_sec_CPPFLAGS     = $(AM_CPPFLAGS_SEC) \
++                             $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
++                             -I$(top_srcdir)/include  \
++                             -I$(top_srcdir)/memcheck \
++                             -I$(top_srcdir)/VEX/pub
++vbit_test_sec_CFLAGS       = $(AM_CFLAGS_SEC) \
++                             $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
++vbit_test_sec_DEPENDENCIES = 
++vbit_test_sec_LDADD        = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
++                              $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
++vbit_test_sec_LDFLAGS      = $(AM_CFLAGS_SEC) @LIB_UBSAN@ \
++                             $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
++endif
+diff --git a/memcheck/tests/vbit-test/vbit-test-sec.stderr.exp b/memcheck/tests/vbit-test/vbit-test-sec.stderr.exp
+new file mode 100644
+index 0000000..e69de29
+diff --git a/memcheck/tests/vbit-test/vbit-test-sec.vgtest b/memcheck/tests/vbit-test/vbit-test-sec.vgtest
+new file mode 100644
+index 0000000..2d3c938
+--- /dev/null
++++ b/memcheck/tests/vbit-test/vbit-test-sec.vgtest
+@@ -0,0 +1,3 @@
++prog: vbit-test-sec
++prereq: test -x vbit-test-sec
++vgopts: -q --expensive-definedness-checks=yes
+-- 
+1.8.3.1
+
+diff -ur valgrind-3.14.0.orig/memcheck/tests/vbit-test/Makefile.in valgrind-3.14.0/memcheck/tests/vbit-test/Makefile.in
+--- valgrind-3.14.0.orig/memcheck/tests/vbit-test/Makefile.in	2018-12-23 21:08:18.816768360 +0100
++++ valgrind-3.14.0/memcheck/tests/vbit-test/Makefile.in	2018-12-23 21:09:07.239704508 +0100
+@@ -108,7 +108,8 @@
+ # bionic which is bad because we are not linking with it and the Android
+ # linker will panic.
+ @VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_5 = -nostdlib
+-noinst_PROGRAMS = vbit-test$(EXEEXT)
++noinst_PROGRAMS = vbit-test$(EXEEXT) $(am__EXEEXT_1)
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_6 = vbit-test-sec
+ subdir = memcheck/tests/vbit-test
+ ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+ am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+@@ -120,6 +121,7 @@
+ CONFIG_HEADER = $(top_builddir)/config.h
+ CONFIG_CLEAN_FILES =
+ CONFIG_CLEAN_VPATH_FILES =
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = vbit-test-sec$(EXEEXT)
+ PROGRAMS = $(noinst_PROGRAMS)
+ am__objects_1 = vbit_test-main.$(OBJEXT) vbit_test-unary.$(OBJEXT) \
+ 	vbit_test-binary.$(OBJEXT) vbit_test-ternary.$(OBJEXT) \
+@@ -130,6 +132,19 @@
+ vbit_test_OBJECTS = $(am_vbit_test_OBJECTS)
+ vbit_test_LINK = $(CCLD) $(vbit_test_CFLAGS) $(CFLAGS) \
+ 	$(vbit_test_LDFLAGS) $(LDFLAGS) -o $@
++am__vbit_test_sec_SOURCES_DIST = main.c unary.c binary.c ternary.c \
++	qernary.c util.c vbits.c irops.c valgrind.c
++am__objects_2 = vbit_test_sec-main.$(OBJEXT) \
++	vbit_test_sec-unary.$(OBJEXT) vbit_test_sec-binary.$(OBJEXT) \
++	vbit_test_sec-ternary.$(OBJEXT) \
++	vbit_test_sec-qernary.$(OBJEXT) vbit_test_sec-util.$(OBJEXT) \
++	vbit_test_sec-vbits.$(OBJEXT) vbit_test_sec-irops.$(OBJEXT) \
++	vbit_test_sec-valgrind.$(OBJEXT)
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_vbit_test_sec_OBJECTS =  \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@	$(am__objects_2)
++vbit_test_sec_OBJECTS = $(am_vbit_test_sec_OBJECTS)
++vbit_test_sec_LINK = $(CCLD) $(vbit_test_sec_CFLAGS) $(CFLAGS) \
++	$(vbit_test_sec_LDFLAGS) $(LDFLAGS) -o $@
+ SCRIPTS = $(dist_noinst_SCRIPTS)
+ AM_V_P = $(am__v_P_@AM_V@)
+ am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+@@ -163,7 +178,7 @@
+ am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+ am__v_CCLD_0 = @echo "  CCLD    " $@;
+ am__v_CCLD_1 = 
+-DIST_SOURCES = $(vbit_test_SOURCES)
++DIST_SOURCES = $(vbit_test_SOURCES) $(am__vbit_test_sec_SOURCES_DIST)
+ am__can_run_installinfo = \
+   case $$AM_UPDATE_INFO_DIR in \
+     n|no|NO) false;; \
+@@ -600,6 +615,23 @@
+ vbit_test_DEPENDENCIES = 
+ vbit_test_LDADD = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+ vbit_test_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@vbit_test_sec_SOURCES = $(SOURCES)
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@vbit_test_sec_CPPFLAGS = $(AM_CPPFLAGS_SEC) \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                             $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                             -I$(top_srcdir)/include  \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                             -I$(top_srcdir)/memcheck \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                             -I$(top_srcdir)/VEX/pub
++
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@vbit_test_sec_CFLAGS = $(AM_CFLAGS_SEC) \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                             $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
++
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@vbit_test_sec_DEPENDENCIES = 
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@vbit_test_sec_LDADD = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                              $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
++
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@vbit_test_sec_LDFLAGS = $(AM_CFLAGS_SEC) @LIB_UBSAN@ \
++@VGCONF_HAVE_PLATFORM_SEC_TRUE@                             $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
++
+ all: all-am
+ 
+ .SUFFIXES:
+@@ -642,6 +674,10 @@
+ 	@rm -f vbit-test$(EXEEXT)
+ 	$(AM_V_CCLD)$(vbit_test_LINK) $(vbit_test_OBJECTS) $(vbit_test_LDADD) $(LIBS)
+ 
++vbit-test-sec$(EXEEXT): $(vbit_test_sec_OBJECTS) $(vbit_test_sec_DEPENDENCIES) $(EXTRA_vbit_test_sec_DEPENDENCIES) 
++	@rm -f vbit-test-sec$(EXEEXT)
++	$(AM_V_CCLD)$(vbit_test_sec_LINK) $(vbit_test_sec_OBJECTS) $(vbit_test_sec_LDADD) $(LIBS)
++
+ mostlyclean-compile:
+ 	-rm -f *.$(OBJEXT)
+ 
+@@ -657,6 +693,15 @@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test-util.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test-valgrind.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test-vbits.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-binary.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-irops.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-main.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-qernary.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-ternary.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-unary.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-util.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-valgrind.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vbit_test_sec-vbits.Po@am__quote@
+ 
+ .c.o:
+ @am__fastdepCC_TRUE@	$(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
+@@ -799,6 +844,132 @@
+ @AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='valgrind.c' object='vbit_test-valgrind.obj' libtool=no @AMDEPBACKSLASH@
+ @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ @am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_CPPFLAGS) $(CPPFLAGS) $(vbit_test_CFLAGS) $(CFLAGS) -c -o vbit_test-valgrind.obj `if test -f 'valgrind.c'; then $(CYGPATH_W) 'valgrind.c'; else $(CYGPATH_W) '$(srcdir)/valgrind.c'; fi`
++
++vbit_test_sec-main.o: main.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-main.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-main.Tpo -c -o vbit_test_sec-main.o `test -f 'main.c' || echo '$(srcdir)/'`main.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-main.Tpo $(DEPDIR)/vbit_test_sec-main.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='main.c' object='vbit_test_sec-main.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-main.o `test -f 'main.c' || echo '$(srcdir)/'`main.c
++
++vbit_test_sec-main.obj: main.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-main.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-main.Tpo -c -o vbit_test_sec-main.obj `if test -f 'main.c'; then $(CYGPATH_W) 'main.c'; else $(CYGPATH_W) '$(srcdir)/main.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-main.Tpo $(DEPDIR)/vbit_test_sec-main.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='main.c' object='vbit_test_sec-main.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-main.obj `if test -f 'main.c'; then $(CYGPATH_W) 'main.c'; else $(CYGPATH_W) '$(srcdir)/main.c'; fi`
++
++vbit_test_sec-unary.o: unary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-unary.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-unary.Tpo -c -o vbit_test_sec-unary.o `test -f 'unary.c' || echo '$(srcdir)/'`unary.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-unary.Tpo $(DEPDIR)/vbit_test_sec-unary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='unary.c' object='vbit_test_sec-unary.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-unary.o `test -f 'unary.c' || echo '$(srcdir)/'`unary.c
++
++vbit_test_sec-unary.obj: unary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-unary.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-unary.Tpo -c -o vbit_test_sec-unary.obj `if test -f 'unary.c'; then $(CYGPATH_W) 'unary.c'; else $(CYGPATH_W) '$(srcdir)/unary.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-unary.Tpo $(DEPDIR)/vbit_test_sec-unary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='unary.c' object='vbit_test_sec-unary.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-unary.obj `if test -f 'unary.c'; then $(CYGPATH_W) 'unary.c'; else $(CYGPATH_W) '$(srcdir)/unary.c'; fi`
++
++vbit_test_sec-binary.o: binary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-binary.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-binary.Tpo -c -o vbit_test_sec-binary.o `test -f 'binary.c' || echo '$(srcdir)/'`binary.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-binary.Tpo $(DEPDIR)/vbit_test_sec-binary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='binary.c' object='vbit_test_sec-binary.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-binary.o `test -f 'binary.c' || echo '$(srcdir)/'`binary.c
++
++vbit_test_sec-binary.obj: binary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-binary.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-binary.Tpo -c -o vbit_test_sec-binary.obj `if test -f 'binary.c'; then $(CYGPATH_W) 'binary.c'; else $(CYGPATH_W) '$(srcdir)/binary.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-binary.Tpo $(DEPDIR)/vbit_test_sec-binary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='binary.c' object='vbit_test_sec-binary.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-binary.obj `if test -f 'binary.c'; then $(CYGPATH_W) 'binary.c'; else $(CYGPATH_W) '$(srcdir)/binary.c'; fi`
++
++vbit_test_sec-ternary.o: ternary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-ternary.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-ternary.Tpo -c -o vbit_test_sec-ternary.o `test -f 'ternary.c' || echo '$(srcdir)/'`ternary.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-ternary.Tpo $(DEPDIR)/vbit_test_sec-ternary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='ternary.c' object='vbit_test_sec-ternary.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-ternary.o `test -f 'ternary.c' || echo '$(srcdir)/'`ternary.c
++
++vbit_test_sec-ternary.obj: ternary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-ternary.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-ternary.Tpo -c -o vbit_test_sec-ternary.obj `if test -f 'ternary.c'; then $(CYGPATH_W) 'ternary.c'; else $(CYGPATH_W) '$(srcdir)/ternary.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-ternary.Tpo $(DEPDIR)/vbit_test_sec-ternary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='ternary.c' object='vbit_test_sec-ternary.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-ternary.obj `if test -f 'ternary.c'; then $(CYGPATH_W) 'ternary.c'; else $(CYGPATH_W) '$(srcdir)/ternary.c'; fi`
++
++vbit_test_sec-qernary.o: qernary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-qernary.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-qernary.Tpo -c -o vbit_test_sec-qernary.o `test -f 'qernary.c' || echo '$(srcdir)/'`qernary.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-qernary.Tpo $(DEPDIR)/vbit_test_sec-qernary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='qernary.c' object='vbit_test_sec-qernary.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-qernary.o `test -f 'qernary.c' || echo '$(srcdir)/'`qernary.c
++
++vbit_test_sec-qernary.obj: qernary.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-qernary.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-qernary.Tpo -c -o vbit_test_sec-qernary.obj `if test -f 'qernary.c'; then $(CYGPATH_W) 'qernary.c'; else $(CYGPATH_W) '$(srcdir)/qernary.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-qernary.Tpo $(DEPDIR)/vbit_test_sec-qernary.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='qernary.c' object='vbit_test_sec-qernary.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-qernary.obj `if test -f 'qernary.c'; then $(CYGPATH_W) 'qernary.c'; else $(CYGPATH_W) '$(srcdir)/qernary.c'; fi`
++
++vbit_test_sec-util.o: util.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-util.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-util.Tpo -c -o vbit_test_sec-util.o `test -f 'util.c' || echo '$(srcdir)/'`util.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-util.Tpo $(DEPDIR)/vbit_test_sec-util.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='util.c' object='vbit_test_sec-util.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-util.o `test -f 'util.c' || echo '$(srcdir)/'`util.c
++
++vbit_test_sec-util.obj: util.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-util.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-util.Tpo -c -o vbit_test_sec-util.obj `if test -f 'util.c'; then $(CYGPATH_W) 'util.c'; else $(CYGPATH_W) '$(srcdir)/util.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-util.Tpo $(DEPDIR)/vbit_test_sec-util.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='util.c' object='vbit_test_sec-util.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-util.obj `if test -f 'util.c'; then $(CYGPATH_W) 'util.c'; else $(CYGPATH_W) '$(srcdir)/util.c'; fi`
++
++vbit_test_sec-vbits.o: vbits.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-vbits.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-vbits.Tpo -c -o vbit_test_sec-vbits.o `test -f 'vbits.c' || echo '$(srcdir)/'`vbits.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-vbits.Tpo $(DEPDIR)/vbit_test_sec-vbits.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='vbits.c' object='vbit_test_sec-vbits.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-vbits.o `test -f 'vbits.c' || echo '$(srcdir)/'`vbits.c
++
++vbit_test_sec-vbits.obj: vbits.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-vbits.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-vbits.Tpo -c -o vbit_test_sec-vbits.obj `if test -f 'vbits.c'; then $(CYGPATH_W) 'vbits.c'; else $(CYGPATH_W) '$(srcdir)/vbits.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-vbits.Tpo $(DEPDIR)/vbit_test_sec-vbits.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='vbits.c' object='vbit_test_sec-vbits.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-vbits.obj `if test -f 'vbits.c'; then $(CYGPATH_W) 'vbits.c'; else $(CYGPATH_W) '$(srcdir)/vbits.c'; fi`
++
++vbit_test_sec-irops.o: irops.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-irops.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-irops.Tpo -c -o vbit_test_sec-irops.o `test -f 'irops.c' || echo '$(srcdir)/'`irops.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-irops.Tpo $(DEPDIR)/vbit_test_sec-irops.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='irops.c' object='vbit_test_sec-irops.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-irops.o `test -f 'irops.c' || echo '$(srcdir)/'`irops.c
++
++vbit_test_sec-irops.obj: irops.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-irops.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-irops.Tpo -c -o vbit_test_sec-irops.obj `if test -f 'irops.c'; then $(CYGPATH_W) 'irops.c'; else $(CYGPATH_W) '$(srcdir)/irops.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-irops.Tpo $(DEPDIR)/vbit_test_sec-irops.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='irops.c' object='vbit_test_sec-irops.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-irops.obj `if test -f 'irops.c'; then $(CYGPATH_W) 'irops.c'; else $(CYGPATH_W) '$(srcdir)/irops.c'; fi`
++
++vbit_test_sec-valgrind.o: valgrind.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-valgrind.o -MD -MP -MF $(DEPDIR)/vbit_test_sec-valgrind.Tpo -c -o vbit_test_sec-valgrind.o `test -f 'valgrind.c' || echo '$(srcdir)/'`valgrind.c
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-valgrind.Tpo $(DEPDIR)/vbit_test_sec-valgrind.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='valgrind.c' object='vbit_test_sec-valgrind.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-valgrind.o `test -f 'valgrind.c' || echo '$(srcdir)/'`valgrind.c
++
++vbit_test_sec-valgrind.obj: valgrind.c
++@am__fastdepCC_TRUE@	$(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -MT vbit_test_sec-valgrind.obj -MD -MP -MF $(DEPDIR)/vbit_test_sec-valgrind.Tpo -c -o vbit_test_sec-valgrind.obj `if test -f 'valgrind.c'; then $(CYGPATH_W) 'valgrind.c'; else $(CYGPATH_W) '$(srcdir)/valgrind.c'; fi`
++@am__fastdepCC_TRUE@	$(AM_V_at)$(am__mv) $(DEPDIR)/vbit_test_sec-valgrind.Tpo $(DEPDIR)/vbit_test_sec-valgrind.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(AM_V_CC)source='valgrind.c' object='vbit_test_sec-valgrind.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vbit_test_sec_CPPFLAGS) $(CPPFLAGS) $(vbit_test_sec_CFLAGS) $(CFLAGS) -c -o vbit_test_sec-valgrind.obj `if test -f 'valgrind.c'; then $(CYGPATH_W) 'valgrind.c'; else $(CYGPATH_W) '$(srcdir)/valgrind.c'; fi`
+ install-pkgincludeHEADERS: $(pkginclude_HEADERS)
+ 	@$(NORMAL_INSTALL)
+ 	@list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
diff --git a/SOURCES/valgrind-3.14.0-wcsncmp.patch b/SOURCES/valgrind-3.14.0-wcsncmp.patch
new file mode 100644
index 0000000..8940910
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-wcsncmp.patch
@@ -0,0 +1,89 @@
+commit 5fdabb72fdcba6bcf788eaa19c1ee557c13b8a7a
+Author: Mark Wielaard <mark@klomp.org>
+Date:   Sat Dec 1 23:54:40 2018 +0100
+
+    Bug 401627 - Add wcsncmp override and testcase.
+    
+    glibc 2.28 added an avx2 optimized variant of wstrncmp which memcheck
+    cannot proof correct. Add a simple override in vg_replace_strmem.c.
+
+diff --git a/memcheck/tests/wcs.c b/memcheck/tests/wcs.c
+index 15730ad..538304b 100644
+--- a/memcheck/tests/wcs.c
++++ b/memcheck/tests/wcs.c
+@@ -1,5 +1,6 @@
+-// Uses various wchar_t * functions that have hand written SSE assembly
+-// implementations in glibc. wcslen, wcscpy, wcscmp, wcsrchr, wcschr.
++// Uses various wchar_t * functions that have hand written SSE and/or AVX2
++// assembly implementations in glibc.
++// wcslen, wcscpy, wcscmp, wcsncmp, wcsrchr, wcschr.
+ 
+ #include <stdio.h>
+ #include <stdlib.h>
+@@ -18,6 +19,8 @@ int main(int argc, char **argv)
+   c = wcscpy (b, a);
+ 
+   fprintf (stderr, "wcscmp equal: %d\n", wcscmp (a, b)); // wcscmp equal: 0
++  fprintf (stderr,
++	   "wcsncmp equal: %d\n", wcsncmp (a, b, l)); // wcsncmp equal: 0
+ 
+   d = wcsrchr (a, L'd');
+   e = wcschr (a, L'd');
+diff --git a/memcheck/tests/wcs.stderr.exp b/memcheck/tests/wcs.stderr.exp
+index 41d74c8..d5b5959 100644
+--- a/memcheck/tests/wcs.stderr.exp
++++ b/memcheck/tests/wcs.stderr.exp
+@@ -1,3 +1,4 @@
+ wcslen: 53
+ wcscmp equal: 0
++wcsncmp equal: 0
+ wcsrchr == wcschr: 1
+diff --git a/shared/vg_replace_strmem.c b/shared/vg_replace_strmem.c
+index d6927f0..89a7dcc 100644
+--- a/shared/vg_replace_strmem.c
++++ b/shared/vg_replace_strmem.c
+@@ -103,6 +103,7 @@
+    20420 STPNCPY
+    20430 WMEMCHR
+    20440 WCSNLEN
++   20450 WSTRNCMP
+ */
+ 
+ #if defined(VGO_solaris)
+@@ -1927,6 +1928,36 @@ static inline void my_exit ( int x )
+  WCSCMP(VG_Z_LIBC_SONAME,          wcscmp)
+ #endif
+ 
++/*---------------------- wcsncmp ----------------------*/
++
++// This is a wchar_t equivalent to strncmp.  We don't
++// have wchar_t available here, but in the GNU C Library
++// wchar_t is always 32 bits wide and wcsncmp uses signed
++// comparison, not unsigned as in strncmp function.
++
++#define WCSNCMP(soname, fnname) \
++   int VG_REPLACE_FUNCTION_EZU(20450,soname,fnname) \
++          ( const Int* s1, const Int* s2, SizeT nmax ); \
++   int VG_REPLACE_FUNCTION_EZU(20450,soname,fnname) \
++          ( const Int* s1, const Int* s2, SizeT nmax ) \
++   { \
++      SizeT n = 0; \
++      while (True) { \
++         if (n >= nmax) return 0; \
++         if (*s1 == 0 && *s2 == 0) return 0; \
++         if (*s1 == 0) return -1; \
++         if (*s2 == 0) return 1; \
++         \
++         if (*s1 < *s2) return -1; \
++         if (*s1 > *s2) return 1; \
++         \
++         s1++; s2++; n++; \
++      } \
++   }
++#if defined(VGO_linux)
++ WCSNCMP(VG_Z_LIBC_SONAME,          wcsncmp)
++#endif
++
+ /*---------------------- wcscpy ----------------------*/
+ 
+ // This is a wchar_t equivalent to strcpy.  We don't
diff --git a/SOURCES/valgrind-3.14.0-x86-Iop_Sar64.patch b/SOURCES/valgrind-3.14.0-x86-Iop_Sar64.patch
new file mode 100644
index 0000000..143f32d
--- /dev/null
+++ b/SOURCES/valgrind-3.14.0-x86-Iop_Sar64.patch
@@ -0,0 +1,73 @@
+From f730da53e59ab25c5b250d7730ead57b6f72fdcf Mon Sep 17 00:00:00 2001
+From: Julian Seward <jseward@acm.org>
+Date: Sun, 23 Dec 2018 21:03:08 +0100
+Subject: [PATCH] Implement Iop_Sar64 in the x86 back end.
+
+---
+ VEX/priv/host_x86_isel.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c
+index 45aafeb..9ca8a45 100644
+--- a/VEX/priv/host_x86_isel.c
++++ b/VEX/priv/host_x86_isel.c
+@@ -2380,6 +2380,56 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
+             return;
+          }
+ 
++         case Iop_Sar64: {
++            /* gcc -O2 does the following.  I don't know how it works, but it
++               does work.  Don't mess with it.  This is hard to test because the
++               x86 front end doesn't create Iop_Sar64 for any x86 instruction,
++               so it's impossible to write a test program that feeds values
++               through Iop_Sar64 and prints their results.  The implementation
++               here was tested by using psrlq on mmx registers -- that generates
++               Iop_Shr64 -- and temporarily hacking the front end to generate
++               Iop_Sar64 for that instruction instead.
++
++               movl  %amount, %ecx
++               movl  %srcHi,  %r1
++               movl  %srcLo,  %r2
++
++               movl   %r1, %r3
++               sarl   %cl, %r3
++               movl   %r2, %r4
++               shrdl  %cl, %r1, %r4
++               movl   %r3, %r2
++               sarl   $31, %r2
++               andl   $32, %ecx
++               cmovne %r3, %r4   // = resLo
++               cmovne %r2, %r3   // = resHi
++            */
++            HReg amount = iselIntExpr_R(env, e->Iex.Binop.arg2);
++            HReg srcHi = INVALID_HREG, srcLo = INVALID_HREG;
++            iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Binop.arg1);
++            HReg r1 = newVRegI(env);
++            HReg r2 = newVRegI(env);
++            HReg r3 = newVRegI(env);
++            HReg r4 = newVRegI(env);
++            addInstr(env, mk_iMOVsd_RR(amount, hregX86_ECX()));
++            addInstr(env, mk_iMOVsd_RR(srcHi, r1));
++            addInstr(env, mk_iMOVsd_RR(srcLo, r2));
++
++            addInstr(env, mk_iMOVsd_RR(r1, r3));
++            addInstr(env, X86Instr_Sh32(Xsh_SAR, 0/*%cl*/, r3));
++            addInstr(env, mk_iMOVsd_RR(r2, r4));
++            addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, r1, r4));
++            addInstr(env, mk_iMOVsd_RR(r3, r2));
++            addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, r2));
++            addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(32),
++                                                    hregX86_ECX()));
++            addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(r3), r4));
++            addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(r2), r3));
++            *rHi = r3;
++            *rLo = r4;
++            return;
++         }
++
+          /* F64 -> I64 */
+          /* Sigh, this is an almost exact copy of the F64 -> I32/I16
+             case.  Unfortunately I see no easy way to avoid the
+-- 
+1.8.3.1
+
diff --git a/SPECS/valgrind.spec b/SPECS/valgrind.spec
index 270b7a3..27cb2be 100644
--- a/SPECS/valgrind.spec
+++ b/SPECS/valgrind.spec
@@ -2,8 +2,8 @@
 
 Summary: Tool for finding memory management bugs in programs
 Name: %{?scl_prefix}valgrind
-Version: 3.13.0
-Release: 13%{?dist}
+Version: 3.14.0
+Release: 16%{?dist}
 Epoch: 1
 License: GPLv2+
 URL: http://www.valgrind.org/
@@ -60,26 +60,23 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
 %endif
 
 # Whether to run the full regtest or only a limited set
-# The full regtest includes gdb_server integration tests.
-# On arm the gdb integration tests hang for unknown reasons.
-# On rhel6 the gdb_server tests hang.
-# On rhel7 they hang on ppc64 and ppc64le.
-%ifarch %{arm}
-  %global run_full_regtest 0
-%else
-  %if 0%{?rhel} == 6
+# The full regtest includes gdb_server integration tests
+# and experimental tools.
+# Only run full regtests on x86_64, but not on older rhel
+# or when creating scl, the gdb_server tests might hang.
+%ifarch x86_64
+  %if %{is_scl}
     %global run_full_regtest 0
   %else
-    %if 0%{?rhel} == 7
-      %ifarch ppc64 ppc64le
-        %global run_full_regtest 0
-      %else
-        %global run_full_regtest 1
-      %endif
-    %else
+    %if 0%{?fedora}
       %global run_full_regtest 1
     %endif
+    %if 0%{?rhel}
+      %global run_full_regtest (%rhel >= 7)
+    %endif
   %endif
+%else
+  %global run_full_regtest 0
 %endif
 
 # Generating minisymtabs doesn't really work for the staticly linked
@@ -100,77 +97,89 @@ Patch2: valgrind-3.9.0-helgrind-race-supp.patch
 # Make ld.so supressions slightly less specific.
 Patch3: valgrind-3.9.0-ldso-supp.patch
 
-# KDE#381272  ppc64 doesn't compile test_isa_2_06_partx.c without VSX support
-Patch4: valgrind-3.13.0-ppc64-check-no-vsx.patch
+# KDE#400490 s390x: Fix register allocation for VRs vs FPRs
+Patch4: valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch
+
+# KDE#400491 s390x: Sign-extend immediate operand of LOCHI and friends
+Patch5: valgrind-3.14.0-s390x-sign-extend-lochi.patch
+
+# KDE#397187 s390x: Add vector register support for vgdb
+Patch6: valgrind-3.14.0-s390x-vec-reg-vgdb.patch
 
-# KDE#381289 epoll_pwait can have a NULL sigmask.
-Patch5: valgrind-3.13.0-epoll_pwait.patch
+# KDE#385411 s390x: z13 vector floating-point instructions not implemented
+Patch7: valgrind-3.14.0-s390x-vec-float-point-code.patch
+Patch8: valgrind-3.14.0-s390x-vec-float-point-tests.patch
 
-# KDE#381274 powerpc too chatty even with --sigill-diagnostics=no
-Patch6: valgrind-3.13.0-ppc64-diag.patch
+# KDE#401277 More bugs in z13 support
+Patch9: valgrind-3.14.0-s390z-more-z13-fixes.patch
 
-# KDE#381556 arm64: Handle feature registers access on 4.11 Linux kernel
-# Workaround that masks CPUID support in HWCAP on aarch64 (#1464211)
-Patch7: valgrind-3.13.0-arm64-hwcap.patch
+# KDE#386945 Bogus memcheck errors on ppc64(le) when using strcmp
+Patch10: valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch
+Patch11: valgrind-3.14.0-new-strlen-IROps.patch
+Patch12: valgrind-3.14.0-ppc-instr-new-IROps.patch
+Patch13: valgrind-3.14.0-memcheck-new-IROps.patch
+Patch14: valgrind-3.14.0-ppc-frontend-new-IROps.patch
+Patch15: valgrind-3.14.0-transform-popcount64-ctznat64.patch
+Patch16: valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch
 
-# RHBZ#1466017 ARM ld.so index warnings.
-# KDE#381805 arm32 needs ld.so index hardwire for new glibc security fixes
-Patch8: valgrind-3.13.0-arm-index-hardwire.patch
+# KDE#401627 memcheck errors with glibc avx2 optimized wcsncmp
+Patch17: valgrind-3.14.0-wcsncmp.patch
 
-# KDE#381769 Use ucontext_t instead of struct ucontext
-Patch9: valgrind-3.13.0-ucontext_t.patch
+# KDE#402006 mark helper regs defined in final_tidyup before freeres_wrapper
+# Prereq for KDE#386945
+Patch18: valgrind-3.14.0-final_tidyup.patch
 
-# valgrind svn r16453 Fix some tests failure with GDB 8.0
-Patch10: valgrind-3.13.0-gdb-8-testfix.patch
+# KDE#386945 Bogus memcheck errors on ppc64(le) when using strcmp
+# See also patches 10 to 16 (yes, there are this many...)
+Patch19: valgrind-3.14.0-ppc64-ldbrx.patch
+Patch20: valgrind-3.14.0-ppc64-unaligned-words.patch
+Patch21: valgrind-3.14.0-ppc64-lxvd2x.patch
+Patch22: valgrind-3.14.0-ppc64-unaligned-vecs.patch
+Patch23: valgrind-3.14.0-ppc64-lxvb16x.patch
+Patch24: valgrind-3.14.0-set_AV_CR6.patch
+Patch25: valgrind-3.14.0-undef_malloc_args.patch
 
-# valgrind svn r16454. disable vgdb poll in the child after fork
-Patch11: valgrind-3.13.0-disable-vgdb-child.patch
+# KDE#401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings
+Patch26: valgrind-3.14.0-jm-vmx-constraints.patch
 
-# KDE#382998 xml-socket doesn't work
-Patch12: valgrind-3.13.0-xml-socket.patch
+# commit 0c701ba2a Fix sigkill.stderr.exp for glibc-2.28.
+Patch27: valgrind-3.14.0-sigkill.patch
 
-# KDE#385334
-# PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field
-# PPC64, revert the change to vperm instruction.
-# KDE#385183
-# PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions
-# PPC64, Fix bug in vperm instruction.
-# KDE#385210
-# PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16.
-# KDE#385208
-# PPC64, Use the vperm code to implement the xxperm inst.
-# PPC64, Replace body of generate_store_FPRF with C helper function.
-# PPC64, Add support for the Data Stream Control Register (DSCR)
-Patch13: valgrind-3.13.0-ppc64-vex-fixes.patch
+# KDE#402048 Implement minimal ptrace support for ppc64[le]-linux.
+Patch28: valgrind-3.14.0-ppc64-ptrace.patch
 
-# Fix eflags handling in amd64 instruction tests
-Patch14: valgrind-3.13.0-amd64-eflags-tests.patch
+# commit 43fe4bc23 arm64: Fix PTRACE_TRACEME
+Patch29: valgrind-3.14.0-arm64-ptrace-traceme.patch
 
-# KDE#385868 ld.so _dl_runtime_resolve_avx_slow conditional jump warning
-Patch15: valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch
+# KDE#402134 - assert fail mc_translate.c (noteTmpUsesIn) Iex_VECRET on arm64
+Patch30: valgrind-3.14.0-mc_translate-vecret.patch
 
-# Implement static TLS code for more platforms
-Patch16: valgrind-3.13.0-static-tls.patch
+# KDE#402481 vbit-test fails on x86 for Iop_CmpEQ64 iselInt64Expr Sar64
+Patch31: valgrind-3.14.0-vbit-test-sec.patch
+Patch32: valgrind-3.14.0-x86-Iop_Sar64.patch
 
-# KDE#386397 PPC64 valgrind truncates powerpc timebase to 32-bits.
-Patch17: valgrind-3.13.0-ppc64-timebase.patch
+# KDE#402519 POWER 3.0 addex instruction incorrectly implemented
+Patch33: valgrind-3.14.0-power9-addex.patch
 
-# KDE#387773 - Files in .gnu_debugaltlink should be resolved relative to .debug
-Patch18: valgrind-3.13.0-debug-alt-file.patch
+# KDE#402480  Do not use %rsp in clobber list
+Patch34: valgrind-3.14.0-rsp-clobber.patch
 
-# KDE#387712 s390x cgijnl reports Conditional jump depends on uninit value
-Patch19: valgrind-3.13.0-s390-cgijnl.patch
+# commit 3528f8 Accept DW_TAG_subrange_type with DW_AT_count
+Patch35: valgrind-3.14.0-subrange_type-count.patch
 
-# KDE#391164 constraint bug in tests/ppc64/test_isa_2_07_part1.c for mtfprwa
-Patch20: valgrind-3.13.0-ppc64-mtfprwa-constraint.patch
 
-# KDE#393062 Reading build-id ELF note "debuginfo reader: ensure_valid failed"
-Patch21: valgrind-3.13.0-build-id-phdrs.patch
+# KDE#403552 s390x: wrong facility bit checked for vector facility
+Patch36: valgrind-3.14.0-s390x-vec-facility-bit.patch
 
-# KDE#368913 WARNING: unhandled arm64-linux syscall: 117 (ptrace)
-Patch22: valgrind-3.13.0-arm64-ptrace.patch
+# KDE#404054 powerpc subfe x, x, x initializes x to 0 or -1 based on CA
+Patch37: valgrind-3.14.0-ppc-subfe.patch
+
+# KDE#405079 unhandled ppc64le-linux syscall: 131 (quotactl)
+Patch38: valgrind-3.14.0-ppc64-quotactl.patch
+
+# SW#6399 glibc might implement gettid itself, rename to gettid_sys.
+Patch39: valgrind-3.14.0-gettid.patch
 
-# RHEL7 specific patches.
 
 # RHBZ#996927 Ignore PPC floating point phased out category.
 # The result might differ on ppc vs ppc64 and config.h ends up as
@@ -178,8 +187,8 @@ Patch22: valgrind-3.13.0-arm64-ptrace.patch
 # The result would only be used for two test cases.
 Patch7001: valgrind-3.11.0-ppc-fppo.patch
 
-%if %{build_multilib}
 
+%if %{build_multilib}
 # Ensure glibc{,-devel} is installed for both multilib arches
 BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so
 %endif
@@ -198,12 +207,9 @@ BuildRequires: glibc-devel >= 2.5
 BuildRequires: openmpi-devel >= 1.3.3
 %endif
 
-# For %%build and %%check.
-# In case of a software collection, pick the matching gdb and binutils.
 %if %{run_full_regtest}
-BuildRequires: %{?scl_prefix}gdb
+BuildRequires: gdb
 %endif
-BuildRequires: %{?scl_prefix}binutils
 
 # gdbserver_tests/filter_make_empty uses ps in test
 BuildRequires: procps
@@ -219,6 +225,15 @@ BuildRequires: perl(Getopt::Long)
 
 %{?scl:Requires:%scl_runtime}
 
+# We need to fixup selinux file context when doing a scl build.
+# In RHEL6 we might need to fix up the labels even though the
+# meta package sets up a fs equivalence. See post.
+%if 0%{?rhel} == 6
+%{?scl:Requires(post): /sbin/restorecon}
+%endif
+
+# Explicit list, should use valgrind_arches from redhat-rpm-config
+# but that currently doesn't include s390x (z13 support is not complete).
 ExclusiveArch: %{ix86} x86_64 ppc ppc64 ppc64le s390x armv7hl aarch64
 %ifarch %{ix86}
 %define valarch x86
@@ -315,16 +330,30 @@ Valgrind User Manual for details.
 %patch20 -p1
 %patch21 -p1
 %patch22 -p1
+%patch23 -p1
+%patch24 -p1
+%patch25 -p1
+%patch26 -p1
+%patch27 -p1
+%patch28 -p1
+%patch29 -p1
+%patch30 -p1
+%patch31 -p1
+%patch32 -p1
+%patch33 -p1
+%patch34 -p1
+%patch35 -p1
+%patch36 -p1
+%patch37 -p1
+%patch38 -p1
+%patch39 -p1
+
 
 # RHEL7 specific patches
 %patch7001 -p1
 
-%build
-# We need to use the software collection compiler and binutils if available.
-# The configure checks might otherwise miss support for various newer
-# assembler instructions.
-%{?scl:PATH=%{_bindir}${PATH:+:${PATH}}}
 
+%build
 CC=gcc
 %if %{build_multilib}
 # Ugly hack - libgcc 32-bit package might not be installed
@@ -352,8 +381,11 @@ CC="gcc -B `pwd`/shared/libgcc/"
 # not for tests which should be -O0, as they aren't meant to be
 # compiled with -O2 unless explicitely requested. Same for any -mcpu flag.
 # Ideally we will change this to only be done for the non-primary build
-# and the test suite.
+# and the test suite. Also disable strict symbol checks because the
+# vg_preload library will use hidden/undefined symbols from glibc
+# like __libc_freeres.
 %undefine _hardened_build
+%undefine _strict_symbol_defs_build
 OPTFLAGS="`echo " %{optflags} " | sed 's/ -m\(64\|3[21]\) / /g;s/ -fexceptions / /g;s/ -fstack-protector\([-a-z]*\) / / g;s/ -Wp,-D_FORTIFY_SOURCE=2 / /g;s/ -O2 / /g;s/ -mcpu=\([a-z0-9]\+\) / /g;s/^ //;s/ $//'`"
 %configure CC="$CC" CFLAGS="$OPTFLAGS" CXXFLAGS="$OPTFLAGS" \
   --with-mpicc=%{mpiccpath} \
@@ -434,9 +466,9 @@ chmod 644 $RPM_BUILD_ROOT%{_libdir}/valgrind/vgpreload*-%{valarch}-*so
 # Add || true because rpm on copr EPEL6 acts weirdly and we don't want
 # to break the build.
 uname -a
-rpm -q glibc gcc %{?scl_prefix}binutils || true
+rpm -q glibc gcc binutils || true
 %if %{run_full_regtest}
-rpm -q %{?scl_prefix}gdb || true
+rpm -q gdb || true
 %endif
 
 LD_SHOW_AUXV=1 /bin/true
@@ -465,7 +497,7 @@ echo ===============TESTING===================
 # Make sure test failures show up in build.log
 # Gather up the diffs (at most the first 20 lines for each one)
 MAX_LINES=20
-diff_files=`find . -name '*.diff' | sort`
+diff_files=`find */tests -name '*.diff*' | sort`
 if [ z"$diff_files" = z ] ; then
    echo "Congratulations, all tests passed!" >> diffs
 else
@@ -522,6 +554,9 @@ echo ===============END TESTING===============
 %endif
 
 %changelog
+* Tue Mar  5 2019 Mark Wielaard <mjw@redhat.com> - 3.14.0-16
+- Rebase to 3.14.0 plus backports and z13 support (#1519410)
+
 * Thu Jun 21 2018 Mark Wielaard <mjw@redhat.com> - 3.13.0-13
 - Improved valgrind-3.13.0-arm64-hwcap.patch (#1593686)
 - Add valgrind-3.13.0-arm64-ptrace.patch (#1593682)