diff --git a/valgrind-3.10.0-aarch64-fcvta.patch b/valgrind-3.10.0-aarch64-fcvta.patch new file mode 100644 index 0000000..8146c3b --- /dev/null +++ b/valgrind-3.10.0-aarch64-fcvta.patch @@ -0,0 +1,108 @@ +commit f9fae2ab83f7263f8d58f83ddd58921cd5d1dca8 +Author: sewardj +Date: Thu Oct 30 23:10:45 2014 +0000 + + Implement FCVTAS W_S and FCVTAU W_S. Fixes #340509. + + + git-svn-id: svn://svn.valgrind.org/vex/trunk@2984 8f6e269a-dfd6-0310-a8e1-e2731360e62c + +diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c +index 2677211..acfdc02 100644 +--- a/VEX/priv/guest_arm64_toIR.c ++++ b/VEX/priv/guest_arm64_toIR.c +@@ -12189,6 +12189,7 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn) + /* 31 30 29 28 23 21 20 18 15 9 4 + sf 0 0 11110 type 1 rmode opcode 000000 n d + The first 3 bits are really "sf 0 S", but S is always zero. ++ Decode fields: sf,type,rmode,opcode + */ + # define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) + if (INSN(30,29) != BITS2(0,0) +@@ -12205,7 +12206,7 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn) + UInt dd = INSN(4,0); + + // op = 000, 001 +- /* -------- FCVT{N,P,M,Z}{S,U} (scalar, integer) -------- */ ++ /* -------- FCVT{N,P,M,Z,A}{S,U} (scalar, integer) -------- */ + /* 30 23 20 18 15 9 4 + sf 00 11110 0x 1 00 000 000000 n d FCVTNS Rd, Fn (round to + sf 00 11110 0x 1 00 001 000000 n d FCVTNU Rd, Fn nearest) +@@ -12213,23 +12214,38 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn) + ---------------- 10 -------------- FCVTM-------- (round to -inf) + ---------------- 11 -------------- FCVTZ-------- (round to zero) + ++ ---------------- 00 100 ---------- FCVTAS------- (nearest, ties away) ++ ---------------- 00 101 ---------- FCVTAU------- (nearest, ties away) ++ + Rd is Xd when sf==1, Wd when sf==0 + Fn is Dn when x==1, Sn when x==0 + 20:19 carry the rounding mode, using the same encoding as FPCR + */ +- if (ty <= X01 && (op == BITS3(0,0,0) || op == BITS3(0,0,1))) { ++ if (ty <= X01 ++ && ( ((op == BITS3(0,0,0) || op == BITS3(0,0,1)) && True) ++ || ((op == BITS3(1,0,0) || op == BITS3(1,0,1)) && rm == BITS2(0,0)) ++ ) ++ ) { + Bool isI64 = bitSF == 1; + Bool isF64 = (ty & 1) == 1; + Bool isU = (op & 1) == 1; + /* Decide on the IR rounding mode to use. */ + IRRoundingMode irrm = 8; /*impossible*/ + HChar ch = '?'; +- switch (rm) { +- case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break; +- case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break; +- case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break; +- case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break; +- default: vassert(0); ++ if (op == BITS3(0,0,0) || op == BITS3(0,0,1)) { ++ switch (rm) { ++ case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break; ++ case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break; ++ case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break; ++ case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break; ++ default: vassert(0); ++ } ++ } else { ++ vassert(op == BITS3(1,0,0) || op == BITS3(1,0,1)); ++ switch (rm) { ++ case BITS2(0,0): ch = 'a'; irrm = Irrm_NEAREST; break; ++ default: vassert(0); ++ } + } + vassert(irrm != 8); + /* Decide on the conversion primop, based on the source size, +@@ -12254,9 +12270,11 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn) + (iop == Iop_F32toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Sn */ + || (iop == Iop_F32toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Sn */ + || (iop == Iop_F32toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Sn */ ++ || (iop == Iop_F32toI32S && irrm == Irrm_NEAREST)/* FCVT{A,N}S W,S */ + /* F32toI32U */ + || (iop == Iop_F32toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Sn */ + || (iop == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */ ++ || (iop == Iop_F32toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,S */ + /* F32toI64S */ + || (iop == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */ + /* F32toI64U */ +commit 9f69352a36003c35cfe8ffe01ba8ef0f830b4198 +Author: mjw +Date: Tue Nov 4 15:30:42 2014 +0000 + + Bug 340632 arm64: unhandled instruction fcvtas + + git-svn-id: svn://svn.valgrind.org/vex/trunk@2987 8f6e269a-dfd6-0310-a8e1-e2731360e62c + +diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c +index 4229d6a..1426d00 100644 +--- a/VEX/priv/guest_arm64_toIR.c ++++ b/VEX/priv/guest_arm64_toIR.c +@@ -12304,6 +12304,7 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn) + || (iop == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */ + || (iop == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */ + || (iop == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */ ++ || (iop == Iop_F64toI64S && irrm == Irrm_NEAREST) /* FCVT{A,N}S Xd,Dn */ + /* F64toI64U */ + || (iop == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */ + || (iop == Iop_F64toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Dn */ diff --git a/valgrind.spec b/valgrind.spec index b60229f..5302690 100644 --- a/valgrind.spec +++ b/valgrind.spec @@ -3,7 +3,7 @@ Summary: Tool for finding memory management bugs in programs Name: %{?scl_prefix}valgrind Version: 3.10.0 -Release: 4%{?dist} +Release: 5%{?dist} Epoch: 1 License: GPLv2+ URL: http://www.valgrind.org/ @@ -79,6 +79,10 @@ Patch8: valgrind-3.10.0-aarch64-frint.patch # KDE#339927 Implement fcvtmu x_d. Patch9: valgrind-3.10.0-fcvtmu.patch +# KDE#340509 Implement FCVTAS W_S and FCVTAU W_S. +# KDE#340632 arm64: unhandled instruction fcvtas +Patch10: valgrind-3.10.0-aarch64-fcvta.patch + %if %{build_multilib} # Ensure glibc{,-devel} is installed for both multilib arches BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so @@ -186,6 +190,7 @@ Valgrind User Manual for details. %patch7 -p1 %patch8 -p1 %patch9 -p1 +%patch10 -p1 %build # We need to use the software collection compiler and binutils if available. @@ -334,7 +339,7 @@ echo ===============END TESTING=============== %endif %changelog -* Tue Nov 4 2014 Mark Wielaard +* Tue Nov 4 2014 Mark Wielaard - 3.10.0-5 - Merge valgrind-3.10.0-aarch64-times.patch and valgrind-3.10.0-aarch64-getsetsid.patch into valgrind-3.10.0-aarch64-syscalls.patch @@ -342,6 +347,7 @@ echo ===============END TESTING=============== mknodat, fchdir, chroot, fchownat, fchmod and fchown. - Add valgrind-3.10.0-aarch64-frint.patch - Add valgrind-3.10.0-fcvtmu.patch +- Add valgrind-3.10.0-aarch64-fcvta.patch * Sat Oct 11 2014 Mark Wielaard - 3.10.0-4 - Add valgrind-3.10.0-aarch64-times.patch