diff --git a/.gitignore b/.gitignore
index ef7bf06..9d2fd58 100644
--- a/.gitignore
+++ b/.gitignore
@@ -31,3 +31,4 @@
/valgrind-3.14.0.GIT.tar.bz2
/valgrind-3.14.0.RC2.tar.bz2
/valgrind-3.14.0.tar.bz2
+/valgrind-3.15.0.RC1.tar.bz2
diff --git a/sources b/sources
index cb41757..754fe1f 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-SHA512 (valgrind-3.14.0.tar.bz2) = 68e548c42df31dc2b883a403e0faff7480c49b3054841870f5d2f742141ba199eca5d83c96bbf283115f0633f2bdb0860161d422f98e3ec720ec65760d250f97
+SHA512 (valgrind-3.15.0.RC1.tar.bz2) = 597173ada0989ad4ee8cf3b120b87d6575377101db9f6514458e86f6a743b9514f5b1469486a297ca7b46da70d3c91bc1a19ac0ee19bf50f4fdb645b689df20e
diff --git a/valgrind-3.14.0-arm64-ptrace-traceme.patch b/valgrind-3.14.0-arm64-ptrace-traceme.patch
deleted file mode 100644
index 726be00..0000000
--- a/valgrind-3.14.0-arm64-ptrace-traceme.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 43fe4bc236d667257eeebfb4f6bcbe2b92aea455
-Author: Mark Wielaard <mark@klomp.org>
-Date: Fri Dec 14 14:32:27 2018 +0100
-
- arm64: Fix PTRACE_TRACEME memcheck/tests/linux/getregset.vgtest testcase.
-
- The sys_ptrace post didn't mark the thread as being in traceme mode.
- This occassionally would make the memcheck/tests/linux/getregset.vgtest
- testcase fail. With this patch it reliably passes.
-
-diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
-index 9ef54b4..650f5b9 100644
---- a/coregrind/m_syswrap/syswrap-arm64-linux.c
-+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
-@@ -499,6 +499,9 @@ PRE(sys_ptrace)
- POST(sys_ptrace)
- {
- switch (ARG1) {
-+ case VKI_PTRACE_TRACEME:
-+ ML_(linux_POST_traceme)(tid);
-+ break;
- case VKI_PTRACE_PEEKTEXT:
- case VKI_PTRACE_PEEKDATA:
- case VKI_PTRACE_PEEKUSR:
diff --git a/valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch b/valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch
deleted file mode 100644
index 8101f93..0000000
--- a/valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch
+++ /dev/null
@@ -1,18 +0,0 @@
-commit 27fe22378da38424102c5292b782cacdd9d7b9e4
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 12:09:03 2018 +0100
-
- Add support for Iop_{Sar,Shr}8 on ppc. --expensive-definedness-checks=yes needs them.
-
-diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
-index 5242176..750cf8d 100644
---- a/VEX/priv/host_ppc_isel.c
-+++ b/VEX/priv/host_ppc_isel.c
-@@ -1528,7 +1528,6 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
- True/*32bit shift*/,
- tmp, tmp, amt));
- r_srcL = tmp;
-- vassert(0); /* AWAITING TEST CASE */
- }
- }
- /* Only 64 expressions need 64bit shifts,
diff --git a/valgrind-3.14.0-final_tidyup.patch b/valgrind-3.14.0-final_tidyup.patch
deleted file mode 100644
index f4e7698..0000000
--- a/valgrind-3.14.0-final_tidyup.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-commit be7a73004583aab5d4c97cf55276ca58d5b3090b
-Author: Mark Wielaard <mark@klomp.org>
-Date: Wed Dec 12 14:15:28 2018 +0100
-
- Mark helper regs defined in final_tidyup before freeres_wrapper call.
-
- In final_tidyup we setup the guest to call the freeres_wrapper, which
- will (possibly) call __gnu_cxx::__freeres() and/or __libc_freeres().
-
- In a couple of cases (ppc64be, ppc64le and mips32) this involves setting
- up one or more helper registers. Since we setup these guest registers
- we should make sure to mark them as fully defined. Otherwise we might
- see spurious warnings about undefined value usage if the guest register
- happened to not be fully defined before.
-
- This fixes PR402006.
-
-diff --git a/coregrind/m_main.c b/coregrind/m_main.c
-index 00702fc..22872a2 100644
---- a/coregrind/m_main.c
-+++ b/coregrind/m_main.c
-@@ -2304,22 +2304,35 @@ static void final_tidyup(ThreadId tid)
- "Caught __NR_exit; running %s wrapper\n", msgs[to_run - 1]);
- }
-
-- /* set thread context to point to freeres_wrapper */
-- /* ppc64be-linux note: freeres_wrapper gives us the real
-+ /* Set thread context to point to freeres_wrapper.
-+ ppc64be-linux note: freeres_wrapper gives us the real
- function entry point, not a fn descriptor, so can use it
- directly. However, we need to set R2 (the toc pointer)
- appropriately. */
- VG_(set_IP)(tid, freeres_wrapper);
-+
- # if defined(VGP_ppc64be_linux)
- VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
-+ VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
-+ offsetof(VexGuestPPC64State, guest_GPR2),
-+ sizeof(VG_(threads)[tid].arch.vex.guest_GPR2));
- # elif defined(VGP_ppc64le_linux)
- /* setting GPR2 but not really needed, GPR12 is needed */
- VG_(threads)[tid].arch.vex.guest_GPR2 = freeres_wrapper;
-+ VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
-+ offsetof(VexGuestPPC64State, guest_GPR2),
-+ sizeof(VG_(threads)[tid].arch.vex.guest_GPR2));
- VG_(threads)[tid].arch.vex.guest_GPR12 = freeres_wrapper;
-+ VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
-+ offsetof(VexGuestPPC64State, guest_GPR12),
-+ sizeof(VG_(threads)[tid].arch.vex.guest_GPR12));
- # endif
- /* mips-linux note: we need to set t9 */
- # if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
- VG_(threads)[tid].arch.vex.guest_r25 = freeres_wrapper;
-+ VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
-+ offsetof(VexGuestMIPS32State, guest_r25),
-+ sizeof(VG_(threads)[tid].arch.vex.guest_r25));
- # endif
-
- /* Pass a parameter to freeres_wrapper(). */
diff --git a/valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch b/valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch
deleted file mode 100644
index d9df0d9..0000000
--- a/valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-commit 7f1dd9d5aec1f1fd4eb0ae3a311358a914f1d73f
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 10:18:29 2018 +0100
-
- get_otrack_shadow_offset_wrk for ppc32 and ppc64: add missing cases for XER_OV32, XER_CA32 and C_FPCC.
-
- The missing cases were discovered whilst testing fixes for bug 386945, but are
- otherwise unrelated to that bug.
-
-diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
-index 5ed101f..4ce746e 100644
---- a/memcheck/mc_machine.c
-+++ b/memcheck/mc_machine.c
-@@ -120,11 +120,11 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
- Int o = offset;
- tl_assert(sz > 0);
-
--#if defined(VGA_ppc64be)
-+# if defined(VGA_ppc64be)
- tl_assert(host_is_big_endian());
--#elif defined(VGA_ppc64le)
-+# elif defined(VGA_ppc64le)
- tl_assert(host_is_little_endian());
--#endif
-+# endif
-
- if (sz == 8 || sz == 4) {
- /* The point of this is to achieve
-@@ -132,11 +132,11 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
- return GOF(GPRn);
- by testing ox instead of o, and setting ox back 4 bytes when sz == 4.
- */
--#if defined(VGA_ppc64le)
-+# if defined(VGA_ppc64le)
- Int ox = o;
--#else
-+# else
- Int ox = sz == 8 ? o : (o - 4);
--#endif
-+# endif
- if (ox == GOF(GPR0)) return ox;
- if (ox == GOF(GPR1)) return ox;
- if (ox == GOF(GPR2)) return ox;
-@@ -240,11 +240,13 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
- if (o == GOF(VSR31) && sz == 8) return o;
-
- /* For the various byte sized XER/CR pieces, use offset 8
-- in VSR0 .. VSR19. */
-+ in VSR0 .. VSR21. */
- tl_assert(SZB(VSR0) == 16);
- if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
- if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
-+ if (o == GOF(XER_OV32) && sz == 1) return 8 +GOF(VSR20);
- if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
-+ if (o == GOF(XER_CA32) && sz == 1) return 8 +GOF(VSR21);
- if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
-
- if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
-@@ -388,6 +390,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
- if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
- if (o == GOF(FPROUND) && sz == 1) return -1;
- if (o == GOF(DFPROUND) && sz == 1) return -1;
-+ if (o == GOF(C_FPCC) && sz == 1) return -1;
- if (o == GOF(VRSAVE) && sz == 4) return -1;
- if (o == GOF(EMNOTE) && sz == 4) return -1;
- if (o == GOF(CMSTART) && sz == 4) return -1;
-@@ -440,11 +443,13 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
- if (o == GOF(VSR31) && sz == 8) return o;
-
- /* For the various byte sized XER/CR pieces, use offset 8
-- in VSR0 .. VSR19. */
-+ in VSR0 .. VSR21. */
- tl_assert(SZB(VSR0) == 16);
- if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
- if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
-+ if (o == GOF(XER_OV32) && sz == 1) return 8 +GOF(VSR20);
- if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
-+ if (o == GOF(XER_CA32) && sz == 1) return 8 +GOF(VSR21);
- if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
-
- if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
diff --git a/valgrind-3.14.0-gettid.patch b/valgrind-3.14.0-gettid.patch
deleted file mode 100644
index ecdd209..0000000
--- a/valgrind-3.14.0-gettid.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-commit b46023d525b6e38a096ff4fdf9e6a96c7d7b7d40
-Author: Mark Wielaard <mark@klomp.org>
-Date: Mon Mar 4 19:47:59 2019 +0100
-
- Rename gettid() to gettid_sys() in gdbserver_tests.
-
- glibc might defined gettid() itself through unistd.h:
- https://sourceware.org/bugzilla/show_bug.cgi?id=6399
-
- Rename to gettid_sys() so we don't clash with the glibc definition.
-
-diff --git a/gdbserver_tests/sleepers.c b/gdbserver_tests/sleepers.c
-index 5ffc6f8..dfda828 100644
---- a/gdbserver_tests/sleepers.c
-+++ b/gdbserver_tests/sleepers.c
-@@ -15,7 +15,7 @@ static int sleepms = 1000; // in each loop, will sleep "sleepms" milliseconds
- static int burn = 0; // after each sleep, will burn cpu in a tight 'burn' loop
- static void setup_sigusr_handler(void); // sigusr1 and 2 sigaction setup.
-
--static pid_t gettid()
-+static pid_t gettid_sys()
- {
- #ifdef __NR_gettid
- return syscall(__NR_gettid);
-@@ -27,7 +27,7 @@ static pid_t gettid()
- static void whoami(char *msg) __attribute__((unused));
- static void whoami(char *msg)
- {
-- fprintf(stderr, "pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid(),
-+ fprintf(stderr, "pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid_sys(),
- msg);
- fflush(stderr);
- }
-diff --git a/gdbserver_tests/t.c b/gdbserver_tests/t.c
-index 228d4a4..b3e7a28 100644
---- a/gdbserver_tests/t.c
-+++ b/gdbserver_tests/t.c
-@@ -16,7 +16,7 @@ static int loopmain, loopt1, loopt2;
-
- static double pi = 3.14159265358979323846264338327950288;
-
--static pid_t gettid()
-+static pid_t gettid_sys()
- {
- #ifdef __NT_gettid
- return syscall(__NR_gettid);
-@@ -26,7 +26,7 @@ static pid_t gettid()
- }
- static void whoami(char *msg)
- {
-- printf("pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid(), msg);
-+ printf("pid %ld Thread %ld %s\n", (long) getpid(), (long) gettid_sys(), msg);
- fflush(stdout);
- }
-
diff --git a/valgrind-3.14.0-jm-vmx-constraints.patch b/valgrind-3.14.0-jm-vmx-constraints.patch
deleted file mode 100644
index cd6463b..0000000
--- a/valgrind-3.14.0-jm-vmx-constraints.patch
+++ /dev/null
@@ -1,654 +0,0 @@
-commit a0d97e88ec6d71239d30a5a4b2b129e094150873
-Author: Mark Wielaard <mark@klomp.org>
-Date: Thu Dec 6 20:52:22 2018 +0100
-
- Bug 401822 Fix asm constraints for ppc64 jm-vmx jm-insns.c test.
-
- The mfvscr and vor instructions in jm-insns.c had a "=vr" constraint.
- This should have been an "=v" constraint. This resolved assembler
- warnings and the testcase failing on ppc64le with gcc 8.2 and
- binutils 2.30.
-
-diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c
-index e1a7da9..be02425 100644
---- a/none/tests/ppc32/jm-insns.c
-+++ b/none/tests/ppc32/jm-insns.c
-@@ -6269,7 +6269,7 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
- for (i=0; i<nb_viargs; i++) {
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- vec_in = (vector unsigned int)viargs[i];
- vec_out = (vector unsigned int){ 0,0,0,0 };
-@@ -6287,11 +6287,11 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6333,7 +6333,7 @@ static void test_av_int_two_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6349,11 +6349,11 @@ static void test_av_int_two_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6401,7 +6401,7 @@ static void test_av_int_three_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6418,11 +6418,11 @@ static void test_av_int_three_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6475,7 +6475,7 @@ static void vs128_cb (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6491,11 +6491,11 @@ static void vs128_cb (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6548,7 +6548,7 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6563,11 +6563,11 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6615,7 +6615,7 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6627,11 +6627,11 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6677,7 +6677,7 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6693,11 +6693,11 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6750,7 +6750,7 @@ static void lvs_cb (const char *name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6762,11 +6762,11 @@ static void lvs_cb (const char *name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6870,7 +6870,7 @@ static void test_av_int_ld_two_regs (const char *name,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6882,11 +6882,11 @@ static void test_av_int_ld_two_regs (const char *name,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6956,7 +6956,7 @@ static void test_av_int_st_three_regs (const char *name,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6974,7 +6974,7 @@ static void test_av_int_st_three_regs (const char *name,
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7037,7 +7037,7 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7052,11 +7052,11 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7099,7 +7099,7 @@ static void test_av_float_two_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7115,11 +7115,11 @@ static void test_av_float_two_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7168,7 +7168,7 @@ static void test_av_float_three_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7185,11 +7185,11 @@ static void test_av_float_three_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7276,7 +7276,7 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7291,11 +7291,11 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-
-diff --git a/none/tests/ppc64/jm-insns.c b/none/tests/ppc64/jm-insns.c
-index e1a7da9..be02425 100644
---- a/none/tests/ppc64/jm-insns.c
-+++ b/none/tests/ppc64/jm-insns.c
-@@ -6269,7 +6269,7 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
- for (i=0; i<nb_viargs; i++) {
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- vec_in = (vector unsigned int)viargs[i];
- vec_out = (vector unsigned int){ 0,0,0,0 };
-@@ -6287,11 +6287,11 @@ static void test_av_int_one_arg (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6333,7 +6333,7 @@ static void test_av_int_two_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6349,11 +6349,11 @@ static void test_av_int_two_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6401,7 +6401,7 @@ static void test_av_int_three_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6418,11 +6418,11 @@ static void test_av_int_three_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6475,7 +6475,7 @@ static void vs128_cb (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6491,11 +6491,11 @@ static void vs128_cb (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6548,7 +6548,7 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6563,11 +6563,11 @@ static void vsplt_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6615,7 +6615,7 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6627,11 +6627,11 @@ static void vspltis_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6677,7 +6677,7 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6693,11 +6693,11 @@ static void vsldoi_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6750,7 +6750,7 @@ static void lvs_cb (const char *name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6762,11 +6762,11 @@ static void lvs_cb (const char *name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6870,7 +6870,7 @@ static void test_av_int_ld_two_regs (const char *name,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6882,11 +6882,11 @@ static void test_av_int_ld_two_regs (const char *name,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -6956,7 +6956,7 @@ static void test_av_int_st_three_regs (const char *name,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -6974,7 +6974,7 @@ static void test_av_int_st_three_regs (const char *name,
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7037,7 +7037,7 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7052,11 +7052,11 @@ static void test_av_float_one_arg (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7099,7 +7099,7 @@ static void test_av_float_two_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7115,11 +7115,11 @@ static void test_av_float_two_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7168,7 +7168,7 @@ static void test_av_float_three_args (const char* name, test_func_t func,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7185,11 +7185,11 @@ static void test_av_float_three_args (const char* name, test_func_t func,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
-@@ -7276,7 +7276,7 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
-
- /* Save flags */
- __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
-
- // reset VSCR and CR
- vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
-@@ -7291,11 +7291,11 @@ static void vcvt_cb (const char* name, test_func_t func_IN,
- (*func)();
-
- // retrieve output <- r17
-- __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
-+ __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
-
- // get CR,VSCR flags
- __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
-- __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
-+ __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
-
- /* Restore flags */
- __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
diff --git a/valgrind-3.14.0-mc_translate-vecret.patch b/valgrind-3.14.0-mc_translate-vecret.patch
deleted file mode 100644
index 487d328..0000000
--- a/valgrind-3.14.0-mc_translate-vecret.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
-index c24db91..1e770b3 100644
---- a/memcheck/mc_translate.c
-+++ b/memcheck/mc_translate.c
-@@ -8022,6 +8022,7 @@ static inline void noteTmpUsesIn ( /*MOD*/HowUsed* useEnv,
- use info. */
- switch (at->tag) {
- case Iex_GSPTR:
-+ case Iex_VECRET:
- case Iex_Const:
- return;
- case Iex_RdTmp: {
diff --git a/valgrind-3.14.0-memcheck-new-IROps.patch b/valgrind-3.14.0-memcheck-new-IROps.patch
deleted file mode 100644
index 79e7113..0000000
--- a/valgrind-3.14.0-memcheck-new-IROps.patch
+++ /dev/null
@@ -1,453 +0,0 @@
-commit e221eca26be6b2396e3fcbf4117e630fc22e79f6
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 11:28:42 2018 +0100
-
- Add Memcheck support for IROps added in 42719898.
-
- memcheck/mc_translate.c:
-
- Add mkRight{32,64} as right-travelling analogues to mkLeft{32,64}.
-
- doCmpORD: for the cases of a signed comparison against zero, compute
- definedness of the 3 result bits (lt,gt,eq) separately, and, for the lt and eq
- bits, do it exactly accurately.
-
- expensiveCountTrailingZeroes: no functional change. Re-analyse/verify and add
- comments.
-
- expensiveCountLeadingZeroes: add. Very similar to
- expensiveCountTrailingZeroes.
-
- Add some comments to mark unary ops which are self-shadowing.
-
- Route Iop_Ctz{,Nat}{32,64} through expensiveCountTrailingZeroes.
- Route Iop_Clz{,Nat}{32,64} through expensiveCountLeadingZeroes.
-
- Add instrumentation for Iop_PopCount{32,64} and Iop_Reverse8sIn32_x1.
-
- memcheck/tests/vbit-test/irops.c
-
- Add dummy new entries for all new IROps, just enough to make it compile and
- run.
-
-diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
-index 68a2ab3..c24db91 100644
---- a/memcheck/mc_translate.c
-+++ b/memcheck/mc_translate.c
-@@ -737,6 +737,34 @@ static IRAtom* mkLeft64 ( MCEnv* mce, IRAtom* a1 ) {
- return assignNew('V', mce, Ity_I64, unop(Iop_Left64, a1));
- }
-
-+/* --------- The Right-family of operations. --------- */
-+
-+/* Unfortunately these are a lot more expensive then their Left
-+ counterparts. Fortunately they are only very rarely used -- only for
-+ count-leading-zeroes instrumentation. */
-+
-+static IRAtom* mkRight32 ( MCEnv* mce, IRAtom* a1 )
-+{
-+ for (Int i = 1; i <= 16; i *= 2) {
-+ // a1 |= (a1 >>u i)
-+ IRAtom* tmp
-+ = assignNew('V', mce, Ity_I32, binop(Iop_Shr32, a1, mkU8(i)));
-+ a1 = assignNew('V', mce, Ity_I32, binop(Iop_Or32, a1, tmp));
-+ }
-+ return a1;
-+}
-+
-+static IRAtom* mkRight64 ( MCEnv* mce, IRAtom* a1 )
-+{
-+ for (Int i = 1; i <= 32; i *= 2) {
-+ // a1 |= (a1 >>u i)
-+ IRAtom* tmp
-+ = assignNew('V', mce, Ity_I64, binop(Iop_Shr64, a1, mkU8(i)));
-+ a1 = assignNew('V', mce, Ity_I64, binop(Iop_Or64, a1, tmp));
-+ }
-+ return a1;
-+}
-+
- /* --------- 'Improvement' functions for AND/OR. --------- */
-
- /* ImproveAND(data, vbits) = data OR vbits. Defined (0) data 0s give
-@@ -1280,20 +1308,18 @@ static IRAtom* doCmpORD ( MCEnv* mce,
- IRAtom* xxhash, IRAtom* yyhash,
- IRAtom* xx, IRAtom* yy )
- {
-- Bool m64 = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD64U;
-- Bool syned = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD32S;
-- IROp opOR = m64 ? Iop_Or64 : Iop_Or32;
-- IROp opAND = m64 ? Iop_And64 : Iop_And32;
-- IROp opSHL = m64 ? Iop_Shl64 : Iop_Shl32;
-- IROp opSHR = m64 ? Iop_Shr64 : Iop_Shr32;
-- IRType ty = m64 ? Ity_I64 : Ity_I32;
-- Int width = m64 ? 64 : 32;
-+ Bool m64 = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD64U;
-+ Bool syned = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD32S;
-+ IROp opOR = m64 ? Iop_Or64 : Iop_Or32;
-+ IROp opAND = m64 ? Iop_And64 : Iop_And32;
-+ IROp opSHL = m64 ? Iop_Shl64 : Iop_Shl32;
-+ IROp opSHR = m64 ? Iop_Shr64 : Iop_Shr32;
-+ IROp op1UtoWS = m64 ? Iop_1Uto64 : Iop_1Uto32;
-+ IRType ty = m64 ? Ity_I64 : Ity_I32;
-+ Int width = m64 ? 64 : 32;
-
- Bool (*isZero)(IRAtom*) = m64 ? isZeroU64 : isZeroU32;
-
-- IRAtom* threeLeft1 = NULL;
-- IRAtom* sevenLeft1 = NULL;
--
- tl_assert(isShadowAtom(mce,xxhash));
- tl_assert(isShadowAtom(mce,yyhash));
- tl_assert(isOriginalAtom(mce,xx));
-@@ -1312,30 +1338,55 @@ static IRAtom* doCmpORD ( MCEnv* mce,
- /* fancy interpretation */
- /* if yy is zero, then it must be fully defined (zero#). */
- tl_assert(isZero(yyhash));
-- threeLeft1 = m64 ? mkU64(3<<1) : mkU32(3<<1);
-+ // This is still inaccurate, but I don't think it matters, since
-+ // nobody writes code of the form
-+ // "is <partially-undefined-value> signedly greater than zero?".
-+ // We therefore simply declare "x >s 0" to be undefined if any bit in
-+ // x is undefined. That's clearly suboptimal in some cases. Eg, if
-+ // the highest order bit is a defined 1 then x is negative so it
-+ // doesn't matter whether the remaining bits are defined or not.
-+ IRAtom* t_0_gt_0_0
-+ = assignNew(
-+ 'V', mce,ty,
-+ binop(
-+ opAND,
-+ mkPCastTo(mce,ty, xxhash),
-+ m64 ? mkU64(1<<2) : mkU32(1<<2)
-+ ));
-+ // For "x <s 0", we can just copy the definedness of the top bit of x
-+ // and we have a precise result.
-+ IRAtom* t_lt_0_0_0
-+ = assignNew(
-+ 'V', mce,ty,
-+ binop(
-+ opSHL,
-+ assignNew(
-+ 'V', mce,ty,
-+ binop(opSHR, xxhash, mkU8(width-1))),
-+ mkU8(3)
-+ ));
-+ // For "x == 0" we can hand the problem off to expensiveCmpEQorNE.
-+ IRAtom* t_0_0_eq_0
-+ = assignNew(
-+ 'V', mce,ty,
-+ binop(
-+ opSHL,
-+ assignNew('V', mce,ty,
-+ unop(
-+ op1UtoWS,
-+ expensiveCmpEQorNE(mce, ty, xxhash, yyhash, xx, yy))
-+ ),
-+ mkU8(1)
-+ ));
- return
- binop(
- opOR,
-- assignNew(
-- 'V', mce,ty,
-- binop(
-- opAND,
-- mkPCastTo(mce,ty, xxhash),
-- threeLeft1
-- )),
-- assignNew(
-- 'V', mce,ty,
-- binop(
-- opSHL,
-- assignNew(
-- 'V', mce,ty,
-- binop(opSHR, xxhash, mkU8(width-1))),
-- mkU8(3)
-- ))
-- );
-+ assignNew('V', mce,ty, binop(opOR, t_lt_0_0_0, t_0_gt_0_0)),
-+ t_0_0_eq_0
-+ );
- } else {
- /* standard interpretation */
-- sevenLeft1 = m64 ? mkU64(7<<1) : mkU32(7<<1);
-+ IRAtom* sevenLeft1 = m64 ? mkU64(7<<1) : mkU32(7<<1);
- return
- binop(
- opAND,
-@@ -2211,14 +2262,14 @@ IRAtom* expensiveCountTrailingZeroes ( MCEnv* mce, IROp czop,
- tl_assert(sameKindedAtoms(atom,vatom));
-
- switch (czop) {
-- case Iop_Ctz32:
-+ case Iop_Ctz32: case Iop_CtzNat32:
- ty = Ity_I32;
- xorOp = Iop_Xor32;
- subOp = Iop_Sub32;
- andOp = Iop_And32;
- one = mkU32(1);
- break;
-- case Iop_Ctz64:
-+ case Iop_Ctz64: case Iop_CtzNat64:
- ty = Ity_I64;
- xorOp = Iop_Xor64;
- subOp = Iop_Sub64;
-@@ -2232,8 +2283,30 @@ IRAtom* expensiveCountTrailingZeroes ( MCEnv* mce, IROp czop,
-
- // improver = atom ^ (atom - 1)
- //
-- // That is, improver has its low ctz(atom) bits equal to one;
-- // higher bits (if any) equal to zero.
-+ // That is, improver has its low ctz(atom)+1 bits equal to one;
-+ // higher bits (if any) equal to zero. So it's exactly the right
-+ // mask to use to remove the irrelevant undefined input bits.
-+ /* Here are some examples:
-+ atom = U...U 1 0...0
-+ atom-1 = U...U 0 1...1
-+ ^ed = 0...0 1 11111, which correctly describes which bits of |atom|
-+ actually influence the result
-+ A boundary case
-+ atom = 0...0
-+ atom-1 = 1...1
-+ ^ed = 11111, also a correct mask for the input: all input bits
-+ are relevant
-+ Another boundary case
-+ atom = 1..1 1
-+ atom-1 = 1..1 0
-+ ^ed = 0..0 1, also a correct mask: only the rightmost input bit
-+ is relevant
-+ Now with misc U bits interspersed:
-+ atom = U...U 1 0 U...U 0 1 0...0
-+ atom-1 = U...U 1 0 U...U 0 0 1...1
-+ ^ed = 0...0 0 0 0...0 0 1 1...1, also correct
-+ (Per re-check/analysis of 14 Nov 2018)
-+ */
- improver = assignNew('V', mce,ty,
- binop(xorOp,
- atom,
-@@ -2242,8 +2315,96 @@ IRAtom* expensiveCountTrailingZeroes ( MCEnv* mce, IROp czop,
-
- // improved = vatom & improver
- //
-- // That is, treat any V bits above the first ctz(atom) bits as
-- // "defined".
-+ // That is, treat any V bits to the left of the rightmost ctz(atom)+1
-+ // bits as "defined".
-+ improved = assignNew('V', mce, ty,
-+ binop(andOp, vatom, improver));
-+
-+ // Return pessimizing cast of improved.
-+ return mkPCastTo(mce, ty, improved);
-+}
-+
-+static
-+IRAtom* expensiveCountLeadingZeroes ( MCEnv* mce, IROp czop,
-+ IRAtom* atom, IRAtom* vatom )
-+{
-+ IRType ty;
-+ IROp shrOp, notOp, andOp;
-+ IRAtom* (*mkRight)(MCEnv*, IRAtom*);
-+ IRAtom *improver, *improved;
-+ tl_assert(isShadowAtom(mce,vatom));
-+ tl_assert(isOriginalAtom(mce,atom));
-+ tl_assert(sameKindedAtoms(atom,vatom));
-+
-+ switch (czop) {
-+ case Iop_Clz32: case Iop_ClzNat32:
-+ ty = Ity_I32;
-+ shrOp = Iop_Shr32;
-+ notOp = Iop_Not32;
-+ andOp = Iop_And32;
-+ mkRight = mkRight32;
-+ break;
-+ case Iop_Clz64: case Iop_ClzNat64:
-+ ty = Ity_I64;
-+ shrOp = Iop_Shr64;
-+ notOp = Iop_Not64;
-+ andOp = Iop_And64;
-+ mkRight = mkRight64;
-+ break;
-+ default:
-+ ppIROp(czop);
-+ VG_(tool_panic)("memcheck:expensiveCountLeadingZeroes");
-+ }
-+
-+ // This is in principle very similar to how expensiveCountTrailingZeroes
-+ // works. That function computed an "improver", which it used to mask
-+ // off all but the rightmost 1-bit and the zeroes to the right of it,
-+ // hence removing irrelevant bits from the input. Here, we play the
-+ // exact same game but with the left-vs-right roles interchanged.
-+ // Unfortunately calculation of the improver in this case is
-+ // significantly more expensive.
-+ //
-+ // improver = ~(RIGHT(atom) >>u 1)
-+ //
-+ // That is, improver has its upper clz(atom)+1 bits equal to one;
-+ // lower bits (if any) equal to zero. So it's exactly the right
-+ // mask to use to remove the irrelevant undefined input bits.
-+ /* Here are some examples:
-+ atom = 0...0 1 U...U
-+ R(atom) = 0...0 1 1...1
-+ R(atom) >>u 1 = 0...0 0 1...1
-+ ~(R(atom) >>u 1) = 1...1 1 0...0
-+ which correctly describes which bits of |atom|
-+ actually influence the result
-+ A boundary case
-+ atom = 0...0
-+ R(atom) = 0...0
-+ R(atom) >>u 1 = 0...0
-+ ~(R(atom) >>u 1) = 1...1
-+ also a correct mask for the input: all input bits
-+ are relevant
-+ Another boundary case
-+ atom = 1 1..1
-+ R(atom) = 1 1..1
-+ R(atom) >>u 1 = 0 1..1
-+ ~(R(atom) >>u 1) = 1 0..0
-+ also a correct mask: only the leftmost input bit
-+ is relevant
-+ Now with misc U bits interspersed:
-+ atom = 0...0 1 U...U 0 1 U...U
-+ R(atom) = 0...0 1 1...1 1 1 1...1
-+ R(atom) >>u 1 = 0...0 0 1...1 1 1 1...1
-+ ~(R(atom) >>u 1) = 1...1 1 0...0 0 0 0...0, also correct
-+ (Per initial implementation of 15 Nov 2018)
-+ */
-+ improver = mkRight(mce, atom);
-+ improver = assignNew('V', mce, ty, binop(shrOp, improver, mkU8(1)));
-+ improver = assignNew('V', mce, ty, unop(notOp, improver));
-+
-+ // improved = vatom & improver
-+ //
-+ // That is, treat any V bits to the right of the leftmost clz(atom)+1
-+ // bits as "defined".
- improved = assignNew('V', mce, ty,
- binop(andOp, vatom, improver));
-
-@@ -4705,6 +4866,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_RecipEst32F0x4:
- return unary32F0x4(mce, vatom);
-
-+ // These are self-shadowing.
- case Iop_32UtoV128:
- case Iop_64UtoV128:
- case Iop_Dup8x16:
-@@ -4745,6 +4907,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_MulI128by10Carry:
- case Iop_F16toF64x2:
- case Iop_F64toF16x2:
-+ // FIXME JRS 2018-Nov-15. This is surely not correct!
- return vatom;
-
- case Iop_I32StoF128: /* signed I32 -> F128 */
-@@ -4770,7 +4933,6 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_RoundF64toF64_NegINF:
- case Iop_RoundF64toF64_PosINF:
- case Iop_RoundF64toF64_ZERO:
-- case Iop_Clz64:
- case Iop_D32toD64:
- case Iop_I32StoD64:
- case Iop_I32UtoD64:
-@@ -4785,17 +4947,32 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_D64toD128:
- return mkPCastTo(mce, Ity_I128, vatom);
-
-- case Iop_Clz32:
- case Iop_TruncF64asF32:
- case Iop_NegF32:
- case Iop_AbsF32:
- case Iop_F16toF32:
- return mkPCastTo(mce, Ity_I32, vatom);
-
-- case Iop_Ctz32:
-- case Iop_Ctz64:
-+ case Iop_Ctz32: case Iop_CtzNat32:
-+ case Iop_Ctz64: case Iop_CtzNat64:
- return expensiveCountTrailingZeroes(mce, op, atom, vatom);
-
-+ case Iop_Clz32: case Iop_ClzNat32:
-+ case Iop_Clz64: case Iop_ClzNat64:
-+ return expensiveCountLeadingZeroes(mce, op, atom, vatom);
-+
-+ // PopCount32: this is slightly pessimistic. It is true that the
-+ // result depends on all input bits, so that aspect of the PCast is
-+ // correct. However, regardless of the input, only the lowest 5 bits
-+ // out of the output can ever be undefined. So we could actually
-+ // "improve" the results here by marking the top 27 bits of output as
-+ // defined. A similar comment applies for PopCount64.
-+ case Iop_PopCount32:
-+ return mkPCastTo(mce, Ity_I32, vatom);
-+ case Iop_PopCount64:
-+ return mkPCastTo(mce, Ity_I64, vatom);
-+
-+ // These are self-shadowing.
- case Iop_1Uto64:
- case Iop_1Sto64:
- case Iop_8Uto64:
-@@ -4821,6 +4998,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_V256to64_2: case Iop_V256to64_3:
- return assignNew('V', mce, Ity_I64, unop(op, vatom));
-
-+ // These are self-shadowing.
- case Iop_64to32:
- case Iop_64HIto32:
- case Iop_1Uto32:
-@@ -4830,8 +5008,10 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_16Sto32:
- case Iop_8Sto32:
- case Iop_V128to32:
-+ case Iop_Reverse8sIn32_x1:
- return assignNew('V', mce, Ity_I32, unop(op, vatom));
-
-+ // These are self-shadowing.
- case Iop_8Sto16:
- case Iop_8Uto16:
- case Iop_32to16:
-@@ -4840,6 +5020,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_GetMSBs8x16:
- return assignNew('V', mce, Ity_I16, unop(op, vatom));
-
-+ // These are self-shadowing.
- case Iop_1Uto8:
- case Iop_1Sto8:
- case Iop_16to8:
-@@ -4868,6 +5049,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_Not16:
- case Iop_Not8:
- case Iop_Not1:
-+ // FIXME JRS 2018-Nov-15. This is surely not correct!
- return vatom;
-
- case Iop_CmpNEZ8x8:
-@@ -4929,6 +5111,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
- case Iop_Ctz64x2:
- return mkPCast64x2(mce, vatom);
-
-+ // This is self-shadowing.
- case Iop_PwBitMtxXpose64x2:
- return assignNew('V', mce, Ity_V128, unop(op, vatom));
-
-diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
-index bfd82fc..e8bf67d 100644
---- a/memcheck/tests/vbit-test/irops.c
-+++ b/memcheck/tests/vbit-test/irops.c
-@@ -111,6 +111,12 @@ static irop_t irops[] = {
- { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
- { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
- { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
-+ { DEFOP(Iop_ClzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts
-+ { DEFOP(Iop_ClzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
-+ { DEFOP(Iop_CtzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
-+ { DEFOP(Iop_CtzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
-+ { DEFOP(Iop_PopCount64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
-+ { DEFOP(Iop_PopCount32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
- { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
- { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
- { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
-@@ -336,6 +342,7 @@ static irop_t irops[] = {
- { DEFOP(Iop_Sad8Ux4, UNDEF_UNKNOWN), },
- { DEFOP(Iop_CmpNEZ16x2, UNDEF_UNKNOWN), },
- { DEFOP(Iop_CmpNEZ8x4, UNDEF_UNKNOWN), },
-+ { DEFOP(Iop_Reverse8sIn32_x1, UNDEF_UNKNOWN) },
- /* ------------------ 64-bit SIMD FP ------------------------ */
- { DEFOP(Iop_I32UtoFx2, UNDEF_UNKNOWN), },
- { DEFOP(Iop_I32StoFx2, UNDEF_UNKNOWN), },
diff --git a/valgrind-3.14.0-new-strlen-IROps.patch b/valgrind-3.14.0-new-strlen-IROps.patch
deleted file mode 100644
index d6587d8..0000000
--- a/valgrind-3.14.0-new-strlen-IROps.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-commit 4271989815b5fc933c1e29bc75507c2726dc3738
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 10:52:33 2018 +0100
-
- Add some new IROps to support improved Memcheck analysis of strlen etc.
-
- This is part of the fix for bug 386945. It adds the following IROps, plus
- their supporting type- and printing- fragments:
-
- Iop_Reverse8sIn32_x1: 32-bit byteswap. A fancy name, but it is consistent
- with naming for the other swapping IROps that already exist.
-
- Iop_PopCount64, Iop_PopCount32: population count
-
- Iop_ClzNat64, Iop_ClzNat32, Iop_CtzNat64, Iop_CtzNat32: counting leading and
- trailing zeroes, with "natural" (Nat) semantics for a zero input, meaning, in
- the case of zero input, return the number of bits in the word. These
- functionally overlap with the existing Iop_Clz64, Iop_Clz32, Iop_Ctz64,
- Iop_Ctz32. The existing operations are undefined in case of a zero input.
- Adding these new variants avoids the complexity of having to change the
- declared semantics of the existing operations. Instead they are deprecated
- but still available for use.
-
-diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c
-index 823b6be..3221033 100644
---- a/VEX/priv/ir_defs.c
-+++ b/VEX/priv/ir_defs.c
-@@ -194,6 +194,14 @@ void ppIROp ( IROp op )
- case Iop_Ctz64: vex_printf("Ctz64"); return;
- case Iop_Ctz32: vex_printf("Ctz32"); return;
-
-+ case Iop_ClzNat64: vex_printf("ClzNat64"); return;
-+ case Iop_ClzNat32: vex_printf("ClzNat32"); return;
-+ case Iop_CtzNat64: vex_printf("CtzNat64"); return;
-+ case Iop_CtzNat32: vex_printf("CtzNat32"); return;
-+
-+ case Iop_PopCount64: vex_printf("PopCount64"); return;
-+ case Iop_PopCount32: vex_printf("PopCount32"); return;
-+
- case Iop_CmpLT32S: vex_printf("CmpLT32S"); return;
- case Iop_CmpLE32S: vex_printf("CmpLE32S"); return;
- case Iop_CmpLT32U: vex_printf("CmpLT32U"); return;
-@@ -395,6 +403,7 @@ void ppIROp ( IROp op )
-
- case Iop_CmpNEZ16x2: vex_printf("CmpNEZ16x2"); return;
- case Iop_CmpNEZ8x4: vex_printf("CmpNEZ8x4"); return;
-+ case Iop_Reverse8sIn32_x1: vex_printf("Reverse8sIn32_x1"); return;
-
- case Iop_CmpF64: vex_printf("CmpF64"); return;
-
-@@ -2719,6 +2728,7 @@ void typeOfPrimop ( IROp op,
- UNARY(Ity_I16, Ity_I16);
- case Iop_Not32:
- case Iop_CmpNEZ16x2: case Iop_CmpNEZ8x4:
-+ case Iop_Reverse8sIn32_x1:
- UNARY(Ity_I32, Ity_I32);
-
- case Iop_Not64:
-@@ -2782,9 +2792,13 @@ void typeOfPrimop ( IROp op,
- BINARY(Ity_I64,Ity_I64, Ity_I128);
-
- case Iop_Clz32: case Iop_Ctz32:
-+ case Iop_ClzNat32: case Iop_CtzNat32:
-+ case Iop_PopCount32:
- UNARY(Ity_I32, Ity_I32);
-
- case Iop_Clz64: case Iop_Ctz64:
-+ case Iop_ClzNat64: case Iop_CtzNat64:
-+ case Iop_PopCount64:
- UNARY(Ity_I64, Ity_I64);
-
- case Iop_DivU32: case Iop_DivS32: case Iop_DivU32E: case Iop_DivS32E:
-diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
-index 17bcb55..93fa5ac 100644
---- a/VEX/pub/libvex_ir.h
-+++ b/VEX/pub/libvex_ir.h
-@@ -452,12 +452,21 @@ typedef
- Iop_MullS8, Iop_MullS16, Iop_MullS32, Iop_MullS64,
- Iop_MullU8, Iop_MullU16, Iop_MullU32, Iop_MullU64,
-
-- /* Wierdo integer stuff */
-+ /* Counting bits */
-+ /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of zero.
-+ You must ensure they are never given a zero argument. As of
-+ 2018-Nov-14 they are deprecated. Try to use the Nat variants
-+ immediately below, if you can.
-+ */
- Iop_Clz64, Iop_Clz32, /* count leading zeroes */
- Iop_Ctz64, Iop_Ctz32, /* count trailing zeros */
-- /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of
-- zero. You must ensure they are never given a zero argument.
-- */
-+ /* Count leading/trailing zeroes, with "natural" semantics for the
-+ case where the input is zero: then the result is the number of bits
-+ in the word. */
-+ Iop_ClzNat64, Iop_ClzNat32,
-+ Iop_CtzNat64, Iop_CtzNat32,
-+ /* Population count -- compute the number of 1 bits in the argument. */
-+ Iop_PopCount64, Iop_PopCount32,
-
- /* Standard integer comparisons */
- Iop_CmpLT32S, Iop_CmpLT64S,
-@@ -831,6 +840,9 @@ typedef
- /* MISC (vector integer cmp != 0) */
- Iop_CmpNEZ16x2, Iop_CmpNEZ8x4,
-
-+ /* Byte swap in a 32-bit word */
-+ Iop_Reverse8sIn32_x1,
-+
- /* ------------------ 64-bit SIMD FP ------------------------ */
-
- /* Convertion to/from int */
-@@ -1034,8 +1046,9 @@ typedef
- Iop_Slice64, // (I64, I64, I8) -> I64
-
- /* REVERSE the order of chunks in vector lanes. Chunks must be
-- smaller than the vector lanes (obviously) and so may be 8-,
-- 16- and 32-bit in size. */
-+ smaller than the vector lanes (obviously) and so may be 8-, 16- and
-+ 32-bit in size. Note that the degenerate case,
-+ Iop_Reverse8sIn64_x1, is a simply a vanilla byte-swap. */
- /* Examples:
- Reverse8sIn16_x4([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
- Reverse8sIn32_x2([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e]
diff --git a/valgrind-3.14.0-pkglibexecdir.patch b/valgrind-3.14.0-pkglibexecdir.patch
deleted file mode 100644
index cd52729..0000000
--- a/valgrind-3.14.0-pkglibexecdir.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-diff --git a/Makefile.all.am b/Makefile.all.am
-index 3786e34..1befef5 100644
---- a/Makefile.all.am
-+++ b/Makefile.all.am
-@@ -50,20 +50,20 @@ inplace-noinst_DSYMS: build-noinst_DSYMS
- done
-
- # This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
--# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
-+# "make install". It copies $(noinst_PROGRAMS) into $prefix/libexec/valgrind/.
- # It needs to be depended on by an 'install-exec-local' rule.
- install-noinst_PROGRAMS: $(noinst_PROGRAMS)
-- $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
-+ $(mkinstalldirs) $(DESTDIR)$(pkglibexecdir); \
- for f in $(noinst_PROGRAMS); do \
-- $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
-+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibexecdir); \
- done
-
- # This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
--# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
-+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/libexec/valgrind/.
- # It needs to be depended on by an 'uninstall-local' rule.
- uninstall-noinst_PROGRAMS:
- for f in $(noinst_PROGRAMS); do \
-- rm -f $(DESTDIR)$(pkglibdir)/$$f; \
-+ rm -f $(DESTDIR)$(pkglibexecdir)/$$f; \
- done
-
- # Similar to install-noinst_PROGRAMS.
-@@ -71,15 +71,15 @@ uninstall-noinst_PROGRAMS:
- # directories. XXX: not sure whether the resulting permissions will be
- # correct when using 'cp -R'...
- install-noinst_DSYMS: build-noinst_DSYMS
-- $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
-+ $(mkinstalldirs) $(DESTDIR)$(pkglibexecdir); \
- for f in $(noinst_DSYMS); do \
-- cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
-+ cp -R $$f.dSYM $(DESTDIR)$(pkglibexecdir); \
- done
-
- # Similar to uninstall-noinst_PROGRAMS.
- uninstall-noinst_DSYMS:
- for f in $(noinst_DSYMS); do \
-- rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
-+ rm -f $(DESTDIR)$(pkglibexecdir)/$$f.dSYM; \
- done
-
- # This needs to be depended on by a 'clean-local' rule.
-diff --git a/Makefile.am b/Makefile.am
-index 242b38a..3b7c806 100644
---- a/Makefile.am
-+++ b/Makefile.am
-@@ -58,7 +58,7 @@ DEFAULT_SUPP_FILES = @DEFAULT_SUPP@
- # default.supp, as it is built from the base .supp files at compile-time.
- dist_noinst_DATA = $(SUPP_FILES)
-
--vglibdir = $(pkglibdir)
-+vglibdir = $(pkglibexecdir)
- vglib_DATA = default.supp
-
- pkgconfigdir = $(libdir)/pkgconfig
-diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am
-index 94030fd..f09763a 100644
---- a/coregrind/Makefile.am
-+++ b/coregrind/Makefile.am
-@@ -11,12 +11,12 @@ include $(top_srcdir)/Makefile.all.am
-
- AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ += \
- -I$(top_srcdir)/coregrind \
-- -DVG_LIBDIR="\"$(pkglibdir)"\" \
-+ -DVG_LIBDIR="\"$(pkglibexecdir)"\" \
- -DVG_PLATFORM="\"@VGCONF_ARCH_PRI@-@VGCONF_OS@\""
- if VGCONF_HAVE_PLATFORM_SEC
- AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ += \
- -I$(top_srcdir)/coregrind \
-- -DVG_LIBDIR="\"$(pkglibdir)"\" \
-+ -DVG_LIBDIR="\"$(pkglibexecdir)"\" \
- -DVG_PLATFORM="\"@VGCONF_ARCH_SEC@-@VGCONF_OS@\""
- endif
-
-@@ -714,7 +714,7 @@ GDBSERVER_XML_FILES = \
- m_gdbserver/mips64-fpu.xml
-
- # so as to make sure these get copied into the install tree
--vglibdir = $(pkglibdir)
-+vglibdir = $(pkglibexecdir)
- vglib_DATA = $(GDBSERVER_XML_FILES)
-
- # so as to make sure these get copied into the tarball
-diff --git a/mpi/Makefile.am b/mpi/Makefile.am
-index 7ad9a25..471fee0 100644
---- a/mpi/Makefile.am
-+++ b/mpi/Makefile.am
-@@ -18,16 +18,18 @@ EXTRA_DIST = \
- # libmpiwrap-<platform>.so
- #----------------------------------------------------------------------------
-
--noinst_PROGRAMS =
-+# These are really real libraries, so they should go to libdir, not libexec.
-+mpidir = $(pkglibdir)
-+mpi_PROGRAMS =
- if BUILD_MPIWRAP_PRI
--noinst_PROGRAMS += libmpiwrap-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so
-+mpi_PROGRAMS += libmpiwrap-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so
- endif
- if BUILD_MPIWRAP_SEC
--noinst_PROGRAMS += libmpiwrap-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
-+mpi_PROGRAMS += libmpiwrap-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
- endif
-
- if VGCONF_OS_IS_DARWIN
--noinst_DSYMS = $(noinst_PROGRAMS)
-+mpi_DSYMS = $(mpi_PROGRAMS)
- endif
-
-
diff --git a/valgrind-3.14.0-power9-addex.patch b/valgrind-3.14.0-power9-addex.patch
deleted file mode 100644
index 1b8d9f2..0000000
--- a/valgrind-3.14.0-power9-addex.patch
+++ /dev/null
@@ -1,256 +0,0 @@
-From 2c1f016e634bf79faf45e81c14c955c711bc202f Mon Sep 17 00:00:00 2001
-From: Mark Wielaard <mark@klomp.org>
-Date: Mon, 31 Dec 2018 22:26:31 +0100
-Subject: [PATCH] Bug 402519 - POWER 3.0 addex instruction incorrectly
- implemented
-
-addex uses OV as carry in and carry out. For all other instructions
-OV is the signed overflow flag. And instructions like adde use CA
-as carry.
-
-Replace set_XER_OV_OV32 with set_XER_OV_OV32_ADDEX, which will
-call calculate_XER_CA_64 and calculate_XER_CA_32, but with OV
-as input, and sets OV and OV32.
-
-Enable test_addex in none/tests/ppc64/test_isa_3_0.c and update
-the expected output. test_addex would fail to match the expected
-output before this patch.
----
- NEWS | 1 +
- VEX/priv/guest_ppc_toIR.c | 52 ++++++++++++++---------
- none/tests/ppc64/test_isa_3_0.c | 3 +-
- none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE | 36 ++++++++++------
- 4 files changed, 58 insertions(+), 34 deletions(-)
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 18df822..d685383 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -2645,21 +2645,6 @@ static void copy_OV_to_OV32( void ) {
- putXER_OV32( getXER_OV() );
- }
-
--static void set_XER_OV_OV32 ( IRType ty, UInt op, IRExpr* res,
-- IRExpr* argL, IRExpr* argR )
--{
-- if (ty == Ity_I32) {
-- set_XER_OV_OV32_32( op, res, argL, argR );
-- } else {
-- IRExpr* xer_ov_32;
-- set_XER_OV_64( op, res, argL, argR );
-- xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
-- unop(Iop_64to32, argL),
-- unop(Iop_64to32, argR));
-- putXER_OV32( unop(Iop_32to8, xer_ov_32) );
-- }
--}
--
- static void set_XER_OV_OV32_SO ( IRType ty, UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
- {
-@@ -3005,6 +2990,33 @@ static void set_XER_CA_CA32 ( IRType ty, UInt op, IRExpr* res,
- }
- }
-
-+/* Used only by addex instruction, which uses and sets OV as carry. */
-+static void set_XER_OV_OV32_ADDEX ( IRType ty, IRExpr* res,
-+ IRExpr* argL, IRExpr* argR,
-+ IRExpr* old_ov )
-+{
-+ if (ty == Ity_I32) {
-+ IRTemp xer_ov = newTemp(Ity_I32);
-+ assign ( xer_ov, unop(Iop_32to8,
-+ calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
-+ res, argL, argR, old_ov ) ) );
-+ putXER_OV( mkexpr (xer_ov) );
-+ putXER_OV32( mkexpr (xer_ov) );
-+ } else {
-+ IRExpr *xer_ov;
-+ IRExpr* xer_ov_32;
-+ xer_ov = calculate_XER_CA_64( PPCG_FLAG_OP_ADDE,
-+ res, argL, argR, old_ov );
-+ putXER_OV( unop(Iop_32to8, xer_ov) );
-+ xer_ov_32 = calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
-+ unop(Iop_64to32, res),
-+ unop(Iop_64to32, argL),
-+ unop(Iop_64to32, argR),
-+ unop(Iop_64to32, old_ov) );
-+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
-+ }
-+}
-+
-
-
- /*------------------------------------------------------------*/
-@@ -5094,16 +5106,18 @@ static Bool dis_int_arith ( UInt theInstr )
- }
-
- case 0xAA: {// addex (Add Extended alternate carry bit Z23-form)
-+ IRTemp old_xer_ov = newTemp(ty);
- DIP("addex r%u,r%u,r%u,%d\n", rD_addr, rA_addr, rB_addr, (Int)flag_OE);
-+ assign( old_xer_ov, mkWidenFrom32(ty, getXER_OV_32(), False) );
- assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
- binop( mkSzOp(ty, Iop_Add8), mkexpr(rB),
-- mkWidenFrom8( ty, getXER_OV(), False ) ) ) );
-+ mkexpr(old_xer_ov) ) ) );
-
- /* CY bit is same as OE bit */
- if (flag_OE == 0) {
-- /* Exception, do not set SO bit */
-- set_XER_OV_OV32( ty, PPCG_FLAG_OP_ADDE,
-- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
-+ /* Exception, do not set SO bit and set OV from carry. */
-+ set_XER_OV_OV32_ADDEX( ty, mkexpr(rD), mkexpr(rA), mkexpr(rB),
-+ mkexpr(old_xer_ov) );
- } else {
- /* CY=1, 2 and 3 (AKA flag_OE) are reserved */
- vex_printf("addex instruction, CY = %d is reserved.\n", flag_OE);
-diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
-index 2d13505..1c2cda3 100644
---- a/none/tests/ppc64/test_isa_3_0.c
-+++ b/none/tests/ppc64/test_isa_3_0.c
-@@ -286,7 +286,7 @@ static test_list_t testgroup_ia_ops_two[] = {
- { &test_moduw, "moduw" },
- { &test_modsd, "modsd" },
- { &test_modud, "modud" },
-- //{ &test_addex, "addex" },
-+ { &test_addex, "addex" },
- { NULL , NULL },
- };
-
-@@ -2741,7 +2741,6 @@ static void testfunction_gpr_vector_logical_one (const char* instruction_name,
- * rt, xa
- */
- int i;
-- int t;
- volatile HWord_t res;
-
- VERBOSE_FUNCTION_CALLOUT
-diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
-index 152ff28..cc0e88e 100644
---- a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
-+++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
-@@ -40,7 +40,17 @@ modud ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
- modud ffffffffffffffff, 0000001cbe991def => 000000043eb0c0b2 (00000000)
- modud ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
-
--All done. Tested 4 different instructions
-+addex 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
-+addex 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
-+addex 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
-+addex 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000)
-+addex 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000) OV32
-+addex 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000) OV OV32
-+addex ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000) OV OV32
-+addex ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000) OV OV32
-+addex ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000) OV OV32
-+
-+All done. Tested 5 different instructions
- ppc one argument plus shift:
- Test instruction group [ppc one argument plus shift]
- extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
-@@ -85,7 +95,7 @@ extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaa
- extswsli. 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
- extswsli. 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
-
--All done. Tested 6 different instructions
-+All done. Tested 7 different instructions
- ppc three parameter ops:
- Test instruction group [ppc three parameter ops]
- maddhd 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
-@@ -172,7 +182,7 @@ maddld ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 000000000000000
- maddld ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000)
- maddld ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
-
--All done. Tested 9 different instructions
-+All done. Tested 10 different instructions
- ppc count zeros:
- Test instruction group [ppc count zeros]
- cnttzw 0000000000000000 => 0000000000000020
-@@ -197,7 +207,7 @@ cnttzd. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (200
- cnttzd. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
-
-
--All done. Tested 13 different instructions
-+All done. Tested 14 different instructions
- ppc set boolean:
- Test instruction group [ppc set boolean]
- setb cr_field:0 cr_value::00000000 => 0000000000000000
-@@ -265,7 +275,7 @@ setb cr_field:7 cr_value::00000005 => 0000000000000001
- setb cr_field:7 cr_value::00000006 => 0000000000000001
- setb cr_field:7 cr_value::00000007 => 0000000000000001
-
--All done. Tested 14 different instructions
-+All done. Tested 15 different instructions
- ppc char compare:
- Test instruction group [ppc char compare]
- cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
-@@ -1711,7 +1721,7 @@ cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
- cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
- cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
-
--All done. Tested 17 different instructions
-+All done. Tested 18 different instructions
- ppc vector scalar move to/from:
- Test instruction group [ppc vector scalar move to/from]
- mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
-@@ -1777,7 +1787,7 @@ mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 113377cc113377cc
- mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
- mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
-
--All done. Tested 20 different instructions
-+All done. Tested 21 different instructions
- ppc dfp significance:
- Test instruction group [ppc dfp significance]
- dtstsfi significance(0x00) +Finite 0 * 10 ^ -12 (GT) (4)
-@@ -1862,7 +1872,7 @@ dtstsfiq significance(0x20) -inf (GT) (4)
- dtstsfiq significance(0x30) -inf (GT) (4)
- dtstsfiq significance(0x3f) -inf (GT) (4)
-
--All done. Tested 22 different instructions
-+All done. Tested 23 different instructions
- ppc bcd misc:
- Test instruction group [ppc bcd misc]
- bcdadd. p0 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000000000000c (+|0) => (EQ) (2) xt:0000000000000000 000000000000000c(+|0)
-@@ -33338,12 +33348,12 @@ bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:9999999999999999 99999
- bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000001234567d ( - ) => (GT) (4) xt:0000000000000000 000000305419901f(+|0)
-
-
--All done. Tested 51 different instructions
-+All done. Tested 52 different instructions
- ppc noop misc:
- Test instruction group [ppc noop misc]
- wait =>
-
--All done. Tested 52 different instructions
-+All done. Tested 53 different instructions
- ppc addpc_misc:
- Test instruction group [ppc addpc_misc]
- addpcis 0000000000000000 => 0000000000000000
-@@ -33380,7 +33390,7 @@ subpcis 000000000000000d => 0000000000000000
- subpcis 000000000000000e => 0000000000000000
- subpcis 000000000000000f => 0000000000000000
-
--All done. Tested 54 different instructions
-+All done. Tested 55 different instructions
- ppc mffpscr:
- Test instruction group [ppc mffpscr]
- mffsce => 000000000.000000
-@@ -33395,7 +33405,7 @@ mffs => 000000000.000000
- fpscr: f14
- local_fpscr:
-
--All done. Tested 57 different instructions
-+All done. Tested 58 different instructions
- ppc mffpscr:
- Test instruction group [ppc mffpscr]
- mffscdrni 0 => 0X0
-@@ -33426,4 +33436,4 @@ mffscrn f15 0X1 => 0X200000000
- mffscrn f15 0X2 => 0X200000000
- fpscr: f14 local_fpscr: 30-DRN1 RN-bit62
-
--All done. Tested 61 different instructions
-+All done. Tested 62 different instructions
---
-1.8.3.1
-
diff --git a/valgrind-3.14.0-ppc-frontend-new-IROps.patch b/valgrind-3.14.0-ppc-frontend-new-IROps.patch
deleted file mode 100644
index a550975..0000000
--- a/valgrind-3.14.0-ppc-frontend-new-IROps.patch
+++ /dev/null
@@ -1,381 +0,0 @@
-commit 81d9832226d6e3d1ee78ee3133189d7b520e7eea
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 11:36:53 2018 +0100
-
- ppc front end: use new IROps added in 42719898.
-
- This pertains to bug 386945.
-
- VEX/priv/guest_ppc_toIR.c:
-
- gen_POPCOUNT: use Iop_PopCount{32,64} where possible.
-
- gen_vpopcntd_mode32: use Iop_PopCount32.
-
- for cntlz{w,d}, use Iop_CtzNat{32,64}.
-
- gen_byterev32: use Iop_Reverse8sIn32_x1 instead of lengthy sequence.
-
- verbose_Clz32: remove (was unused anyway).
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index cb1cae1..8977d4f 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -1595,7 +1595,8 @@ typedef enum {
- /* Generate an IR sequence to do a popcount operation on the supplied
- IRTemp, and return a new IRTemp holding the result. 'ty' may be
- Ity_I32 or Ity_I64 only. */
--static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_type )
-+static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src,
-+ _popcount_data_type data_type )
- {
- /* Do count across 2^data_type bits,
- byte: data_type = 3
-@@ -1611,6 +1612,22 @@ static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_typ
-
- vassert(ty == Ity_I64 || ty == Ity_I32);
-
-+ // Use a single IROp in cases where we can.
-+
-+ if (ty == Ity_I64 && data_type == DWORD) {
-+ IRTemp res = newTemp(Ity_I64);
-+ assign(res, unop(Iop_PopCount64, mkexpr(src)));
-+ return res;
-+ }
-+
-+ if (ty == Ity_I32 && data_type == WORD) {
-+ IRTemp res = newTemp(Ity_I32);
-+ assign(res, unop(Iop_PopCount32, mkexpr(src)));
-+ return res;
-+ }
-+
-+ // For the rest, we have to do it the slow way.
-+
- if (ty == Ity_I32) {
-
- for (idx = 0; idx < WORD; idx++) {
-@@ -1638,7 +1655,7 @@ static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_typ
- return nyu;
- }
-
--// else, ty == Ity_I64
-+ // else, ty == Ity_I64
- vassert(mode64);
-
- for (i = 0; i < DWORD; i++) {
-@@ -1670,52 +1687,15 @@ static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_typ
- */
- static IRTemp gen_vpopcntd_mode32 ( IRTemp src1, IRTemp src2 )
- {
-- Int i, shift[6];
-- IRTemp mask[6];
-- IRTemp old = IRTemp_INVALID;
-- IRTemp nyu1 = IRTemp_INVALID;
-- IRTemp nyu2 = IRTemp_INVALID;
- IRTemp retval = newTemp(Ity_I64);
-
- vassert(!mode64);
-
-- for (i = 0; i < WORD; i++) {
-- mask[i] = newTemp(Ity_I32);
-- shift[i] = 1 << i;
-- }
-- assign(mask[0], mkU32(0x55555555));
-- assign(mask[1], mkU32(0x33333333));
-- assign(mask[2], mkU32(0x0F0F0F0F));
-- assign(mask[3], mkU32(0x00FF00FF));
-- assign(mask[4], mkU32(0x0000FFFF));
-- old = src1;
-- for (i = 0; i < WORD; i++) {
-- nyu1 = newTemp(Ity_I32);
-- assign(nyu1,
-- binop(Iop_Add32,
-- binop(Iop_And32,
-- mkexpr(old),
-- mkexpr(mask[i])),
-- binop(Iop_And32,
-- binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
-- mkexpr(mask[i]))));
-- old = nyu1;
-- }
--
-- old = src2;
-- for (i = 0; i < WORD; i++) {
-- nyu2 = newTemp(Ity_I32);
-- assign(nyu2,
-- binop(Iop_Add32,
-- binop(Iop_And32,
-- mkexpr(old),
-- mkexpr(mask[i])),
-- binop(Iop_And32,
-- binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
-- mkexpr(mask[i]))));
-- old = nyu2;
-- }
-- assign(retval, unop(Iop_32Uto64, binop(Iop_Add32, mkexpr(nyu1), mkexpr(nyu2))));
-+ assign(retval,
-+ unop(Iop_32Uto64,
-+ binop(Iop_Add32,
-+ unop(Iop_PopCount32, mkexpr(src1)),
-+ unop(Iop_PopCount32, mkexpr(src2)))));
- return retval;
- }
-
-@@ -5715,7 +5695,7 @@ static Bool dis_modulo_int ( UInt theInstr )
- rA_address, rS_address);
-
- assign( rS, getIReg( rS_address ) );
-- assign( result, unop( Iop_Ctz32,
-+ assign( result, unop( Iop_CtzNat32,
- unop( Iop_64to32, mkexpr( rS ) ) ) );
- assign( rA, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( result ) ) );
-
-@@ -5746,7 +5726,7 @@ static Bool dis_modulo_int ( UInt theInstr )
- rA_address, rS_address);
-
- assign( rS, getIReg( rS_address ) );
-- assign( rA, unop( Iop_Ctz64, mkexpr( rS ) ) );
-+ assign( rA, unop( Iop_CtzNat64, mkexpr( rS ) ) );
-
- if ( flag_rC == 1 )
- set_CR0( mkexpr( rA ) );
-@@ -6307,7 +6287,6 @@ static Bool dis_int_logic ( UInt theInstr )
- IRTemp rS = newTemp(ty);
- IRTemp rA = newTemp(ty);
- IRTemp rB = newTemp(ty);
-- IRExpr* irx;
- Bool do_rc = False;
-
- assign( rS, getIReg(rS_addr) );
-@@ -6404,26 +6383,16 @@ static Bool dis_int_logic ( UInt theInstr )
- break;
-
- case 0x01A: { // cntlzw (Count Leading Zeros Word, PPC32 p371)
-- IRExpr* lo32;
- if (rB_addr!=0) {
- vex_printf("dis_int_logic(ppc)(cntlzw,rB_addr)\n");
- return False;
- }
-- DIP("cntlzw%s r%u,r%u\n",
-- flag_rC ? ".":"", rA_addr, rS_addr);
-+ DIP("cntlzw%s r%u,r%u\n", flag_rC ? ".":"", rA_addr, rS_addr);
-
- // mode64: count in low word only
-- lo32 = mode64 ? unop(Iop_64to32, mkexpr(rS)) : mkexpr(rS);
--
-- // Iop_Clz32 undefined for arg==0, so deal with that case:
-- irx = binop(Iop_CmpNE32, lo32, mkU32(0));
-- assign(rA, mkWidenFrom32(ty,
-- IRExpr_ITE( irx,
-- unop(Iop_Clz32, lo32),
-- mkU32(32)),
-- False));
--
-- // TODO: alternatively: assign(rA, verbose_Clz32(rS));
-+ IRExpr* lo32 = mode64 ? unop(Iop_64to32, mkexpr(rS)) : mkexpr(rS);
-+ IRExpr* res32 = unop(Iop_ClzNat32, lo32);
-+ assign(rA, mode64 ? unop(Iop_32Uto64, res32) : res32);
- break;
- }
-
-@@ -6521,14 +6490,8 @@ static Bool dis_int_logic ( UInt theInstr )
- vex_printf("dis_int_logic(ppc)(cntlzd,rB_addr)\n");
- return False;
- }
-- DIP("cntlzd%s r%u,r%u\n",
-- flag_rC ? ".":"", rA_addr, rS_addr);
-- // Iop_Clz64 undefined for arg==0, so deal with that case:
-- irx = binop(Iop_CmpNE64, mkexpr(rS), mkU64(0));
-- assign(rA, IRExpr_ITE( irx,
-- unop(Iop_Clz64, mkexpr(rS)),
-- mkU64(64) ));
-- // TODO: alternatively: assign(rA, verbose_Clz64(rS));
-+ DIP("cntlzd%s r%u,r%u\n", flag_rC ? ".":"", rA_addr, rS_addr);
-+ assign(rA, unop(Iop_ClzNat64, mkexpr(rS)));
- break;
-
- case 0x1FC: // cmpb (Power6: compare bytes)
-@@ -6574,8 +6537,9 @@ static Bool dis_int_logic ( UInt theInstr )
- putFReg( rS_addr, mkexpr(frA));
- return True;
- }
-- case 0x1FA: // popcntd (population count doubleword
-+ case 0x1FA: // popcntd (population count doubleword)
- {
-+ vassert(mode64);
- DIP("popcntd r%u,r%u\n", rA_addr, rS_addr);
- IRTemp result = gen_POPCOUNT(ty, rS, DWORD);
- putIReg( rA_addr, mkexpr(result) );
-@@ -9154,18 +9118,7 @@ static Bool dis_int_shift ( UInt theInstr )
- static IRExpr* /* :: Ity_I32 */ gen_byterev32 ( IRTemp t )
- {
- vassert(typeOfIRTemp(irsb->tyenv, t) == Ity_I32);
-- return
-- binop(Iop_Or32,
-- binop(Iop_Shl32, mkexpr(t), mkU8(24)),
-- binop(Iop_Or32,
-- binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)),
-- mkU32(0x00FF0000)),
-- binop(Iop_Or32,
-- binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(8)),
-- mkU32(0x0000FF00)),
-- binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(24)),
-- mkU32(0x000000FF) )
-- )));
-+ return unop(Iop_Reverse8sIn32_x1, mkexpr(t));
- }
-
- /* Generates code to swap the byte order in the lower half of an Ity_I32,
-@@ -9225,6 +9178,10 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
-
- case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed)
- {
-+ // JRS FIXME:
-+ // * is the host_endness conditional below actually necessary?
-+ // * can we just do a 64-bit load followed by by Iop_Reverse8sIn64_x1?
-+ // That would be a lot more efficient.
- IRExpr * nextAddr;
- IRTemp w3 = newTemp( Ity_I32 );
- IRTemp w4 = newTemp( Ity_I32 );
-@@ -17056,8 +17013,8 @@ dis_av_count_bitTranspose ( UInt theInstr, UInt opc2 )
- case 0x7C3: // vpopcntd
- {
- if (mode64) {
-- /* Break vector into 64-bit double words and do the population count
-- * on each double word.
-+ /* Break vector into 64-bit double words and do the population
-+ count on each double word.
- */
- IRType ty = Ity_I64;
- IRTemp bits0_63 = newTemp(Ity_I64);
-@@ -17077,15 +17034,16 @@ dis_av_count_bitTranspose ( UInt theInstr, UInt opc2 )
- mkexpr( cnt_bits0_63 ) ) );
- } else {
- /* Break vector into 32-bit words and do the population count
-- * on each doubleword.
-+ on each 32-bit word.
- */
- IRTemp bits0_31, bits32_63, bits64_95, bits96_127;
- bits0_31 = bits32_63 = bits64_95 = bits96_127 = IRTemp_INVALID;
-- IRTemp cnt_bits0_63 = newTemp(Ity_I64);
-+ IRTemp cnt_bits0_63 = newTemp(Ity_I64);
- IRTemp cnt_bits64_127 = newTemp(Ity_I64);
-
- DIP("vpopcntd v%d,v%d\n", vRT_addr, vRB_addr);
-- breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95, &bits32_63, &bits0_31 );
-+ breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95,
-+ &bits32_63, &bits0_31 );
-
- cnt_bits0_63 = gen_vpopcntd_mode32(bits0_31, bits32_63);
- cnt_bits64_127 = gen_vpopcntd_mode32(bits64_95, bits96_127);
-@@ -29103,10 +29061,12 @@ DisResult disInstr_PPC_WRK (
-
- /* Miscellaneous ISA 2.06 instructions */
- case 0x1FA: // popcntd
-+ if (!mode64) goto decode_failure;
-+ /* else fallthru */
- case 0x17A: // popcntw
- case 0x7A: // popcntb
-- if (dis_int_logic( theInstr )) goto decode_success;
-- goto decode_failure;
-+ if (dis_int_logic( theInstr )) goto decode_success;
-+ goto decode_failure;
-
- case 0x0FC: // bpermd
- if (!mode64) goto decode_failure;
-@@ -29669,94 +29629,6 @@ DisResult disInstr_PPC ( IRSB* irsb_IN,
- return dres;
- }
-
--
--/*------------------------------------------------------------*/
--/*--- Unused stuff ---*/
--/*------------------------------------------------------------*/
--
--///* A potentially more memcheck-friendly implementation of Clz32, with
--// the boundary case Clz32(0) = 32, which is what ppc requires. */
--//
--//static IRExpr* /* :: Ity_I32 */ verbose_Clz32 ( IRTemp arg )
--//{
--// /* Welcome ... to SSA R Us. */
--// IRTemp n1 = newTemp(Ity_I32);
--// IRTemp n2 = newTemp(Ity_I32);
--// IRTemp n3 = newTemp(Ity_I32);
--// IRTemp n4 = newTemp(Ity_I32);
--// IRTemp n5 = newTemp(Ity_I32);
--// IRTemp n6 = newTemp(Ity_I32);
--// IRTemp n7 = newTemp(Ity_I32);
--// IRTemp n8 = newTemp(Ity_I32);
--// IRTemp n9 = newTemp(Ity_I32);
--// IRTemp n10 = newTemp(Ity_I32);
--// IRTemp n11 = newTemp(Ity_I32);
--// IRTemp n12 = newTemp(Ity_I32);
--//
--// /* First, propagate the most significant 1-bit into all lower
--// positions in the word. */
--// /* unsigned int clz ( unsigned int n )
--// {
--// n |= (n >> 1);
--// n |= (n >> 2);
--// n |= (n >> 4);
--// n |= (n >> 8);
--// n |= (n >> 16);
--// return bitcount(~n);
--// }
--// */
--// assign(n1, mkexpr(arg));
--// assign(n2, binop(Iop_Or32, mkexpr(n1), binop(Iop_Shr32, mkexpr(n1), mkU8(1))));
--// assign(n3, binop(Iop_Or32, mkexpr(n2), binop(Iop_Shr32, mkexpr(n2), mkU8(2))));
--// assign(n4, binop(Iop_Or32, mkexpr(n3), binop(Iop_Shr32, mkexpr(n3), mkU8(4))));
--// assign(n5, binop(Iop_Or32, mkexpr(n4), binop(Iop_Shr32, mkexpr(n4), mkU8(8))));
--// assign(n6, binop(Iop_Or32, mkexpr(n5), binop(Iop_Shr32, mkexpr(n5), mkU8(16))));
--// /* This gives a word of the form 0---01---1. Now invert it, giving
--// a word of the form 1---10---0, then do a population-count idiom
--// (to count the 1s, which is the number of leading zeroes, or 32
--// if the original word was 0. */
--// assign(n7, unop(Iop_Not32, mkexpr(n6)));
--//
--// /* unsigned int bitcount ( unsigned int n )
--// {
--// n = n - ((n >> 1) & 0x55555555);
--// n = (n & 0x33333333) + ((n >> 2) & 0x33333333);
--// n = (n + (n >> 4)) & 0x0F0F0F0F;
--// n = n + (n >> 8);
--// n = (n + (n >> 16)) & 0x3F;
--// return n;
--// }
--// */
--// assign(n8,
--// binop(Iop_Sub32,
--// mkexpr(n7),
--// binop(Iop_And32,
--// binop(Iop_Shr32, mkexpr(n7), mkU8(1)),
--// mkU32(0x55555555))));
--// assign(n9,
--// binop(Iop_Add32,
--// binop(Iop_And32, mkexpr(n8), mkU32(0x33333333)),
--// binop(Iop_And32,
--// binop(Iop_Shr32, mkexpr(n8), mkU8(2)),
--// mkU32(0x33333333))));
--// assign(n10,
--// binop(Iop_And32,
--// binop(Iop_Add32,
--// mkexpr(n9),
--// binop(Iop_Shr32, mkexpr(n9), mkU8(4))),
--// mkU32(0x0F0F0F0F)));
--// assign(n11,
--// binop(Iop_Add32,
--// mkexpr(n10),
--// binop(Iop_Shr32, mkexpr(n10), mkU8(8))));
--// assign(n12,
--// binop(Iop_Add32,
--// mkexpr(n11),
--// binop(Iop_Shr32, mkexpr(n11), mkU8(16))));
--// return
--// binop(Iop_And32, mkexpr(n12), mkU32(0x3F));
--//}
--
- /*--------------------------------------------------------------------*/
- /*--- end guest_ppc_toIR.c ---*/
- /*--------------------------------------------------------------------*/
diff --git a/valgrind-3.14.0-ppc-instr-new-IROps.patch b/valgrind-3.14.0-ppc-instr-new-IROps.patch
deleted file mode 100644
index 4332736..0000000
--- a/valgrind-3.14.0-ppc-instr-new-IROps.patch
+++ /dev/null
@@ -1,257 +0,0 @@
-commit 97d336b79e36f6c99d8b07f49ebc9b780e6df84e
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 11:07:37 2018 +0100
-
- Add ppc host-side isel and instruction support for IROps added in previous commit.
-
- VEX/priv/host_ppc_defs.c, VEX/priv/host_ppc_defs.h:
-
- Dont emit cnttz{w,d}. We may need them on a target which doesn't support
- them. Instead we can generate a fairly reasonable alternative sequence with
- cntlz{w,d} instead.
-
- Add support for emitting popcnt{w,d}.
-
- VEX/priv/host_ppc_isel.c
-
- Add support for: Iop_ClzNat32 Iop_ClzNat64
-
- Redo support for: Iop_Ctz{32,64} and their Nat equivalents, so as to not use
- cnttz{w,d}, as mentioned above.
-
- Add support for: Iop_PopCount64 Iop_PopCount32 Iop_Reverse8sIn32_x1
-
-diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
-index b073c1d..f4b52e4 100644
---- a/VEX/priv/host_ppc_defs.c
-+++ b/VEX/priv/host_ppc_defs.c
-@@ -501,9 +501,9 @@ const HChar* showPPCUnaryOp ( PPCUnaryOp op ) {
- case Pun_NEG: return "neg";
- case Pun_CLZ32: return "cntlzw";
- case Pun_CLZ64: return "cntlzd";
-- case Pun_CTZ32: return "cnttzw";
-- case Pun_CTZ64: return "cnttzd";
- case Pun_EXTSW: return "extsw";
-+ case Pun_POP32: return "popcntw";
-+ case Pun_POP64: return "popcntd";
- default: vpanic("showPPCUnaryOp");
- }
- }
-@@ -4265,20 +4265,19 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
- vassert(mode64);
- p = mkFormX(p, 31, r_src, r_dst, 0, 58, 0, endness_host);
- break;
-- case Pun_CTZ32: // cnttzw r_dst, r_src
-- /* Note oder of src and dst is backwards from normal */
-- p = mkFormX(p, 31, r_src, r_dst, 0, 538, 0, endness_host);
-- break;
-- case Pun_CTZ64: // cnttzd r_dst, r_src
-- /* Note oder of src and dst is backwards from normal */
-- vassert(mode64);
-- p = mkFormX(p, 31, r_src, r_dst, 0, 570, 0, endness_host);
-- break;
- case Pun_EXTSW: // extsw r_dst, r_src
- vassert(mode64);
- p = mkFormX(p, 31, r_src, r_dst, 0, 986, 0, endness_host);
- break;
-- default: goto bad;
-+ case Pun_POP32: // popcntw r_dst, r_src
-+ p = mkFormX(p, 31, r_src, r_dst, 0, 378, 0, endness_host);
-+ break;
-+ case Pun_POP64: // popcntd r_dst, r_src
-+ vassert(mode64);
-+ p = mkFormX(p, 31, r_src, r_dst, 0, 506, 0, endness_host);
-+ break;
-+ default:
-+ goto bad;
- }
- goto done;
- }
-diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h
-index 17baff5..321fba9 100644
---- a/VEX/priv/host_ppc_defs.h
-+++ b/VEX/priv/host_ppc_defs.h
-@@ -291,9 +291,9 @@ typedef
- Pun_NOT,
- Pun_CLZ32,
- Pun_CLZ64,
-- Pun_CTZ32,
-- Pun_CTZ64,
-- Pun_EXTSW
-+ Pun_EXTSW,
-+ Pun_POP32, // popcntw
-+ Pun_POP64 // popcntd
- }
- PPCUnaryOp;
-
-diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
-index 6bdb5f7..5242176 100644
---- a/VEX/priv/host_ppc_isel.c
-+++ b/VEX/priv/host_ppc_isel.c
-@@ -2065,12 +2065,15 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
- return r_dst;
- }
- break;
-- case Iop_Clz32:
-- case Iop_Clz64: {
-+
-+ case Iop_Clz32: case Iop_ClzNat32:
-+ case Iop_Clz64: case Iop_ClzNat64: {
-+ // cntlz is available even in the most basic (earliest) ppc
-+ // variants, so it's safe to generate it unconditionally.
- HReg r_src, r_dst;
-- PPCUnaryOp op_clz = (op_unop == Iop_Clz32) ? Pun_CLZ32 :
-- Pun_CLZ64;
-- if (op_unop == Iop_Clz64 && !mode64)
-+ PPCUnaryOp op_clz = (op_unop == Iop_Clz32 || op_unop == Iop_ClzNat32)
-+ ? Pun_CLZ32 : Pun_CLZ64;
-+ if ((op_unop == Iop_Clz64 || op_unop == Iop_ClzNat64) && !mode64)
- goto irreducible;
- /* Count leading zeroes. */
- r_dst = newVRegI(env);
-@@ -2079,18 +2082,133 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
- return r_dst;
- }
-
-- case Iop_Ctz32:
-- case Iop_Ctz64: {
-- HReg r_src, r_dst;
-- PPCUnaryOp op_clz = (op_unop == Iop_Ctz32) ? Pun_CTZ32 :
-- Pun_CTZ64;
-- if (op_unop == Iop_Ctz64 && !mode64)
-- goto irreducible;
-- /* Count trailing zeroes. */
-- r_dst = newVRegI(env);
-- r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
-- addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
-- return r_dst;
-+ //case Iop_Ctz32:
-+ case Iop_CtzNat32:
-+ //case Iop_Ctz64:
-+ case Iop_CtzNat64:
-+ {
-+ // Generate code using Clz, because we can't assume the host has
-+ // Ctz. In particular, part of the fix for bug 386945 involves
-+ // creating a Ctz in ir_opt.c from smaller fragments.
-+ PPCUnaryOp op_clz = Pun_CLZ64;
-+ Int WS = 64;
-+ if (op_unop == Iop_Ctz32 || op_unop == Iop_CtzNat32) {
-+ op_clz = Pun_CLZ32;
-+ WS = 32;
-+ }
-+ /* Compute ctz(arg) = wordsize - clz(~arg & (arg - 1)), thusly:
-+ t1 = arg - 1
-+ t2 = not arg
-+ t2 = t2 & t1
-+ t2 = clz t2
-+ t1 = WS
-+ t2 = t1 - t2
-+ // result in t2
-+ */
-+ HReg arg = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
-+ HReg t1 = newVRegI(env);
-+ HReg t2 = newVRegI(env);
-+ addInstr(env, PPCInstr_Alu(Palu_SUB, t1, arg, PPCRH_Imm(True, 1)));
-+ addInstr(env, PPCInstr_Unary(Pun_NOT, t2, arg));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, t2, t2, PPCRH_Reg(t1)));
-+ addInstr(env, PPCInstr_Unary(op_clz, t2, t2));
-+ addInstr(env, PPCInstr_LI(t1, WS, False/*!64-bit imm*/));
-+ addInstr(env, PPCInstr_Alu(Palu_SUB, t2, t1, PPCRH_Reg(t2)));
-+ return t2;
-+ }
-+
-+ case Iop_PopCount64: {
-+ // popcnt{x,d} is only available in later arch revs (ISA 3.0,
-+ // maybe) so it's not really correct to emit it here without a caps
-+ // check for the host.
-+ if (mode64) {
-+ HReg r_dst = newVRegI(env);
-+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
-+ addInstr(env, PPCInstr_Unary(Pun_POP64, r_dst, r_src));
-+ return r_dst;
-+ }
-+ // We don't expect to be required to handle this in 32-bit mode.
-+ break;
-+ }
-+
-+ case Iop_PopCount32: {
-+ // Similar comment as for Ctz just above applies -- we really
-+ // should have a caps check here.
-+
-+ HReg r_dst = newVRegI(env);
-+ // This actually generates popcntw, which in 64 bit mode does a
-+ // 32-bit count individually for both low and high halves of the
-+ // word. Per the comment at the top of iselIntExpr_R, in the 64
-+ // bit mode case, the user of this result is required to ignore
-+ // the upper 32 bits of the result. In 32 bit mode this is all
-+ // moot. It is however unclear from the PowerISA 3.0 docs that
-+ // the instruction exists in 32 bit mode; however our own front
-+ // end (guest_ppc_toIR.c) accepts it, so I guess it does exist.
-+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
-+ addInstr(env, PPCInstr_Unary(Pun_POP32, r_dst, r_src));
-+ return r_dst;
-+ }
-+
-+ case Iop_Reverse8sIn32_x1: {
-+ // A bit of a mouthful, but simply .. 32-bit byte swap.
-+ // This is pretty rubbish code. We could do vastly better if
-+ // rotates, and better, rotate-inserts, were allowed. Note that
-+ // even on a 64 bit target, the right shifts must be done as 32-bit
-+ // so as to introduce zero bits in the right places. So it seems
-+ // simplest to do the whole sequence in 32-bit insns.
-+ /*
-+ r = <argument> // working temporary, initial byte order ABCD
-+ Mask = 00FF00FF
-+ nMask = not Mask
-+ tHi = and r, Mask
-+ tHi = shl tHi, 8
-+ tLo = and r, nMask
-+ tLo = shr tLo, 8
-+ r = or tHi, tLo // now r has order BADC
-+ and repeat for 16 bit chunks ..
-+ Mask = 0000FFFF
-+ nMask = not Mask
-+ tHi = and r, Mask
-+ tHi = shl tHi, 16
-+ tLo = and r, nMask
-+ tLo = shr tLo, 16
-+ r = or tHi, tLo // now r has order DCBA
-+ */
-+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
-+ HReg rr = newVRegI(env);
-+ HReg rMask = newVRegI(env);
-+ HReg rnMask = newVRegI(env);
-+ HReg rtHi = newVRegI(env);
-+ HReg rtLo = newVRegI(env);
-+ // Copy r_src since we need to modify it
-+ addInstr(env, mk_iMOVds_RR(rr, r_src));
-+ // Swap within 16-bit lanes
-+ addInstr(env, PPCInstr_LI(rMask, 0x00FF00FFULL,
-+ False/* !64bit imm*/));
-+ addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32 bit shift*/,
-+ rtHi, rtHi,
-+ PPCRH_Imm(False/*!signed imm*/, 8)));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32 bit shift*/,
-+ rtLo, rtLo,
-+ PPCRH_Imm(False/*!signed imm*/, 8)));
-+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
-+ // And now swap the two 16-bit chunks
-+ addInstr(env, PPCInstr_LI(rMask, 0x0000FFFFULL,
-+ False/* !64bit imm*/));
-+ addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32 bit shift*/,
-+ rtHi, rtHi,
-+ PPCRH_Imm(False/*!signed imm*/, 16)));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32 bit shift*/,
-+ rtLo, rtLo,
-+ PPCRH_Imm(False/*!signed imm*/, 16)));
-+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
-+ return rr;
- }
-
- case Iop_Left8:
diff --git a/valgrind-3.14.0-ppc-subfe.patch b/valgrind-3.14.0-ppc-subfe.patch
deleted file mode 100644
index 301dd8c..0000000
--- a/valgrind-3.14.0-ppc-subfe.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-commit 256cf43c5eadb28edb45436aca6fda8ee55eb10e
-Author: Mark Wielaard <mark@klomp.org>
-Date: Thu Feb 21 17:21:53 2019 +0100
-
- memcheck powerpc subfe x, x, x initializes x to 0 or -1 based on CA
-
- GCC might use subfe x, x, x to initialize x to 0 or -1, based on
- whether the carry flag is set. This happens in some cases when g++
- compiles resetting a unique_ptr. The "trick" used by the compiler is
- that it can AND a pointer with the register x (now 0x0 or 0xffffffff)
- to set something to NULL or to the given pointer.
-
- subfe is implemented as rD = (log not)rA + rB + XER[CA]
- if we instead implement it as rD = rB - rA - (XER[CA] ^ 1)
- then memcheck can see that rB and Ra cancel each other out if they
- are the same.
-
- https://bugs.kde.org/show_bug.cgi?id=404054
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index e207642..00ae6df 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -5361,11 +5361,15 @@ static Bool dis_int_arith ( UInt theInstr )
- flag_OE ? "o" : "", flag_rC ? ".":"",
- rD_addr, rA_addr, rB_addr);
- // rD = (log not)rA + rB + XER[CA]
-+ // ==>
-+ // rD = rB - rA - (XER[CA] ^ 1)
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
-- assign( rD, binop( mkSzOp(ty, Iop_Add8),
-- unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)),
-- binop( mkSzOp(ty, Iop_Add8),
-- mkexpr(rB), mkexpr(old_xer_ca))) );
-+ assign( rD, binop( mkSzOp(ty, Iop_Sub8),
-+ binop( mkSzOp(ty, Iop_Sub8),
-+ mkexpr(rB), mkexpr(rA)),
-+ binop(mkSzOp(ty, Iop_Xor8),
-+ mkexpr(old_xer_ca),
-+ mkSzImm(ty, 1))) );
- set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkexpr(old_xer_ca) );
diff --git a/valgrind-3.14.0-ppc64-ldbrx.patch b/valgrind-3.14.0-ppc64-ldbrx.patch
deleted file mode 100644
index d4f5ab8..0000000
--- a/valgrind-3.14.0-ppc64-ldbrx.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-commit 7bdd6731f8337fd57bf91772aa1917e44239d7c2
-Author: Mark Wielaard <mark@klomp.org>
-Date: Fri Dec 7 10:42:22 2018 -0500
-
- Implement ppc64 ldbrx as 64-bit load and Iop_Reverse8sIn64_x1.
-
- This makes it possible for memcheck to analyse the new gcc strcmp
- inlined code correctly even if the ldbrx load is partly beyond an
- addressable block.
-
- Partially resolves bug 386945.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 8977d4f..a81dace 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -9178,24 +9178,28 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
-
- case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed)
- {
-- // JRS FIXME:
-- // * is the host_endness conditional below actually necessary?
-- // * can we just do a 64-bit load followed by by Iop_Reverse8sIn64_x1?
-- // That would be a lot more efficient.
-- IRExpr * nextAddr;
-- IRTemp w3 = newTemp( Ity_I32 );
-- IRTemp w4 = newTemp( Ity_I32 );
-- DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
-- assign( w1, load( Ity_I32, mkexpr( EA ) ) );
-- assign( w2, gen_byterev32( w1 ) );
-- nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
-- ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );
-- assign( w3, load( Ity_I32, nextAddr ) );
-- assign( w4, gen_byterev32( w3 ) );
-- if (host_endness == VexEndnessLE)
-- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) );
-+ /* Caller makes sure we are only called in mode64. */
-+
-+ /* If we supported swapping LE/BE loads in the backend then we could
-+ just load the value with the bytes reversed by doing a BE load
-+ on an LE machine and a LE load on a BE machine.
-+
-+ IRTemp dw1 = newTemp(Ity_I64);
-+ if (host_endness == VexEndnessBE)
-+ assign( dw1, IRExpr_Load(Iend_LE, Ity_I64, mkexpr(EA)));
- else
-- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
-+ assign( dw1, IRExpr_Load(Iend_BE, Ity_I64, mkexpr(EA)));
-+ putIReg( rD_addr, mkexpr(dw1) );
-+
-+ But since we currently don't we load the value as is and then
-+ switch it around with Iop_Reverse8sIn64_x1. */
-+
-+ IRTemp dw1 = newTemp(Ity_I64);
-+ IRTemp dw2 = newTemp(Ity_I64);
-+ DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
-+ assign( dw1, load(Ity_I64, mkexpr(EA)) );
-+ assign( dw2, unop(Iop_Reverse8sIn64_x1, mkexpr(dw1)) );
-+ putIReg( rD_addr, mkexpr(dw2) );
- break;
- }
-
-diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
-index 750cf8d..4fc3eb5 100644
---- a/VEX/priv/host_ppc_isel.c
-+++ b/VEX/priv/host_ppc_isel.c
-@@ -2210,6 +2210,63 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
- return rr;
- }
-
-+ case Iop_Reverse8sIn64_x1: {
-+ /* See Iop_Reverse8sIn32_x1, but extended to 64bit.
-+ Can only be used in 64bit mode. */
-+ vassert (mode64);
-+
-+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
-+ HReg rr = newVRegI(env);
-+ HReg rMask = newVRegI(env);
-+ HReg rnMask = newVRegI(env);
-+ HReg rtHi = newVRegI(env);
-+ HReg rtLo = newVRegI(env);
-+
-+ // Copy r_src since we need to modify it
-+ addInstr(env, mk_iMOVds_RR(rr, r_src));
-+
-+ // r = (r & 0x00FF00FF00FF00FF) << 8 | (r & 0xFF00FF00FF00FF00) >> 8
-+ addInstr(env, PPCInstr_LI(rMask, 0x00FF00FF00FF00FFULL,
-+ True/* 64bit imm*/));
-+ addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
-+ rtHi, rtHi,
-+ PPCRH_Imm(False/*!signed imm*/, 8)));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
-+ rtLo, rtLo,
-+ PPCRH_Imm(False/*!signed imm*/, 8)));
-+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
-+
-+ // r = (r & 0x0000FFFF0000FFFF) << 16 | (r & 0xFFFF0000FFFF0000) >> 16
-+ addInstr(env, PPCInstr_LI(rMask, 0x0000FFFF0000FFFFULL,
-+ True/* !64bit imm*/));
-+ addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
-+ rtHi, rtHi,
-+ PPCRH_Imm(False/*!signed imm*/, 16)));
-+ addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
-+ rtLo, rtLo,
-+ PPCRH_Imm(False/*!signed imm*/, 16)));
-+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
-+
-+ // r = (r & 0x00000000FFFFFFFF) << 32 | (r & 0xFFFFFFFF00000000) >> 32
-+ /* We don't need to mask anymore, just two more shifts and an or. */
-+ addInstr(env, mk_iMOVds_RR(rtLo, rr));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
-+ rtLo, rtLo,
-+ PPCRH_Imm(False/*!signed imm*/, 32)));
-+ addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
-+ rr, rr,
-+ PPCRH_Imm(False/*!signed imm*/, 32)));
-+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rr, PPCRH_Reg(rtLo)));
-+
-+ return rr;
-+ }
-+
- case Iop_Left8:
- case Iop_Left16:
- case Iop_Left32:
diff --git a/valgrind-3.14.0-ppc64-lxvb16x.patch b/valgrind-3.14.0-ppc64-lxvb16x.patch
deleted file mode 100644
index e821d81..0000000
--- a/valgrind-3.14.0-ppc64-lxvb16x.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-commit 5c00e04a1b61475a7f731f8cfede114201815e0a
-Author: Mark Wielaard <mark@klomp.org>
-Date: Sun Dec 9 23:25:05 2018 +0100
-
- Implement ppc64 lxvb16x as 128-bit vector load with reversed double words.
-
- This makes it possible for memcheck to know which part of the 128bit
- vector is defined, even if the load is partly beyond an addressable block.
-
- Partially resolves bug 386945.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index 7af4973..ec2f90a 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -20702,54 +20702,29 @@ dis_vx_load ( UInt theInstr )
- {
- DIP("lxvb16x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
-
-- IRTemp byte[16];
-- int i;
-- UInt ea_off = 0;
-- IRExpr* irx_addr;
-- IRTemp tmp_low[9];
-- IRTemp tmp_hi[9];
-+ /* The result of lxvb16x should be the same on big and little
-+ endian systems. We do a host load, then reverse the bytes in
-+ the double words. If the host load was little endian we swap
-+ them around again. */
-
-- tmp_low[0] = newTemp( Ity_I64 );
-- tmp_hi[0] = newTemp( Ity_I64 );
-- assign( tmp_low[0], mkU64( 0 ) );
-- assign( tmp_hi[0], mkU64( 0 ) );
--
-- for ( i = 0; i < 8; i++ ) {
-- byte[i] = newTemp( Ity_I64 );
-- tmp_low[i+1] = newTemp( Ity_I64 );
--
-- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
-- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-- ea_off += 1;
--
-- assign( byte[i], binop( Iop_Shl64,
-- unop( Iop_8Uto64,
-- load( Ity_I8, irx_addr ) ),
-- mkU8( 8 * ( 7 - i ) ) ) );
-+ IRTemp high = newTemp(Ity_I64);
-+ IRTemp high_rev = newTemp(Ity_I64);
-+ IRTemp low = newTemp(Ity_I64);
-+ IRTemp low_rev = newTemp(Ity_I64);
-
-- assign( tmp_low[i+1],
-- binop( Iop_Or64,
-- mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
-- }
-+ IRExpr *t128 = load( Ity_V128, mkexpr( EA ) );
-
-- for ( i = 0; i < 8; i++ ) {
-- byte[i + 8] = newTemp( Ity_I64 );
-- tmp_hi[i+1] = newTemp( Ity_I64 );
-+ assign( high, unop(Iop_V128HIto64, t128) );
-+ assign( high_rev, unop(Iop_Reverse8sIn64_x1, mkexpr(high)) );
-+ assign( low, unop(Iop_V128to64, t128) );
-+ assign( low_rev, unop(Iop_Reverse8sIn64_x1, mkexpr(low)) );
-
-- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
-- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-- ea_off += 1;
-+ if (host_endness == VexEndnessLE)
-+ t128 = binop( Iop_64HLtoV128, mkexpr (low_rev), mkexpr (high_rev) );
-+ else
-+ t128 = binop( Iop_64HLtoV128, mkexpr (high_rev), mkexpr (low_rev) );
-
-- assign( byte[i+8], binop( Iop_Shl64,
-- unop( Iop_8Uto64,
-- load( Ity_I8, irx_addr ) ),
-- mkU8( 8 * ( 7 - i ) ) ) );
-- assign( tmp_hi[i+1], binop( Iop_Or64,
-- mkexpr( byte[i+8] ),
-- mkexpr( tmp_hi[i] ) ) );
-- }
-- putVSReg( XT, binop( Iop_64HLtoV128,
-- mkexpr( tmp_low[8] ), mkexpr( tmp_hi[8] ) ) );
-+ putVSReg( XT, t128 );
- break;
- }
-
diff --git a/valgrind-3.14.0-ppc64-lxvd2x.patch b/valgrind-3.14.0-ppc64-lxvd2x.patch
deleted file mode 100644
index cf2aa0c..0000000
--- a/valgrind-3.14.0-ppc64-lxvd2x.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-commit b7d65cab4f3e9a6f66a496e723e53ed736c4d2e7
-Author: Mark Wielaard <mark@klomp.org>
-Date: Sun Dec 9 00:55:42 2018 +0100
-
- Implement ppc64 lxvd2x as 128-bit load with double word swap for ppc64le.
-
- This makes it possible for memcheck to know which part of the 128bit
- vector is defined, even if the load is partly beyond an addressable block.
-
- Partially resolves bug 386945.
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index a81dace..7af4973 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -20590,16 +20590,22 @@ dis_vx_load ( UInt theInstr )
- }
- case 0x34C: // lxvd2x
- {
-- IROp addOp = ty == Ity_I64 ? Iop_Add64 : Iop_Add32;
-- IRExpr * high, *low;
-- ULong ea_off = 8;
-- IRExpr* high_addr;
-+ IRExpr *t128;
- DIP("lxvd2x %d,r%u,r%u\n", XT, rA_addr, rB_addr);
-- high = load( Ity_I64, mkexpr( EA ) );
-- high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off )
-- : mkU32( ea_off ) );
-- low = load( Ity_I64, high_addr );
-- putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
-+ t128 = load( Ity_V128, mkexpr( EA ) );
-+
-+ /* The data in the vec register should be in big endian order.
-+ So if we just did a little endian load then swap around the
-+ high and low double words. */
-+ if (host_endness == VexEndnessLE) {
-+ IRTemp high = newTemp(Ity_I64);
-+ IRTemp low = newTemp(Ity_I64);
-+ assign( high, unop(Iop_V128HIto64, t128) );
-+ assign( low, unop(Iop_V128to64, t128) );
-+ t128 = binop( Iop_64HLtoV128, mkexpr (low), mkexpr (high) );
-+ }
-+
-+ putVSReg( XT, t128 );
- break;
- }
- case 0x14C: // lxvdsx
diff --git a/valgrind-3.14.0-ppc64-ptrace.patch b/valgrind-3.14.0-ppc64-ptrace.patch
deleted file mode 100644
index 5ce2a7e..0000000
--- a/valgrind-3.14.0-ppc64-ptrace.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-commit 3967a99c26e8b314634a6b1fd8927cbb2bb5d060
-Author: Mark Wielaard <mark@klomp.org>
-Date: Wed Dec 12 14:11:29 2018 +0100
-
- Implement minimal ptrace support for ppc64[le]-linux.
-
-diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
-index 6549dd1..0fdcc8e 100644
---- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
-+++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
-@@ -388,6 +388,7 @@ DECL_TEMPLATE(ppc64_linux, sys_mmap);
- //zz DECL_TEMPLATE(ppc64_linux, sys_sigreturn);
- DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn);
- DECL_TEMPLATE(ppc64_linux, sys_fadvise64);
-+DECL_TEMPLATE(ppc64_linux, sys_ptrace);
-
- PRE(sys_mmap)
- {
-@@ -511,6 +512,72 @@ PRE(sys_rt_sigreturn)
- *flags |= SfPollAfter;
- }
-
-+// ARG3 is only used for pointers into the traced process's address
-+// space and for offsets into the traced process's struct
-+// user_regs_struct. It is never a pointer into this process's memory
-+// space, and we should therefore not check anything it points to.
-+// powerpc does have other ways to get/set registers, we only support
-+// GET/SETREGSET for now.
-+PRE(sys_ptrace)
-+{
-+ PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4);
-+ PRE_REG_READ4(int, "ptrace",
-+ long, request, long, pid, long, addr, long, data);
-+ switch (ARG1) {
-+ case VKI_PTRACE_PEEKTEXT:
-+ case VKI_PTRACE_PEEKDATA:
-+ case VKI_PTRACE_PEEKUSR:
-+ PRE_MEM_WRITE( "ptrace(peek)", ARG4,
-+ sizeof (long));
-+ break;
-+ case VKI_PTRACE_GETEVENTMSG:
-+ PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long));
-+ break;
-+ case VKI_PTRACE_GETSIGINFO:
-+ PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t));
-+ break;
-+ case VKI_PTRACE_SETSIGINFO:
-+ PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t));
-+ break;
-+ case VKI_PTRACE_GETREGSET:
-+ ML_(linux_PRE_getregset)(tid, ARG3, ARG4);
-+ break;
-+ case VKI_PTRACE_SETREGSET:
-+ ML_(linux_PRE_setregset)(tid, ARG3, ARG4);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+POST(sys_ptrace)
-+{
-+ switch (ARG1) {
-+ case VKI_PTRACE_TRACEME:
-+ ML_(linux_POST_traceme)(tid);
-+ break;
-+ case VKI_PTRACE_PEEKTEXT:
-+ case VKI_PTRACE_PEEKDATA:
-+ case VKI_PTRACE_PEEKUSR:
-+ POST_MEM_WRITE( ARG4, sizeof (long));
-+ break;
-+ case VKI_PTRACE_GETEVENTMSG:
-+ POST_MEM_WRITE( ARG4, sizeof(unsigned long));
-+ break;
-+ case VKI_PTRACE_GETSIGINFO:
-+ /* XXX: This is a simplification. Different parts of the
-+ * siginfo_t are valid depending on the type of signal.
-+ */
-+ POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t));
-+ break;
-+ case VKI_PTRACE_GETREGSET:
-+ ML_(linux_POST_getregset)(tid, ARG3, ARG4);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
- #undef PRE
- #undef POST
-
-@@ -562,8 +629,7 @@ static SyscallTableEntry syscall_table[] = {
- GENX_(__NR_getuid, sys_getuid), // 24
-
- // _____(__NR_stime, sys_stime), // 25
--// When ptrace is supported, memcheck/tests/linux/getregset should be enabled
--// _____(__NR_ptrace, sys_ptrace), // 26
-+ PLAXY(__NR_ptrace, sys_ptrace), // 26
- GENX_(__NR_alarm, sys_alarm), // 27
- // _____(__NR_oldfstat, sys_oldfstat), // 28
- GENX_(__NR_pause, sys_pause), // 29
-diff --git a/memcheck/tests/linux/getregset.vgtest b/memcheck/tests/linux/getregset.vgtest
-index 4c66108..c35be4c 100644
---- a/memcheck/tests/linux/getregset.vgtest
-+++ b/memcheck/tests/linux/getregset.vgtest
-@@ -1,4 +1,4 @@
- prog: getregset
- vgopts: -q
--prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 ) && ! ../../../tests/arch_test ppc64
-+prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 )
-
diff --git a/valgrind-3.14.0-ppc64-quotactl.patch b/valgrind-3.14.0-ppc64-quotactl.patch
deleted file mode 100644
index 87b4033..0000000
--- a/valgrind-3.14.0-ppc64-quotactl.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-commit 7f74ba249ead48f351676c37d498b17305212123
-Author: Mark Wielaard <mark@klomp.org>
-Date: Mon Mar 4 17:22:56 2019 +0100
-
- Bug 405079 - unhandled ppc64le-linux syscall: 131 (quotactl)
-
- quotactl is really a "generic" linux syscall that just happened to not
- have been hooked up for ppc64le. Add it to syswrap-ppc64-linux.c.
-
-diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
-index 0fdcc8e..eada099 100644
---- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
-+++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
-@@ -755,7 +755,7 @@ static SyscallTableEntry syscall_table[] = {
- LINX_(__NR_delete_module, sys_delete_module), // 129
-
- // _____(__NR_get_kernel_syms, sys_get_kernel_syms), // 130
--// _____(__NR_quotactl, sys_quotactl), // 131
-+ LINX_(__NR_quotactl, sys_quotactl), // 131
- GENX_(__NR_getpgid, sys_getpgid), // 132
- GENX_(__NR_fchdir, sys_fchdir), // 133
- // _____(__NR_bdflush, sys_bdflush), // 134
diff --git a/valgrind-3.14.0-ppc64-unaligned-vecs.patch b/valgrind-3.14.0-ppc64-unaligned-vecs.patch
deleted file mode 100644
index 00c64fc..0000000
--- a/valgrind-3.14.0-ppc64-unaligned-vecs.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-commit 321771ee63740333ad355244e0764295218843b8
-Author: Mark Wielaard <mark@klomp.org>
-Date: Sun Dec 9 14:26:39 2018 +0100
-
- memcheck: Allow unaligned loads of 128bit vectors on ppc64[le].
-
- On powerpc partial unaligned loads of vectors from partially invalid
- addresses are OK and could be generated by our translation of lxvd2x.
-
- Adjust partial_load memcheck tests to allow partial loads of 16 byte
- vectors on powerpc64.
-
- Part of resolving bug #386945.
-
-diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
-index 737f79d..101916b 100644
---- a/memcheck/mc_main.c
-+++ b/memcheck/mc_main.c
-@@ -1354,6 +1354,9 @@ void mc_LOADV_128_or_256_slow ( /*OUT*/ULong* res,
- tl_assert(szB == 16); // s390 doesn't have > 128 bit SIMD
- /* OK if all loaded bytes are from the same page. */
- Bool alignedOK = ((a & 0xfff) <= 0x1000 - szB);
-+# elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
-+ /* lxvd2x might generate an unaligned 128 bit vector load. */
-+ Bool alignedOK = (szB == 16);
- # else
- /* OK if the address is aligned by the load size. */
- Bool alignedOK = (0 == (a & (szB - 1)));
diff --git a/valgrind-3.14.0-ppc64-unaligned-words.patch b/valgrind-3.14.0-ppc64-unaligned-words.patch
deleted file mode 100644
index f9a94dc..0000000
--- a/valgrind-3.14.0-ppc64-unaligned-words.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-commit c5a5bea00af75f6ac50da10967d956f117b956f1
-Author: Mark Wielaard <mark@klomp.org>
-Date: Sat Dec 8 13:47:43 2018 -0500
-
- memcheck: Allow unaligned loads of words on ppc64[le].
-
- On powerpc partial unaligned loads of words from partially invalid
- addresses are OK and could be generated by our translation of ldbrx.
-
- Adjust partial_load memcheck tests to allow partial loads of words
- on powerpc64.
-
- Part of resolving bug #386945.
-
-diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
-index 3ef7cb9..737f79d 100644
---- a/memcheck/mc_main.c
-+++ b/memcheck/mc_main.c
-@@ -1508,6 +1508,9 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian )
- # if defined(VGA_mips64) && defined(VGABI_N32)
- if (szB == VG_WORDSIZE * 2 && VG_IS_WORD_ALIGNED(a)
- && n_addrs_bad < VG_WORDSIZE * 2)
-+# elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
-+ /* On power unaligned loads of words are OK. */
-+ if (szB == VG_WORDSIZE && n_addrs_bad < VG_WORDSIZE)
- # else
- if (szB == VG_WORDSIZE && VG_IS_WORD_ALIGNED(a)
- && n_addrs_bad < VG_WORDSIZE)
-diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
-index 2af4dd1..70b8ada 100644
---- a/memcheck/tests/Makefile.am
-+++ b/memcheck/tests/Makefile.am
-@@ -235,8 +235,10 @@ EXTRA_DIST = \
- partiallydefinedeq.stdout.exp \
- partial_load_ok.vgtest partial_load_ok.stderr.exp \
- partial_load_ok.stderr.exp64 \
-+ partial_load_ok.stderr.exp-ppc64 \
- partial_load_dflt.vgtest partial_load_dflt.stderr.exp \
- partial_load_dflt.stderr.exp64 \
-+ partial_load_dflt.stderr.exp-ppc64 \
- partial_load_dflt.stderr.expr-s390x-mvc \
- pdb-realloc.stderr.exp pdb-realloc.vgtest \
- pdb-realloc2.stderr.exp pdb-realloc2.stdout.exp pdb-realloc2.vgtest \
-diff --git a/memcheck/tests/partial_load.c b/memcheck/tests/partial_load.c
-index 0b2f10b..685ca8d 100644
---- a/memcheck/tests/partial_load.c
-+++ b/memcheck/tests/partial_load.c
-@@ -1,14 +1,14 @@
--
-+#include <stdio.h>
- #include <stdlib.h>
- #include <assert.h>
-
- int main ( void )
- {
-- long w;
-- int i;
-- char* p;
--
-+ long w; int i; char* p;
- assert(sizeof(long) == sizeof(void*));
-+#if defined(__powerpc64__)
-+ fprintf (stderr, "powerpc64\n"); /* Used to select correct .exp file. */
-+#endif
-
- /* partial load, which --partial-loads-ok=yes should suppress */
- p = calloc( sizeof(long)-1, 1 );
-@@ -16,7 +16,7 @@ int main ( void )
- w = *(long*)p;
- free(p);
-
-- /* partial but misaligned, cannot be suppressed */
-+ /* partial but misaligned, ppc64[le] ok, but otherwise cannot be suppressed */
- p = calloc( sizeof(long), 1 );
- assert(p);
- p++;
-diff --git a/memcheck/tests/partial_load_dflt.stderr.exp-ppc64 b/memcheck/tests/partial_load_dflt.stderr.exp-ppc64
-new file mode 100644
-index 0000000..cf32bcf
---- /dev/null
-+++ b/memcheck/tests/partial_load_dflt.stderr.exp-ppc64
-@@ -0,0 +1,23 @@
-+
-+powerpc64
-+Invalid read of size 2
-+ at 0x........: main (partial_load.c:30)
-+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
-+ at 0x........: calloc (vg_replace_malloc.c:...)
-+ by 0x........: main (partial_load.c:28)
-+
-+Invalid read of size 8
-+ at 0x........: main (partial_load.c:37)
-+ Address 0x........ is 0 bytes inside a block of size 8 free'd
-+ at 0x........: free (vg_replace_malloc.c:...)
-+ by 0x........: main (partial_load.c:36)
-+
-+
-+HEAP SUMMARY:
-+ in use at exit: ... bytes in ... blocks
-+ total heap usage: ... allocs, ... frees, ... bytes allocated
-+
-+For a detailed leak analysis, rerun with: --leak-check=full
-+
-+For counts of detected and suppressed errors, rerun with: -v
-+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
-diff --git a/memcheck/tests/partial_load_ok.stderr.exp-ppc64 b/memcheck/tests/partial_load_ok.stderr.exp-ppc64
-new file mode 100644
-index 0000000..cf32bcf
---- /dev/null
-+++ b/memcheck/tests/partial_load_ok.stderr.exp-ppc64
-@@ -0,0 +1,23 @@
-+
-+powerpc64
-+Invalid read of size 2
-+ at 0x........: main (partial_load.c:30)
-+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
-+ at 0x........: calloc (vg_replace_malloc.c:...)
-+ by 0x........: main (partial_load.c:28)
-+
-+Invalid read of size 8
-+ at 0x........: main (partial_load.c:37)
-+ Address 0x........ is 0 bytes inside a block of size 8 free'd
-+ at 0x........: free (vg_replace_malloc.c:...)
-+ by 0x........: main (partial_load.c:36)
-+
-+
-+HEAP SUMMARY:
-+ in use at exit: ... bytes in ... blocks
-+ total heap usage: ... allocs, ... frees, ... bytes allocated
-+
-+For a detailed leak analysis, rerun with: --leak-check=full
-+
-+For counts of detected and suppressed errors, rerun with: -v
-+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
diff --git a/valgrind-3.14.0-rsp-clobber.patch b/valgrind-3.14.0-rsp-clobber.patch
deleted file mode 100644
index 87aadc8..0000000
--- a/valgrind-3.14.0-rsp-clobber.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-commit 022f5af61bc3cbfa2b74ab355b0d2d30b3dab027
-Author: Khem Raj <raj.khem@gmail.com>
-Date: Sat Dec 22 15:28:40 2018 -0800
-
- tests/amd64: Do not clobber %rsp register
-
- This is seen with gcc-9.0 compiler now which is fix that gcc community
- did recently
- https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52813
-
- Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-diff --git a/none/tests/amd64-linux/bug345887.c b/none/tests/amd64-linux/bug345887.c
-index 0f9237d..269bd70 100644
---- a/none/tests/amd64-linux/bug345887.c
-+++ b/none/tests/amd64-linux/bug345887.c
-@@ -20,13 +20,17 @@ static void inner(void)
- "movq $0x10d, %%r14\n"
- "movq $0x10e, %%r15\n"
- // not %rbp as mdb is then not able to reconstruct stack trace
-+ // Do change %rsp (to test a bogus stack pointer),
-+ // but don't add %rsp to the clobber list since gcc ignores it
-+ // and since gcc >= 9.0 errors about it
-+ // see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52813
- "movq $0x10f, %%rsp\n"
- "movq $0x1234, (%%rax)\n" // should cause SEGV here
- "ud2" // should never get here
- : // no output registers
- : // no input registers
- : "memory", "%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi",
-- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", "%rsp");
-+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15");
- }
-
- __attribute__((noinline))
-commit c512949082c4fc2285a82e102d4212c66e034a31
-Author: Mark Wielaard <mark@klomp.org>
-Date: Fri Jan 11 20:00:17 2019 +0100
-
- Bug 402480 Do not use %esp in clobber list.
-
- This is the same fix as for amd64-linux, but now for x86-linux.
-
-diff --git a/none/tests/x86-linux/bug345887.c b/none/tests/x86-linux/bug345887.c
-index f2e8a8d..ef21d4e 100644
---- a/none/tests/x86-linux/bug345887.c
-+++ b/none/tests/x86-linux/bug345887.c
-@@ -12,12 +12,14 @@ static void inner(void)
- "movl $0x105, %%esi\n"
- "movl $0x106, %%edi\n"
- // not %ebp as mdb is then not able to reconstruct stack trace
-+ // clobbering %esp is really bad, but that is kind of the point
-+ // we don't add it to the clobber list since gcc9 warns about that
- "movl $0x108, %%esp\n"
- "movl $0x1234, (%%eax)\n" // should cause SEGV here
- "ud2" // should never get here
- : // no output registers
- : // no input registers
-- : "memory", "%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%esp");
-+ : "memory", "%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi");
- }
-
- __attribute__((noinline))
diff --git a/valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch b/valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch
deleted file mode 100644
index b5c8282..0000000
--- a/valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-commit 71002d8a5111d02ce8049c55017a8d948c820e35
-Author: Andreas Arnez <arnez@linux.ibm.com>
-Date: Thu Oct 25 13:47:12 2018 +0200
-
- Bug 400490 s390x: Fix register allocation for VRs vs FPRs
-
- On s390x, if vector registers are available, they are fed to the register
- allocator as if they were separate from the floating-point registers. But
- in fact the FPRs are embedded in the VRs. So for instance, if both f3 and
- v3 are allocated and used at the same time, corruption will result.
-
- This is fixed by offering only the non-overlapping VRs, v16 to v31, to the
- register allocator instead.
-
-diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
-index 6c22ac8..98ac938 100644
---- a/VEX/priv/host_s390_defs.c
-+++ b/VEX/priv/host_s390_defs.c
-@@ -59,7 +59,6 @@ static UInt s390_tchain_load64_len(void);
-
- /* A mapping from register number to register index */
- static Int gpr_index[16]; // GPR regno -> register index
--static Int fpr_index[16]; // FPR regno -> register index
- static Int vr_index[32]; // VR regno -> register index
-
- HReg
-@@ -73,7 +72,7 @@ s390_hreg_gpr(UInt regno)
- HReg
- s390_hreg_fpr(UInt regno)
- {
-- Int ix = fpr_index[regno];
-+ Int ix = vr_index[regno];
- vassert(ix >= 0);
- return mkHReg(/*virtual*/False, HRcFlt64, regno, ix);
- }
-@@ -463,11 +462,9 @@ getRRegUniverse_S390(void)
-
- RRegUniverse__init(ru);
-
-- /* Assign invalid values to the gpr/fpr/vr_index */
-+ /* Assign invalid values to the gpr/vr_index */
- for (UInt i = 0; i < sizeof gpr_index / sizeof gpr_index[0]; ++i)
- gpr_index[i] = -1;
-- for (UInt i = 0; i < sizeof fpr_index / sizeof fpr_index[0]; ++i)
-- fpr_index[i] = -1;
- for (UInt i = 0; i < sizeof vr_index / sizeof vr_index[0]; ++i)
- vr_index[i] = -1;
-
-@@ -494,17 +491,17 @@ getRRegUniverse_S390(void)
-
- ru->allocable_start[HRcFlt64] = ru->size;
- for (UInt regno = 8; regno <= 15; ++regno) {
-- fpr_index[regno] = ru->size;
-+ vr_index[regno] = ru->size;
- ru->regs[ru->size++] = s390_hreg_fpr(regno);
- }
- for (UInt regno = 0; regno <= 7; ++regno) {
-- fpr_index[regno] = ru->size;
-+ vr_index[regno] = ru->size;
- ru->regs[ru->size++] = s390_hreg_fpr(regno);
- }
- ru->allocable_end[HRcFlt64] = ru->size - 1;
-
- ru->allocable_start[HRcVec128] = ru->size;
-- for (UInt regno = 0; regno <= 31; ++regno) {
-+ for (UInt regno = 16; regno <= 31; ++regno) {
- vr_index[regno] = ru->size;
- ru->regs[ru->size++] = s390_hreg_vr(regno);
- }
-@@ -527,12 +524,12 @@ getRRegUniverse_S390(void)
- /* Sanity checking */
- for (UInt i = 0; i < sizeof gpr_index / sizeof gpr_index[0]; ++i)
- vassert(gpr_index[i] >= 0);
-- for (UInt i = 0; i < sizeof fpr_index / sizeof fpr_index[0]; ++i)
-- vassert(fpr_index[i] >= 0);
- for (UInt i = 0; i < sizeof vr_index / sizeof vr_index[0]; ++i)
- vassert(vr_index[i] >= 0);
-
- initialised = True;
-+
-+ RRegUniverse__check_is_sane(ru);
- return ru;
- }
-
diff --git a/valgrind-3.14.0-s390x-sign-extend-lochi.patch b/valgrind-3.14.0-s390x-sign-extend-lochi.patch
deleted file mode 100644
index 318012f..0000000
--- a/valgrind-3.14.0-s390x-sign-extend-lochi.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-commit 9545e9f96beda6e9f2205bdb3c3e96edaf8d9e2b
-Author: Andreas Arnez <arnez@linux.ibm.com>
-Date: Tue Oct 30 17:06:38 2018 +0100
-
- Bug 400491 s390x: Sign-extend immediate operand of LOCHI and friends
-
- The VEX implementation of each of the z/Architecture instructions LOCHI,
- LOCHHI, and LOCGHI treats the immediate 16-bit operand as an unsigned
- integer instead of a signed integer. This is fixed.
-
-diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
-index 60b6081..9c4d79b 100644
---- a/VEX/priv/guest_s390_toIR.c
-+++ b/VEX/priv/guest_s390_toIR.c
-@@ -16307,7 +16307,7 @@ static const HChar *
- s390_irgen_LOCHHI(UChar r1, UChar m3, UShort i2, UChar unused)
- {
- next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
-- put_gpr_w0(r1, mkU32(i2));
-+ put_gpr_w0(r1, mkU32((UInt)(Int)(Short)i2));
-
- return "lochhi";
- }
-@@ -16316,7 +16316,7 @@ static const HChar *
- s390_irgen_LOCHI(UChar r1, UChar m3, UShort i2, UChar unused)
- {
- next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
-- put_gpr_w1(r1, mkU32(i2));
-+ put_gpr_w1(r1, mkU32((UInt)(Int)(Short)i2));
-
- return "lochi";
- }
-@@ -16325,7 +16325,7 @@ static const HChar *
- s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2, UChar unused)
- {
- next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
-- put_gpr_dw0(r1, mkU64(i2));
-+ put_gpr_dw0(r1, mkU64((UInt)(Int)(Short)i2));
-
- return "locghi";
- }
diff --git a/valgrind-3.14.0-s390x-vec-facility-bit.patch b/valgrind-3.14.0-s390x-vec-facility-bit.patch
deleted file mode 100644
index c00ed62..0000000
--- a/valgrind-3.14.0-s390x-vec-facility-bit.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-commit 467c7c4c9665c0f8b41a4416722a027ebc05df2b
-Author: Andreas Arnez <arnez@linux.ibm.com>
-Date: Mon Jan 21 14:10:00 2019 +0100
-
- Bug 403552 s390x: Fix vector facility bit number
-
- The wrong bit number was used when checking for the vector facility. This
- can result in a fatal emulation error: "Encountered an instruction that
- requires the vector facility. That facility is not available on this
- host."
-
- In many cases the wrong facility bit was usually set as well, hence
- nothing bad happened. But when running Valgrind within a Qemu/KVM guest,
- the wrong bit was not (always?) set and the emulation error occurred.
-
- This fix simply corrects the vector facility bit number, changing it from
- 128 to 129.
-
-
-diff --git a/VEX/pub/libvex_s390x_common.h b/VEX/pub/libvex_s390x_common.h
-index a8a66b96b..8723ee21d 100644
---- a/VEX/pub/libvex_s390x_common.h
-+++ b/VEX/pub/libvex_s390x_common.h
-@@ -103,7 +103,7 @@
- #define S390_FAC_MSA5 57 // message-security-assist 5
- #define S390_FAC_TREXE 73 // transactional execution
- #define S390_FAC_MSA4 77 // message-security-assist 4
--#define S390_FAC_VX 128 // vector facility
-+#define S390_FAC_VX 129 // vector facility
-
-
- /*--------------------------------------------------------------*/
diff --git a/valgrind-3.14.0-s390x-vec-float-point-code.patch b/valgrind-3.14.0-s390x-vec-float-point-code.patch
deleted file mode 100644
index 1e73a6f..0000000
--- a/valgrind-3.14.0-s390x-vec-float-point-code.patch
+++ /dev/null
@@ -1,1618 +0,0 @@
-commit 600a0099a1eb2335a3f9563534c112e11817002b
-Author: Vadim Barkov <vbrkov@gmail.com>
-Date: Fri Oct 5 13:51:49 2018 +0300
-
- Bug 385411 s390x: Add z13 vector floating point support
-
- This adds support for the z/Architecture vector FP instructions that were
- introduced with z13.
-
- The patch was contributed by Vadim Barkov, with some clean-up and minor
- adjustments by Andreas Arnez.
-
-diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h
-index 3bfecbe..d72cc9f 100644
---- a/VEX/priv/guest_s390_defs.h
-+++ b/VEX/priv/guest_s390_defs.h
-@@ -281,7 +281,11 @@ enum {
- S390_VEC_OP_VMALH = 13,
- S390_VEC_OP_VCH = 14,
- S390_VEC_OP_VCHL = 15,
-- S390_VEC_OP_LAST = 16 // supposed to be the last element in enum
-+ S390_VEC_OP_VFCE = 16,
-+ S390_VEC_OP_VFCH = 17,
-+ S390_VEC_OP_VFCHE = 18,
-+ S390_VEC_OP_VFTCI = 19,
-+ S390_VEC_OP_LAST = 20 // supposed to be the last element in enum
- } s390x_vec_op_t;
-
- /* Arguments of s390x_dirtyhelper_vec_op(...) which are packed into one
-@@ -300,8 +304,10 @@ typedef union {
-
- unsigned int m4 : 4; // field m4 of insn or zero if it's missing
- unsigned int m5 : 4; // field m5 of insn or zero if it's missing
-+ unsigned int m6 : 4; // field m6 of insn or zero if it's missing
-+ unsigned int i3 : 12; // field i3 of insn or zero if it's missing
- unsigned int read_only: 1; // don't write result to Guest State
-- unsigned int reserved : 27; // reserved for future
-+ unsigned int reserved : 11; // reserved for future
- };
- ULong serialized;
- } s390x_vec_op_details_t;
-diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c
-index d9773e7..5877743 100644
---- a/VEX/priv/guest_s390_helpers.c
-+++ b/VEX/priv/guest_s390_helpers.c
-@@ -2498,6 +2498,10 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
- {0xe7, 0xa9}, /* VMALH */
- {0xe7, 0xfb}, /* VCH */
- {0xe7, 0xf9}, /* VCHL */
-+ {0xe7, 0xe8}, /* VFCE */
-+ {0xe7, 0xeb}, /* VFCH */
-+ {0xe7, 0xea}, /* VFCHE */
-+ {0xe7, 0x4a} /* VFTCI */
- };
-
- union {
-@@ -2525,6 +2529,28 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
- unsigned int rxb : 4;
- unsigned int op2 : 8;
- } VRRd;
-+ struct {
-+ UInt op1 : 8;
-+ UInt v1 : 4;
-+ UInt v2 : 4;
-+ UInt v3 : 4;
-+ UInt : 4;
-+ UInt m6 : 4;
-+ UInt m5 : 4;
-+ UInt m4 : 4;
-+ UInt rxb : 4;
-+ UInt op2 : 8;
-+ } VRRc;
-+ struct {
-+ UInt op1 : 8;
-+ UInt v1 : 4;
-+ UInt v2 : 4;
-+ UInt i3 : 12;
-+ UInt m5 : 4;
-+ UInt m4 : 4;
-+ UInt rxb : 4;
-+ UInt op2 : 8;
-+ } VRIe;
- UChar bytes[6];
- } the_insn;
-
-@@ -2578,6 +2604,27 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
- the_insn.VRRd.m6 = d->m5;
- break;
-
-+ case S390_VEC_OP_VFCE:
-+ case S390_VEC_OP_VFCH:
-+ case S390_VEC_OP_VFCHE:
-+ the_insn.VRRc.v1 = 1;
-+ the_insn.VRRc.v2 = 2;
-+ the_insn.VRRc.v3 = 3;
-+ the_insn.VRRc.rxb = 0b1110;
-+ the_insn.VRRc.m4 = d->m4;
-+ the_insn.VRRc.m5 = d->m5;
-+ the_insn.VRRc.m6 = d->m6;
-+ break;
-+
-+ case S390_VEC_OP_VFTCI:
-+ the_insn.VRIe.v1 = 1;
-+ the_insn.VRIe.v2 = 2;
-+ the_insn.VRIe.rxb = 0b1100;
-+ the_insn.VRIe.i3 = d->i3;
-+ the_insn.VRIe.m4 = d->m4;
-+ the_insn.VRIe.m5 = d->m5;
-+ break;
-+
- default:
- vex_printf("operation = %d\n", d->op);
- vpanic("s390x_dirtyhelper_vec_op: unknown operation");
-diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
-index 50a5a41..1c4ac39 100644
---- a/VEX/priv/guest_s390_toIR.c
-+++ b/VEX/priv/guest_s390_toIR.c
-@@ -86,6 +86,7 @@ typedef enum {
- S390_DECODE_UNKNOWN_INSN,
- S390_DECODE_UNIMPLEMENTED_INSN,
- S390_DECODE_UNKNOWN_SPECIAL_INSN,
-+ S390_DECODE_SPECIFICATION_EXCEPTION,
- S390_DECODE_ERROR
- } s390_decode_t;
-
-@@ -421,6 +422,26 @@ yield_if(IRExpr *condition)
- S390X_GUEST_OFFSET(guest_IA)));
- }
-
-+/* Convenience macro to yield a specification exception if the given condition
-+ is not met. Used to pass this type of decoding error up through the call
-+ chain. */
-+#define s390_insn_assert(mnm, cond) \
-+ do { \
-+ if (!(cond)) { \
-+ dis_res->whatNext = Dis_StopHere; \
-+ dis_res->jk_StopHere = Ijk_NoDecode; \
-+ return (mnm); \
-+ } \
-+ } while (0)
-+
-+/* Convenience function to check for a specification exception. */
-+static Bool
-+is_specification_exception(void)
-+{
-+ return (dis_res->whatNext == Dis_StopHere &&
-+ dis_res->jk_StopHere == Ijk_NoDecode);
-+}
-+
- static __inline__ IRExpr *get_fpr_dw0(UInt);
- static __inline__ void put_fpr_dw0(UInt, IRExpr *);
- static __inline__ IRExpr *get_dpr_dw0(UInt);
-@@ -1770,6 +1791,11 @@ s390_vr_get_type(const UChar m)
- /* Determine if Zero Search (ZS) flag is set in m field */
- #define s390_vr_is_zs_set(m) (((m) & 0b0010) != 0)
-
-+/* Check if the "Single-Element-Control" bit is set.
-+ Used in vector FP instructions.
-+ */
-+#define s390_vr_is_single_element_control_set(m) (((m) & 0x8) != 0)
-+
- /* Generates arg1 < arg2 (or arg1 <= arg2 if allow_equal == True) expression.
- Arguments must have V128 type and are treated as unsigned 128-bit numbers.
- */
-@@ -2001,12 +2027,14 @@ s390_vr_offset_by_index(UInt archreg,IRType type, UChar index)
- return vr_offset(archreg) + sizeof(UShort) * index;
-
- case Ity_I32:
-+ case Ity_F32:
- if(index > 3) {
- goto invalidIndex;
- }
- return vr_offset(archreg) + sizeof(UInt) * index;
-
- case Ity_I64:
-+ case Ity_F64:
- if(index > 1) {
- goto invalidIndex;
- }
-@@ -2237,8 +2265,8 @@ encode_bfp_rounding_mode(UChar mode)
- case S390_BFP_ROUND_PER_FPC:
- rm = get_bfp_rounding_mode_from_fpc();
- break;
-- case S390_BFP_ROUND_NEAREST_AWAY: /* not supported */
-- case S390_BFP_ROUND_PREPARE_SHORT: /* not supported */
-+ case S390_BFP_ROUND_NEAREST_AWAY: rm = mkU32(Irrm_NEAREST_TIE_AWAY_0); break;
-+ case S390_BFP_ROUND_PREPARE_SHORT: rm = mkU32(Irrm_PREPARE_SHORTER); break;
- case S390_BFP_ROUND_NEAREST_EVEN: rm = mkU32(Irrm_NEAREST); break;
- case S390_BFP_ROUND_ZERO: rm = mkU32(Irrm_ZERO); break;
- case S390_BFP_ROUND_POSINF: rm = mkU32(Irrm_PosINF); break;
-@@ -3524,6 +3552,26 @@ s390_format_VRI_VVIM(const HChar *(*irgen)(UChar v1, UChar v3, UShort i2, UChar
- s390_disasm(ENC5(MNM, VR, VR, UINT, UINT), mnm, v1, v3, i2, m4);
- }
-
-+static void
-+s390_format_VRI_VVIMM(const HChar *(*irgen)(UChar v1, UChar v2, UShort i3,
-+ UChar m4, UChar m5),
-+ UChar v1, UChar v2, UShort i3, UChar m4, UChar m5,
-+ UChar rxb)
-+{
-+ const HChar *mnm;
-+
-+ if (!s390_host_has_vx) {
-+ emulation_failure(EmFail_S390X_vx);
-+ return;
-+ }
-+
-+ v1 = s390_vr_getVRindex(v1, 1, rxb);
-+ v2 = s390_vr_getVRindex(v2, 2, rxb);
-+ mnm = irgen(v1, v2, i3, m4, m5);
-+
-+ if (vex_traceflags & VEX_TRACE_FE)
-+ s390_disasm(ENC6(MNM, VR, VR, UINT, UINT, UINT), mnm, v1, v2, i3, m4, m5);
-+}
-
- static void
- s390_format_VRS_RRDVM(const HChar *(*irgen)(UChar r1, IRTemp op2addr, UChar v3,
-@@ -3680,7 +3728,7 @@ s390_format_VRV_VVRDMT(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar m3)
-
-
- static void
--s390_format_VRRd_VVVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
-+s390_format_VRR_VVVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
- UChar v4, UChar m5, UChar m6),
- UChar v1, UChar v2, UChar v3, UChar v4, UChar m5,
- UChar m6, UChar rxb)
-@@ -3794,6 +3842,92 @@ s390_format_VRRd_VVVVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
- }
-
-
-+static void
-+s390_format_VRRa_VVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3,
-+ UChar m4, UChar m5),
-+ UChar v1, UChar v2, UChar m3, UChar m4, UChar m5,
-+ UChar rxb)
-+{
-+ const HChar *mnm;
-+
-+ if (!s390_host_has_vx) {
-+ emulation_failure(EmFail_S390X_vx);
-+ return;
-+ }
-+
-+ v1 = s390_vr_getVRindex(v1, 1, rxb);
-+ v2 = s390_vr_getVRindex(v2, 2, rxb);
-+ mnm = irgen(v1, v2, m3, m4, m5);
-+
-+ if (vex_traceflags & VEX_TRACE_FE)
-+ s390_disasm(ENC6(MNM, VR, VR, UINT, UINT, UINT), mnm, v1, v2, m3, m4, m5);
-+}
-+
-+static void
-+s390_format_VRRa_VVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
-+ UChar m4, UChar m5),
-+ UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
-+ UChar rxb)
-+{
-+ const HChar *mnm;
-+
-+ if (!s390_host_has_vx) {
-+ emulation_failure(EmFail_S390X_vx);
-+ return;
-+ }
-+
-+ v1 = s390_vr_getVRindex(v1, 1, rxb);
-+ v2 = s390_vr_getVRindex(v2, 2, rxb);
-+ v3 = s390_vr_getVRindex(v3, 3, rxb);
-+ mnm = irgen(v1, v2, v3, m4, m5);
-+
-+ if (vex_traceflags & VEX_TRACE_FE)
-+ s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), mnm, v1, v2, v3, m4, m5);
-+}
-+
-+static void
-+s390_format_VRRa_VVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3,
-+ UChar m4),
-+ UChar v1, UChar v2, UChar m3, UChar m4, UChar rxb)
-+{
-+ const HChar *mnm;
-+
-+ if (!s390_host_has_vx) {
-+ emulation_failure(EmFail_S390X_vx);
-+ return;
-+ }
-+
-+ v1 = s390_vr_getVRindex(v1, 1, rxb);
-+ v2 = s390_vr_getVRindex(v2, 2, rxb);
-+ mnm = irgen(v1, v2, m3, m4);
-+
-+ if (vex_traceflags & VEX_TRACE_FE)
-+ s390_disasm(ENC5(MNM, VR, VR, UINT, UINT), mnm, v1, v2, m3, m4);
-+}
-+
-+static void
-+s390_format_VRRa_VVVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3,
-+ UChar m4, UChar m5, UChar m6),
-+ UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
-+ UChar m6, UChar rxb)
-+{
-+ const HChar *mnm;
-+
-+ if (!s390_host_has_vx) {
-+ emulation_failure(EmFail_S390X_vx);
-+ return;
-+ }
-+
-+ v1 = s390_vr_getVRindex(v1, 1, rxb);
-+ v2 = s390_vr_getVRindex(v2, 2, rxb);
-+ v3 = s390_vr_getVRindex(v3, 3, rxb);
-+ mnm = irgen(v1, v2, v3, m4, m5, m6);
-+
-+ if (vex_traceflags & VEX_TRACE_FE)
-+ s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT),
-+ mnm, v1, v2, v3, m4, m5, m6);
-+}
-+
- /*------------------------------------------------------------*/
- /*--- Build IR for opcodes ---*/
- /*------------------------------------------------------------*/
-@@ -17895,6 +18029,575 @@ s390_irgen_VMALH(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5)
- return "vmalh";
- }
-
-+static void
-+s390_vector_fp_convert(IROp op, IRType fromType, IRType toType,
-+ UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ Bool isSingleElementOp = s390_vr_is_single_element_control_set(m4);
-+ UChar maxIndex = isSingleElementOp ? 0 : 1;
-+
-+ /* For Iop_F32toF64 we do this:
-+ f32[0] -> f64[0]
-+ f32[2] -> f64[1]
-+
-+ For Iop_F64toF32 we do this:
-+ f64[0] -> f32[0]
-+ f64[1] -> f32[2]
-+
-+ The magic below with scaling factors is used to achieve the logic
-+ described above.
-+ */
-+ const UChar sourceIndexScaleFactor = (op == Iop_F32toF64) ? 2 : 1;
-+ const UChar destinationIndexScaleFactor = (op == Iop_F64toF32) ? 2 : 1;
-+
-+ const Bool isUnary = (op == Iop_F32toF64);
-+ for (UChar i = 0; i <= maxIndex; i++) {
-+ IRExpr* argument = get_vr(v2, fromType, i * sourceIndexScaleFactor);
-+ IRExpr* result;
-+ if (!isUnary) {
-+ result = binop(op,
-+ mkexpr(encode_bfp_rounding_mode(m5)),
-+ argument);
-+ } else {
-+ result = unop(op, argument);
-+ }
-+ put_vr(v1, toType, i * destinationIndexScaleFactor, result);
-+ }
-+
-+ if (isSingleElementOp) {
-+ put_vr_dw1(v1, mkU64(0));
-+ }
-+}
-+
-+static const HChar *
-+s390_irgen_VCDG(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vcdg", m3 == 3);
-+
-+ if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
-+ emulation_warning(EmWarn_S390X_fpext_rounding);
-+ m5 = S390_BFP_ROUND_PER_FPC;
-+ }
-+
-+ s390_vector_fp_convert(Iop_I64StoF64, Ity_I64, Ity_F64, v1, v2, m3, m4, m5);
-+
-+ return "vcdg";
-+}
-+
-+static const HChar *
-+s390_irgen_VCDLG(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vcdlg", m3 == 3);
-+
-+ if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
-+ emulation_warning(EmWarn_S390X_fpext_rounding);
-+ m5 = S390_BFP_ROUND_PER_FPC;
-+ }
-+
-+ s390_vector_fp_convert(Iop_I64UtoF64, Ity_I64, Ity_F64, v1, v2, m3, m4, m5);
-+
-+ return "vcdlg";
-+}
-+
-+static const HChar *
-+s390_irgen_VCGD(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vcgd", m3 == 3);
-+
-+ if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
-+ emulation_warning(EmWarn_S390X_fpext_rounding);
-+ m5 = S390_BFP_ROUND_PER_FPC;
-+ }
-+
-+ s390_vector_fp_convert(Iop_F64toI64S, Ity_F64, Ity_I64, v1, v2, m3, m4, m5);
-+
-+ return "vcgd";
-+}
-+
-+static const HChar *
-+s390_irgen_VCLGD(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vclgd", m3 == 3);
-+
-+ if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
-+ emulation_warning(EmWarn_S390X_fpext_rounding);
-+ m5 = S390_BFP_ROUND_PER_FPC;
-+ }
-+
-+ s390_vector_fp_convert(Iop_F64toI64U, Ity_F64, Ity_I64, v1, v2, m3, m4, m5);
-+
-+ return "vclgd";
-+}
-+
-+static const HChar *
-+s390_irgen_VFI(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vfi", m3 == 3);
-+
-+ if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
-+ emulation_warning(EmWarn_S390X_fpext_rounding);
-+ m5 = S390_BFP_ROUND_PER_FPC;
-+ }
-+
-+ s390_vector_fp_convert(Iop_RoundF64toInt, Ity_F64, Ity_F64,
-+ v1, v2, m3, m4, m5);
-+
-+ return "vcgld";
-+}
-+
-+static const HChar *
-+s390_irgen_VLDE(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vlde", m3 == 2);
-+
-+ s390_vector_fp_convert(Iop_F32toF64, Ity_F32, Ity_F64, v1, v2, m3, m4, m5);
-+
-+ return "vlde";
-+}
-+
-+static const HChar *
-+s390_irgen_VLED(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vled", m3 == 3);
-+
-+ if (!s390_host_has_fpext && m5 != S390_BFP_ROUND_PER_FPC) {
-+ m5 = S390_BFP_ROUND_PER_FPC;
-+ }
-+
-+ s390_vector_fp_convert(Iop_F64toF32, Ity_F64, Ity_F32, v1, v2, m3, m4, m5);
-+
-+ return "vled";
-+}
-+
-+static const HChar *
-+s390_irgen_VFPSO(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vfpso", m3 == 3);
-+
-+ IRExpr* result;
-+ switch (m5) {
-+ case 0: {
-+ /* Invert sign */
-+ if (!s390_vr_is_single_element_control_set(m4)) {
-+ result = unop(Iop_Neg64Fx2, get_vr_qw(v2));
-+ }
-+ else {
-+ result = binop(Iop_64HLtoV128,
-+ unop(Iop_ReinterpF64asI64,
-+ unop(Iop_NegF64, get_vr(v2, Ity_F64, 0))),
-+ mkU64(0));
-+ }
-+ break;
-+ }
-+
-+ case 1: {
-+ /* Set sign to negative */
-+ IRExpr* highHalf = mkU64(0x8000000000000000ULL);
-+ if (!s390_vr_is_single_element_control_set(m4)) {
-+ IRExpr* lowHalf = highHalf;
-+ IRExpr* mask = binop(Iop_64HLtoV128, highHalf, lowHalf);
-+ result = binop(Iop_OrV128, get_vr_qw(v2), mask);
-+ }
-+ else {
-+ result = binop(Iop_64HLtoV128,
-+ binop(Iop_Or64, get_vr_dw0(v2), highHalf),
-+ mkU64(0ULL));
-+ }
-+
-+ break;
-+ }
-+
-+ case 2: {
-+ /* Set sign to positive */
-+ if (!s390_vr_is_single_element_control_set(m4)) {
-+ result = unop(Iop_Abs64Fx2, get_vr_qw(v2));
-+ }
-+ else {
-+ result = binop(Iop_64HLtoV128,
-+ unop(Iop_ReinterpF64asI64,
-+ unop(Iop_AbsF64, get_vr(v2, Ity_F64, 0))),
-+ mkU64(0));
-+ }
-+
-+ break;
-+ }
-+
-+ default:
-+ vpanic("s390_irgen_VFPSO: Invalid m5 value");
-+ }
-+
-+ put_vr_qw(v1, result);
-+ if (s390_vr_is_single_element_control_set(m4)) {
-+ put_vr_dw1(v1, mkU64(0ULL));
-+ }
-+
-+ return "vfpso";
-+}
-+
-+static void s390x_vec_fp_binary_op(IROp generalOp, IROp singleElementOp,
-+ UChar v1, UChar v2, UChar v3, UChar m4,
-+ UChar m5)
-+{
-+ IRExpr* result;
-+ if (!s390_vr_is_single_element_control_set(m5)) {
-+ result = triop(generalOp, get_bfp_rounding_mode_from_fpc(),
-+ get_vr_qw(v2), get_vr_qw(v3));
-+ } else {
-+ IRExpr* highHalf = triop(singleElementOp,
-+ get_bfp_rounding_mode_from_fpc(),
-+ get_vr(v2, Ity_F64, 0),
-+ get_vr(v3, Ity_F64, 0));
-+ result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
-+ mkU64(0ULL));
-+ }
-+
-+ put_vr_qw(v1, result);
-+}
-+
-+static void s390x_vec_fp_unary_op(IROp generalOp, IROp singleElementOp,
-+ UChar v1, UChar v2, UChar m3, UChar m4)
-+{
-+ IRExpr* result;
-+ if (!s390_vr_is_single_element_control_set(m4)) {
-+ result = binop(generalOp, get_bfp_rounding_mode_from_fpc(),
-+ get_vr_qw(v2));
-+ }
-+ else {
-+ IRExpr* highHalf = binop(singleElementOp,
-+ get_bfp_rounding_mode_from_fpc(),
-+ get_vr(v2, Ity_F64, 0));
-+ result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
-+ mkU64(0ULL));
-+ }
-+
-+ put_vr_qw(v1, result);
-+}
-+
-+
-+static void
-+s390_vector_fp_mulAddOrSub(IROp singleElementOp,
-+ UChar v1, UChar v2, UChar v3, UChar v4,
-+ UChar m5, UChar m6)
-+{
-+ Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
-+ IRTemp irrm_temp = newTemp(Ity_I32);
-+ assign(irrm_temp, get_bfp_rounding_mode_from_fpc());
-+ IRExpr* irrm = mkexpr(irrm_temp);
-+ IRExpr* result;
-+ IRExpr* highHalf = qop(singleElementOp,
-+ irrm,
-+ get_vr(v2, Ity_F64, 0),
-+ get_vr(v3, Ity_F64, 0),
-+ get_vr(v4, Ity_F64, 0));
-+
-+ if (isSingleElementOp) {
-+ result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
-+ mkU64(0ULL));
-+ } else {
-+ IRExpr* lowHalf = qop(singleElementOp,
-+ irrm,
-+ get_vr(v2, Ity_F64, 1),
-+ get_vr(v3, Ity_F64, 1),
-+ get_vr(v4, Ity_F64, 1));
-+ result = binop(Iop_64HLtoV128, unop(Iop_ReinterpF64asI64, highHalf),
-+ unop(Iop_ReinterpF64asI64, lowHalf));
-+ }
-+
-+ put_vr_qw(v1, result);
-+}
-+
-+static const HChar *
-+s390_irgen_VFA(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vfa", m4 == 3);
-+ s390x_vec_fp_binary_op(Iop_Add64Fx2, Iop_AddF64, v1, v2, v3, m4, m5);
-+ return "vfa";
-+}
-+
-+static const HChar *
-+s390_irgen_VFS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vfs", m4 == 3);
-+ s390x_vec_fp_binary_op(Iop_Sub64Fx2, Iop_SubF64, v1, v2, v3, m4, m5);
-+ return "vfs";
-+}
-+
-+static const HChar *
-+s390_irgen_VFM(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vfm", m4 == 3);
-+ s390x_vec_fp_binary_op(Iop_Mul64Fx2, Iop_MulF64, v1, v2, v3, m4, m5);
-+ return "vfm";
-+}
-+
-+static const HChar *
-+s390_irgen_VFD(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vfd", m4 == 3);
-+ s390x_vec_fp_binary_op(Iop_Div64Fx2, Iop_DivF64, v1, v2, v3, m4, m5);
-+ return "vfd";
-+}
-+
-+static const HChar *
-+s390_irgen_VFSQ(UChar v1, UChar v2, UChar m3, UChar m4)
-+{
-+ s390_insn_assert("vfsq", m3 == 3);
-+ s390x_vec_fp_unary_op(Iop_Sqrt64Fx2, Iop_SqrtF64, v1, v2, m3, m4);
-+
-+ return "vfsq";
-+}
-+
-+static const HChar *
-+s390_irgen_VFMA(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6)
-+{
-+ s390_insn_assert("vfma", m6 == 3);
-+ s390_vector_fp_mulAddOrSub(Iop_MAddF64, v1, v2, v3, v4, m5, m6);
-+ return "vfma";
-+}
-+
-+static const HChar *
-+s390_irgen_VFMS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6)
-+{
-+ s390_insn_assert("vfms", m6 == 3);
-+ s390_vector_fp_mulAddOrSub(Iop_MSubF64, v1, v2, v3, v4, m5, m6);
-+ return "vfms";
-+}
-+
-+static const HChar *
-+s390_irgen_WFC(UChar v1, UChar v2, UChar m3, UChar m4)
-+{
-+ s390_insn_assert("wfc", m3 == 3);
-+ s390_insn_assert("wfc", m4 == 0);
-+
-+ IRTemp cc_vex = newTemp(Ity_I32);
-+ assign(cc_vex, binop(Iop_CmpF64,
-+ get_vr(v1, Ity_F64, 0), get_vr(v2, Ity_F64, 0)));
-+
-+ IRTemp cc_s390 = newTemp(Ity_I32);
-+ assign(cc_s390, convert_vex_bfpcc_to_s390(cc_vex));
-+ s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False);
-+
-+ return "wfc";
-+}
-+
-+static const HChar *
-+s390_irgen_WFK(UChar v1, UChar v2, UChar m3, UChar m4)
-+{
-+ s390_irgen_WFC(v1, v2, m3, m4);
-+
-+ return "wfk";
-+}
-+
-+static const HChar *
-+s390_irgen_VFCE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6)
-+{
-+ s390_insn_assert("vfce", m4 == 3);
-+
-+ Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
-+ if (!s390_vr_is_cs_set(m6)) {
-+ if (!isSingleElementOp) {
-+ put_vr_qw(v1, binop(Iop_CmpEQ64Fx2, get_vr_qw(v2), get_vr_qw(v3)));
-+ } else {
-+ IRExpr* comparisonResult = binop(Iop_CmpF64, get_vr(v2, Ity_F64, 0),
-+ get_vr(v3, Ity_F64, 0));
-+ IRExpr* result = mkite(binop(Iop_CmpEQ32, comparisonResult,
-+ mkU32(Ircr_EQ)),
-+ mkU64(0xffffffffffffffffULL),
-+ mkU64(0ULL));
-+ put_vr_qw(v1, binop(Iop_64HLtoV128, result, mkU64(0ULL)));
-+ }
-+ } else {
-+ IRDirty* d;
-+ IRTemp cc = newTemp(Ity_I64);
-+
-+ s390x_vec_op_details_t details = { .serialized = 0ULL };
-+ details.op = S390_VEC_OP_VFCE;
-+ details.v1 = v1;
-+ details.v2 = v2;
-+ details.v3 = v3;
-+ details.m4 = m4;
-+ details.m5 = m5;
-+ details.m6 = m6;
-+
-+ d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
-+ &s390x_dirtyhelper_vec_op,
-+ mkIRExprVec_2(IRExpr_GSPTR(),
-+ mkU64(details.serialized)));
-+
-+ const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
-+ d->nFxState = 3;
-+ vex_bzero(&d->fxState, sizeof(d->fxState));
-+ d->fxState[0].fx = Ifx_Read;
-+ d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
-+ d->fxState[0].size = elementSize;
-+ d->fxState[1].fx = Ifx_Read;
-+ d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v3 * sizeof(V128);
-+ d->fxState[1].size = elementSize;
-+ d->fxState[2].fx = Ifx_Write;
-+ d->fxState[2].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
-+ d->fxState[2].size = sizeof(V128);
-+
-+ stmt(IRStmt_Dirty(d));
-+ s390_cc_set(cc);
-+ }
-+
-+ return "vfce";
-+}
-+
-+static const HChar *
-+s390_irgen_VFCH(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6)
-+{
-+ vassert(m4 == 3);
-+
-+ Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
-+ if (!s390_vr_is_cs_set(m6)) {
-+ if (!isSingleElementOp) {
-+ put_vr_qw(v1, binop(Iop_CmpLE64Fx2, get_vr_qw(v3), get_vr_qw(v2)));
-+ } else {
-+ IRExpr* comparisonResult = binop(Iop_CmpF64, get_vr(v2, Ity_F64, 0),
-+ get_vr(v3, Ity_F64, 0));
-+ IRExpr* result = mkite(binop(Iop_CmpEQ32, comparisonResult,
-+ mkU32(Ircr_GT)),
-+ mkU64(0xffffffffffffffffULL),
-+ mkU64(0ULL));
-+ put_vr_qw(v1, binop(Iop_64HLtoV128, result, mkU64(0ULL)));
-+ }
-+ }
-+ else {
-+ IRDirty* d;
-+ IRTemp cc = newTemp(Ity_I64);
-+
-+ s390x_vec_op_details_t details = { .serialized = 0ULL };
-+ details.op = S390_VEC_OP_VFCH;
-+ details.v1 = v1;
-+ details.v2 = v2;
-+ details.v3 = v3;
-+ details.m4 = m4;
-+ details.m5 = m5;
-+ details.m6 = m6;
-+
-+ d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
-+ &s390x_dirtyhelper_vec_op,
-+ mkIRExprVec_2(IRExpr_GSPTR(),
-+ mkU64(details.serialized)));
-+
-+ const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
-+ d->nFxState = 3;
-+ vex_bzero(&d->fxState, sizeof(d->fxState));
-+ d->fxState[0].fx = Ifx_Read;
-+ d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
-+ d->fxState[0].size = elementSize;
-+ d->fxState[1].fx = Ifx_Read;
-+ d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v3 * sizeof(V128);
-+ d->fxState[1].size = elementSize;
-+ d->fxState[2].fx = Ifx_Write;
-+ d->fxState[2].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
-+ d->fxState[2].size = sizeof(V128);
-+
-+ stmt(IRStmt_Dirty(d));
-+ s390_cc_set(cc);
-+ }
-+
-+ return "vfch";
-+}
-+
-+static const HChar *
-+s390_irgen_VFCHE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6)
-+{
-+ s390_insn_assert("vfche", m4 == 3);
-+
-+ Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
-+ if (!s390_vr_is_cs_set(m6)) {
-+ if (!isSingleElementOp) {
-+ put_vr_qw(v1, binop(Iop_CmpLT64Fx2, get_vr_qw(v3), get_vr_qw(v2)));
-+ }
-+ else {
-+ IRExpr* comparisonResult = binop(Iop_CmpF64, get_vr(v3, Ity_F64, 0),
-+ get_vr(v2, Ity_F64, 0));
-+ IRExpr* result = mkite(binop(Iop_CmpEQ32, comparisonResult,
-+ mkU32(Ircr_LT)),
-+ mkU64(0xffffffffffffffffULL),
-+ mkU64(0ULL));
-+ put_vr_qw(v1, binop(Iop_64HLtoV128, result, mkU64(0ULL)));
-+ }
-+ }
-+ else {
-+ IRDirty* d;
-+ IRTemp cc = newTemp(Ity_I64);
-+
-+ s390x_vec_op_details_t details = { .serialized = 0ULL };
-+ details.op = S390_VEC_OP_VFCHE;
-+ details.v1 = v1;
-+ details.v2 = v2;
-+ details.v3 = v3;
-+ details.m4 = m4;
-+ details.m5 = m5;
-+ details.m6 = m6;
-+
-+ d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
-+ &s390x_dirtyhelper_vec_op,
-+ mkIRExprVec_2(IRExpr_GSPTR(),
-+ mkU64(details.serialized)));
-+
-+ const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
-+ d->nFxState = 3;
-+ vex_bzero(&d->fxState, sizeof(d->fxState));
-+ d->fxState[0].fx = Ifx_Read;
-+ d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
-+ d->fxState[0].size = elementSize;
-+ d->fxState[1].fx = Ifx_Read;
-+ d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v3 * sizeof(V128);
-+ d->fxState[1].size = elementSize;
-+ d->fxState[2].fx = Ifx_Write;
-+ d->fxState[2].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
-+ d->fxState[2].size = sizeof(V128);
-+
-+ stmt(IRStmt_Dirty(d));
-+ s390_cc_set(cc);
-+ }
-+
-+ return "vfche";
-+}
-+
-+static const HChar *
-+s390_irgen_VFTCI(UChar v1, UChar v2, UShort i3, UChar m4, UChar m5)
-+{
-+ s390_insn_assert("vftci", m4 == 3);
-+
-+ Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5);
-+
-+ IRDirty* d;
-+ IRTemp cc = newTemp(Ity_I64);
-+
-+ s390x_vec_op_details_t details = { .serialized = 0ULL };
-+ details.op = S390_VEC_OP_VFTCI;
-+ details.v1 = v1;
-+ details.v2 = v2;
-+ details.i3 = i3;
-+ details.m4 = m4;
-+ details.m5 = m5;
-+
-+ d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op",
-+ &s390x_dirtyhelper_vec_op,
-+ mkIRExprVec_2(IRExpr_GSPTR(),
-+ mkU64(details.serialized)));
-+
-+ const UChar elementSize = isSingleElementOp ? sizeof(ULong) : sizeof(V128);
-+ d->nFxState = 2;
-+ vex_bzero(&d->fxState, sizeof(d->fxState));
-+ d->fxState[0].fx = Ifx_Read;
-+ d->fxState[0].offset = S390X_GUEST_OFFSET(guest_v0) + v2 * sizeof(V128);
-+ d->fxState[0].size = elementSize;
-+ d->fxState[1].fx = Ifx_Write;
-+ d->fxState[1].offset = S390X_GUEST_OFFSET(guest_v0) + v1 * sizeof(V128);
-+ d->fxState[1].size = sizeof(V128);
-+
-+ stmt(IRStmt_Dirty(d));
-+ s390_cc_set(cc);
-+
-+ return "vftci";
-+}
-+
- /* New insns are added here.
- If an insn is contingent on a facility being installed also
- check whether the list of supported facilities in function
-@@ -19358,6 +20061,18 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- unsigned int op2 : 8;
- } VRR;
- struct {
-+ UInt op1 : 8;
-+ UInt v1 : 4;
-+ UInt v2 : 4;
-+ UInt v3 : 4;
-+ UInt : 4;
-+ UInt m5 : 4;
-+ UInt m4 : 4;
-+ UInt m3 : 4;
-+ UInt rxb : 4;
-+ UInt op2 : 8;
-+ } VRRa;
-+ struct {
- unsigned int op1 : 8;
- unsigned int v1 : 4;
- unsigned int v2 : 4;
-@@ -19370,6 +20085,18 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- unsigned int op2 : 8;
- } VRRd;
- struct {
-+ unsigned int op1 : 8;
-+ unsigned int v1 : 4;
-+ unsigned int v2 : 4;
-+ unsigned int v3 : 4;
-+ unsigned int m6 : 4;
-+ unsigned int : 4;
-+ unsigned int m5 : 4;
-+ unsigned int v4 : 4;
-+ unsigned int rxb : 4;
-+ unsigned int op2 : 8;
-+ } VRRe;
-+ struct {
- unsigned int op1 : 8;
- unsigned int v1 : 4;
- unsigned int v3 : 4;
-@@ -19390,6 +20117,16 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- unsigned int op2 : 8;
- } VRId;
- struct {
-+ UInt op1 : 8;
-+ UInt v1 : 4;
-+ UInt v2 : 4;
-+ UInt i3 : 12;
-+ UInt m5 : 4;
-+ UInt m4 : 4;
-+ UInt rxb : 4;
-+ UInt op2 : 8;
-+ } VRIe;
-+ struct {
- unsigned int op1 : 8;
- unsigned int v1 : 4;
- unsigned int v3 : 4;
-@@ -19974,7 +20711,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- case 0xe70000000046ULL: s390_format_VRI_VIM(s390_irgen_VGM, ovl.fmt.VRI.v1,
- ovl.fmt.VRI.i2, ovl.fmt.VRI.m3,
- ovl.fmt.VRI.rxb); goto ok;
-- case 0xe7000000004aULL: /* VFTCI */ goto unimplemented;
-+ case 0xe7000000004aULL: s390_format_VRI_VVIMM(s390_irgen_VFTCI, ovl.fmt.VRIe.v1,
-+ ovl.fmt.VRIe.v2, ovl.fmt.VRIe.i3,
-+ ovl.fmt.VRIe.m4, ovl.fmt.VRIe.m5,
-+ ovl.fmt.VRIe.rxb); goto ok;
- case 0xe7000000004dULL: s390_format_VRI_VVIM(s390_irgen_VREP, ovl.fmt.VRI.v1,
- ovl.fmt.VRI.v3, ovl.fmt.VRI.i2,
- ovl.fmt.VRI.m3, ovl.fmt.VRI.rxb); goto ok;
-@@ -20087,19 +20827,27 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
- ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb); goto ok;
- case 0xe70000000085ULL: /* VBPERM */ goto unimplemented;
-- case 0xe7000000008aULL: s390_format_VRRd_VVVVMM(s390_irgen_VSTRC, ovl.fmt.VRRd.v1,
-- ovl.fmt.VRRd.v2, ovl.fmt.VRRd.v3,
-- ovl.fmt.VRRd.v4, ovl.fmt.VRRd.m5,
-- ovl.fmt.VRRd.m6,
-- ovl.fmt.VRRd.rxb); goto ok;
-+ case 0xe7000000008aULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRC, ovl.fmt.VRRd.v1,
-+ ovl.fmt.VRRd.v2, ovl.fmt.VRRd.v3,
-+ ovl.fmt.VRRd.v4, ovl.fmt.VRRd.m5,
-+ ovl.fmt.VRRd.m6,
-+ ovl.fmt.VRRd.rxb); goto ok;
- case 0xe7000000008cULL: s390_format_VRR_VVVV(s390_irgen_VPERM, ovl.fmt.VRR.v1,
- ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
- ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb); goto ok;
- case 0xe7000000008dULL: s390_format_VRR_VVVV(s390_irgen_VSEL, ovl.fmt.VRR.v1,
- ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
- ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb); goto ok;
-- case 0xe7000000008eULL: /* VFMS */ goto unimplemented;
-- case 0xe7000000008fULL: /* VFMA */ goto unimplemented;
-+ case 0xe7000000008eULL: s390_format_VRR_VVVVMM(s390_irgen_VFMS, ovl.fmt.VRRe.v1,
-+ ovl.fmt.VRRe.v2, ovl.fmt.VRRe.v3,
-+ ovl.fmt.VRRe.v4, ovl.fmt.VRRe.m5,
-+ ovl.fmt.VRRe.m6,
-+ ovl.fmt.VRRe.rxb); goto ok;
-+ case 0xe7000000008fULL: s390_format_VRR_VVVVMM(s390_irgen_VFMA, ovl.fmt.VRRe.v1,
-+ ovl.fmt.VRRe.v2, ovl.fmt.VRRe.v3,
-+ ovl.fmt.VRRe.v4, ovl.fmt.VRRe.m5,
-+ ovl.fmt.VRRe.m6,
-+ ovl.fmt.VRRe.rxb); goto ok;
- case 0xe70000000094ULL: s390_format_VRR_VVVM(s390_irgen_VPK, ovl.fmt.VRR.v1,
- ovl.fmt.VRR.v2, ovl.fmt.VRR.r3,
- ovl.fmt.VRR.m4, ovl.fmt.VRR.rxb); goto ok;
-@@ -20184,17 +20932,50 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- ovl.fmt.VRRd.v2, ovl.fmt.VRRd.v3,
- ovl.fmt.VRRd.v4, ovl.fmt.VRRd.m5,
- ovl.fmt.VRRd.rxb); goto ok;
-- case 0xe700000000c0ULL: /* VCLGD */ goto unimplemented;
-- case 0xe700000000c1ULL: /* VCDLG */ goto unimplemented;
-- case 0xe700000000c2ULL: /* VCGD */ goto unimplemented;
-- case 0xe700000000c3ULL: /* VCDG */ goto unimplemented;
-- case 0xe700000000c4ULL: /* VLDE */ goto unimplemented;
-- case 0xe700000000c5ULL: /* VLED */ goto unimplemented;
-- case 0xe700000000c7ULL: /* VFI */ goto unimplemented;
-- case 0xe700000000caULL: /* WFK */ goto unimplemented;
-- case 0xe700000000cbULL: /* WFC */ goto unimplemented;
-- case 0xe700000000ccULL: /* VFPSO */ goto unimplemented;
-- case 0xe700000000ceULL: /* VFSQ */ goto unimplemented;
-+ case 0xe700000000c0ULL: s390_format_VRRa_VVMMM(s390_irgen_VCLGD, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000c1ULL: s390_format_VRRa_VVMMM(s390_irgen_VCDLG, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000c2ULL: s390_format_VRRa_VVMMM(s390_irgen_VCGD, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000c3ULL: s390_format_VRRa_VVMMM(s390_irgen_VCDG, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000c4ULL: s390_format_VRRa_VVMMM(s390_irgen_VLDE, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000c5ULL: s390_format_VRRa_VVMMM(s390_irgen_VLED, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000c7ULL: s390_format_VRRa_VVMMM(s390_irgen_VFI, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000caULL: s390_format_VRRa_VVMM(s390_irgen_WFK, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000cbULL: s390_format_VRRa_VVMM(s390_irgen_WFC, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000ccULL: s390_format_VRRa_VVMMM(s390_irgen_VFPSO, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4, ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000ceULL: s390_format_VRRa_VVMM(s390_irgen_VFSQ, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.m3,
-+ ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
- case 0xe700000000d4ULL: s390_format_VRR_VVM(s390_irgen_VUPLL, ovl.fmt.VRR.v1,
- ovl.fmt.VRR.v2, ovl.fmt.VRR.m4,
- ovl.fmt.VRR.rxb); goto ok;
-@@ -20221,13 +21002,37 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
- case 0xe700000000dfULL: s390_format_VRR_VVM(s390_irgen_VLP, ovl.fmt.VRR.v1,
- ovl.fmt.VRR.v2, ovl.fmt.VRR.m4,
- ovl.fmt.VRR.rxb); goto ok;
-- case 0xe700000000e2ULL: /* VFS */ goto unimplemented;
-- case 0xe700000000e3ULL: /* VFA */ goto unimplemented;
-- case 0xe700000000e5ULL: /* VFD */ goto unimplemented;
-- case 0xe700000000e7ULL: /* VFM */ goto unimplemented;
-- case 0xe700000000e8ULL: /* VFCE */ goto unimplemented;
-- case 0xe700000000eaULL: /* VFCHE */ goto unimplemented;
-- case 0xe700000000ebULL: /* VFCH */ goto unimplemented;
-+ case 0xe700000000e2ULL: s390_format_VRRa_VVVMM(s390_irgen_VFS, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000e3ULL: s390_format_VRRa_VVVMM(s390_irgen_VFA, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000e5ULL: s390_format_VRRa_VVVMM(s390_irgen_VFD, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000e7ULL: s390_format_VRRa_VVVMM(s390_irgen_VFM, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000e8ULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCE, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000eaULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCHE, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
-+ case 0xe700000000ebULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCH, ovl.fmt.VRRa.v1,
-+ ovl.fmt.VRRa.v2, ovl.fmt.VRRa.v3,
-+ ovl.fmt.VRRa.m3, ovl.fmt.VRRa.m4,
-+ ovl.fmt.VRRa.m5,
-+ ovl.fmt.VRRa.rxb); goto ok;
- case 0xe700000000eeULL: /* VFMIN */ goto unimplemented;
- case 0xe700000000efULL: /* VFMAX */ goto unimplemented;
- case 0xe700000000f0ULL: s390_format_VRR_VVVM(s390_irgen_VAVGL, ovl.fmt.VRR.v1,
-@@ -21148,7 +21953,13 @@ s390_decode_and_irgen(const UChar *bytes, UInt insn_length, DisResult *dres)
- dis_res->jk_StopHere = Ijk_Boring;
- }
-
-- if (status == S390_DECODE_OK) return insn_length; /* OK */
-+ if (status == S390_DECODE_OK) {
-+ /* Adjust status if a specification exception was indicated. */
-+ if (is_specification_exception())
-+ status = S390_DECODE_SPECIFICATION_EXCEPTION;
-+ else
-+ return insn_length; /* OK */
-+ }
-
- /* Decoding failed somehow */
- if (sigill_diag) {
-@@ -21166,6 +21977,10 @@ s390_decode_and_irgen(const UChar *bytes, UInt insn_length, DisResult *dres)
- vex_printf("unimplemented special insn: ");
- break;
-
-+ case S390_DECODE_SPECIFICATION_EXCEPTION:
-+ vex_printf("specification exception: ");
-+ break;
-+
- case S390_DECODE_ERROR:
- vex_printf("decoding error: ");
- break;
-diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
-index 98ac938..22cdd04 100644
---- a/VEX/priv/host_s390_defs.c
-+++ b/VEX/priv/host_s390_defs.c
-@@ -1711,6 +1711,23 @@ emit_VRR_VVM(UChar *p, ULong op, UChar v1, UChar v2, UChar m4)
- return emit_6bytes(p, the_insn);
- }
-
-+static UChar *
-+emit_VRR_VVMMM(UChar *p, ULong op, UChar v1, UChar v2, UChar m3, UChar m4,
-+ UChar m5)
-+{
-+ ULong the_insn = op;
-+ ULong rxb = s390_update_rxb(0, 1, &v1);
-+ rxb = s390_update_rxb(rxb, 2, &v2);
-+
-+ the_insn |= ((ULong)v1) << 36;
-+ the_insn |= ((ULong)v2) << 32;
-+ the_insn |= ((ULong)m5) << 20;
-+ the_insn |= ((ULong)m4) << 16;
-+ the_insn |= ((ULong)m3) << 12;
-+ the_insn |= ((ULong)rxb) << 8;
-+
-+ return emit_6bytes(p, the_insn);
-+}
-
- static UChar *
- emit_VRR_VVVM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4)
-@@ -1762,6 +1779,26 @@ emit_VRR_VVVV(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar v4)
- return emit_6bytes(p, the_insn);
- }
-
-+static UChar *
-+emit_VRRe_VVVVMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar v4,
-+ UChar m5, UChar m6)
-+{
-+ ULong the_insn = op;
-+ ULong rxb = s390_update_rxb(0, 1, &v1);
-+ rxb = s390_update_rxb(rxb, 2, &v2);
-+ rxb = s390_update_rxb(rxb, 3, &v3);
-+ rxb = s390_update_rxb(rxb, 4, &v4);
-+
-+ the_insn |= ((ULong)v1) << 36;
-+ the_insn |= ((ULong)v2) << 32;
-+ the_insn |= ((ULong)v3) << 28;
-+ the_insn |= ((ULong)m6) << 24;
-+ the_insn |= ((ULong)m5) << 16;
-+ the_insn |= ((ULong)v4) << 12;
-+ the_insn |= ((ULong)rxb) << 8;
-+
-+ return emit_6bytes(p, the_insn);
-+}
-
- static UChar *
- emit_VRR_VRR(UChar *p, ULong op, UChar v1, UChar r2, UChar r3)
-@@ -1777,6 +1814,33 @@ emit_VRR_VRR(UChar *p, ULong op, UChar v1, UChar r2, UChar r3)
- return emit_6bytes(p, the_insn);
- }
-
-+static UChar *
-+emit_VRR_VVVMMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4,
-+ UChar m5, UChar m6)
-+{
-+ ULong the_insn = op;
-+ ULong rxb = s390_update_rxb(0, 1, &v1);
-+ rxb = s390_update_rxb(rxb, 2, &v2);
-+ rxb = s390_update_rxb(rxb, 3, &v3);
-+
-+ the_insn |= ((ULong)v1) << 36;
-+ the_insn |= ((ULong)v2) << 32;
-+ the_insn |= ((ULong)v3) << 28;
-+ the_insn |= ((ULong)m6) << 20;
-+ the_insn |= ((ULong)m5) << 16;
-+ the_insn |= ((ULong)m4) << 12;
-+ the_insn |= ((ULong)rxb) << 8;
-+
-+ return emit_6bytes(p, the_insn);
-+}
-+
-+static UChar*
-+emit_VRR_VVVMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4,
-+ UChar m5)
-+{
-+ return emit_VRR_VVVMMM(p, op, v1, v2, v3, m4, m5, 0);
-+}
-+
- /*------------------------------------------------------------*/
- /*--- Functions to emit particular instructions ---*/
- /*------------------------------------------------------------*/
-@@ -6057,6 +6121,116 @@ s390_emit_VLVGP(UChar *p, UChar v1, UChar r2, UChar r3)
- return emit_VRR_VRR(p, 0xE70000000062ULL, v1, r2, r3);
- }
-
-+static UChar *
-+s390_emit_VFPSO(UChar *p, UChar v1, UChar v2, UChar m3, UChar m4, UChar m5)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC6(MNM, VR, VR, UINT, UINT, UINT), "vfpso", v1, v2, m3, m4,
-+ m5);
-+
-+ return emit_VRR_VVMMM(p, 0xE700000000CCULL, v1, v2, m3, m4, m5);
-+}
-+
-+static UChar *
-+s390_emit_VFA(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfa", v1, v2, v3, m4, m5);
-+
-+ return emit_VRR_VVVMM(p, 0xE700000000e3ULL, v1, v2, v3, m4, m5);
-+}
-+
-+static UChar *
-+s390_emit_VFS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfs", v1, v2, v3, m4, m5);
-+
-+ return emit_VRR_VVVMM(p, 0xE700000000e2ULL, v1, v2, v3, m4, m5);
-+}
-+
-+static UChar *
-+s390_emit_VFM(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfm", v1, v2, v3, m4, m5);
-+
-+ return emit_VRR_VVVMM(p, 0xE700000000e7ULL, v1, v2, v3, m4, m5);
-+}
-+
-+static UChar *
-+s390_emit_VFD(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC6(MNM, VR, VR, VR, UINT, UINT), "vfd", v1, v2, v3, m4, m5);
-+
-+ return emit_VRR_VVVMM(p, 0xE700000000e5ULL, v1, v2, v3, m4, m5);
-+}
-+
-+static UChar *
-+s390_emit_VFSQ(UChar *p, UChar v1, UChar v2, UChar m3, UChar m4)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC5(MNM, VR, VR, UINT, UINT), "vfsq", v1, v2, m3, m4);
-+
-+ return emit_VRR_VVMMM(p, 0xE700000000CEULL, v1, v2, m3, m4, 0);
-+}
-+
-+static UChar *
-+s390_emit_VFMA(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4, UChar m5,
-+ UChar m6)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC7(MNM, VR, VR, VR, VR, UINT, UINT), "vfma",
-+ v1, v2, v3, v4, m5, m6);
-+
-+ return emit_VRRe_VVVVMM(p, 0xE7000000008fULL, v1, v2, v3, v4, m5, m6);
-+}
-+
-+static UChar *
-+s390_emit_VFMS(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4, UChar m5,
-+ UChar m6)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC7(MNM, VR, VR, VR, VR, UINT, UINT), "vfms",
-+ v1, v2, v3, v4, m5, m6);
-+
-+ return emit_VRRe_VVVVMM(p, 0xE7000000008eULL, v1, v2, v3, v4, m5, m6);
-+}
-+
-+static UChar *
-+s390_emit_VFCE(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
-+ UChar m6)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC7(MNM, VR, VR, VR, UINT, UINT, UINT), "vfce",
-+ v1, v2, v3, m4, m5, m6);
-+
-+ return emit_VRR_VVVMMM(p, 0xE700000000e8ULL, v1, v2, v3, m4, m5, m6);
-+}
-+
-+static UChar *
-+s390_emit_VFCH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
-+ UChar m6)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC7(MNM, VR, VR, VR, UINT, UINT, UINT), "vfch",
-+ v1, v2, v3, m4, m5, m6);
-+
-+ return emit_VRR_VVVMMM(p, 0xE700000000ebULL, v1, v2, v3, m4, m5, m6);
-+}
-+
-+static UChar *
-+s390_emit_VFCHE(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
-+ UChar m6)
-+{
-+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-+ s390_disasm(ENC7(MNM, VR, VR, VR, UINT, UINT, UINT), "vfche",
-+ v1, v2, v3, m4, m5, m6);
-+
-+ return emit_VRR_VVVMMM(p, 0xE700000000eaULL, v1, v2, v3, m4, m5, m6);
-+}
-+
- /*---------------------------------------------------------------*/
- /*--- Constructors for the various s390_insn kinds ---*/
- /*---------------------------------------------------------------*/
-@@ -7201,7 +7375,6 @@ s390_insn *s390_insn_vec_triop(UChar size, s390_vec_triop_t tag, HReg dst,
- {
- s390_insn *insn = LibVEX_Alloc_inline(sizeof(s390_insn));
-
-- vassert(size == 16);
-
- insn->tag = S390_INSN_VEC_TRIOP;
- insn->size = size;
-@@ -7508,6 +7681,18 @@ s390_insn_as_string(const s390_insn *insn)
- op = "v-vunpacku";
- break;
-
-+ case S390_VEC_FLOAT_NEG:
-+ op = "v-vfloatneg";
-+ break;
-+
-+ case S390_VEC_FLOAT_SQRT:
-+ op = "v-vfloatsqrt";
-+ break;
-+
-+ case S390_VEC_FLOAT_ABS:
-+ op = "v-vfloatabs";
-+ break;
-+
- default:
- goto fail;
- }
-@@ -7880,6 +8065,13 @@ s390_insn_as_string(const s390_insn *insn)
- case S390_VEC_PWSUM_DW: op = "v-vpwsumdw"; break;
- case S390_VEC_PWSUM_QW: op = "v-vpwsumqw"; break;
- case S390_VEC_INIT_FROM_GPRS: op = "v-vinitfromgprs"; break;
-+ case S390_VEC_FLOAT_ADD: op = "v-vfloatadd"; break;
-+ case S390_VEC_FLOAT_SUB: op = "v-vfloatsub"; break;
-+ case S390_VEC_FLOAT_MUL: op = "v-vfloatmul"; break;
-+ case S390_VEC_FLOAT_DIV: op = "v-vfloatdiv"; break;
-+ case S390_VEC_FLOAT_COMPARE_EQUAL: op = "v-vfloatcmpeq"; break;
-+ case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL: op = "v-vfloatcmple"; break;
-+ case S390_VEC_FLOAT_COMPARE_LESS: op = "v-vfloatcmpl"; break;
- default: goto fail;
- }
- s390_sprintf(buf, "%M %R, %R, %R", op, insn->variant.vec_binop.dst,
-@@ -7889,6 +8081,8 @@ s390_insn_as_string(const s390_insn *insn)
- case S390_INSN_VEC_TRIOP:
- switch (insn->variant.vec_triop.tag) {
- case S390_VEC_PERM: op = "v-vperm"; break;
-+ case S390_VEC_FLOAT_MADD: op = "v-vfloatmadd"; break;
-+ case S390_VEC_FLOAT_MSUB: op = "v-vfloatmsub"; break;
- default: goto fail;
- }
- s390_sprintf(buf, "%M %R, %R, %R, %R", op, insn->variant.vec_triop.dst,
-@@ -9036,6 +9230,27 @@ s390_insn_unop_emit(UChar *buf, const s390_insn *insn)
- return s390_emit_VPOPCT(buf, v1, v2, s390_getM_from_size(insn->size));
- }
-
-+ case S390_VEC_FLOAT_NEG: {
-+ vassert(insn->variant.unop.src.tag == S390_OPND_REG);
-+ vassert(insn->size == 8);
-+ UChar v1 = hregNumber(insn->variant.unop.dst);
-+ UChar v2 = hregNumber(insn->variant.unop.src.variant.reg);
-+ return s390_emit_VFPSO(buf, v1, v2, s390_getM_from_size(insn->size), 0, 0);
-+ }
-+ case S390_VEC_FLOAT_ABS: {
-+ vassert(insn->variant.unop.src.tag == S390_OPND_REG);
-+ vassert(insn->size == 8);
-+ UChar v1 = hregNumber(insn->variant.unop.dst);
-+ UChar v2 = hregNumber(insn->variant.unop.src.variant.reg);
-+ return s390_emit_VFPSO(buf, v1, v2, s390_getM_from_size(insn->size), 0, 2);
-+ }
-+ case S390_VEC_FLOAT_SQRT: {
-+ vassert(insn->variant.unop.src.tag == S390_OPND_REG);
-+ vassert(insn->size == 8);
-+ UChar v1 = hregNumber(insn->variant.unop.dst);
-+ UChar v2 = hregNumber(insn->variant.unop.src.variant.reg);
-+ return s390_emit_VFSQ(buf, v1, v2, s390_getM_from_size(insn->size), 0);
-+ }
- default:
- vpanic("s390_insn_unop_emit");
- }
-@@ -11049,6 +11264,21 @@ s390_insn_vec_binop_emit(UChar *buf, const s390_insn *insn)
- return s390_emit_VSUMQ(buf, v1, v2, v3, s390_getM_from_size(size));
- case S390_VEC_INIT_FROM_GPRS:
- return s390_emit_VLVGP(buf, v1, v2, v3);
-+ case S390_VEC_FLOAT_ADD:
-+ return s390_emit_VFA(buf, v1, v2, v3, s390_getM_from_size(size), 0);
-+ case S390_VEC_FLOAT_SUB:
-+ return s390_emit_VFS(buf, v1, v2, v3, s390_getM_from_size(size), 0);
-+ case S390_VEC_FLOAT_MUL:
-+ return s390_emit_VFM(buf, v1, v2, v3, s390_getM_from_size(size), 0);
-+ case S390_VEC_FLOAT_DIV:
-+ return s390_emit_VFD(buf, v1, v2, v3, s390_getM_from_size(size), 0);
-+ case S390_VEC_FLOAT_COMPARE_EQUAL:
-+ return s390_emit_VFCE(buf, v1, v2, v3, s390_getM_from_size(size), 0, 0);
-+ case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL:
-+ return s390_emit_VFCH(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0);
-+ case S390_VEC_FLOAT_COMPARE_LESS:
-+ return s390_emit_VFCHE(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0);
-+
- default:
- goto fail;
- }
-@@ -11070,8 +11300,14 @@ s390_insn_vec_triop_emit(UChar *buf, const s390_insn *insn)
- UChar v4 = hregNumber(insn->variant.vec_triop.op3);
-
- switch (tag) {
-- case S390_VEC_PERM:
-+ case S390_VEC_PERM: {
-+ vassert(insn->size == 16);
- return s390_emit_VPERM(buf, v1, v2, v3, v4);
-+ }
-+ case S390_VEC_FLOAT_MADD:
-+ return s390_emit_VFMA(buf, v1, v2, v3, v4, 0, 3);
-+ case S390_VEC_FLOAT_MSUB:
-+ return s390_emit_VFMS(buf, v1, v2, v3, v4, 0, 3);
- default:
- goto fail;
- }
-diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h
-index 7ea0101..40f0472 100644
---- a/VEX/priv/host_s390_defs.h
-+++ b/VEX/priv/host_s390_defs.h
-@@ -202,7 +202,10 @@ typedef enum {
- S390_VEC_ABS,
- S390_VEC_COUNT_LEADING_ZEROES,
- S390_VEC_COUNT_TRAILING_ZEROES,
-- S390_VEC_COUNT_ONES
-+ S390_VEC_COUNT_ONES,
-+ S390_VEC_FLOAT_NEG,
-+ S390_VEC_FLOAT_ABS,
-+ S390_VEC_FLOAT_SQRT
- } s390_unop_t;
-
- /* The kind of ternary BFP operations */
-@@ -394,11 +397,20 @@ typedef enum {
- S390_VEC_PWSUM_QW,
-
- S390_VEC_INIT_FROM_GPRS,
-+ S390_VEC_FLOAT_ADD,
-+ S390_VEC_FLOAT_SUB,
-+ S390_VEC_FLOAT_MUL,
-+ S390_VEC_FLOAT_DIV,
-+ S390_VEC_FLOAT_COMPARE_EQUAL,
-+ S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL,
-+ S390_VEC_FLOAT_COMPARE_LESS
- } s390_vec_binop_t;
-
- /* The vector operations with three operands */
- typedef enum {
-- S390_VEC_PERM
-+ S390_VEC_PERM,
-+ S390_VEC_FLOAT_MADD,
-+ S390_VEC_FLOAT_MSUB
- } s390_vec_triop_t;
-
- /* The details of a CDAS insn. Carved out to keep the size of
-diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c
-index bc34f90..79581ff 100644
---- a/VEX/priv/host_s390_isel.c
-+++ b/VEX/priv/host_s390_isel.c
-@@ -787,10 +787,12 @@ get_bfp_rounding_mode(ISelEnv *env, IRExpr *irrm)
- IRRoundingMode mode = irrm->Iex.Const.con->Ico.U32;
-
- switch (mode) {
-- case Irrm_NEAREST: return S390_BFP_ROUND_NEAREST_EVEN;
-- case Irrm_ZERO: return S390_BFP_ROUND_ZERO;
-- case Irrm_PosINF: return S390_BFP_ROUND_POSINF;
-- case Irrm_NegINF: return S390_BFP_ROUND_NEGINF;
-+ case Irrm_NEAREST_TIE_AWAY_0: return S390_BFP_ROUND_NEAREST_AWAY;
-+ case Irrm_PREPARE_SHORTER: return S390_BFP_ROUND_PREPARE_SHORT;
-+ case Irrm_NEAREST: return S390_BFP_ROUND_NEAREST_EVEN;
-+ case Irrm_ZERO: return S390_BFP_ROUND_ZERO;
-+ case Irrm_PosINF: return S390_BFP_ROUND_POSINF;
-+ case Irrm_NegINF: return S390_BFP_ROUND_NEGINF;
- default:
- vpanic("get_bfp_rounding_mode");
- }
-@@ -3871,6 +3873,17 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
- vec_op = S390_VEC_COUNT_ONES;
- goto Iop_V_wrk;
-
-+ case Iop_Neg64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_NEG;
-+ goto Iop_V_wrk;
-+
-+ case Iop_Abs64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_ABS;
-+ goto Iop_V_wrk;
-+
-+
- Iop_V_wrk: {
- dst = newVRegV(env);
- reg1 = s390_isel_vec_expr(env, arg);
-@@ -4388,6 +4401,28 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
- vec_op = S390_VEC_ELEM_ROLL_V;
- goto Iop_VV_wrk;
-
-+ case Iop_CmpEQ64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_COMPARE_EQUAL;
-+ goto Iop_VV_wrk;
-+
-+ case Iop_CmpLE64Fx2: {
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL;
-+ goto Iop_VV_wrk;
-+ }
-+
-+ case Iop_CmpLT64Fx2: {
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_COMPARE_LESS;
-+ goto Iop_VV_wrk;
-+ }
-+
-+ case Iop_Sqrt64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_SQRT;
-+ goto Iop_irrm_V_wrk;
-+
- case Iop_ShlN8x16:
- size = 1;
- shift_op = S390_VEC_ELEM_SHL_INT;
-@@ -4493,6 +4528,14 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
- return dst;
- }
-
-+ Iop_irrm_V_wrk: {
-+ set_bfp_rounding_mode_in_fpc(env, arg1);
-+ reg1 = s390_isel_vec_expr(env, arg2);
-+
-+ addInstr(env, s390_insn_unop(size, vec_op, dst, s390_opnd_reg(reg1)));
-+ return dst;
-+ }
-+
- case Iop_64HLtoV128:
- reg1 = s390_isel_int_expr(env, arg1);
- reg2 = s390_isel_int_expr(env, arg2);
-@@ -4516,6 +4559,7 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
- IRExpr* arg1 = expr->Iex.Triop.details->arg1;
- IRExpr* arg2 = expr->Iex.Triop.details->arg2;
- IRExpr* arg3 = expr->Iex.Triop.details->arg3;
-+ IROp vec_op;
- switch (op) {
- case Iop_SetElem8x16:
- size = 1;
-@@ -4551,6 +4595,36 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr)
- dst, reg1, reg2, reg3));
- return dst;
-
-+ case Iop_Add64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_ADD;
-+ goto Iop_irrm_VV_wrk;
-+
-+ case Iop_Sub64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_SUB;
-+ goto Iop_irrm_VV_wrk;
-+
-+ case Iop_Mul64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_MUL;
-+ goto Iop_irrm_VV_wrk;
-+ case Iop_Div64Fx2:
-+ size = 8;
-+ vec_op = S390_VEC_FLOAT_DIV;
-+ goto Iop_irrm_VV_wrk;
-+
-+ Iop_irrm_VV_wrk: {
-+ set_bfp_rounding_mode_in_fpc(env, arg1);
-+ reg1 = s390_isel_vec_expr(env, arg2);
-+ reg2 = s390_isel_vec_expr(env, arg3);
-+
-+ addInstr(env, s390_insn_vec_binop(size, vec_op,
-+ dst, reg1, reg2));
-+
-+ return dst;
-+ }
-+
- default:
- goto irreducible;
- }
diff --git a/valgrind-3.14.0-s390x-vec-float-point-tests.patch b/valgrind-3.14.0-s390x-vec-float-point-tests.patch
deleted file mode 100644
index a9e3866..0000000
--- a/valgrind-3.14.0-s390x-vec-float-point-tests.patch
+++ /dev/null
@@ -1,2316 +0,0 @@
-commit 86bd889458883295b73c36696ec64dea9338a7a3
-Author: Vadim Barkov <vbrkov@gmail.com>
-Date: Fri Oct 5 13:46:44 2018 +0300
-
- Bug 385411 s390x: Tests and internals for z13 vector FP support
-
- Add test cases for the z13 vector FP support. Bring s390-opcodes.csv
- up-to-date, reflecting that the z13 vector instructions are now supported.
- Also remove the non-support disclaimer for the vector facility from
- README.s390.
-
- The patch was contributed by Vadim Barkov, with some clean-up and minor
- adjustments by Andreas Arnez.
-
-diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am
-index 77c00ba..097c85a 100644
---- a/none/tests/s390x/Makefile.am
-+++ b/none/tests/s390x/Makefile.am
-@@ -18,7 +18,8 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \
- spechelper-cr spechelper-clr \
- spechelper-ltr spechelper-or \
- spechelper-icm-1 spechelper-icm-2 spechelper-tmll \
-- spechelper-tm laa vector lsc2 ppno vector_string vector_integer
-+ spechelper-tm laa vector lsc2 ppno vector_string vector_integer \
-+ vector_float
-
- if BUILD_DFP_TESTS
- INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo
-@@ -71,4 +72,4 @@ vector_CFLAGS = $(AM_CFLAGS) -march=z13
- lsc2_CFLAGS = -march=z13 -DS390_TESTS_NOCOLOR
- vector_string_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=5
- vector_integer_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4
--
-+vector_float_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4
-diff --git a/none/tests/s390x/vector.h b/none/tests/s390x/vector.h
-index adefbcd..de23914 100644
---- a/none/tests/s390x/vector.h
-+++ b/none/tests/s390x/vector.h
-@@ -12,17 +12,21 @@
- #endif
-
- /* Test the instruction exactly one time. */
--#define test_once(insn) test_##insn()
-+#define test_once(insn) test_##insn ()
-
- /* Test the instruction exactly S390_TEST_COUNT times.
- "..." arguments specifies code which must be executed after each tests
- */
- #define test(insn, ...) \
- for(iteration = 0; iteration < S390_TEST_COUNT; iteration++) \
-- { test_##insn(); \
-+ { test_once(insn); \
- __VA_ARGS__; \
- }
-
-+#define test_with_selective_printing(insn, info) \
-+ for(iteration = 0; iteration < S390_TEST_COUNT; iteration++) \
-+ { test_ ## insn ## _selective(info); }
-+
- #ifdef __GNUC__
- /* GCC complains about __int128 with -pedantic */
- /* Hope that we will have int128_t in C standard someday. */
-@@ -38,18 +42,67 @@ typedef union {
-
- uint32_t u32[4];
- int32_t s32[4];
-+ float f32[4];
-
- uint64_t u64[2];
- int64_t s64[2];
-+ double f64[2];
-
- unsigned __int128 u128[1];
- __int128 s128[1];
- } V128;
-
-+typedef enum {
-+ V128_NO_PRINTING = 0,
-+ V128_V_RES_AS_INT = 1 << 0,
-+ V128_V_ARG1_AS_INT = 1 << 1,
-+ V128_V_ARG2_AS_INT = 1 << 2,
-+ V128_V_ARG3_AS_INT = 1 << 3,
-+ V128_V_RES_AS_FLOAT64 = 1 << 4,
-+ V128_V_ARG1_AS_FLOAT64 = 1 << 5,
-+ V128_V_ARG2_AS_FLOAT64 = 1 << 6,
-+ V128_V_ARG3_AS_FLOAT64 = 1 << 7,
-+ V128_V_RES_AS_FLOAT32 = 1 << 8,
-+ V128_V_ARG1_AS_FLOAT32 = 1 << 9,
-+ V128_V_ARG2_AS_FLOAT32 = 1 << 10,
-+ V128_V_ARG3_AS_FLOAT32 = 1 << 11,
-+ V128_R_RES = 1 << 12,
-+ V128_R_ARG1 = 1 << 13,
-+ V128_R_ARG2 = 1 << 14,
-+ V128_R_ARG3 = 1 << 15,
-+ V128_V_RES_EVEN_ONLY = 1 << 16,
-+ V128_V_RES_ZERO_ONLY = 1 << 17,
-+ V128_PRINT_ALL = (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_INT |
-+ V128_V_ARG2_AS_INT |
-+ V128_V_ARG3_AS_INT |
-+ V128_R_RES |
-+ V128_R_ARG1 |
-+ V128_R_ARG2 |
-+ V128_R_ARG3),
-+} s390x_test_usageInfo;
-+
- void print_hex(const V128 value) {
- printf("%016lx | %016lx\n", value.u64[0], value.u64[1]);
- }
-
-+void print_f32(const V128 value, int even_only, int zero_only) {
-+ if (zero_only)
-+ printf("%a | -- | -- | --\n", value.f32[0]);
-+ else if (even_only)
-+ printf("%a | -- | %a | --\n", value.f32[0], value.f32[2]);
-+ else
-+ printf("%a | %a | %a | %a\n",
-+ value.f32[0], value.f32[1], value.f32[2], value.f32[3]);
-+}
-+
-+void print_f64(const V128 value, int zero_only) {
-+ if (zero_only)
-+ printf("%a | --\n", value.f64[0]);
-+ else
-+ printf("%a | %a\n", value.f64[0], value.f64[1]);
-+}
-+
- void print_uint64_t(const uint64_t value) {
- printf("%016lx\n", value);
- }
-@@ -118,7 +171,7 @@ void randomize_memory_pool()
-
- */
- #define s390_test_generate(insn, asm_string) \
--static void test_##insn() \
-+static void test_##insn##_selective(const s390x_test_usageInfo info) \
- { \
- V128 v_result = { .u64 = {0ULL, 0ULL} }; \
- V128 v_arg1; \
-@@ -138,6 +191,7 @@ static void test_##insn() \
- "vl %%v2, %[v_arg2]\n" \
- "vl %%v3, %[v_arg3]\n" \
- "vone %%v5\n" \
-+ "srnmb 1(0)\n " \
- asm_string "\n"\
- "vst %%v5, %[v_result]\n" \
- "vst %%v1, %[v_arg1]\n" \
-@@ -162,14 +216,49 @@ static void test_##insn() \
- "v1", "v2", "v3", "v5"); \
- \
- printf("insn %s:\n", #insn); \
-- printf(" v_arg1 = "); print_hex(v_arg1); \
-- printf(" v_arg2 = "); print_hex(v_arg2); \
-- printf(" v_arg3 = "); print_hex(v_arg3); \
-- printf(" v_result = "); print_hex(v_result); \
-- printf(" r_arg1 = "); print_uint64_t(r_arg1); \
-- printf(" r_arg2 = "); print_uint64_t(r_arg2); \
-- printf(" r_arg3 = "); print_uint64_t(r_arg3); \
-- printf(" r_result = "); print_uint64_t(r_result); \
-+ if (info & V128_V_ARG1_AS_INT) \
-+ {printf(" v_arg1 = "); print_hex(v_arg1);} \
-+ if (info & V128_V_ARG2_AS_INT) \
-+ {printf(" v_arg2 = "); print_hex(v_arg2);} \
-+ if (info & V128_V_ARG3_AS_INT) \
-+ {printf(" v_arg3 = "); print_hex(v_arg3);} \
-+ if (info & V128_V_RES_AS_INT) \
-+ {printf(" v_result = "); print_hex(v_result);} \
-+ \
-+ if (info & V128_V_ARG1_AS_FLOAT64) \
-+ {printf(" v_arg1 = "); print_f64(v_arg1, 0);} \
-+ if (info & V128_V_ARG2_AS_FLOAT64) \
-+ {printf(" v_arg2 = "); print_f64(v_arg2, 0);} \
-+ if (info & V128_V_ARG3_AS_FLOAT64) \
-+ {printf(" v_arg3 = "); print_f64(v_arg3, 0);} \
-+ if (info & V128_V_RES_AS_FLOAT64) { \
-+ printf(" v_result = "); \
-+ print_f64(v_result, info & V128_V_RES_ZERO_ONLY); \
-+ } \
-+ \
-+ if (info & V128_V_ARG1_AS_FLOAT32) \
-+ {printf(" v_arg1 = "); print_f32(v_arg1, 0, 0);} \
-+ if (info & V128_V_ARG2_AS_FLOAT32) \
-+ {printf(" v_arg2 = "); print_f32(v_arg2, 0, 0);} \
-+ if (info & V128_V_ARG3_AS_FLOAT32) \
-+ {printf(" v_arg3 = "); print_f32(v_arg3, 0, 0);} \
-+ if (info & V128_V_RES_AS_FLOAT32) { \
-+ printf(" v_result = "); \
-+ print_f32(v_result, info & V128_V_RES_EVEN_ONLY, \
-+ info & V128_V_RES_ZERO_ONLY); \
-+ } \
-+ if (info & V128_R_ARG1) \
-+ {printf(" r_arg1 = "); print_uint64_t(r_arg1);} \
-+ if (info & V128_R_ARG2) \
-+ {printf(" r_arg2 = "); print_uint64_t(r_arg2);} \
-+ if (info & V128_R_ARG3) \
-+ {printf(" r_arg3 = "); print_uint64_t(r_arg3);} \
-+ if (info & V128_R_RES) \
-+ {printf(" r_result = "); print_uint64_t(r_result);} \
-+} \
-+__attribute__((unused)) static void test_##insn() \
-+{ \
-+ test_##insn##_selective (V128_PRINT_ALL); \
- }
-
- /* Stores CC to %[r_result].
-diff --git a/none/tests/s390x/vector_float.c b/none/tests/s390x/vector_float.c
-new file mode 100644
-index 0000000..52f3a29
---- /dev/null
-+++ b/none/tests/s390x/vector_float.c
-@@ -0,0 +1,275 @@
-+#include "vector.h"
-+
-+#define s390_generate_float_test(insn, asm_string) \
-+ s390_test_generate(v##insn##00, "v" #insn " " asm_string ",0, 0") \
-+ s390_test_generate(v##insn##01, "v" #insn " " asm_string ",0, 1") \
-+ s390_test_generate(v##insn##03, "v" #insn " " asm_string ",0, 3") \
-+ s390_test_generate(v##insn##04, "v" #insn " " asm_string ",0, 4") \
-+ s390_test_generate(v##insn##05, "v" #insn " " asm_string ",0, 5") \
-+ s390_test_generate(v##insn##06, "v" #insn " " asm_string ",0, 6") \
-+ s390_test_generate(v##insn##07, "v" #insn " " asm_string ",0, 7") \
-+ s390_test_generate(w##insn##00, "w" #insn " " asm_string ",0, 0") \
-+ s390_test_generate(w##insn##01, "w" #insn " " asm_string ",0, 1") \
-+ s390_test_generate(w##insn##03, "w" #insn " " asm_string ",0, 3") \
-+ s390_test_generate(w##insn##04, "w" #insn " " asm_string ",0, 4") \
-+ s390_test_generate(w##insn##05, "w" #insn " " asm_string ",0, 5") \
-+ s390_test_generate(w##insn##06, "w" #insn " " asm_string ",0, 6") \
-+ s390_test_generate(w##insn##07, "w" #insn " " asm_string ",0, 7") \
-+
-+#define s390_call_float_test(insn, info) \
-+ test_with_selective_printing(v ##insn ## 00, info); \
-+ test_with_selective_printing(v ##insn ## 01, info); \
-+ test_with_selective_printing(v ##insn ## 03, info); \
-+ test_with_selective_printing(v ##insn ## 04, info); \
-+ test_with_selective_printing(v ##insn ## 05, info); \
-+ test_with_selective_printing(v ##insn ## 06, info); \
-+ test_with_selective_printing(v ##insn ## 07, info); \
-+ test_with_selective_printing(w ##insn ## 00, info | V128_V_RES_ZERO_ONLY); \
-+ test_with_selective_printing(w ##insn ## 01, info | V128_V_RES_ZERO_ONLY); \
-+ test_with_selective_printing(w ##insn ## 03, info | V128_V_RES_ZERO_ONLY); \
-+ test_with_selective_printing(w ##insn ## 04, info | V128_V_RES_ZERO_ONLY); \
-+ test_with_selective_printing(w ##insn ## 05, info | V128_V_RES_ZERO_ONLY); \
-+ test_with_selective_printing(w ##insn ## 06, info | V128_V_RES_ZERO_ONLY); \
-+ test_with_selective_printing(w ##insn ## 07, info | V128_V_RES_ZERO_ONLY); \
-+
-+s390_generate_float_test(cdgb, " %%v5, %%v1")
-+s390_generate_float_test(cdlgb, " %%v5, %%v1")
-+s390_generate_float_test(cgdb, " %%v5, %%v1")
-+s390_generate_float_test(clgdb, " %%v5, %%v1")
-+s390_generate_float_test(fidb, " %%v5, %%v1")
-+s390_generate_float_test(ledb, " %%v5, %%v1")
-+
-+s390_test_generate(vldeb, "vldeb %%v5, %%v1")
-+s390_test_generate(wldeb, "wldeb %%v5, %%v1")
-+
-+s390_test_generate(vflcdb, "vflcdb %%v5, %%v1")
-+s390_test_generate(wflcdb, "wflcdb %%v5, %%v1")
-+s390_test_generate(vflndb, "vflndb %%v5, %%v1")
-+s390_test_generate(wflndb, "wflndb %%v5, %%v1")
-+s390_test_generate(vflpdb, "vflpdb %%v5, %%v1")
-+s390_test_generate(wflpdb, "wflpdb %%v5, %%v1")
-+
-+s390_test_generate(vfadb, "vfadb %%v5, %%v1, %%v2")
-+s390_test_generate(wfadb, "wfadb %%v5, %%v1, %%v2")
-+s390_test_generate(vfsdb, "vfsdb %%v5, %%v1, %%v2")
-+s390_test_generate(wfsdb, "wfsdb %%v5, %%v1, %%v2")
-+s390_test_generate(vfmdb, "vfmdb %%v5, %%v1, %%v2")
-+s390_test_generate(wfmdb, "wfmdb %%v5, %%v1, %%v2")
-+s390_test_generate(vfddb, "vfddb %%v5, %%v1, %%v2")
-+s390_test_generate(wfddb, "wfddb %%v5, %%v1, %%v2")
-+
-+s390_test_generate(vfsqdb, "vfsqdb %%v5, %%v1")
-+s390_test_generate(wfsqdb, "wfsqdb %%v5, %%v1")
-+
-+s390_test_generate(vfmadb, "vfmadb %%v5, %%v1, %%v2, %%v3")
-+s390_test_generate(wfmadb, "wfmadb %%v5, %%v1, %%v2, %%v3")
-+s390_test_generate(vfmsdb, "vfmsdb %%v5, %%v1, %%v2, %%v3")
-+s390_test_generate(wfmsdb, "wfmsdb %%v5, %%v1, %%v2, %%v3")
-+
-+s390_test_generate(wfcdb, "wfcdb %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(wfkdb, "wfkdb %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+
-+s390_test_generate(vfcedb, "vfcedb %%v5, %%v1, %%v2")
-+s390_test_generate(wfcedb, "wfcedb %%v5, %%v1, %%v2")
-+s390_test_generate(vfcedbs, "vfcedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(wfcedbs, "wfcedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+
-+s390_test_generate(vfchdb, "vfchdb %%v5, %%v1, %%v2")
-+s390_test_generate(wfchdb, "wfchdb %%v5, %%v1, %%v2")
-+s390_test_generate(vfchdbs, "vfchdbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(wfchdbs, "wfchdbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+
-+s390_test_generate(vfchedb, "vfchedb %%v5, %%v1, %%v2")
-+s390_test_generate(wfchedb, "wfchedb %%v5, %%v1, %%v2")
-+s390_test_generate(vfchedbs, "vfchedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(wfchedbs, "wfchedbs %%v5, %%v1, %%v2\n" S390_TEST_PUT_CC_TO_RESULT)
-+
-+s390_test_generate(vftcidb0, "vftcidb %%v5, %%v1, 0 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb1, "vftcidb %%v5, %%v1, 1 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb2, "vftcidb %%v5, %%v1, 2 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb3, "vftcidb %%v5, %%v1, 0 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb4, "vftcidb %%v5, %%v1, 4 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb8, "vftcidb %%v5, %%v1, 8 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb16, "vftcidb %%v5, %%v1, 16 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb32, "vftcidb %%v5, %%v1, 32 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb64, "vftcidb %%v5, %%v1, 64 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb128, "vftcidb %%v5, %%v1, 128 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb256, "vftcidb %%v5, %%v1, 256 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb512, "vftcidb %%v5, %%v1, 512 \n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb1024, "vftcidb %%v5, %%v1, 1024\n" S390_TEST_PUT_CC_TO_RESULT)
-+s390_test_generate(vftcidb2048, "vftcidb %%v5, %%v1, 2048\n" S390_TEST_PUT_CC_TO_RESULT)
-+
-+int main()
-+{
-+ size_t iteration = 0;
-+
-+ s390_call_float_test(cdgb, (V128_V_RES_AS_FLOAT64 | V128_V_ARG1_AS_INT));
-+ s390_call_float_test(cdlgb, (V128_V_RES_AS_FLOAT64 | V128_V_ARG1_AS_INT));
-+ s390_call_float_test(cgdb, (V128_V_RES_AS_INT | V128_V_ARG1_AS_FLOAT64));
-+ s390_call_float_test(clgdb, (V128_V_RES_AS_INT | V128_V_ARG1_AS_FLOAT64));
-+ s390_call_float_test(fidb, (V128_V_RES_AS_FLOAT64 | V128_V_ARG1_AS_FLOAT64));
-+ s390_call_float_test(ledb, (V128_V_RES_AS_FLOAT32 | V128_V_RES_EVEN_ONLY |
-+ V128_V_ARG1_AS_FLOAT64));
-+
-+ test_with_selective_printing(vldeb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(wldeb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+
-+ test_with_selective_printing(vflcdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(wflcdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(vflndb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(wflndb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(vflpdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(wflpdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+
-+ test_with_selective_printing(vfadb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfadb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(vfsdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfsdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(vfmdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfmdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(vfddb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfddb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+
-+ test_with_selective_printing(vfsqdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+ test_with_selective_printing(wfsqdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64));
-+
-+ test_with_selective_printing(vfmadb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_V_ARG3_AS_FLOAT64));
-+ test_with_selective_printing(wfmadb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_V_ARG3_AS_FLOAT64));
-+ test_with_selective_printing(vfmsdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_V_ARG3_AS_FLOAT64));
-+ test_with_selective_printing(wfmsdb, (V128_V_RES_AS_FLOAT64 |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_V_ARG3_AS_FLOAT64));
-+
-+ test_with_selective_printing(wfcdb, (V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(wfkdb, (V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+
-+ test_with_selective_printing(vfcedb, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfcedb, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(vfcedbs, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(wfcedbs, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+
-+ test_with_selective_printing(vfchdb, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfchdb, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(vfchdbs, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(wfchdbs, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+
-+ test_with_selective_printing(vfchedb, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(wfchedb, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64));
-+ test_with_selective_printing(vfchedbs, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(wfchedbs, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_V_ARG2_AS_FLOAT64 |
-+ V128_R_RES));
-+
-+ test_with_selective_printing(vftcidb0, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb1, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb2, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb3, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb4, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb8, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb16, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb32, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb64, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb128, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb256, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb512, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb1024, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+ test_with_selective_printing(vftcidb2048, (V128_V_RES_AS_INT |
-+ V128_V_ARG1_AS_FLOAT64 |
-+ V128_R_RES));
-+
-+ return 0;
-+}
-diff --git a/none/tests/s390x/vector_float.stderr.exp b/none/tests/s390x/vector_float.stderr.exp
-new file mode 100644
-index 0000000..139597f
---- /dev/null
-+++ b/none/tests/s390x/vector_float.stderr.exp
-@@ -0,0 +1,2 @@
-+
-+
-diff --git a/none/tests/s390x/vector_float.stdout.exp b/none/tests/s390x/vector_float.stdout.exp
-new file mode 100644
-index 0000000..eac5250
---- /dev/null
-+++ b/none/tests/s390x/vector_float.stdout.exp
-@@ -0,0 +1,1808 @@
-+insn vcdgb00:
-+ v_arg1 = 0d6a95fac528657d | 501eefeec0d8b847
-+ v_result = 0x1.ad52bf58a50cap+59 | 0x1.407bbfbb0362ep+62
-+insn vcdgb00:
-+ v_arg1 = e540bc6839c44b4a | 36ed3550df9899d8
-+ v_result = -0x1.abf4397c63bb4p+60 | 0x1.b769aa86fcc4cp+61
-+insn vcdgb00:
-+ v_arg1 = 979569ee6d5cbcd8 | 966cf73d98a42d54
-+ v_result = -0x1.a1aa58464a8dp+62 | -0x1.a64c23099d6f4p+62
-+insn vcdgb00:
-+ v_arg1 = 10985cc9e2b9c255 | b2683bbf21432695
-+ v_result = 0x1.0985cc9e2b9c2p+60 | -0x1.365f11037af36p+62
-+insn vcdgb01:
-+ v_arg1 = 4208cb757c0f3e0a | 91fe3de1d5e7ca54
-+ v_result = 0x1.08232dd5f03dp+62 | -0x1.b8070878a860dp+62
-+insn vcdgb01:
-+ v_arg1 = e5f1216d47c3a621 | c1582e6bf6f3b5e9
-+ v_result = -0x1.a0ede92b83c5ap+60 | -0x1.f53e8ca048625p+61
-+insn vcdgb01:
-+ v_arg1 = 376fbfe93425c861 | 1870f7a36a759b08
-+ v_result = 0x1.bb7dff49a12e4p+61 | 0x1.870f7a36a759bp+60
-+insn vcdgb01:
-+ v_arg1 = bc68bf9dda3685ee | 6fcaf40c7feb0484
-+ v_result = -0x1.0e5d01889725fp+62 | 0x1.bf2bd031ffac1p+62
-+insn vcdgb03:
-+ v_arg1 = ff55ac7f3661970c | 663cba29a8010f0e
-+ v_result = -0x1.54a701933cd1fp+55 | 0x1.98f2e8a6a0043p+62
-+insn vcdgb03:
-+ v_arg1 = 50f94b806c444cdc | 23a9d13a3e4f30f5
-+ v_result = 0x1.43e52e01b1113p+62 | 0x1.1d4e89d1f2799p+61
-+insn vcdgb03:
-+ v_arg1 = 8526565084674a1c | 13c07bfc401df2e6
-+ v_result = -0x1.eb66a6bdee62dp+62 | 0x1.3c07bfc401df3p+60
-+insn vcdgb03:
-+ v_arg1 = bb7d3d1d2e024aea | a9bf6c6c1422b7ac
-+ v_result = -0x1.120b0b8b47f6dp+62 | -0x1.59024e4faf753p+62
-+insn vcdgb04:
-+ v_arg1 = 122de4537ebadd80 | 1b359083443f73f0
-+ v_result = 0x1.22de4537ebadep+60 | 0x1.b359083443f74p+60
-+insn vcdgb04:
-+ v_arg1 = 74b2685cb1632af8 | 28bac9f9424875f9
-+ v_result = 0x1.d2c9a172c58cbp+62 | 0x1.45d64fca1243bp+61
-+insn vcdgb04:
-+ v_arg1 = 4f96da5fe8beae08 | d5b8af0426ba1f6b
-+ v_result = 0x1.3e5b697fa2facp+62 | -0x1.523a87deca2fp+61
-+insn vcdgb04:
-+ v_arg1 = 57330304e93afcc5 | 2c244e196b83aa0a
-+ v_result = 0x1.5ccc0c13a4ebfp+62 | 0x1.612270cb5c1d5p+61
-+insn vcdgb05:
-+ v_arg1 = 466d1f2de1b67b62 | fc44eca9b6c0e377
-+ v_result = 0x1.19b47cb786d9ep+62 | -0x1.dd89ab249f8e4p+57
-+insn vcdgb05:
-+ v_arg1 = 9c7aa2bc253b2bf0 | 9c69c1e38f79f1f0
-+ v_result = -0x1.8e15750f6b135p+62 | -0x1.8e58f871c2183p+62
-+insn vcdgb05:
-+ v_arg1 = 609cf752ecc5611e | a9b4be7727660d13
-+ v_result = 0x1.8273dd4bb3158p+62 | -0x1.592d06236267cp+62
-+insn vcdgb05:
-+ v_arg1 = dde43c0d17fa87f9 | c4d4485011ac499a
-+ v_result = -0x1.10de1f97402bcp+61 | -0x1.d95dbd7f729dbp+61
-+insn vcdgb06:
-+ v_arg1 = 67f00848ebf0ddad | 55c5fa58099e4a1e
-+ v_result = 0x1.9fc02123afc38p+62 | 0x1.5717e96026793p+62
-+insn vcdgb06:
-+ v_arg1 = 14ac275ed2ea3c41 | 4c916736b17f0fd7
-+ v_result = 0x1.4ac275ed2ea3dp+60 | 0x1.32459cdac5fc4p+62
-+insn vcdgb06:
-+ v_arg1 = 841359651e19ce5c | db11d6114f3da959
-+ v_result = -0x1.efb29a6b8798cp+62 | -0x1.27714f758612bp+61
-+insn vcdgb06:
-+ v_arg1 = 9aee16f6c65ed705 | 3dab044d91370057
-+ v_result = -0x1.9447a424e684ap+62 | 0x1.ed58226c89b81p+61
-+insn vcdgb07:
-+ v_arg1 = 41924de22705705d | 7314e64c4af69562
-+ v_result = 0x1.064937889c15cp+62 | 0x1.cc5399312bda5p+62
-+insn vcdgb07:
-+ v_arg1 = 28a421fcc48a4766 | 020e652d33f63ba9
-+ v_result = 0x1.45210fe624523p+61 | 0x1.07329699fb1ddp+57
-+insn vcdgb07:
-+ v_arg1 = 87d7abd5085662be | b72a218eab5dddb9
-+ v_result = -0x1.e0a150abdea68p+62 | -0x1.235779c552889p+62
-+insn vcdgb07:
-+ v_arg1 = d9abbb790081d963 | 63852f4c78c03c3d
-+ v_result = -0x1.32a22437fbf14p+61 | 0x1.8e14bd31e300fp+62
-+insn wcdgb00:
-+ v_arg1 = a02f983522909f6f | a08ddc4185e4afbe
-+ v_result = -0x1.7f419f2b75bd8p+62 | --
-+insn wcdgb00:
-+ v_arg1 = 24bfbc5409373bdb | 8bbc6803a279e263
-+ v_result = 0x1.25fde2a049b9dp+61 | --
-+insn wcdgb00:
-+ v_arg1 = 35c59adc3617873f | 895bccaa47e097b0
-+ v_result = 0x1.ae2cd6e1b0bc3p+61 | --
-+insn wcdgb00:
-+ v_arg1 = e5795953d180798f | 033f758952e56949
-+ v_result = -0x1.a86a6ac2e7f86p+60 | --
-+insn wcdgb01:
-+ v_arg1 = 50a3967f672fd7de | 2a8d07f3c58484af
-+ v_result = 0x1.428e59fd9cbf6p+62 | --
-+insn wcdgb01:
-+ v_arg1 = 55572620ab0f011d | b4781cf689a66f00
-+ v_result = 0x1.555c9882ac3cp+62 | --
-+insn wcdgb01:
-+ v_arg1 = 5ab7d2b735faacdb | 9d0003212fe3c3b9
-+ v_result = 0x1.6adf4adcd7eabp+62 | --
-+insn wcdgb01:
-+ v_arg1 = 0cb41a414677a106 | e7b48241aa40f176
-+ v_result = 0x1.96834828cef42p+59 | --
-+insn wcdgb03:
-+ v_arg1 = 1dcbf3fa837c83a7 | 5c6f941e16f101b0
-+ v_result = 0x1.dcbf3fa837c83p+60 | --
-+insn wcdgb03:
-+ v_arg1 = 05ca8a1db62c87a8 | 471d2d4175174e7c
-+ v_result = 0x1.72a2876d8b21fp+58 | --
-+insn wcdgb03:
-+ v_arg1 = c28bffa291993a8f | 3f76f2af6e814c51
-+ v_result = -0x1.eba002eb73363p+61 | --
-+insn wcdgb03:
-+ v_arg1 = 99b62bfd6b813f43 | ddc001ae0d6e42c1
-+ v_result = -0x1.9927500a51fb1p+62 | --
-+insn wcdgb04:
-+ v_arg1 = d3825be401140fc5 | 818fb07e8648113d
-+ v_result = -0x1.63ed20dff75f8p+61 | --
-+insn wcdgb04:
-+ v_arg1 = 8273130837abb8f7 | 1287461ff268ecd4
-+ v_result = -0x1.f633b3df21512p+62 | --
-+insn wcdgb04:
-+ v_arg1 = 3a1ccdd9d5909f57 | bc17c41010d81ef3
-+ v_result = 0x1.d0e66eceac85p+61 | --
-+insn wcdgb04:
-+ v_arg1 = d8ddb8444bbc3ec3 | b03fa00d060ac825
-+ v_result = -0x1.39123ddda21e1p+61 | --
-+insn wcdgb05:
-+ v_arg1 = 3fa47a776e92e735 | e74a85ce1fa4a0d3
-+ v_result = 0x1.fd23d3bb74973p+61 | --
-+insn wcdgb05:
-+ v_arg1 = 16aeee9b39a78086 | e09214ce8b37b404
-+ v_result = 0x1.6aeee9b39a78p+60 | --
-+insn wcdgb05:
-+ v_arg1 = 8c46e7988e7d462e | 5e41a7002202251c
-+ v_result = -0x1.cee4619dc60aep+62 | --
-+insn wcdgb05:
-+ v_arg1 = 1584ecd3f3428b01 | 2c0d099a22b2ed9f
-+ v_result = 0x1.584ecd3f3428bp+60 | --
-+insn wcdgb06:
-+ v_arg1 = 2b0dfbf1569378f2 | d9fa40cced239bee
-+ v_result = 0x1.586fdf8ab49bdp+61 | --
-+insn wcdgb06:
-+ v_arg1 = 0fd84793ca3eccd2 | 7d1b4488cd1e1207
-+ v_result = 0x1.fb08f27947d9ap+59 | --
-+insn wcdgb06:
-+ v_arg1 = 86e6fb1a47fa9c10 | 7350c53bb01b4e47
-+ v_result = -0x1.e4641396e0158p+62 | --
-+insn wcdgb06:
-+ v_arg1 = 9c07f5646f2f1179 | 1d07e991ed001f2a
-+ v_result = -0x1.8fe02a6e4343bp+62 | --
-+insn wcdgb07:
-+ v_arg1 = 659a8c8c44b32df8 | a3fd0c33fddfed09
-+ v_result = 0x1.966a323112ccbp+62 | --
-+insn wcdgb07:
-+ v_arg1 = b84c4aadf38a8756 | b5fd808b43ba73d9
-+ v_result = -0x1.1eced54831d5fp+62 | --
-+insn wcdgb07:
-+ v_arg1 = f2d6b39d8ea40bfa | 459e4b7dc64184f1
-+ v_result = -0x1.a5298c4e2b7e9p+59 | --
-+insn wcdgb07:
-+ v_arg1 = bac2fdb4caa1bca9 | 4f08ec2df290cac3
-+ v_result = -0x1.14f4092cd5791p+62 | --
-+insn vcdlgb00:
-+ v_arg1 = b826d785c58e7345 | 91ae17bf5bf582a0
-+ v_result = 0x1.704daf0b8b1cep+63 | 0x1.235c2f7eb7ebp+63
-+insn vcdlgb00:
-+ v_arg1 = 5c6623a3c3a79e8f | 541375117aa74277
-+ v_result = 0x1.71988e8f0e9e7p+62 | 0x1.504dd445ea9dp+62
-+insn vcdlgb00:
-+ v_arg1 = 9ef4bc5cec1602e7 | 228965816f8eb495
-+ v_result = 0x1.3de978b9d82cp+63 | 0x1.144b2c0b7c75ap+61
-+insn vcdlgb00:
-+ v_arg1 = b912318010b2790a | 8eecbeacbe005865
-+ v_result = 0x1.722463002164fp+63 | 0x1.1dd97d597c00bp+63
-+insn vcdlgb01:
-+ v_arg1 = f08d891964bfb5d2 | f0698b2c12804730
-+ v_result = 0x1.e11b1232c97f7p+63 | 0x1.e0d3165825009p+63
-+insn vcdlgb01:
-+ v_arg1 = 4982fe3244b3fcf9 | 263cce57fe80ebdd
-+ v_result = 0x1.260bf8c912cffp+62 | 0x1.31e672bff4076p+61
-+insn vcdlgb01:
-+ v_arg1 = 551bc293efedead4 | 556b3f05b71fc8b0
-+ v_result = 0x1.546f0a4fbfb7bp+62 | 0x1.55acfc16dc7f2p+62
-+insn vcdlgb01:
-+ v_arg1 = e751bd824f7e331a | a68f0b49dcea370d
-+ v_result = 0x1.cea37b049efc6p+63 | 0x1.4d1e1693b9d47p+63
-+insn vcdlgb03:
-+ v_arg1 = d8ab4e82afe45f9d | 0a8b96352f9d2734
-+ v_result = 0x1.b1569d055fc8bp+63 | 0x1.5172c6a5f3a4fp+59
-+insn vcdlgb03:
-+ v_arg1 = cafc061682c88d0e | f751399a5ae2db05
-+ v_result = 0x1.95f80c2d05911p+63 | 0x1.eea27334b5c5bp+63
-+insn vcdlgb03:
-+ v_arg1 = e328717e23c531bd | 2aa205c4ab0fafbd
-+ v_result = 0x1.c650e2fc478a7p+63 | 0x1.55102e25587d7p+61
-+insn vcdlgb03:
-+ v_arg1 = 8eddcd779023d755 | 63cd7e40d9ebd3b6
-+ v_result = 0x1.1dbb9aef2047bp+63 | 0x1.8f35f90367af5p+62
-+insn vcdlgb04:
-+ v_arg1 = 3e5cd1fd2f96dea2 | 2d6e6298be680e29
-+ v_result = 0x1.f2e68fe97cb6fp+61 | 0x1.6b7314c5f3407p+61
-+insn vcdlgb04:
-+ v_arg1 = 2c31690b8a033d4d | 943061141b697dee
-+ v_result = 0x1.618b485c5019fp+61 | 0x1.2860c22836d3p+63
-+insn vcdlgb04:
-+ v_arg1 = 14f57558143a429c | ed8ae27a577c5238
-+ v_result = 0x1.4f57558143a43p+60 | 0x1.db15c4f4aef8ap+63
-+insn vcdlgb04:
-+ v_arg1 = fc128d1be2bb4f36 | 9283c5cd409f975c
-+ v_result = 0x1.f8251a37c576ap+63 | 0x1.25078b9a813f3p+63
-+insn vcdlgb05:
-+ v_arg1 = ee7dc0c772749ddc | a3701c10cafde98a
-+ v_result = 0x1.dcfb818ee4e93p+63 | 0x1.46e0382195fbdp+63
-+insn vcdlgb05:
-+ v_arg1 = b97c51cd687ff92f | c7b3f102ccb03d91
-+ v_result = 0x1.72f8a39ad0fffp+63 | 0x1.8f67e20599607p+63
-+insn vcdlgb05:
-+ v_arg1 = b460795f4de78a6f | ea7d04e2c6809f9e
-+ v_result = 0x1.68c0f2be9bcf1p+63 | 0x1.d4fa09c58d013p+63
-+insn vcdlgb05:
-+ v_arg1 = 7c4a292a4f638939 | fd8c8a2c9fa1effc
-+ v_result = 0x1.f128a4a93d8e2p+62 | 0x1.fb1914593f43dp+63
-+insn vcdlgb06:
-+ v_arg1 = b2e9c51a04180847 | baecf0585f77a3d4
-+ v_result = 0x1.65d38a3408302p+63 | 0x1.75d9e0b0beef5p+63
-+insn vcdlgb06:
-+ v_arg1 = be39eb18285aad32 | 5eb896a0fa5488ed
-+ v_result = 0x1.7c73d63050b56p+63 | 0x1.7ae25a83e9523p+62
-+insn vcdlgb06:
-+ v_arg1 = 8f442ace5a6a7432 | 6dd995ba0537816b
-+ v_result = 0x1.1e88559cb4d4fp+63 | 0x1.b76656e814de1p+62
-+insn vcdlgb06:
-+ v_arg1 = 5ae3cc60e43771db | 72c47a987f8e4792
-+ v_result = 0x1.6b8f318390dddp+62 | 0x1.cb11ea61fe392p+62
-+insn vcdlgb07:
-+ v_arg1 = 577c8e33711f8ce0 | bc3f092e8bf32882
-+ v_result = 0x1.5df238cdc47e3p+62 | 0x1.787e125d17e65p+63
-+insn vcdlgb07:
-+ v_arg1 = 88c462a8d4ae43d2 | 231bfc2b30f1c9fb
-+ v_result = 0x1.1188c551a95c8p+63 | 0x1.18dfe159878e4p+61
-+insn vcdlgb07:
-+ v_arg1 = 727d35e1c85c6ce0 | c2f9c2bc20bfe51a
-+ v_result = 0x1.c9f4d7872171bp+62 | 0x1.85f38578417fcp+63
-+insn vcdlgb07:
-+ v_arg1 = e238a379ac52f197 | bb08414f6f020c19
-+ v_result = 0x1.c47146f358a5ep+63 | 0x1.7610829ede041p+63
-+insn wcdlgb00:
-+ v_arg1 = a912c54e442593a2 | f7c3954d578d6511
-+ v_result = 0x1.52258a9c884b2p+63 | --
-+insn wcdlgb00:
-+ v_arg1 = 6179e4397b98a98a | e4b6cfddfb236dba
-+ v_result = 0x1.85e790e5ee62ap+62 | --
-+insn wcdlgb00:
-+ v_arg1 = 27e744d3235cdf76 | 3539b7a62232b627
-+ v_result = 0x1.3f3a26991ae6fp+61 | --
-+insn wcdlgb00:
-+ v_arg1 = 60a5da31b4d1f8ea | a6328b8cf898a98d
-+ v_result = 0x1.829768c6d347ep+62 | --
-+insn wcdlgb01:
-+ v_arg1 = 758817a709c58c8a | b6d6be70d26145fc
-+ v_result = 0x1.d6205e9c27163p+62 | --
-+insn wcdlgb01:
-+ v_arg1 = 97b59c872733cad7 | 6c67baf3e785de23
-+ v_result = 0x1.2f6b390e4e679p+63 | --
-+insn wcdlgb01:
-+ v_arg1 = 7c5f03e2f70438ef | 13f5a03218ade00f
-+ v_result = 0x1.f17c0f8bdc10ep+62 | --
-+insn wcdlgb01:
-+ v_arg1 = 20869d4407d06f50 | fe20038aa9ed8aeb
-+ v_result = 0x1.0434ea203e838p+61 | --
-+insn wcdlgb03:
-+ v_arg1 = 85b92f7a4d9ce094 | 45d3b155068ab4c0
-+ v_result = 0x1.0b725ef49b39dp+63 | --
-+insn wcdlgb03:
-+ v_arg1 = 74d3b54ee59c9334 | 87096ba97fb48a34
-+ v_result = 0x1.d34ed53b96725p+62 | --
-+insn wcdlgb03:
-+ v_arg1 = 3bc02048cff1e348 | a78aa81e0d4c504e
-+ v_result = 0x1.de0102467f8f1p+61 | --
-+insn wcdlgb03:
-+ v_arg1 = 6e38186eb26b4443 | 8fad57870c9d1c2e
-+ v_result = 0x1.b8e061bac9ad1p+62 | --
-+insn wcdlgb04:
-+ v_arg1 = a781bb039c46fdba | f0169ab6ff259fd8
-+ v_result = 0x1.4f037607388ep+63 | --
-+insn wcdlgb04:
-+ v_arg1 = 462f5c4ac0efef1d | 01788c3b504cdde9
-+ v_result = 0x1.18bd712b03bfcp+62 | --
-+insn wcdlgb04:
-+ v_arg1 = 32e6464337bf4d7c | 3c53fd240e2af05e
-+ v_result = 0x1.97323219bdfa7p+61 | --
-+insn wcdlgb04:
-+ v_arg1 = 9615776bc1bd6242 | 25b531bdae44ca53
-+ v_result = 0x1.2c2aeed7837acp+63 | --
-+insn wcdlgb05:
-+ v_arg1 = a6bc667e825f4ffb | 04fca550cb4ef1c0
-+ v_result = 0x1.4d78ccfd04be9p+63 | --
-+insn wcdlgb05:
-+ v_arg1 = 5826bd37c548ca0f | a690cbe5e6e9423d
-+ v_result = 0x1.609af4df15232p+62 | --
-+insn wcdlgb05:
-+ v_arg1 = 2cad200dbc09e187 | 20acc9022764afbe
-+ v_result = 0x1.6569006de04fp+61 | --
-+insn wcdlgb05:
-+ v_arg1 = e57be5f73fe3b5c6 | 8c153e6a1a7d0156
-+ v_result = 0x1.caf7cbee7fc76p+63 | --
-+insn wcdlgb06:
-+ v_arg1 = 4e46db2789824050 | cbdffee0732097f5
-+ v_result = 0x1.391b6c9e26091p+62 | --
-+insn wcdlgb06:
-+ v_arg1 = f61204d100c21186 | 422ed2e3cc26252c
-+ v_result = 0x1.ec2409a201843p+63 | --
-+insn wcdlgb06:
-+ v_arg1 = f5f25be4ea6d0b66 | 9ef13972631676e7
-+ v_result = 0x1.ebe4b7c9d4da2p+63 | --
-+insn wcdlgb06:
-+ v_arg1 = a5c590ce39f92a4e | 90a72ac9dde52c31
-+ v_result = 0x1.4b8b219c73f26p+63 | --
-+insn wcdlgb07:
-+ v_arg1 = 6afcc73a404c3eb8 | 921dd02006b87bf3
-+ v_result = 0x1.abf31ce90130fp+62 | --
-+insn wcdlgb07:
-+ v_arg1 = 6c515dd47c7aaffd | a12d4e718fa0f2b3
-+ v_result = 0x1.b1457751f1eabp+62 | --
-+insn wcdlgb07:
-+ v_arg1 = 598fa3024d843814 | 027f7932ce5b3358
-+ v_result = 0x1.663e8c093610ep+62 | --
-+insn wcdlgb07:
-+ v_arg1 = 2450a2abba1aac53 | fe49a1158218b7e3
-+ v_result = 0x1.2285155dd0d56p+61 | --
-+insn vcgdb00:
-+ v_result = 8000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.9d6f33159b52cp+140 | -0x1.149ce8e328c35p-414
-+insn vcgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.ef4fc458c90fp-924 | -0x1.9eacbbaf216cep-761
-+insn vcgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.2a4a56fedd38ep-441 | -0x1.0b5fc7650d28ap-628
-+insn vcgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.7484ccf632853p-296 | -0x1.64f8b96b20e65p-498
-+insn vcgdb01:
-+ v_result = 0000000000000000 | 7fffffffffffffff
-+ v_arg1 = 0x1.9b48ee9440faap-186 | 0x1.793a417aab337p+274
-+insn vcgdb01:
-+ v_result = 0000000000000000 | 8000000000000000
-+ v_arg1 = 0x1.5f4046914a1dcp-748 | -0x1.e542ddabafc78p+412
-+insn vcgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.70a07df4248dp-475 | -0x1.2198d65113dfcp-305
-+insn vcgdb01:
-+ v_result = 0000000000000000 | 7fffffffffffffff
-+ v_arg1 = -0x1.5ae6c84f089cap-838 | 0x1.bdf68a54e9eb5p+67
-+insn vcgdb03:
-+ v_result = 7fffffffffffffff | 8000000000000000
-+ v_arg1 = 0x1.80d47f3abbb2ep+908 | -0x1.cdb5faf3bde76p+537
-+insn vcgdb03:
-+ v_result = 8000000000000000 | 7fffffffffffffff
-+ v_arg1 = -0x1.38aaaf12dcd3cp+378 | 0x1.836d37a9211adp+161
-+insn vcgdb03:
-+ v_result = 0000000000000001 | ffffffffffffffff
-+ v_arg1 = 0x1.88165272004d5p-526 | -0x1.0d0a1a7ba6227p-856
-+insn vcgdb03:
-+ v_result = 0000000000000001 | ffffffffffffffff
-+ v_arg1 = 0x1.8ffc7e4ddbb33p-831 | -0x1.2ffe63a89d2cfp-189
-+insn vcgdb04:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.28c5adc2722b3p+540 | -0x1.b4dbb5f02f86ep-483
-+insn vcgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.2e2a9ecf4008dp-420 | -0x1.43ef92717c06ap-301
-+insn vcgdb04:
-+ v_result = 8000000000000000 | 7fffffffffffffff
-+ v_arg1 = -0x1.3b4fcd4237299p+636 | 0x1.707f549662d89p+1004
-+insn vcgdb04:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.c6918fb45aa0bp+947 | -0x1.95943e2ff17aep-22
-+insn vcgdb05:
-+ v_result = 0000000000000000 | 8000000000000000
-+ v_arg1 = -0x1.4de033057b236p-61 | -0x1.01575361bed9ap+468
-+insn vcgdb05:
-+ v_result = 8000000000000000 | 8000000000000000
-+ v_arg1 = -0x1.028bc6484274bp+144 | -0x1.d16db6de475aap+271
-+insn vcgdb05:
-+ v_result = 7fffffffffffffff | 8000000000000000
-+ v_arg1 = 0x1.2500671e7fe19p+128 | -0x1.1eb435732889ep+338
-+insn vcgdb05:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.b161dd74543cdp-442 | 0x1.b9ab9294bd84fp-297
-+insn vcgdb06:
-+ v_result = 7fffffffffffffff | 8000000000000000
-+ v_arg1 = 0x1.9b07d7ad5d6b2p+319 | -0x1.75e473ea1aa76p+514
-+insn vcgdb06:
-+ v_result = 0000000000000000 | 7fffffffffffffff
-+ v_arg1 = -0x1.888a166fb2dfp-837 | 0x1.f6bb5d7969d6ap+996
-+insn vcgdb06:
-+ v_result = 0000000000000001 | 8000000000000000
-+ v_arg1 = 0x1.302c08b07155p-868 | -0x1.ca648dc3a61e1p+414
-+insn vcgdb06:
-+ v_result = 7fffffffffffffff | 8000000000000000
-+ v_arg1 = 0x1.3349182f971f5p+336 | -0x1.46e859a0a81adp+216
-+insn vcgdb07:
-+ v_result = 8000000000000000 | 8000000000000000
-+ v_arg1 = -0x1.dac06473efa23p+846 | -0x1.c56ee83b11b7fp+926
-+insn vcgdb07:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = 0x1.72e13fd73fefbp-108 | -0x1.6e8c2f2c9a3a6p-960
-+insn vcgdb07:
-+ v_result = 8000000000000000 | 8000000000000000
-+ v_arg1 = -0x1.27466ae20223bp+958 | -0x1.365c0e59aa4cep+392
-+insn vcgdb07:
-+ v_result = 7fffffffffffffff | 7fffffffffffffff
-+ v_arg1 = 0x1.fed2f087c21p+341 | 0x1.180e4c1d87fc4p+682
-+insn wcgdb00:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.d7fd9222e8b86p+670 | 0x1.c272612672a3p+798
-+insn wcgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.745cd360987e5p-496 | -0x1.f3b404919f358p-321
-+insn wcgdb00:
-+ v_result = 8000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.9523565cd92d5p+643 | 0x1.253677d6d3be2p-556
-+insn wcgdb00:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.b6eb576ec3e6ap+845 | -0x1.c7e102c503d91p+266
-+insn wcgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.3d4319841f4d6p-1011 | -0x1.2feabf7dfc506p-680
-+insn wcgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.6fb8d1cd8b32cp-843 | -0x1.50f6a6922f97ep+33
-+insn wcgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.64a673daccf1ap-566 | -0x1.69ef9b1d01499p+824
-+insn wcgdb01:
-+ v_result = 8000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.3e2ddd862b4adp+1005 | -0x1.312466410271p+184
-+insn wcgdb03:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.d594c3412a11p-953 | -0x1.a07393d34d77cp-224
-+insn wcgdb03:
-+ v_result = 8000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.f7a0dbcfd6e4cp+104 | -0x1.40f7cde7f2214p-702
-+insn wcgdb03:
-+ v_result = 8000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.40739c1574808p+560 | -0x1.970328ddf1b6ep-374
-+insn wcgdb03:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.477653afd7048p-38 | 0x1.1eac2f8b2a93cp-384
-+insn wcgdb04:
-+ v_result = ffffffffe9479a7d | 0000000000000000
-+ v_arg1 = -0x1.6b865833eff3p+28 | 0x1.06e8cf1834d0ep-722
-+insn wcgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.eef0b2294a5cp-544 | -0x1.8e8b133ccda15p+752
-+insn wcgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.f34e77e6b6698p-894 | -0x1.9f7ce1cb53bddp-896
-+insn wcgdb04:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.95707a6d75db5p+1018 | -0x1.3b0c072d23011p-224
-+insn wcgdb05:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.a9fb71160793p-968 | 0x1.05f601fe8123ap-986
-+insn wcgdb05:
-+ v_result = 8000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.0864159b94305p+451 | -0x1.d4647f5a78b7ep-599
-+insn wcgdb05:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.37eadff8397c8p+432 | -0x1.15d896b6f6063p+464
-+insn wcgdb05:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.eb0812b0d677p-781 | 0x1.3117c5e0e288cp-202
-+insn wcgdb06:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.6b88069167c0fp-662 | -0x1.70571d27e1279p+254
-+insn wcgdb06:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.f6a6d6e883596p+260 | 0x1.0d578afaaa34ap+604
-+insn wcgdb06:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.d91c7d13c4694p-475 | -0x1.ecf1f8529767bp+830
-+insn wcgdb06:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.fac8dd3bb7af6p-101 | 0x1.fb8324a00fba8p+959
-+insn wcgdb07:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.4b0fa18fa73c7p+111 | -0x1.08e7b17633a49p+61
-+insn wcgdb07:
-+ v_result = e636b693e39a1100 | 0000000000000000
-+ v_arg1 = -0x1.9c9496c1c65efp+60 | 0x1.c4182ee728d76p-572
-+insn wcgdb07:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = -0x1.819718032dff7p-303 | 0x1.a784c77ff6aa2p-622
-+insn wcgdb07:
-+ v_result = 7fffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.978e8abfd83c2p+152 | 0x1.2531ebf451762p+315
-+insn vclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.23363aaa9ca54p+517 | 0x1.7243af9b17426p-313
-+insn vclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.9cd926092c28dp-961 | -0x1.d359f3e9bb6fdp-863
-+insn vclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.0c2e79701cfedp+113 | -0x1.386cc4d0c2753p-639
-+insn vclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.6404fbeee6e51p-833 | -0x1.88c7c4c78e8b5p-875
-+insn vclgdb01:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = -0x1.becf5aabeedb2p-279 | 0x1.8f46a8584af8bp+339
-+insn vclgdb01:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = -0x1.ba405560535ecp+419 | 0x1.f5f0d2ac089dbp+960
-+insn vclgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.13765a3448273p-46 | -0x1.4245b126d990bp-32
-+insn vclgdb01:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.42f7c19ab251ep+182 | -0x1.d11887b37d89ep+652
-+insn vclgdb03:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.c89eea4d649dfp+1002 | -0x1.02ac7c6fad4f4p-857
-+insn vclgdb03:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.c785c5992ac87p-658 | -0x1.e69063f7f720dp-81
-+insn vclgdb03:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.7262730986284p+402 | -0x1.97db5d33ead45p+341
-+insn vclgdb03:
-+ v_result = 0000000000000000 | 0000000000000001
-+ v_arg1 = -0x1.e732cc74f96a5p+338 | 0x1.e8c7ed81c5518p-50
-+insn vclgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.fb488268d49d4p-603 | 0x1.af20dca2dd1dep-649
-+insn vclgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.77654765512dap-986 | 0x1.700c80872de8ep-676
-+insn vclgdb04:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.f3969c999dd1dp+671 | 0x1.ebe969b9a4e7ep-330
-+insn vclgdb04:
-+ v_result = ffffffffffffffff | ffffffffffffffff
-+ v_arg1 = 0x1.1361bd5f8ad64p+859 | 0x1.6aa9af0c3cb2p+281
-+insn vclgdb05:
-+ v_result = ffffffffffffffff | ffffffffffffffff
-+ v_arg1 = 0x1.21a00ba7f5a8fp+265 | 0x1.277f89a3992c5p+139
-+insn vclgdb05:
-+ v_result = ffffffffffffffff | ffffffffffffffff
-+ v_arg1 = 0x1.8c9a9b86a5462p+672 | 0x1.5d08d1235385bp+372
-+insn vclgdb05:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.41d67fae35e3ap-120 | 0x1.013ba779e6931p-854
-+insn vclgdb05:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.7a5064fc054d4p+900 | -0x1.117184fcaa4b1p+826
-+insn vclgdb06:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = -0x1.06793ec47e70cp+690 | 0x1.4e743453c0123p+679
-+insn vclgdb06:
-+ v_result = 0000000000000001 | ffffffffffffffff
-+ v_arg1 = 0x1.b9f182ced5c9ap-622 | 0x1.48593e965ed7p+213
-+insn vclgdb06:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.27e5c501152d5p-727 | -0x1.aa8dc7366e9dbp+4
-+insn vclgdb06:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.eeca740c47973p-380 | -0x1.b7f3480cb4ec7p+750
-+insn vclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.5477b49835c46p-130 | -0x1.d6cacd4500c77p+113
-+insn vclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.c235bdef919ffp+466 | -0x1.1ca14189e67c8p+29
-+insn vclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.5088657c024edp+64 | -0x1.8a9ba9a0ebaf7p-628
-+insn vclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.137bbb51f08bdp+306 | 0x1.18d2a1063356p-795
-+insn wclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.e66f55dcc2639p-1013 | -0x1.733ee56929f3bp-304
-+insn wclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.8802fd9ab740cp-986 | -0x1.64d4d2c7c145fp-1015
-+insn wclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.a67209b8c407bp-645 | -0x1.6410ff9b1c801p+487
-+insn wclgdb00:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.cb2febaefeb2dp+49 | 0x1.dee368b2ec375p-502
-+insn wclgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.5703db3c1b0e2p-728 | 0x1.068c4d51ea4ebp+617
-+insn wclgdb01:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.ae350291e5b3ep+291 | 0x1.1b87bb09b6032p+376
-+insn wclgdb01:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.c4666a710127ep+424 | -0x1.19e969b6c0076p+491
-+insn wclgdb01:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.c892c5a4d103fp+105 | -0x1.d4f937cc76704p+749
-+insn wclgdb03:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.81090d8fc663dp-111 | 0x1.337ec5e0f0904p+1
-+insn wclgdb03:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.e787adc70b91p-593 | 0x1.db8d83196b53cp-762
-+insn wclgdb03:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.6529307e907efp+389 | -0x1.3ea0d8d5b4dd2p+589
-+insn wclgdb03:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.be701a158637p-385 | 0x1.c5a7f70cb8a09p+107
-+insn wclgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.2f328571ab445p+21 | -0x1.dcc21fc82ba01p-930
-+insn wclgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.06b69fcbb7bffp-415 | 0x1.6f9a13a0a827ap+915
-+insn wclgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.738e549b38bcdp+479 | 0x1.a522edb999c9p-45
-+insn wclgdb04:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.7f9399d2bcf3bp-215 | -0x1.7bc35f2d69a7fp+818
-+insn wclgdb05:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.fc542bdb707f6p+880 | -0x1.8521ebc93a25fp-969
-+insn wclgdb05:
-+ v_result = 1ce8d9951b8c8600 | 0000000000000000
-+ v_arg1 = 0x1.ce8d9951b8c86p+60 | 0x1.92712589230e7p+475
-+insn wclgdb05:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.8a297f60a0811p-156 | 0x1.102b79043d82cp-204
-+insn wclgdb05:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.beb9057e1401dp-196 | -0x1.820f18f830262p+15
-+insn wclgdb06:
-+ v_result = 0000000000000001 | 0000000000000000
-+ v_arg1 = 0x1.c321a966ecb4dp-430 | -0x1.2f6a1a95ead99p-943
-+insn wclgdb06:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.f1a86b4aed821p-56 | -0x1.1ee6717cc2d7fp-899
-+insn wclgdb06:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.73ce49d89ecb9p-302 | 0x1.52663b975ed23p-716
-+insn wclgdb06:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.3e9c2de97a292p+879 | 0x1.d34eed36f2eafp+960
-+insn wclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.4e6ec6ddc6a45p-632 | -0x1.6e564d0fec72bp+369
-+insn wclgdb07:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.42e2c658e4c4dp+459 | -0x1.9f9dc0252e44p+85
-+insn wclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.fb40ac8cda3c1p-762 | 0x1.0e9ed614bc8f1p-342
-+insn wclgdb07:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.c1f8b3c68e214p+118 | -0x1.1a26a49368b61p+756
-+insn vfidb00:
-+ v_arg1 = -0x1.38df4cf9d52dbp-545 | -0x1.049253d90dd92p+94
-+ v_result = -0x0p+0 | -0x1.049253d90dd92p+94
-+insn vfidb00:
-+ v_arg1 = 0x1.75187b3d8d386p+793 | -0x1.0f5aea6c1c123p+547
-+ v_result = 0x1.75187b3d8d386p+793 | -0x1.0f5aea6c1c123p+547
-+insn vfidb00:
-+ v_arg1 = 0x1.cb54303729724p-337 | -0x1.0791295e0541p+59
-+ v_result = 0x0p+0 | -0x1.0791295e0541p+59
-+insn vfidb00:
-+ v_arg1 = -0x1.1b9a77d71eb22p+825 | -0x1.0189f7d748475p+647
-+ v_result = -0x1.1b9a77d71eb22p+825 | -0x1.0189f7d748475p+647
-+insn vfidb01:
-+ v_arg1 = -0x1.5d26e474def0ap+1013 | -0x1.c4e9efb30da4ap-580
-+ v_result = -0x1.5d26e474def0ap+1013 | -0x0p+0
-+insn vfidb01:
-+ v_arg1 = 0x1.4ad53aba85947p+105 | -0x1.f8f178fb43126p-350
-+ v_result = 0x1.4ad53aba85947p+105 | -0x0p+0
-+insn vfidb01:
-+ v_arg1 = 0x1.aeacddb1336dep+106 | 0x1.0008f60517dffp-355
-+ v_result = 0x1.aeacddb1336dep+106 | 0x0p+0
-+insn vfidb01:
-+ v_arg1 = -0x1.ee2d2afcea935p+75 | 0x1.740cbfdc486e6p-217
-+ v_result = -0x1.ee2d2afcea935p+75 | 0x0p+0
-+insn vfidb03:
-+ v_arg1 = -0x1.662966287abcfp-856 | -0x1.7228d17f9aacep-413
-+ v_result = -0x1p+0 | -0x1p+0
-+insn vfidb03:
-+ v_arg1 = 0x1.86f4c5919ca0cp-384 | -0x1.4715448c89f45p+675
-+ v_result = 0x1p+0 | -0x1.4715448c89f45p+675
-+insn vfidb03:
-+ v_arg1 = -0x1.500e2dc4dececp-219 | -0x1.dab1ecfba3037p-347
-+ v_result = -0x1p+0 | -0x1p+0
-+insn vfidb03:
-+ v_arg1 = -0x1.fc7c8db9b09ccp-892 | -0x1.1c72852c3fcb1p-605
-+ v_result = -0x1p+0 | -0x1p+0
-+insn vfidb04:
-+ v_arg1 = 0x1.3eaa8ace8f425p-858 | 0x1.cf0ac9c083a9ap-249
-+ v_result = 0x0p+0 | 0x0p+0
-+insn vfidb04:
-+ v_arg1 = 0x1.ec22dc8481352p+516 | 0x1.948a15e99787bp+705
-+ v_result = 0x1.ec22dc8481352p+516 | 0x1.948a15e99787bp+705
-+insn vfidb04:
-+ v_arg1 = 0x1.aa3c092bc234ap-99 | -0x1.1a67dee375837p-741
-+ v_result = 0x0p+0 | -0x0p+0
-+insn vfidb04:
-+ v_arg1 = -0x1.0954410f3f66p-870 | -0x1.959f40b0d52d1p+679
-+ v_result = -0x0p+0 | -0x1.959f40b0d52d1p+679
-+insn vfidb05:
-+ v_arg1 = 0x1.714e0b00c3609p+188 | -0x1.7e3b89779752bp-897
-+ v_result = 0x1.714e0b00c3609p+188 | -0x0p+0
-+insn vfidb05:
-+ v_arg1 = 0x1.2d4b405512095p-36 | -0x1.cbf3a5cc327c4p+987
-+ v_result = 0x0p+0 | -0x1.cbf3a5cc327c4p+987
-+insn vfidb05:
-+ v_arg1 = -0x1.47fa188fc49f3p-399 | 0x1.a1d66c8e3e178p-350
-+ v_result = -0x0p+0 | 0x0p+0
-+insn vfidb05:
-+ v_arg1 = 0x1.e760458f45d6fp-672 | -0x1.ea169b23ef443p+754
-+ v_result = 0x0p+0 | -0x1.ea169b23ef443p+754
-+insn vfidb06:
-+ v_arg1 = 0x1.e8c7afa8edb76p-616 | -0x1.4286e146748fdp+864
-+ v_result = 0x1p+0 | -0x1.4286e146748fdp+864
-+insn vfidb06:
-+ v_arg1 = 0x1.0cf9c1b4fdb5p-852 | 0x1.9845bcfe1181dp+687
-+ v_result = 0x1p+0 | 0x1.9845bcfe1181dp+687
-+insn vfidb06:
-+ v_arg1 = -0x1.f40c24aa8cae3p+141 | -0x1.33b966adbb779p+18
-+ v_result = -0x1.f40c24aa8cae3p+141 | -0x1.33b94p+18
-+insn vfidb06:
-+ v_arg1 = 0x1.497c3bfb72975p+895 | 0x1.94dc5d4f14f02p+866
-+ v_result = 0x1.497c3bfb72975p+895 | 0x1.94dc5d4f14f02p+866
-+insn vfidb07:
-+ v_arg1 = 0x1.400b2180c5169p+9 | -0x1.0eb881ef09e8bp+144
-+ v_result = 0x1.4p+9 | -0x1.0eb881ef09e8bp+144
-+insn vfidb07:
-+ v_arg1 = 0x1.5e1a1176032ffp-694 | 0x1.a413f4290b781p+986
-+ v_result = 0x0p+0 | 0x1.a413f4290b781p+986
-+insn vfidb07:
-+ v_arg1 = 0x1.89260655d1017p+657 | -0x1.82ecae03ac7b3p-465
-+ v_result = 0x1.89260655d1017p+657 | -0x1p+0
-+insn vfidb07:
-+ v_arg1 = -0x1.e233d525b46edp+954 | 0x1.70742fcc3ce0bp+148
-+ v_result = -0x1.e233d525b46edp+954 | 0x1.70742fcc3ce0bp+148
-+insn wfidb00:
-+ v_arg1 = -0x1.61bc4941f04ddp-821 | 0x1.658c3c22e6351p+180
-+ v_result = -0x0p+0 | --
-+insn wfidb00:
-+ v_arg1 = -0x1.b347e049e111fp-420 | 0x1.da424426c71edp-950
-+ v_result = -0x0p+0 | --
-+insn wfidb00:
-+ v_arg1 = 0x1.920b565b7898ap+329 | 0x1.520bc351efda4p-592
-+ v_result = 0x1.920b565b7898ap+329 | --
-+insn wfidb00:
-+ v_arg1 = -0x1.8482d1dfaa054p+729 | 0x1.57c1eb750de59p-154
-+ v_result = -0x1.8482d1dfaa054p+729 | --
-+insn wfidb01:
-+ v_arg1 = -0x1.e88ebfa665fcep+172 | -0x1.29bdb0b3e83ccp+147
-+ v_result = -0x1.e88ebfa665fcep+172 | --
-+insn wfidb01:
-+ v_arg1 = 0x1.0f5f1ef25622bp-839 | -0x1.d57455b11b25dp+173
-+ v_result = 0x0p+0 | --
-+insn wfidb01:
-+ v_arg1 = 0x1.098fed551a139p+372 | 0x1.73f2976a143c8p+826
-+ v_result = 0x1.098fed551a139p+372 | --
-+insn wfidb01:
-+ v_arg1 = -0x1.f30512cb12425p-608 | 0x1.e58939033eae8p-891
-+ v_result = -0x0p+0 | --
-+insn wfidb03:
-+ v_arg1 = -0x1.af465d77bce39p+75 | -0x1.0e08c063beb77p-766
-+ v_result = -0x1.af465d77bce39p+75 | --
-+insn wfidb03:
-+ v_arg1 = -0x1.f50b5e41314ap-764 | -0x1.607de181ae4ccp-591
-+ v_result = -0x1p+0 | --
-+insn wfidb03:
-+ v_arg1 = 0x1.8a47842c8c31fp-50 | -0x1.8b5cdaee0879ap+947
-+ v_result = 0x1p+0 | --
-+insn wfidb03:
-+ v_arg1 = 0x1.d08648a9cbedcp+182 | -0x1.e47de14095eb5p-832
-+ v_result = 0x1.d08648a9cbedcp+182 | --
-+insn wfidb04:
-+ v_arg1 = 0x1.50b6db7fbbd1ap+133 | -0x1.c5293bf4286cfp+694
-+ v_result = 0x1.50b6db7fbbd1ap+133 | --
-+insn wfidb04:
-+ v_arg1 = -0x1.57085ee8210f9p-986 | 0x1.45f2b06247536p+35
-+ v_result = -0x0p+0 | --
-+insn wfidb04:
-+ v_arg1 = -0x1.df15d38b85b39p+278 | -0x1.6ae64eaf6b596p+961
-+ v_result = -0x1.df15d38b85b39p+278 | --
-+insn wfidb04:
-+ v_arg1 = 0x1.0fc2143d758f6p+241 | -0x1.2f53bcf6ea7bcp-843
-+ v_result = 0x1.0fc2143d758f6p+241 | --
-+insn wfidb05:
-+ v_arg1 = 0x1.c793f2582996cp-505 | 0x1.31faa416f414fp-393
-+ v_result = 0x0p+0 | --
-+insn wfidb05:
-+ v_arg1 = 0x1.c831f1a8f44b3p-318 | -0x1.30d67b0cbd098p-799
-+ v_result = 0x0p+0 | --
-+insn wfidb05:
-+ v_arg1 = -0x1.c2aea42bdd582p+522 | -0x1.d58aa3500b839p+73
-+ v_result = -0x1.c2aea42bdd582p+522 | --
-+insn wfidb05:
-+ v_arg1 = -0x1.33846647de0efp+805 | -0x1.40ee74cfe2ff8p+336
-+ v_result = -0x1.33846647de0efp+805 | --
-+insn wfidb06:
-+ v_arg1 = 0x1.9ea16aeaccd2bp-592 | -0x1.0718e98de0774p-791
-+ v_result = 0x1p+0 | --
-+insn wfidb06:
-+ v_arg1 = -0x1.2b33d73559b49p+432 | 0x1.0bcd0a3aa62edp+137
-+ v_result = -0x1.2b33d73559b49p+432 | --
-+insn wfidb06:
-+ v_arg1 = 0x1.0fd5bed729ef7p-136 | -0x1.7de5c9c1a7cffp-542
-+ v_result = 0x1p+0 | --
-+insn wfidb06:
-+ v_arg1 = 0x1.3e88df9ab4141p+1001 | 0x1.23d1c18546565p-208
-+ v_result = 0x1.3e88df9ab4141p+1001 | --
-+insn wfidb07:
-+ v_arg1 = 0x1.a0a30de14c554p-995 | 0x1.f75fbd2aac4b9p+721
-+ v_result = 0x0p+0 | --
-+insn wfidb07:
-+ v_arg1 = -0x1.22d9d06f10138p+388 | 0x1.617a16b5e9631p-40
-+ v_result = -0x1.22d9d06f10138p+388 | --
-+insn wfidb07:
-+ v_arg1 = -0x1.415ecc4742193p-484 | -0x1.26b342b60ed63p+353
-+ v_result = -0x1p+0 | --
-+insn wfidb07:
-+ v_arg1 = 0x1.a38b40d7c686bp+18 | 0x1.72f17be0db2p+786
-+ v_result = 0x1.a38b4p+18 | --
-+insn vledb00:
-+ v_arg1 = -0x1.a84c84057eee2p-484 | 0x1.c57adf9f0649bp-745
-+ v_result = -0x0p+0 | -- | 0x0p+0 | --
-+insn vledb00:
-+ v_arg1 = 0x1.81df9df7f63fbp+804 | 0x1.1cb169383d862p-99
-+ v_result = 0x1.fffffep+127 | -- | 0x1.1cb168p-99 | --
-+insn vledb00:
-+ v_arg1 = -0x1.71dd9545fca52p+677 | -0x1.92cefededf8e1p-117
-+ v_result = -0x1.fffffep+127 | -- | -0x1.92cefep-117 | --
-+insn vledb00:
-+ v_arg1 = -0x1.65375ad0e40e7p-937 | 0x1.09014cbc484c5p+485
-+ v_result = -0x0p+0 | -- | 0x1.fffffep+127 | --
-+insn vledb01:
-+ v_arg1 = -0x1.505196110b3d2p+107 | -0x1.3426019ccd495p+80
-+ v_result = -0x1.505196p+107 | -- | -0x1.342602p+80 | --
-+insn vledb01:
-+ v_arg1 = -0x1.0af0f091bac0ep+839 | 0x1.e846aa8b59579p-876
-+ v_result = -inf | -- | 0x0p+0 | --
-+insn vledb01:
-+ v_arg1 = -0x1.2c25e28cf0631p+481 | -0x1.84e49efdf88f6p-761
-+ v_result = -inf | -- | -0x0p+0 | --
-+insn vledb01:
-+ v_arg1 = -0x1.2668ee57bb531p-627 | -0x1.70c4fcb1747afp+53
-+ v_result = -0x0p+0 | -- | -0x1.70c4fcp+53 | --
-+insn vledb03:
-+ v_arg1 = 0x1.83961ccdd811fp-57 | -0x1.164d03f590024p+321
-+ v_result = 0x1.83961ep-57 | -- | -0x1.fffffep+127 | --
-+insn vledb03:
-+ v_arg1 = -0x1.70f9991e0c8eep-335 | 0x1.7eedb358f3874p+893
-+ v_result = -0x1p-149 | -- | 0x1.fffffep+127 | --
-+insn vledb03:
-+ v_arg1 = 0x1.2b0b7cd5f402cp+157 | -0x1.bfafe3c4f891dp-342
-+ v_result = 0x1.fffffep+127 | -- | -0x1p-149 | --
-+insn vledb03:
-+ v_arg1 = -0x1.a9eb9c0dfb4c6p+89 | 0x1.a4f0449a065bap+737
-+ v_result = -0x1.a9eb9ep+89 | -- | 0x1.fffffep+127 | --
-+insn vledb04:
-+ v_arg1 = -0x1.dccda0e58c3c6p+254 | -0x1.1e7b977b4d2c3p-832
-+ v_result = -inf | -- | -0x0p+0 | --
-+insn vledb04:
-+ v_arg1 = -0x1.8685582eca417p+537 | 0x1.ab5a3c7ae2d4fp+276
-+ v_result = -inf | -- | inf | --
-+insn vledb04:
-+ v_arg1 = -0x1.49320cface53ep+903 | 0x1.e5fc9e15ce8d3p+298
-+ v_result = -inf | -- | inf | --
-+insn vledb04:
-+ v_arg1 = 0x1.b25b34a582821p+386 | 0x1.4056fd2fc4ce3p-361
-+ v_result = inf | -- | 0x0p+0 | --
-+insn vledb05:
-+ v_arg1 = 0x1.26ac2b21ee5c2p+207 | 0x1.ff8d7ccf938eep-142
-+ v_result = 0x1.fffffep+127 | -- | 0x1.fep-142 | --
-+insn vledb05:
-+ v_arg1 = -0x1.fe8fde9582b04p+564 | 0x1.28400eaaee105p+536
-+ v_result = -0x1.fffffep+127 | -- | 0x1.fffffep+127 | --
-+insn vledb05:
-+ v_arg1 = -0x1.317d5b9516063p-163 | -0x1.ea868ea209093p+333
-+ v_result = -0x0p+0 | -- | -0x1.fffffep+127 | --
-+insn vledb05:
-+ v_arg1 = -0x1.027399100fdbfp-546 | -0x1.1d9ccf1c66825p+36
-+ v_result = -0x0p+0 | -- | -0x1.1d9ccep+36 | --
-+insn vledb06:
-+ v_arg1 = 0x1.2bf5345ca531p+982 | 0x1.7c3e64b441d22p-449
-+ v_result = inf | -- | 0x1p-149 | --
-+insn vledb06:
-+ v_arg1 = -0x1.8b94ed2434a31p+1001 | 0x1.c092c292abf92p+853
-+ v_result = -0x1.fffffep+127 | -- | inf | --
-+insn vledb06:
-+ v_arg1 = 0x1.ce81218ec1d98p+236 | 0x1.6009662b86edap+985
-+ v_result = inf | -- | inf | --
-+insn vledb06:
-+ v_arg1 = -0x1.5d2059ff4201bp+513 | 0x1.d7857339c237dp-955
-+ v_result = -0x1.fffffep+127 | -- | 0x1p-149 | --
-+insn vledb07:
-+ v_arg1 = 0x1.a76ca53f97aabp-255 | -0x1.674a200b06edbp-581
-+ v_result = 0x0p+0 | -- | -0x1p-149 | --
-+insn vledb07:
-+ v_arg1 = 0x1.0080548c7ec1bp+989 | 0x1.2ee6511bf33f3p+395
-+ v_result = 0x1.fffffep+127 | -- | 0x1.fffffep+127 | --
-+insn vledb07:
-+ v_arg1 = -0x1.9b113781789d9p-813 | -0x1.2950f56406c23p-653
-+ v_result = -0x1p-149 | -- | -0x1p-149 | --
-+insn vledb07:
-+ v_arg1 = 0x1.651d480507cb1p+722 | -0x1.58f4c2418ebe6p-70
-+ v_result = 0x1.fffffep+127 | -- | -0x1.58f4c4p-70 | --
-+insn wledb00:
-+ v_arg1 = 0x1.43d646747c59p-257 | -0x1.737c6f65a1694p+700
-+ v_result = 0x0p+0 | -- | -- | --
-+insn wledb00:
-+ v_arg1 = -0x1.201dc5801fd3dp-331 | -0x1.2e0e52d09aa24p+358
-+ v_result = -0x0p+0 | -- | -- | --
-+insn wledb00:
-+ v_arg1 = 0x1.81f14646f0e21p+15 | 0x1.f918fd1d379ebp+784
-+ v_result = 0x1.81f146p+15 | -- | -- | --
-+insn wledb00:
-+ v_arg1 = -0x1.fcf63412ffdffp-746 | -0x1.4c8e74fd72c5cp-193
-+ v_result = -0x0p+0 | -- | -- | --
-+insn wledb01:
-+ v_arg1 = 0x1.ebe5b0e50a1bap+140 | 0x1.638103a5e01c9p+504
-+ v_result = inf | -- | -- | --
-+insn wledb01:
-+ v_arg1 = -0x1.9d0900d0d6914p+359 | -0x1.78bea0aa48f2p-76
-+ v_result = -inf | -- | -- | --
-+insn wledb01:
-+ v_arg1 = 0x1.3de51688f1b6cp-210 | 0x1.721d2e08e7eadp+312
-+ v_result = 0x0p+0 | -- | -- | --
-+insn wledb01:
-+ v_arg1 = -0x1.d796ceeae907ep-668 | -0x1.6cf64417450ddp-126
-+ v_result = -0x0p+0 | -- | -- | --
-+insn wledb03:
-+ v_arg1 = 0x1.3a6edd4af7926p+104 | 0x1.fa23bd7d81cf7p+68
-+ v_result = 0x1.3a6edep+104 | -- | -- | --
-+insn wledb03:
-+ v_arg1 = 0x1.4a0dd74061d1cp+154 | -0x1.d9bae342b4ee3p+307
-+ v_result = 0x1.fffffep+127 | -- | -- | --
-+insn wledb03:
-+ v_arg1 = 0x1.99a06111419b7p-275 | -0x1.871938f8d69e6p-833
-+ v_result = 0x1p-149 | -- | -- | --
-+insn wledb03:
-+ v_arg1 = -0x1.a7bac92e920acp+145 | -0x1.752ff858cc562p-671
-+ v_result = -0x1.fffffep+127 | -- | -- | --
-+insn wledb04:
-+ v_arg1 = -0x1.fa1544402b9cfp+862 | -0x1.ea203dae35299p+583
-+ v_result = -inf | -- | -- | --
-+insn wledb04:
-+ v_arg1 = 0x1.c9f7f990a04cfp+258 | -0x1.0bb6e363b546ap+690
-+ v_result = inf | -- | -- | --
-+insn wledb04:
-+ v_arg1 = 0x1.3ff6eeb9a76fdp-981 | 0x1.dac90e9ec2511p+619
-+ v_result = 0x0p+0 | -- | -- | --
-+insn wledb04:
-+ v_arg1 = 0x1.401df3afc9905p+883 | 0x1.4fcf4a8bbf7e9p-598
-+ v_result = inf | -- | -- | --
-+insn wledb05:
-+ v_arg1 = 0x1.f5bcdeae2ceb1p-482 | -0x1.064234e9c8f2cp-825
-+ v_result = 0x0p+0 | -- | -- | --
-+insn wledb05:
-+ v_arg1 = 0x1.ff73387320bacp-138 | -0x1.d99679d700cbp+220
-+ v_result = 0x1.ff6p-138 | -- | -- | --
-+insn wledb05:
-+ v_arg1 = 0x1.eb9c782bd9d3bp+916 | 0x1.30084fbc69faap-269
-+ v_result = 0x1.fffffep+127 | -- | -- | --
-+insn wledb05:
-+ v_arg1 = -0x1.737c1f102e804p+703 | 0x1.7787f359d506ep-790
-+ v_result = -0x1.fffffep+127 | -- | -- | --
-+insn wledb06:
-+ v_arg1 = -0x1.d7f9453ee23c9p-667 | -0x1.01459401fc02bp-872
-+ v_result = -0x0p+0 | -- | -- | --
-+insn wledb06:
-+ v_arg1 = 0x1.7d5b34b9d1d2cp+188 | 0x1.fdfd3f465e2b2p+97
-+ v_result = inf | -- | -- | --
-+insn wledb06:
-+ v_arg1 = 0x1.7734c6119fb6cp+504 | 0x1.4972ad038c12ep-213
-+ v_result = inf | -- | -- | --
-+insn wledb06:
-+ v_arg1 = 0x1.d480ec418f825p+795 | 0x1.e73dbbacd3fecp-1
-+ v_result = inf | -- | -- | --
-+insn wledb07:
-+ v_arg1 = 0x1.7bbe60bc02413p-511 | 0x1.ade60bc87d013p-400
-+ v_result = 0x0p+0 | -- | -- | --
-+insn wledb07:
-+ v_arg1 = -0x1.365bcf06526cdp+361 | 0x1.23aefc8b7436bp-449
-+ v_result = -inf | -- | -- | --
-+insn wledb07:
-+ v_arg1 = -0x1.9db391449fb8dp-1005 | -0x1.e9f40755e7a19p-55
-+ v_result = -0x1p-149 | -- | -- | --
-+insn wledb07:
-+ v_arg1 = 0x1.46282bf59b5e5p+334 | 0x1.59946c0e82d5fp+936
-+ v_result = 0x1.fffffep+127 | -- | -- | --
-+insn vldeb:
-+ v_arg1 = -0x1.8b9fd9ef53d8ap-833 | -0x1.aeef3cdf1ac5fp-282
-+ v_result = -0x1.d173fap-104 | -0x1.b5dde6p-35
-+insn vldeb:
-+ v_arg1 = 0x1.cd30a83a7130bp-430 | 0x1.256f7a4029ad8p-286
-+ v_result = 0x1.39a614p-53 | 0x1.24adeep-35
-+insn vldeb:
-+ v_arg1 = -0x1.09bc929ea0999p-364 | 0x1.c4281f653b3e6p-652
-+ v_result = -0x1.613792p-45 | 0x1.788502p-81
-+insn vldeb:
-+ v_arg1 = -0x1.7afd9ede30cbfp+556 | -0x1.696fbd68a88c4p-863
-+ v_result = -0x1.6f5fb2p+70 | -0x1.0d2df6p-107
-+insn wldeb:
-+ v_arg1 = -0x1.d26169729db2ap-435 | 0x1.d6fd080793e8cp+767
-+ v_result = -0x1.9a4c2cp-54 | 0x0p+0
-+insn wldeb:
-+ v_arg1 = -0x1.f4b59107fce61p-930 | 0x1.cdf2816e253f4p-168
-+ v_result = -0x1.be96b2p-116 | 0x0p+0
-+insn wldeb:
-+ v_arg1 = -0x1.9603a2997928cp-441 | -0x1.aada85e355a11p-767
-+ v_result = -0x1.d2c074p-55 | 0x0p+0
-+insn wldeb:
-+ v_arg1 = 0x1.25ccf5bd0e83p+620 | 0x1.e1635864ebb17p-88
-+ v_result = 0x1.64b99ep+78 | 0x0p+0
-+insn vflcdb:
-+ v_arg1 = 0x1.0ae6d82f76afp-166 | -0x1.e8fb1e03a7415p-191
-+ v_result = -0x1.0ae6d82f76afp-166 | 0x1.e8fb1e03a7415p-191
-+insn vflcdb:
-+ v_arg1 = 0x1.9f865a209464cp+19 | 0x1.a81bca7f2dbbcp-960
-+ v_result = -0x1.9f865a209464cp+19 | -0x1.a81bca7f2dbbcp-960
-+insn vflcdb:
-+ v_arg1 = 0x1.ed6c6a3ed0163p-5 | 0x1.40b73b91e5a17p+838
-+ v_result = -0x1.ed6c6a3ed0163p-5 | -0x1.40b73b91e5a17p+838
-+insn vflcdb:
-+ v_arg1 = 0x1.19520153d35b4p-301 | 0x1.ac5325cd23253p+396
-+ v_result = -0x1.19520153d35b4p-301 | -0x1.ac5325cd23253p+396
-+insn wflcdb:
-+ v_arg1 = 0x1.ffd3eecfd54d7p-831 | -0x1.97854fa523a77p+146
-+ v_result = -0x1.ffd3eecfd54d7p-831 | 0x0p+0
-+insn wflcdb:
-+ v_arg1 = -0x1.508ea45606447p-442 | 0x1.ae7f0e6cf9d2bp+583
-+ v_result = 0x1.508ea45606447p-442 | 0x0p+0
-+insn wflcdb:
-+ v_arg1 = 0x1.da8ab2188c21ap+94 | 0x1.78a9c152aa074p-808
-+ v_result = -0x1.da8ab2188c21ap+94 | 0x0p+0
-+insn wflcdb:
-+ v_arg1 = -0x1.086882645e0c5p-1001 | -0x1.54e2de5af5a74p-262
-+ v_result = 0x1.086882645e0c5p-1001 | 0x0p+0
-+insn vflndb:
-+ v_arg1 = -0x1.5bec561d407dcp+819 | -0x1.a5773dadb7a2dp+935
-+ v_result = -0x1.5bec561d407dcp+819 | -0x1.a5773dadb7a2dp+935
-+insn vflndb:
-+ v_arg1 = -0x1.fa5a407a116cep+972 | 0x1.7bf005c15063dp-437
-+ v_result = -0x1.fa5a407a116cep+972 | -0x1.7bf005c15063dp-437
-+insn vflndb:
-+ v_arg1 = -0x1.184242f0442acp-994 | -0x1.e54e17c7617a2p-355
-+ v_result = -0x1.184242f0442acp-994 | -0x1.e54e17c7617a2p-355
-+insn vflndb:
-+ v_arg1 = -0x1.c5bc39a06d4e2p-259 | 0x1.c5e61ad849e77p-833
-+ v_result = -0x1.c5bc39a06d4e2p-259 | -0x1.c5e61ad849e77p-833
-+insn wflndb:
-+ v_arg1 = -0x1.e9f3e6d1beffap-117 | -0x1.d58cc8bf123b3p-714
-+ v_result = -0x1.e9f3e6d1beffap-117 | 0x0p+0
-+insn wflndb:
-+ v_arg1 = -0x1.3fc4ef2e7485ep-691 | 0x1.eb328986081efp-775
-+ v_result = -0x1.3fc4ef2e7485ep-691 | 0x0p+0
-+insn wflndb:
-+ v_arg1 = -0x1.7146c5afdec16p+23 | -0x1.597fcfa1fab2p-708
-+ v_result = -0x1.7146c5afdec16p+23 | 0x0p+0
-+insn wflndb:
-+ v_arg1 = 0x1.03f8d7e9afe84p-947 | 0x1.9a10c3feb6b57p-118
-+ v_result = -0x1.03f8d7e9afe84p-947 | 0x0p+0
-+insn vflpdb:
-+ v_arg1 = 0x1.64ae59b6c762ep-407 | -0x1.fa7191ab21e86p+533
-+ v_result = 0x1.64ae59b6c762ep-407 | 0x1.fa7191ab21e86p+533
-+insn vflpdb:
-+ v_arg1 = -0x1.e39a61250e473p-116 | -0x1.970a4244b7a3dp+800
-+ v_result = 0x1.e39a61250e473p-116 | 0x1.970a4244b7a3dp+800
-+insn vflpdb:
-+ v_arg1 = -0x1.905c12e0e2c53p+264 | 0x1.87daa9c3e4967p-647
-+ v_result = 0x1.905c12e0e2c53p+264 | 0x1.87daa9c3e4967p-647
-+insn vflpdb:
-+ v_arg1 = -0x1.85fa2de1d492ap+170 | 0x1.ac36828822c11p-968
-+ v_result = 0x1.85fa2de1d492ap+170 | 0x1.ac36828822c11p-968
-+insn wflpdb:
-+ v_arg1 = 0x1.a6cf677640a73p-871 | 0x1.b6f1792385922p-278
-+ v_result = 0x1.a6cf677640a73p-871 | 0x0p+0
-+insn wflpdb:
-+ v_arg1 = -0x1.b886774f6d888p-191 | -0x1.6a2b08d735d22p-643
-+ v_result = 0x1.b886774f6d888p-191 | 0x0p+0
-+insn wflpdb:
-+ v_arg1 = 0x1.5045d37d46f5fp+943 | -0x1.333a86ef2dcf6p-1013
-+ v_result = 0x1.5045d37d46f5fp+943 | 0x0p+0
-+insn wflpdb:
-+ v_arg1 = 0x1.1e7bec6ada14dp+252 | 0x1.a70b3f3e24dap-153
-+ v_result = 0x1.1e7bec6ada14dp+252 | 0x0p+0
-+insn vfadb:
-+ v_arg1 = 0x1.5b1ad8e9f17c6p-294 | -0x1.ddd8300a0bf02p+122
-+ v_arg2 = -0x1.9b49c31ca8ac6p+926 | 0x1.fdbc992926268p+677
-+ v_result = -0x1.9b49c31ca8ac5p+926 | 0x1.fdbc992926267p+677
-+insn vfadb:
-+ v_arg1 = -0x1.6144d24f60f19p+321 | -0x1.0f4885e73979ap+190
-+ v_arg2 = 0x1.cf70ab6af95e5p-656 | -0x1.d2a10763bba9ep+317
-+ v_result = -0x1.6144d24f60f18p+321 | -0x1.d2a10763bba9ep+317
-+insn vfadb:
-+ v_arg1 = -0x1.6ba7d00ea2037p-839 | 0x1.3e5b07b555046p-553
-+ v_arg2 = -0x1.d400afb20401fp+608 | 0x1.600f85fbc2774p-86
-+ v_result = -0x1.d400afb20401fp+608 | 0x1.600f85fbc2774p-86
-+insn vfadb:
-+ v_arg1 = -0x1.5039c4164f26bp+471 | -0x1.554272eaa3a01p-539
-+ v_arg2 = 0x1.a3a594bc042dep+515 | 0x1.6d08aceb68682p+706
-+ v_result = 0x1.a3a594bc0418dp+515 | 0x1.6d08aceb68681p+706
-+insn wfadb:
-+ v_arg1 = 0x1.3c5466cb80722p+489 | -0x1.11e1770053ca2p+924
-+ v_arg2 = 0x1.d876cd721a726p-946 | 0x1.5c04ceb79c9bcp+1001
-+ v_result = 0x1.3c5466cb80722p+489 | 0x0p+0
-+insn wfadb:
-+ v_arg1 = 0x1.b0b142d6b76a3p+577 | 0x1.3146824e993a2p+432
-+ v_arg2 = -0x1.f7f3b7582925fp-684 | -0x1.9700143c2b935p-837
-+ v_result = 0x1.b0b142d6b76a2p+577 | 0x0p+0
-+insn wfadb:
-+ v_arg1 = -0x1.8d65e15edabd6p+244 | 0x1.3be7fd08492d6p-141
-+ v_arg2 = -0x1.5eef86490fb0ap+481 | 0x1.7b26c897cb6dfp+810
-+ v_result = -0x1.5eef86490fb0ap+481 | 0x0p+0
-+insn wfadb:
-+ v_arg1 = -0x1.2dffa5b5f29p+34 | 0x1.71a026274602fp-881
-+ v_arg2 = 0x1.4dad707287289p+756 | -0x1.1500d55807247p-616
-+ v_result = 0x1.4dad707287288p+756 | 0x0p+0
-+insn vfsdb:
-+ v_arg1 = 0x1.054fd9c4d4883p+644 | 0x1.45c90ed85bd7fp-780
-+ v_arg2 = 0x1.f3bc7a611dadap+494 | -0x1.7c9e1e858ba5bp-301
-+ v_result = 0x1.054fd9c4d4882p+644 | 0x1.7c9e1e858ba5bp-301
-+insn vfsdb:
-+ v_arg1 = -0x1.697779c72f8a1p-232 | 0x1.cac8c6a6fbe36p-751
-+ v_arg2 = 0x1.6c23630c5305bp-897 | 0x1.91525e7f72d26p+516
-+ v_result = -0x1.697779c72f8a1p-232 | -0x1.91525e7f72d25p+516
-+insn vfsdb:
-+ v_arg1 = 0x1.7033a03797d39p-722 | 0x1.fecd2799b8d1fp-588
-+ v_arg2 = -0x1.794d0fc274286p+204 | 0x1.25d121c810391p-344
-+ v_result = 0x1.794d0fc274286p+204 | -0x1.25d121c81039p-344
-+insn vfsdb:
-+ v_arg1 = 0x1.3a79321b93187p+146 | 0x1.d707e1ddd2a26p-13
-+ v_arg2 = -0x1.00c3f844d79b5p+354 | 0x1.dc5a03907c923p-869
-+ v_result = 0x1.00c3f844d79b5p+354 | 0x1.d707e1ddd2a25p-13
-+insn wfsdb:
-+ v_arg1 = 0x1.9090dabf846e7p-648 | 0x1.1c4ab843a2d15p+329
-+ v_arg2 = -0x1.a7ceb293690dep+316 | 0x1.22245954a20cp+42
-+ v_result = 0x1.a7ceb293690dep+316 | 0x0p+0
-+insn wfsdb:
-+ v_arg1 = 0x1.4e5347c27819p-933 | -0x1.56a30bda28351p-64
-+ v_arg2 = -0x1.dedb9f3935b56p-155 | 0x1.8c5b6ed76816cp-522
-+ v_result = 0x1.dedb9f3935b56p-155 | 0x0p+0
-+insn wfsdb:
-+ v_arg1 = 0x1.0ec4e562a015bp-491 | 0x1.3996381b52d9fp-686
-+ v_arg2 = 0x1.1dcce4e81819p+960 | -0x1.32fa425e8fc08p-263
-+ v_result = -0x1.1dcce4e81818fp+960 | 0x0p+0
-+insn wfsdb:
-+ v_arg1 = -0x1.587229f90f77dp-19 | 0x1.100d8eb8105e4p-784
-+ v_arg2 = -0x1.afb4cce4c43ddp+530 | -0x1.6da7f05e7f512p-869
-+ v_result = 0x1.afb4cce4c43dcp+530 | 0x0p+0
-+insn vfmdb:
-+ v_arg1 = 0x1.892b425556c47p-124 | 0x1.38222404079dfp-656
-+ v_arg2 = 0x1.af612ed2c342dp-267 | -0x1.1f735fd6ce768p-877
-+ v_result = 0x1.4b428afda35a7p-390 | -0x0p+0
-+insn vfmdb:
-+ v_arg1 = -0x1.02106dba6feecp-272 | 0x1.cf890a91d4eefp-455
-+ v_arg2 = -0x1.12c7fc909ffcbp+782 | -0x1.22bf2e2dd2204p-721
-+ v_result = 0x1.14ff2ed0ce42bp+510 | -0x0p+0
-+insn vfmdb:
-+ v_arg1 = -0x1.e3fd7999ca339p+101 | 0x1.cf2eff4ef5fd2p+816
-+ v_arg2 = -0x1.e722ee73a2523p-135 | 0x1.652dfb0cc8dbfp+179
-+ v_result = 0x1.cc7c9e66fd70ap-33 | 0x1.431fddc319ee2p+996
-+insn vfmdb:
-+ v_arg1 = 0x1.2aa65e0fe665dp+729 | 0x1.1774d58fb5c62p+50
-+ v_arg2 = -0x1.ed5baf340bd7ep+475 | -0x1.83de646bb6511p+564
-+ v_result = -0x1.fffffffffffffp+1023 | -0x1.a76863c8aab11p+614
-+insn wfmdb:
-+ v_arg1 = -0x1.b992d950126a1p-683 | -0x1.9c1b22eb58c59p-497
-+ v_arg2 = 0x1.b557a7d8e32c3p-25 | -0x1.f746b2ddafccep+227
-+ v_result = -0x1.792f6fb13894ap-707 | 0x0p+0
-+insn wfmdb:
-+ v_arg1 = -0x1.677a8c20a5a2fp+876 | 0x1.c03e7b97e8c0dp-645
-+ v_arg2 = 0x1.dab44be430937p-1011 | -0x1.3f51352c67be9p-916
-+ v_result = -0x1.4d4b0a1827064p-134 | 0x0p+0
-+insn wfmdb:
-+ v_arg1 = -0x1.da60f596ad0cep+254 | 0x1.52332e0650e33p+966
-+ v_arg2 = 0x1.a042c52ed993cp+215 | 0x1.8f380c84aa133p+204
-+ v_result = -0x1.81aca4bbcbd24p+470 | 0x0p+0
-+insn wfmdb:
-+ v_arg1 = -0x1.83d17f11f6aa3p-469 | -0x1.98117efe89b9ep-361
-+ v_arg2 = 0x1.8c445fd46d214p-701 | -0x1.f98118821821cp+596
-+ v_result = -0x0p+0 | 0x0p+0
-+insn vfddb:
-+ v_arg1 = -0x1.ecbb48899e0f1p+969 | 0x1.caf175ab352p-20
-+ v_arg2 = -0x1.9455d67f9f79dp+208 | 0x1.bc4a431b04a6fp+482
-+ v_result = 0x1.37f78f2cbe546p+761 | 0x1.087170c12984cp-502
-+insn vfddb:
-+ v_arg1 = 0x1.213d83f7082d8p-330 | 0x1.237737a5fa7a6p+548
-+ v_arg2 = 0x1.d96c3df5d6415p-214 | -0x1.8cd56c8cef818p+139
-+ v_result = 0x1.38cf2a1e99e53p-117 | -0x1.780d86d7eff49p+408
-+insn vfddb:
-+ v_arg1 = 0x1.9ce332231f317p-915 | -0x1.a58e84e32263ep-1000
-+ v_arg2 = 0x1.23d041c374ad6p-905 | -0x1.33e41797e24ep+986
-+ v_result = 0x1.6a3702fbc252cp-10 | 0x0p+0
-+insn vfddb:
-+ v_arg1 = -0x1.26cf3de11efccp-342 | 0x1.3ca733ce42f94p-818
-+ v_arg2 = -0x1.5f5a8f87a6e19p+319 | 0x1.8993c56b2ba2dp+426
-+ v_result = 0x1.ad9a43954644bp-662 | 0x0p+0
-+insn wfddb:
-+ v_arg1 = 0x1.bd48489b60731p-114 | 0x1.a760dcf57b74fp-51
-+ v_arg2 = -0x1.171f83409eeb6p-402 | -0x1.e159d1409bdc6p-972
-+ v_result = -0x1.9864f1511f8cp+288 | 0x0p+0
-+insn wfddb:
-+ v_arg1 = -0x1.120505ef4606p-637 | -0x1.83f6f775c0eb7p+272
-+ v_arg2 = -0x1.d18ba3872fde1p+298 | 0x1.c60f8d191068cp-454
-+ v_result = 0x1.2d5cdb15a686cp-936 | 0x0p+0
-+insn wfddb:
-+ v_arg1 = 0x1.f637f7f8c790fp-97 | -0x1.7bdce4d74947p+189
-+ v_arg2 = -0x1.1c8f2d1b3a2edp-218 | -0x1.55fdfd1840241p-350
-+ v_result = -0x1.c3d0799c1420fp+121 | 0x0p+0
-+insn wfddb:
-+ v_arg1 = -0x1.c63b7b2eee253p+250 | 0x1.dfd9dcd8b823fp-125
-+ v_arg2 = 0x1.094a1f1f87e0cp+629 | 0x1.eeaa23c0d7843p-814
-+ v_result = -0x1.b653a10ebdeccp-379 | 0x0p+0
-+insn vfsqdb:
-+ v_arg1 = 0x1.f60db25f7066p-703 | -0x1.d43509abca8c3p+631
-+ v_result = 0x1.fb009ab25ec11p-352 | nan
-+insn vfsqdb:
-+ v_arg1 = -0x1.ecbce2bb2e245p-872 | 0x1.cc9173d132a3bp-290
-+ v_result = nan | 0x1.575fa6778042ep-145
-+insn vfsqdb:
-+ v_arg1 = 0x1.9102ffd19ccb3p-205 | -0x1.87e9ee7454345p-374
-+ v_result = 0x1.c51ecb6cc318p-103 | nan
-+insn vfsqdb:
-+ v_arg1 = 0x1.24e1d7ad32eb5p+499 | -0x1.1c7d22b78039bp+918
-+ v_result = 0x1.833dba0954bccp+249 | nan
-+insn wfsqdb:
-+ v_arg1 = 0x1.71af4e7f64978p+481 | -0x1.3429dc60011d7p-879
-+ v_result = 0x1.b30fc65551133p+240 | 0x0p+0
-+insn wfsqdb:
-+ v_arg1 = 0x1.5410db1c5f403p+173 | 0x1.97fa6581e692fp+108
-+ v_result = 0x1.a144f43a592c1p+86 | 0x0p+0
-+insn wfsqdb:
-+ v_arg1 = -0x1.5838027725afep+6 | 0x1.ac61529c11f38p+565
-+ v_result = nan | 0x0p+0
-+insn wfsqdb:
-+ v_arg1 = -0x1.159e341dcc06ep-439 | 0x1.ed54ce5481ba5p-574
-+ v_result = nan | 0x0p+0
-+insn vfmadb:
-+ v_arg1 = -0x1.eb00a5c503d75p+538 | 0x1.89fae603ddc07p+767
-+ v_arg2 = -0x1.71c72712c3957p+715 | 0x1.1bd5773442feap+762
-+ v_arg3 = 0x1.bd0daed56ada5p+355 | 0x1.618b7cfa37a8bp-935
-+ v_result = 0x1.fffffffffffffp+1023 | 0x1.fffffffffffffp+1023
-+insn vfmadb:
-+ v_arg1 = 0x1.2acc8fc4a8115p-394 | -0x1.b0e5a531a368ep+599
-+ v_arg2 = 0x1.7e7c008b06eb6p-26 | -0x1.a3368d351c861p+17
-+ v_arg3 = 0x1.665fcd4adbb82p-991 | 0x1.b27284ea351eap+402
-+ v_result = 0x1.be6dfa3f5b30dp-420 | 0x1.62720e4cb1583p+617
-+insn vfmadb:
-+ v_arg1 = -0x1.e66ac8a348fedp-315 | 0x1.8c2ef1e0615c5p+132
-+ v_arg2 = 0x1.01397e671d7fdp+313 | -0x1.97c403198fa76p-750
-+ v_arg3 = -0x1.1568273c73bf1p-843 | 0x1.8f0b6073eadccp+277
-+ v_result = -0x1.e8be715f14671p-2 | 0x1.8f0b6073eadcbp+277
-+insn vfmadb:
-+ v_arg1 = -0x1.4afc3142483f9p+706 | 0x1.dd14885973858p+695
-+ v_arg2 = 0x1.ebc6146439945p-726 | -0x1.77a97fce9117p-586
-+ v_arg3 = 0x1.60a3231346326p+102 | -0x1.621f717816614p-653
-+ v_result = 0x1.60a3231346325p+102 | -0x1.5e0a7a3b97e9bp+110
-+insn wfmadb:
-+ v_arg1 = 0x1.1cc5b10a14d54p+668 | -0x1.686407390f7d1p+616
-+ v_arg2 = -0x1.bf34549e73246p+676 | -0x1.dc5a34cc470f3p+595
-+ v_arg3 = -0x1.95e0fdcf13974p-811 | -0x1.79c7cc1a8ec83p-558
-+ v_result = -0x1.fffffffffffffp+1023 | 0x0p+0
-+insn wfmadb:
-+ v_arg1 = 0x1.138bc1a5d75f8p+713 | -0x1.e226ebba2fe54p+381
-+ v_arg2 = -0x1.081ebb7cc3414p-772 | 0x1.369d99e174fc3p+922
-+ v_arg3 = -0x1.0671c682a5d0cp-1016 | 0x1.03c9530dd0377p+378
-+ v_result = -0x1.1c4933e117d95p-59 | 0x0p+0
-+insn wfmadb:
-+ v_arg1 = -0x1.166f0b1fad67bp+64 | -0x1.e9ee8d32e1069p-452
-+ v_arg2 = -0x1.4a235bdd109e2p-65 | 0x1.bacaa96fc7e81p-403
-+ v_arg3 = -0x1.d2e19acf7c4bdp+99 | 0x1.f901130f685adp-963
-+ v_result = -0x1.d2e19acf7c4bcp+99 | 0x0p+0
-+insn wfmadb:
-+ v_arg1 = -0x1.77d7bfec863d2p-988 | -0x1.b68029700c6b1p-206
-+ v_arg2 = -0x1.aca05ad00aec1p+737 | 0x1.ac746bd7e216bp+51
-+ v_arg3 = 0x1.17342292078b4p+188 | -0x1.49efaf9392301p+555
-+ v_result = 0x1.17342292078b4p+188 | 0x0p+0
-+insn vfmsdb:
-+ v_arg1 = -0x1.a1b218e84e61p+34 | 0x1.b220f0d144daep-111
-+ v_arg2 = 0x1.564fcc2527961p-265 | 0x1.ea85a4154721ep+733
-+ v_arg3 = 0x1.a6c16c3dc593cp-1012 | -0x1.ba15ae51a252bp+979
-+ v_result = -0x1.1743102949c9bp-230 | 0x1.ba15ae51a252bp+979
-+insn vfmsdb:
-+ v_arg1 = 0x1.f13a61419bc27p+603 | -0x1.f671d1b532c7fp+668
-+ v_arg2 = -0x1.68f38da70d3cdp+145 | 0x1.7b7d4b8a38256p+87
-+ v_arg3 = -0x1.4830d858cdf7dp-522 | -0x1.ecdfb36fb2682p+537
-+ v_result = -0x1.5e89932819567p+749 | -0x1.746835a6a3d29p+756
-+insn vfmsdb:
-+ v_arg1 = -0x1.82f8829619ba4p+274 | -0x1.886bc5356fc9fp+4
-+ v_arg2 = 0x1.ae0143a6fff31p-759 | 0x1.08e9ddebff9acp-192
-+ v_arg3 = 0x1.a1c5f6283d74p+602 | 0x1.60722d2eadabcp+573
-+ v_result = -0x1.a1c5f6283d74p+602 | -0x1.60722d2eadabcp+573
-+insn vfmsdb:
-+ v_arg1 = -0x1.6efc50de44d76p-235 | -0x1.546b6a9202facp+17
-+ v_arg2 = 0x1.023eb4e92d296p-593 | 0x1.6c05c52e8d255p-408
-+ v_arg3 = -0x1.54cc2efc022a8p+360 | 0x1.9ae520664c8abp+486
-+ v_result = 0x1.54cc2efc022a7p+360 | -0x1.9ae520664c8abp+486
-+insn wfmsdb:
-+ v_arg1 = -0x1.7499a639673a6p-100 | -0x1.2a0d737e6cb1cp-207
-+ v_arg2 = -0x1.01ad4670a7aa3p-911 | 0x1.f94385e1021e8p+317
-+ v_arg3 = 0x1.aa42b2bb17af9p+982 | 0x1.c550e471711p+786
-+ v_result = -0x1.aa42b2bb17af8p+982 | 0x0p+0
-+insn wfmsdb:
-+ v_arg1 = 0x1.76840f99b431ep+500 | -0x1.989a500c92c08p+594
-+ v_arg2 = 0x1.33c657cb8385cp-84 | -0x1.2c795ad92ce17p+807
-+ v_arg3 = -0x1.ee58a39f02d54p-351 | -0x1.18695ed9a280ap+48
-+ v_result = 0x1.c242894a0068p+416 | 0x0p+0
-+insn wfmsdb:
-+ v_arg1 = -0x1.16db07e054a65p-469 | -0x1.3a627ab99c6e4p+689
-+ v_arg2 = 0x1.17872eae826e5p-538 | 0x1.44ed513fb5873p-929
-+ v_arg3 = 0x1.5ca912008e077p-217 | -0x1.982a6f7359876p-23
-+ v_result = -0x1.5ca912008e077p-217 | 0x0p+0
-+insn wfmsdb:
-+ v_arg1 = -0x1.d315f4a932c6p+122 | 0x1.616a04493e143p+513
-+ v_arg2 = -0x1.cf1cd3516f23fp+552 | 0x1.7121749c3932cp-750
-+ v_arg3 = 0x1.dc26d92304d7fp-192 | -0x1.1fc3cca9ec20ep+371
-+ v_result = 0x1.a67ca6ba395bcp+675 | 0x0p+0
-+insn wfcdb:
-+ v_arg1 = 0x1.302001b736011p-633 | -0x1.72d5300225c97p-468
-+ v_arg2 = -0x1.8c007c5aba108p-17 | -0x1.bb3f9ae136acdp+569
-+ r_result = 0000000000000002
-+insn wfcdb:
-+ v_arg1 = -0x1.56248d3fff55ap-440 | -0x1.83340f6a06bedp-612
-+ v_arg2 = 0x1.5b62caabf4e3ep-302 | 0x1.0465808809e02p+199
-+ r_result = 0000000000000001
-+insn wfcdb:
-+ v_arg1 = 0x1.7cca43b8250bap-969 | 0x1.a2ae4e71459b3p+792
-+ v_arg2 = -0x1.2178959d8e9fbp-238 | -0x1.1180e41cc8654p+609
-+ r_result = 0000000000000002
-+insn wfcdb:
-+ v_arg1 = 0x1.96f03c4f3ec0dp-774 | 0x1.a86fcf7f54875p+448
-+ v_arg2 = -0x1.a61696da8f939p-732 | -0x1.969b12babcde9p+239
-+ r_result = 0000000000000002
-+insn wfkdb:
-+ v_arg1 = -0x1.af19141b6194ep-304 | 0x1.6f34172e4ec9ap+281
-+ v_arg2 = -0x1.903d268d15b8dp-496 | 0x1.132593e7a3848p+663
-+ r_result = 0000000000000001
-+insn wfkdb:
-+ v_arg1 = -0x1.52e78ae61bf57p-979 | -0x1.8132c8874542ap+264
-+ v_arg2 = -0x1.7274a70a201eep+729 | 0x1.ee05a55085e12p-508
-+ r_result = 0000000000000002
-+insn wfkdb:
-+ v_arg1 = -0x1.6f8a0ed73189ep-27 | -0x1.93db112e3a289p-560
-+ v_arg2 = -0x1.a699712dab56fp-677 | 0x1.5170475506fc8p-437
-+ r_result = 0000000000000001
-+insn wfkdb:
-+ v_arg1 = -0x1.5d56e841d7af8p+346 | -0x1.e40064ce1ce3bp-1012
-+ v_arg2 = 0x1.79e790363d4ffp+888 | 0x1.97168873bee8ap-323
-+ r_result = 0000000000000001
-+insn vfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.8c48762fd0b58p+38 | 0x1.c1f5c994768a1p-819
-+ v_arg2 = -0x1.08f71db17132ep+914 | 0x1.a3d14196177d5p-229
-+insn vfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.4f88d97dc8b9p+73 | 0x1.6d3a343e053bap+356
-+ v_arg2 = -0x1.5bc7cd97d3ee9p+135 | 0x1.641d521c77b43p-114
-+insn vfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.b9ce020750f0dp-494 | -0x1.c0d4939228ce1p-82
-+ v_arg2 = -0x1.61ad6a28bf43bp-656 | 0x1.b7973bba1ff4dp-877
-+insn vfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.d8e5c9930c19dp+623 | -0x1.cf1facff4e194p-605
-+ v_arg2 = -0x1.ed6ba02646d0dp+441 | -0x1.2d677e710620bp+810
-+insn wfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.a252009e1a12cp-442 | 0x1.4dc608268bb29p-513
-+ v_arg2 = -0x1.81020aa1a36e6p-687 | -0x1.300e64ce414f1p-899
-+insn wfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.cec439a8d4781p-175 | -0x1.d20e3b281d599p+893
-+ v_arg2 = 0x1.ca17cf16cf0aap-879 | 0x1.61506f8596092p+545
-+insn wfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.0659f5f24a004p+877 | 0x1.fc46867ed0338p-680
-+ v_arg2 = -0x1.1d6849587155ep-1010 | -0x1.f68171edc235fp+575
-+insn wfcedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.dc88a0d46ad79p-816 | 0x1.245140dcaed79p+851
-+ v_arg2 = 0x1.b33e977c7b3ep-818 | -0x1.04319d7c69367p+787
-+insn vfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.ac196c30148c5p-498 | -0x1.a58093963d1aep+355
-+ v_arg2 = 0x1.d321b63762fb1p+28 | -0x1.9a68be31efa17p-143
-+ r_result = 0000000000000003
-+insn vfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.b3657c390dfa7p-452 | 0x1.8a62662f245c4p+1010
-+ v_arg2 = -0x1.70208c68a03aep+974 | 0x1.a0729665a79fap+667
-+ r_result = 0000000000000003
-+insn vfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.3ff1b361c377ep-846 | -0x1.f8fcaa95ff309p+948
-+ v_arg2 = 0x1.749db766981d1p-510 | -0x1.d11abab1dc779p+981
-+ r_result = 0000000000000003
-+insn vfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.2adb2ed7d2b08p-701 | -0x1.be89092fe5ce8p+472
-+ v_arg2 = 0x1.ae2c06ea88ff4p+332 | -0x1.f668ce4f8ef9ap+821
-+ r_result = 0000000000000003
-+insn wfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.645261bf86b1fp-996 | 0x1.abd13c95397aap+992
-+ v_arg2 = -0x1.ba09e8fc66a8cp+113 | 0x1.75dbfe92c16c4p-786
-+ r_result = 0000000000000003
-+insn wfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.d02831d003e7dp+415 | -0x1.611a9dfd10f36p-80
-+ v_arg2 = -0x1.10bda62f4647p+723 | 0x1.cc47af6653378p-614
-+ r_result = 0000000000000003
-+insn wfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.f168f32f84178p-321 | -0x1.79a2a0b9549d1p-136
-+ v_arg2 = 0x1.41e19d1cfa692p+11 | -0x1.2a0ed6e7fd517p-453
-+ r_result = 0000000000000003
-+insn wfcedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.76a9144ee26c5p+188 | -0x1.386aaea2d9cddp-542
-+ v_arg2 = 0x1.810fcf222efc4p-999 | -0x1.ce90a9a43e2a1p+80
-+ r_result = 0000000000000003
-+insn vfchdb:
-+ v_result = ffffffffffffffff | ffffffffffffffff
-+ v_arg1 = -0x1.a5a0d9e617637p-707 | 0x1.039393f56f89cp+540
-+ v_arg2 = -0x1.e08e4bda75373p+861 | -0x1.94f3e6b2a5373p+361
-+insn vfchdb:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = 0x1.c7b84b4fa508p-448 | 0x1.00ca9b4b8a0ecp+837
-+ v_arg2 = 0x1.9e7afd1c5fe6dp-379 | 0x1.af9353417f907p-20
-+insn vfchdb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = -0x1.15637df5529edp-476 | -0x1.3104698aaf00bp-679
-+ v_arg2 = -0x1.503783453ef9dp-282 | 0x1.94198721f3bb6p-491
-+insn vfchdb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.82be31fb88a2dp+946 | -0x1.7ca9e9ff31953p-931
-+ v_arg2 = 0x1.fe75a1052beccp+490 | 0x1.179d18543d678p-255
-+insn wfchdb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.0af85d8d8d609p-464 | -0x1.9f639a686e0fep+203
-+ v_arg2 = -0x1.3142b77b55761p-673 | 0x1.ca9c474339da1p+472
-+insn wfchdb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = -0x1.6cf16959a022bp+213 | 0x1.445606e4363e1p+942
-+ v_arg2 = -0x1.8c343201bbd2p+939 | -0x1.e5095ad0c37a4p-434
-+insn wfchdb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.36b4fc9cf5bdap-52 | -0x1.f1fd95cbcd533p+540
-+ v_arg2 = 0x1.5a2362891c9edp-175 | -0x1.e1f68c319e5d2p+58
-+insn wfchdb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.11c6489f544bbp+811 | 0x1.262a740ec3d47p+456
-+ v_arg2 = -0x1.d9394d354e989p-154 | 0x1.cc21b3094391ap-972
-+insn vfchdbs:
-+ v_result = ffffffffffffffff | ffffffffffffffff
-+ v_arg1 = 0x1.6efcb54fbf69p+929 | 0x1.021ce0bff3c4cp-827
-+ v_arg2 = 0x1.571ae4a8be152p+851 | -0x1.a970c1164e0c9p+737
-+ r_result = 0000000000000000
-+insn vfchdbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.528f5ccfc3efbp-445 | -0x1.c660b9810c512p-663
-+ v_arg2 = -0x1.bcc535b108e06p-294 | 0x1.675d8eddf5a4ap-641
-+ r_result = 0000000000000001
-+insn vfchdbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.300127b01433ap+86 | -0x1.8f19f65e5e3c6p+633
-+ v_arg2 = -0x1.0a88d3c279f7fp-502 | -0x1.d68196f88bde5p+368
-+ r_result = 0000000000000003
-+insn vfchdbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.e68d08fc23febp+955 | -0x1.0f80357b376b4p+800
-+ v_arg2 = 0x1.e426748435a76p+370 | 0x1.8702527d17783p-871
-+ r_result = 0000000000000003
-+insn wfchdbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.6c51b9f6442c8p+639 | 0x1.1e6b37adff703p+702
-+ v_arg2 = 0x1.0cba9c1c75e43p+520 | -0x1.145d44ed90967p+346
-+ r_result = 0000000000000000
-+insn wfchdbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.7b3dd643bf36bp+816 | -0x1.61ce7bfb9307ap-683
-+ v_arg2 = -0x1.f2c998dc15c9ap-776 | 0x1.e16397f2dcdf5p+571
-+ r_result = 0000000000000000
-+insn wfchdbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.cc3be81884e0ap-865 | -0x1.8b353bd41064p+820
-+ v_arg2 = -0x1.2c1bafaafdd4ep-34 | -0x1.24666808ab16ep-435
-+ r_result = 0000000000000000
-+insn wfchdbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.c3de33d3b673ap+554 | 0x1.d39ed71e53096p-798
-+ v_arg2 = -0x1.c1e8f7b3c001p-828 | 0x1.22e2cf797fabp-787
-+ r_result = 0000000000000000
-+insn vfchedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.fdeb244b026aep-169 | 0x1.870a6fe40fd9ep-132
-+ v_arg2 = 0x1.0ce586903392fp-469 | 0x1.cdfd736ae03f8p+471
-+insn vfchedb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.89c8a6a740af8p-958 | 0x1.e132e6edb1316p+78
-+ v_arg2 = -0x1.f10d2c3491358p+683 | 0x1.0def4f092fca2p+322
-+insn vfchedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.a5e8e6900e845p+342 | 0x1.d92b370ee2a1cp+275
-+ v_arg2 = 0x1.799f9efc6ef56p+379 | 0x1.ae60d0239ade7p+933
-+insn vfchedb:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = -0x1.6c5599e7ba923p+829 | -0x1.5d1a1191ed6eap-994
-+ v_arg2 = -0x1.555c8775bc4d2p-478 | -0x1.4aa6a2c82319cp+493
-+insn wfchedb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.ae6cad07b0f3ep-232 | -0x1.2ed61a43f3b99p-74
-+ v_arg2 = -0x1.226f7cddbde13p-902 | -0x1.790d1d6febbf8p+336
-+insn wfchedb:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.20eb8eac3711dp-385 | 0x1.ef71d3312d7e1p+739
-+ v_arg2 = 0x1.7a3ba08c5a0bdp-823 | -0x1.a7845ccaa544dp-129
-+insn wfchedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.97ebdbc057be8p+824 | 0x1.2b7798b063cd6p+237
-+ v_arg2 = 0x1.cdb87a6074294p-81 | -0x1.074c902b19bccp-416
-+insn wfchedb:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.82deebf9ff023p+937 | 0x1.56c5adcf9d4abp-672
-+ v_arg2 = -0x1.311ce49bc9439p+561 | 0x1.c8e1c512d8544p+103
-+insn vfchedbs:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = -0x1.489a0cf606972p-417 | 0x1.a87a278f79c72p+64
-+ v_arg2 = 0x1.17ec17aedbaeap+435 | -0x1.f867d39e61ce2p-919
-+ r_result = 0000000000000001
-+insn vfchedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.33723ef431356p-420 | -0x1.474f097f9ead8p+498
-+ v_arg2 = 0x1.4130d6951ee45p+7 | 0x1.791689e1040f1p+354
-+ r_result = 0000000000000003
-+insn vfchedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.6cf89093275eep-237 | 0x1.451631aa628ebp-186
-+ v_arg2 = 0x1.c349eac0f4204p-200 | 0x1.01c558c10699ap+770
-+ r_result = 0000000000000003
-+insn vfchedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.ea15eabc329b6p+52 | -0x1.7b556461496d6p-682
-+ v_arg2 = -0x1.47f5dfc7a5bcp-569 | 0x1.5877ef33664a3p-758
-+ r_result = 0000000000000003
-+insn wfchedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.a7370ccfd9e49p+505 | 0x1.c6b2385850ca2p-591
-+ v_arg2 = 0x1.984f4fcd338b1p+675 | -0x1.feb996c821232p-39
-+ r_result = 0000000000000003
-+insn wfchedbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.641878612dd2p+207 | 0x1.b35e3292db7f6p+567
-+ v_arg2 = -0x1.18a87f209e96bp+299 | -0x1.3d598f3612d8ap+1016
-+ r_result = 0000000000000000
-+insn wfchedbs:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.cfc2cda244153p+404 | 0x1.d8b2b28e9d8d7p+276
-+ v_arg2 = 0x1.3517b8c7a59a1p-828 | 0x1.6096fab7003ccp-415
-+ r_result = 0000000000000000
-+insn wfchedbs:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.54d656f033e56p-603 | -0x1.95ad0e2088967p+254
-+ v_arg2 = 0x1.4cb319db206e4p-614 | 0x1.b41cd9e3739b6p-862
-+ r_result = 0000000000000003
-+insn vftcidb0:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.7507654eb1cbdp-363 | -0x1.4c5a2d70578a7p-769
-+ r_result = 0000000000000003
-+insn vftcidb0:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.759a0ba4abaf7p+638 | -0x1.fe832724aaa38p+97
-+ r_result = 0000000000000003
-+insn vftcidb0:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.7b3e4bb774c14p-102 | -0x1.b908fc2ed3a14p+766
-+ r_result = 0000000000000003
-+insn vftcidb0:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.85cbf177a1d82p+208 | -0x1.705033c741858p-794
-+ r_result = 0000000000000003
-+insn vftcidb1:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.7cbeef2c94fcap+288 | -0x1.ec1d97b93cbfdp+702
-+ r_result = 0000000000000003
-+insn vftcidb1:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.2ab2a98079656p+47 | -0x1.c371901eb3099p+334
-+ r_result = 0000000000000003
-+insn vftcidb1:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.39eeb39c6012dp-574 | 0x1.98e49f4cc3921p+457
-+ r_result = 0000000000000003
-+insn vftcidb1:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.3fc28ae45b2b3p-452 | -0x1.b632de2f2b0a8p-517
-+ r_result = 0000000000000003
-+insn vftcidb2:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.792143331a16dp-472 | 0x1.78b867d4bf21fp+966
-+ r_result = 0000000000000003
-+insn vftcidb2:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.463e12b675eb9p-361 | 0x1.fcfd460adb415p+411
-+ r_result = 0000000000000003
-+insn vftcidb2:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.d6b7fe0aecc99p+233 | -0x1.3af17c9a3c277p+571
-+ r_result = 0000000000000003
-+insn vftcidb2:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.2575c4180e868p+734 | -0x1.320885d20bb51p+204
-+ r_result = 0000000000000003
-+insn vftcidb3:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.14f24a3c080a1p+651 | -0x1.a4e63e948d889p-821
-+ r_result = 0000000000000003
-+insn vftcidb3:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.8ad818084fd9dp+652 | 0x1.35c9f1c2ca3a9p-489
-+ r_result = 0000000000000003
-+insn vftcidb3:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.0c4da3ccb1a54p-577 | -0x1.620b34e8dc095p+265
-+ r_result = 0000000000000003
-+insn vftcidb3:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.19a17db46ab1ap+844 | -0x1.ae8523c97a84fp+549
-+ r_result = 0000000000000003
-+insn vftcidb4:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.3af5acd125862p+758 | 0x1.3382dcaa769b8p+644
-+ r_result = 0000000000000003
-+insn vftcidb4:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.ab5c5a37a5f7ep+180 | -0x1.48ab6c0046851p+926
-+ r_result = 0000000000000003
-+insn vftcidb4:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.7563ad8b9565bp+255 | 0x1.d0cda8ea71ff4p+761
-+ r_result = 0000000000000003
-+insn vftcidb4:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.df11489b4e747p-917 | -0x1.c66c509f6e09ep-283
-+ r_result = 0000000000000003
-+insn vftcidb8:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.85ef23ec393aep-969 | 0x1.e73a12c839128p+469
-+ r_result = 0000000000000003
-+insn vftcidb8:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.6a66b9f6771d7p-539 | -0x1.e0455d9d06f08p-322
-+ r_result = 0000000000000003
-+insn vftcidb8:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.1ccd94013eda9p-151 | 0x1.3a149960dcc13p-830
-+ r_result = 0000000000000003
-+insn vftcidb8:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.1881157e6896bp+739 | -0x1.5481e51d7d13cp+938
-+ r_result = 0000000000000003
-+insn vftcidb16:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.c0728816e9f7ep+780 | -0x1.82c791cf93d54p-154
-+ r_result = 0000000000000003
-+insn vftcidb16:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.8ad2e81651e24p-284 | 0x1.d78b8f22e24cap-938
-+ r_result = 0000000000000003
-+insn vftcidb16:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.7d4f40176493bp-567 | -0x1.70aba71dbb26bp+824
-+ r_result = 0000000000000003
-+insn vftcidb16:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.98bc950f87c01p+903 | -0x1.2389a9fd7e622p-703
-+ r_result = 0000000000000003
-+insn vftcidb32:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.c583723b0e8dp-973 | -0x1.b8f72a62558b8p-21
-+ r_result = 0000000000000003
-+insn vftcidb32:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.df6ca559152e2p+87 | -0x1.e901b98b7f494p+275
-+ r_result = 0000000000000003
-+insn vftcidb32:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.718c8a77ed80dp+222 | 0x1.272ea2c2cbd7ap+786
-+ r_result = 0000000000000003
-+insn vftcidb32:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.125f88105ad86p+783 | 0x1.ee37380928c4ep+103
-+ r_result = 0000000000000003
-+insn vftcidb64:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.3fb5daf24d9ap-918 | -0x1.5c849d623cfd1p+59
-+ r_result = 0000000000000003
-+insn vftcidb64:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.0adfa2607fa8cp-235 | -0x1.cf9ba570a4a61p+467
-+ r_result = 0000000000000003
-+insn vftcidb64:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.b468fbdc60619p-667 | -0x1.10695d31ddabcp+261
-+ r_result = 0000000000000003
-+insn vftcidb64:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.58459f52a0775p-465 | -0x1.5f6e77fa32ebcp+492
-+ r_result = 0000000000000003
-+insn vftcidb128:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.d9dd5b268dee9p+109 | 0x1.202b8b70f8c1ap-757
-+ r_result = 0000000000000003
-+insn vftcidb128:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.dfe7c00e2019fp-63 | -0x1.35fd1bac1932ep+836
-+ r_result = 0000000000000003
-+insn vftcidb128:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.10886d0eb3e5ep+29 | 0x1.1f27771caf4acp+471
-+ r_result = 0000000000000003
-+insn vftcidb128:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.2d2aab983764ap+430 | 0x1.31a3029a73867p-388
-+ r_result = 0000000000000003
-+insn vftcidb256:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = 0x1.6eadbb81663a7p-756 | -0x1.c6b7c55047e1p+800
-+ r_result = 0000000000000001
-+insn vftcidb256:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = 0x1.0150bf13f5396p-188 | -0x1.f6e9b4e793af6p+546
-+ r_result = 0000000000000001
-+insn vftcidb256:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = -0x1.50be96c89ecd5p-574 | 0x1.d624d134ff7c6p+605
-+ r_result = 0000000000000001
-+insn vftcidb256:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = 0x1.33ca5d92be782p+577 | -0x1.4fe8b0a3a164bp+725
-+ r_result = 0000000000000001
-+insn vftcidb512:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.a8eaa4ccad5d7p-269 | -0x1.12d51bd1f8e2ep-222
-+ r_result = 0000000000000003
-+insn vftcidb512:
-+ v_result = ffffffffffffffff | ffffffffffffffff
-+ v_arg1 = 0x1.61d62033addeep+577 | 0x1.dd1569eceabb6p+829
-+ r_result = 0000000000000000
-+insn vftcidb512:
-+ v_result = 0000000000000000 | ffffffffffffffff
-+ v_arg1 = -0x1.1fbf51c3c7c7cp+803 | 0x1.182d1c5c7d087p-193
-+ r_result = 0000000000000001
-+insn vftcidb512:
-+ v_result = ffffffffffffffff | 0000000000000000
-+ v_arg1 = 0x1.4ee08603f4498p-802 | -0x1.54d34adf83565p+965
-+ r_result = 0000000000000001
-+insn vftcidb1024:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.63580fb229f75p+737 | -0x1.b75f3fb7baaf1p-508
-+ r_result = 0000000000000003
-+insn vftcidb1024:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.a443f42ef8a22p-625 | 0x1.8363d375b5369p+818
-+ r_result = 0000000000000003
-+insn vftcidb1024:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.383e46d9f5b4fp-771 | 0x1.a7dc0924f6a6bp-720
-+ r_result = 0000000000000003
-+insn vftcidb1024:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = -0x1.2148e5bdb7c09p-517 | 0x1.1b2689f7c01b1p-502
-+ r_result = 0000000000000003
-+insn vftcidb2048:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.48b9851b82d7cp-589 | 0x1.86f1e1a36bdd4p-930
-+ r_result = 0000000000000003
-+insn vftcidb2048:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.8b45cbb7947aep-572 | -0x1.c478ca5bd9d0cp-274
-+ r_result = 0000000000000003
-+insn vftcidb2048:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.651f3ea4ff449p-18 | 0x1.381d68603b1edp+264
-+ r_result = 0000000000000003
-+insn vftcidb2048:
-+ v_result = 0000000000000000 | 0000000000000000
-+ v_arg1 = 0x1.7d9f2d51b7851p+653 | 0x1.4da616b63e42ap-415
-+ r_result = 0000000000000003
-diff --git a/none/tests/s390x/vector_float.vgtest b/none/tests/s390x/vector_float.vgtest
-new file mode 100644
-index 0000000..428d2a2
---- /dev/null
-+++ b/none/tests/s390x/vector_float.vgtest
-@@ -0,0 +1,2 @@
-+prog: vector_float
-+prereq: test -e vector_float && ../../../tests/s390x_features s390x-vx
diff --git a/valgrind-3.14.0-s390x-vec-reg-vgdb.patch b/valgrind-3.14.0-s390x-vec-reg-vgdb.patch
deleted file mode 100644
index 3255bd9..0000000
--- a/valgrind-3.14.0-s390x-vec-reg-vgdb.patch
+++ /dev/null
@@ -1,393 +0,0 @@
-commit 50bd2282bce101012a5668b670cb185375600d2d
-Author: Andreas Arnez <arnez@linux.ibm.com>
-Date: Thu Oct 18 17:51:57 2018 +0200
-
- Bug 397187 s390x: Add vector register support for vgdb
-
- On s390x machines with a vector facility, Valgrind's gdbserver didn't
- represent the vector registers. This is fixed.
-
-diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am
-index 8de1996..94030fd 100644
---- a/coregrind/Makefile.am
-+++ b/coregrind/Makefile.am
-@@ -685,6 +685,11 @@ GDBSERVER_XML_FILES = \
- m_gdbserver/s390x-linux64-valgrind-s1.xml \
- m_gdbserver/s390x-linux64-valgrind-s2.xml \
- m_gdbserver/s390x-linux64.xml \
-+ m_gdbserver/s390-vx-valgrind-s1.xml \
-+ m_gdbserver/s390-vx-valgrind-s2.xml \
-+ m_gdbserver/s390-vx.xml \
-+ m_gdbserver/s390x-vx-linux-valgrind.xml \
-+ m_gdbserver/s390x-vx-linux.xml \
- m_gdbserver/mips-cp0-valgrind-s1.xml \
- m_gdbserver/mips-cp0-valgrind-s2.xml \
- m_gdbserver/mips-cp0.xml \
-diff --git a/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml b/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
-new file mode 100644
-index 0000000..ca461b3
---- /dev/null
-+++ b/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
-@@ -0,0 +1,43 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
-+
-+ Copying and distribution of this file, with or without modification,
-+ are permitted in any medium without royalty provided the copyright
-+ notice and this notice are preserved. -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.s390.vx-valgrind-s1">
-+ <reg name="v0ls1" bitsize="64" type="uint64"/>
-+ <reg name="v1ls1" bitsize="64" type="uint64"/>
-+ <reg name="v2ls1" bitsize="64" type="uint64"/>
-+ <reg name="v3ls1" bitsize="64" type="uint64"/>
-+ <reg name="v4ls1" bitsize="64" type="uint64"/>
-+ <reg name="v5ls1" bitsize="64" type="uint64"/>
-+ <reg name="v6ls1" bitsize="64" type="uint64"/>
-+ <reg name="v7ls1" bitsize="64" type="uint64"/>
-+ <reg name="v8ls1" bitsize="64" type="uint64"/>
-+ <reg name="v9ls1" bitsize="64" type="uint64"/>
-+ <reg name="v10ls1" bitsize="64" type="uint64"/>
-+ <reg name="v11ls1" bitsize="64" type="uint64"/>
-+ <reg name="v12ls1" bitsize="64" type="uint64"/>
-+ <reg name="v13ls1" bitsize="64" type="uint64"/>
-+ <reg name="v14ls1" bitsize="64" type="uint64"/>
-+ <reg name="v15ls1" bitsize="64" type="uint64"/>
-+
-+ <reg name="v16s1" bitsize="128" type="uint128"/>
-+ <reg name="v17s1" bitsize="128" type="uint128"/>
-+ <reg name="v18s1" bitsize="128" type="uint128"/>
-+ <reg name="v19s1" bitsize="128" type="uint128"/>
-+ <reg name="v20s1" bitsize="128" type="uint128"/>
-+ <reg name="v21s1" bitsize="128" type="uint128"/>
-+ <reg name="v22s1" bitsize="128" type="uint128"/>
-+ <reg name="v23s1" bitsize="128" type="uint128"/>
-+ <reg name="v24s1" bitsize="128" type="uint128"/>
-+ <reg name="v25s1" bitsize="128" type="uint128"/>
-+ <reg name="v26s1" bitsize="128" type="uint128"/>
-+ <reg name="v27s1" bitsize="128" type="uint128"/>
-+ <reg name="v28s1" bitsize="128" type="uint128"/>
-+ <reg name="v29s1" bitsize="128" type="uint128"/>
-+ <reg name="v30s1" bitsize="128" type="uint128"/>
-+ <reg name="v31s1" bitsize="128" type="uint128"/>
-+</feature>
-diff --git a/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml b/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
-new file mode 100644
-index 0000000..eccbd8d
---- /dev/null
-+++ b/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
-@@ -0,0 +1,43 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
-+
-+ Copying and distribution of this file, with or without modification,
-+ are permitted in any medium without royalty provided the copyright
-+ notice and this notice are preserved. -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.s390.vx-valgrind-s2">
-+ <reg name="v0ls2" bitsize="64" type="uint64"/>
-+ <reg name="v1ls2" bitsize="64" type="uint64"/>
-+ <reg name="v2ls2" bitsize="64" type="uint64"/>
-+ <reg name="v3ls2" bitsize="64" type="uint64"/>
-+ <reg name="v4ls2" bitsize="64" type="uint64"/>
-+ <reg name="v5ls2" bitsize="64" type="uint64"/>
-+ <reg name="v6ls2" bitsize="64" type="uint64"/>
-+ <reg name="v7ls2" bitsize="64" type="uint64"/>
-+ <reg name="v8ls2" bitsize="64" type="uint64"/>
-+ <reg name="v9ls2" bitsize="64" type="uint64"/>
-+ <reg name="v10ls2" bitsize="64" type="uint64"/>
-+ <reg name="v11ls2" bitsize="64" type="uint64"/>
-+ <reg name="v12ls2" bitsize="64" type="uint64"/>
-+ <reg name="v13ls2" bitsize="64" type="uint64"/>
-+ <reg name="v14ls2" bitsize="64" type="uint64"/>
-+ <reg name="v15ls2" bitsize="64" type="uint64"/>
-+
-+ <reg name="v16s2" bitsize="128" type="uint128"/>
-+ <reg name="v17s2" bitsize="128" type="uint128"/>
-+ <reg name="v18s2" bitsize="128" type="uint128"/>
-+ <reg name="v19s2" bitsize="128" type="uint128"/>
-+ <reg name="v20s2" bitsize="128" type="uint128"/>
-+ <reg name="v21s2" bitsize="128" type="uint128"/>
-+ <reg name="v22s2" bitsize="128" type="uint128"/>
-+ <reg name="v23s2" bitsize="128" type="uint128"/>
-+ <reg name="v24s2" bitsize="128" type="uint128"/>
-+ <reg name="v25s2" bitsize="128" type="uint128"/>
-+ <reg name="v26s2" bitsize="128" type="uint128"/>
-+ <reg name="v27s2" bitsize="128" type="uint128"/>
-+ <reg name="v28s2" bitsize="128" type="uint128"/>
-+ <reg name="v29s2" bitsize="128" type="uint128"/>
-+ <reg name="v30s2" bitsize="128" type="uint128"/>
-+ <reg name="v31s2" bitsize="128" type="uint128"/>
-+</feature>
-diff --git a/coregrind/m_gdbserver/s390-vx.xml b/coregrind/m_gdbserver/s390-vx.xml
-new file mode 100644
-index 0000000..2a16873
---- /dev/null
-+++ b/coregrind/m_gdbserver/s390-vx.xml
-@@ -0,0 +1,59 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
-+
-+ Copying and distribution of this file, with or without modification,
-+ are permitted in any medium without royalty provided the copyright
-+ notice and this notice are preserved. -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.s390.vx">
-+ <vector id="v4f" type="ieee_single" count="4"/>
-+ <vector id="v2d" type="ieee_double" count="2"/>
-+ <vector id="v16i8" type="int8" count="16"/>
-+ <vector id="v8i16" type="int16" count="8"/>
-+ <vector id="v4i32" type="int32" count="4"/>
-+ <vector id="v2i64" type="int64" count="2"/>
-+ <union id="vec128">
-+ <field name="v4_float" type="v4f"/>
-+ <field name="v2_double" type="v2d"/>
-+ <field name="v16_int8" type="v16i8"/>
-+ <field name="v8_int16" type="v8i16"/>
-+ <field name="v4_int32" type="v4i32"/>
-+ <field name="v2_int64" type="v2i64"/>
-+ <field name="uint128" type="uint128"/>
-+ </union>
-+
-+ <reg name="v0l" bitsize="64" type="uint64"/>
-+ <reg name="v1l" bitsize="64" type="uint64"/>
-+ <reg name="v2l" bitsize="64" type="uint64"/>
-+ <reg name="v3l" bitsize="64" type="uint64"/>
-+ <reg name="v4l" bitsize="64" type="uint64"/>
-+ <reg name="v5l" bitsize="64" type="uint64"/>
-+ <reg name="v6l" bitsize="64" type="uint64"/>
-+ <reg name="v7l" bitsize="64" type="uint64"/>
-+ <reg name="v8l" bitsize="64" type="uint64"/>
-+ <reg name="v9l" bitsize="64" type="uint64"/>
-+ <reg name="v10l" bitsize="64" type="uint64"/>
-+ <reg name="v11l" bitsize="64" type="uint64"/>
-+ <reg name="v12l" bitsize="64" type="uint64"/>
-+ <reg name="v13l" bitsize="64" type="uint64"/>
-+ <reg name="v14l" bitsize="64" type="uint64"/>
-+ <reg name="v15l" bitsize="64" type="uint64"/>
-+
-+ <reg name="v16" bitsize="128" type="vec128"/>
-+ <reg name="v17" bitsize="128" type="vec128"/>
-+ <reg name="v18" bitsize="128" type="vec128"/>
-+ <reg name="v19" bitsize="128" type="vec128"/>
-+ <reg name="v20" bitsize="128" type="vec128"/>
-+ <reg name="v21" bitsize="128" type="vec128"/>
-+ <reg name="v22" bitsize="128" type="vec128"/>
-+ <reg name="v23" bitsize="128" type="vec128"/>
-+ <reg name="v24" bitsize="128" type="vec128"/>
-+ <reg name="v25" bitsize="128" type="vec128"/>
-+ <reg name="v26" bitsize="128" type="vec128"/>
-+ <reg name="v27" bitsize="128" type="vec128"/>
-+ <reg name="v28" bitsize="128" type="vec128"/>
-+ <reg name="v29" bitsize="128" type="vec128"/>
-+ <reg name="v30" bitsize="128" type="vec128"/>
-+ <reg name="v31" bitsize="128" type="vec128"/>
-+</feature>
-diff --git a/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml b/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
-new file mode 100644
-index 0000000..0237002
---- /dev/null
-+++ b/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
-@@ -0,0 +1,28 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2010-2018 Free Software Foundation, Inc.
-+
-+ Copying and distribution of this file, with or without modification,
-+ are permitted in any medium without royalty provided the copyright
-+ notice and this notice are preserved. -->
-+
-+<!-- S/390 64-bit user-level code. -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+ <architecture>s390:64-bit</architecture>
-+ <xi:include href="s390x-core64.xml"/>
-+ <xi:include href="s390-acr.xml"/>
-+ <xi:include href="s390-fpr.xml"/>
-+ <xi:include href="s390x-linux64.xml"/>
-+ <xi:include href="s390-vx.xml"/>
-+ <xi:include href="s390x-core64-valgrind-s1.xml"/>
-+ <xi:include href="s390-acr-valgrind-s1.xml"/>
-+ <xi:include href="s390-fpr-valgrind-s1.xml"/>
-+ <xi:include href="s390x-linux64-valgrind-s1.xml"/>
-+ <xi:include href="s390-vx-valgrind-s1.xml"/>
-+ <xi:include href="s390x-core64-valgrind-s2.xml"/>
-+ <xi:include href="s390-acr-valgrind-s2.xml"/>
-+ <xi:include href="s390-fpr-valgrind-s2.xml"/>
-+ <xi:include href="s390x-linux64-valgrind-s2.xml"/>
-+ <xi:include href="s390-vx-valgrind-s2.xml"/>
-+</target>
-diff --git a/coregrind/m_gdbserver/s390x-vx-linux.xml b/coregrind/m_gdbserver/s390x-vx-linux.xml
-new file mode 100644
-index 0000000..e431c5b
---- /dev/null
-+++ b/coregrind/m_gdbserver/s390x-vx-linux.xml
-@@ -0,0 +1,18 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2010-2018 Free Software Foundation, Inc.
-+
-+ Copying and distribution of this file, with or without modification,
-+ are permitted in any medium without royalty provided the copyright
-+ notice and this notice are preserved. -->
-+
-+<!-- S/390 64-bit user-level code. -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+ <architecture>s390:64-bit</architecture>
-+ <xi:include href="s390x-core64.xml"/>
-+ <xi:include href="s390-acr.xml"/>
-+ <xi:include href="s390-fpr.xml"/>
-+ <xi:include href="s390x-linux64.xml"/>
-+ <xi:include href="s390-vx.xml"/>
-+</target>
-diff --git a/coregrind/m_gdbserver/valgrind-low-s390x.c b/coregrind/m_gdbserver/valgrind-low-s390x.c
-index 7bbb2e3..a667f4b 100644
---- a/coregrind/m_gdbserver/valgrind-low-s390x.c
-+++ b/coregrind/m_gdbserver/valgrind-low-s390x.c
-@@ -88,9 +88,42 @@ static struct reg regs[] = {
- { "f14", 2592, 64 },
- { "f15", 2656, 64 },
- { "orig_r2", 2720, 64 },
-+ { "v0l", 2784, 64 },
-+ { "v1l", 2848, 64 },
-+ { "v2l", 2912, 64 },
-+ { "v3l", 2976, 64 },
-+ { "v4l", 3040, 64 },
-+ { "v5l", 3104, 64 },
-+ { "v6l", 3168, 64 },
-+ { "v7l", 3232, 64 },
-+ { "v8l", 3296, 64 },
-+ { "v9l", 3360, 64 },
-+ { "v10l", 3424, 64 },
-+ { "v11l", 3488, 64 },
-+ { "v12l", 3552, 64 },
-+ { "v13l", 3616, 64 },
-+ { "v14l", 3680, 64 },
-+ { "v15l", 3744, 64 },
-+ { "v16", 3808, 128 },
-+ { "v17", 3936, 128 },
-+ { "v18", 4064, 128 },
-+ { "v19", 4192, 128 },
-+ { "v20", 4320, 128 },
-+ { "v21", 4448, 128 },
-+ { "v22", 4576, 128 },
-+ { "v23", 4704, 128 },
-+ { "v24", 4832, 128 },
-+ { "v25", 4960, 128 },
-+ { "v26", 5088, 128 },
-+ { "v27", 5216, 128 },
-+ { "v28", 5344, 128 },
-+ { "v29", 5472, 128 },
-+ { "v30", 5600, 128 },
-+ { "v31", 5728, 128 },
- };
- static const char *expedite_regs[] = { "r14", "r15", "pswa", 0 };
--#define num_regs (sizeof (regs) / sizeof (regs[0]))
-+#define num_regs_all (sizeof (regs) / sizeof (regs[0]))
-+static int num_regs;
-
- static
- CORE_ADDR get_pc (void)
-@@ -165,7 +198,7 @@ void transfer_register (ThreadId tid, int abs_regno, void * buf,
- case 32: VG_(transfer) (&s390x->guest_a14, buf, dir, size, mod); break;
- case 33: VG_(transfer) (&s390x->guest_a15, buf, dir, size, mod); break;
- case 34: VG_(transfer) (&s390x->guest_fpc, buf, dir, size, mod); break;
-- case 35: VG_(transfer) (&s390x->guest_v0, buf, dir, size, mod); break;
-+ case 35: VG_(transfer) (&s390x->guest_v0.w64[0], buf, dir, size, mod); break;
- case 36: VG_(transfer) (&s390x->guest_v1.w64[0], buf, dir, size, mod); break;
- case 37: VG_(transfer) (&s390x->guest_v2.w64[0], buf, dir, size, mod); break;
- case 38: VG_(transfer) (&s390x->guest_v3.w64[0], buf, dir, size, mod); break;
-@@ -182,18 +215,65 @@ void transfer_register (ThreadId tid, int abs_regno, void * buf,
- case 49: VG_(transfer) (&s390x->guest_v14.w64[0], buf, dir, size, mod); break;
- case 50: VG_(transfer) (&s390x->guest_v15.w64[0], buf, dir, size, mod); break;
- case 51: *mod = False; break; //GDBTD??? { "orig_r2", 0, 64 },
-+ case 52: VG_(transfer) (&s390x->guest_v0.w64[1], buf, dir, size, mod); break;
-+ case 53: VG_(transfer) (&s390x->guest_v1.w64[1], buf, dir, size, mod); break;
-+ case 54: VG_(transfer) (&s390x->guest_v2.w64[1], buf, dir, size, mod); break;
-+ case 55: VG_(transfer) (&s390x->guest_v3.w64[1], buf, dir, size, mod); break;
-+ case 56: VG_(transfer) (&s390x->guest_v4.w64[1], buf, dir, size, mod); break;
-+ case 57: VG_(transfer) (&s390x->guest_v5.w64[1], buf, dir, size, mod); break;
-+ case 58: VG_(transfer) (&s390x->guest_v6.w64[1], buf, dir, size, mod); break;
-+ case 59: VG_(transfer) (&s390x->guest_v7.w64[1], buf, dir, size, mod); break;
-+ case 60: VG_(transfer) (&s390x->guest_v8.w64[1], buf, dir, size, mod); break;
-+ case 61: VG_(transfer) (&s390x->guest_v9.w64[1], buf, dir, size, mod); break;
-+ case 62: VG_(transfer) (&s390x->guest_v10.w64[1], buf, dir, size, mod); break;
-+ case 63: VG_(transfer) (&s390x->guest_v11.w64[1], buf, dir, size, mod); break;
-+ case 64: VG_(transfer) (&s390x->guest_v12.w64[1], buf, dir, size, mod); break;
-+ case 65: VG_(transfer) (&s390x->guest_v13.w64[1], buf, dir, size, mod); break;
-+ case 66: VG_(transfer) (&s390x->guest_v14.w64[1], buf, dir, size, mod); break;
-+ case 67: VG_(transfer) (&s390x->guest_v15.w64[1], buf, dir, size, mod); break;
-+ case 68: VG_(transfer) (&s390x->guest_v16, buf, dir, size, mod); break;
-+ case 69: VG_(transfer) (&s390x->guest_v17, buf, dir, size, mod); break;
-+ case 70: VG_(transfer) (&s390x->guest_v18, buf, dir, size, mod); break;
-+ case 71: VG_(transfer) (&s390x->guest_v19, buf, dir, size, mod); break;
-+ case 72: VG_(transfer) (&s390x->guest_v20, buf, dir, size, mod); break;
-+ case 73: VG_(transfer) (&s390x->guest_v21, buf, dir, size, mod); break;
-+ case 74: VG_(transfer) (&s390x->guest_v22, buf, dir, size, mod); break;
-+ case 75: VG_(transfer) (&s390x->guest_v23, buf, dir, size, mod); break;
-+ case 76: VG_(transfer) (&s390x->guest_v24, buf, dir, size, mod); break;
-+ case 77: VG_(transfer) (&s390x->guest_v25, buf, dir, size, mod); break;
-+ case 78: VG_(transfer) (&s390x->guest_v26, buf, dir, size, mod); break;
-+ case 79: VG_(transfer) (&s390x->guest_v27, buf, dir, size, mod); break;
-+ case 80: VG_(transfer) (&s390x->guest_v28, buf, dir, size, mod); break;
-+ case 81: VG_(transfer) (&s390x->guest_v29, buf, dir, size, mod); break;
-+ case 82: VG_(transfer) (&s390x->guest_v30, buf, dir, size, mod); break;
-+ case 83: VG_(transfer) (&s390x->guest_v31, buf, dir, size, mod); break;
- default: vg_assert(0);
- }
- }
-
- static
-+Bool have_vx (void)
-+{
-+ VexArch va;
-+ VexArchInfo vai;
-+ VG_(machine_get_VexArchInfo) (&va, &vai);
-+ return (vai.hwcaps & VEX_HWCAPS_S390X_VX) != 0;
-+}
-+
-+static
- const char* target_xml (Bool shadow_mode)
- {
- if (shadow_mode) {
-- return "s390x-generic-valgrind.xml";
-+ if (have_vx())
-+ return "s390x-vx-linux-valgrind.xml";
-+ else
-+ return "s390x-generic-valgrind.xml";
- } else {
-- return "s390x-generic.xml";
-- }
-+ if (have_vx())
-+ return "s390x-vx-linux.xml";
-+ else
-+ return "s390x-generic.xml";
-+ }
- }
-
- static CORE_ADDR** target_get_dtv (ThreadState *tst)
-@@ -206,7 +286,7 @@ static CORE_ADDR** target_get_dtv (ThreadState *tst)
- }
-
- static struct valgrind_target_ops low_target = {
-- num_regs,
-+ -1, // Override at init time.
- regs,
- 17, //sp = r15, which is register offset 17 in regs
- transfer_register,
-@@ -220,6 +300,11 @@ static struct valgrind_target_ops low_target = {
- void s390x_init_architecture (struct valgrind_target_ops *target)
- {
- *target = low_target;
-+ if (have_vx())
-+ num_regs = num_regs_all;
-+ else
-+ num_regs = num_regs_all - 32; // Remove all VX registers.
-+ target->num_regs = num_regs;
- set_register_cache (regs, num_regs);
- gdbserver_expedite_regs = expedite_regs;
- }
diff --git a/valgrind-3.14.0-s390z-more-z13-fixes.patch b/valgrind-3.14.0-s390z-more-z13-fixes.patch
deleted file mode 100644
index 82441b9..0000000
--- a/valgrind-3.14.0-s390z-more-z13-fixes.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From d10cd86ee32bf76495f79c02df62fc242adbcbe3 Mon Sep 17 00:00:00 2001
-From: Andreas Arnez <arnez@linux.vnet.ibm.com>
-Date: Thu, 26 Jul 2018 16:35:24 +0200
-Subject: [PATCH] s390x: More fixes for z13 support
-
-This patch addresses the following:
-
-* Fix the implementation of LOCGHI. Previously Valgrind performed 32-bit
- sign extension instead of 64-bit sign extension on the immediate value.
-
-* Advertise VXRS in HWCAP. If no VXRS are advertised, but the program
- uses vector registers, this could cause problems with a glibc built with
- "-march=z13".
----
- VEX/priv/guest_s390_toIR.c | 2 +-
- coregrind/m_initimg/initimg-linux.c | 6 +++---
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
-index 9c4d79b87..50a5a4177 100644
---- a/VEX/priv/guest_s390_toIR.c
-+++ b/VEX/priv/guest_s390_toIR.c
-@@ -16325,7 +16325,7 @@ static const HChar *
- s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2, UChar unused)
- {
- next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
-- put_gpr_dw0(r1, mkU64((UInt)(Int)(Short)i2));
-+ put_gpr_dw0(r1, mkU64((ULong)(Long)(Short)i2));
-
- return "locghi";
- }
-diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
-index 61cc458bc..8a7f0d024 100644
---- a/coregrind/m_initimg/initimg-linux.c
-+++ b/coregrind/m_initimg/initimg-linux.c
-@@ -699,9 +699,9 @@ Addr setup_client_stack( void* init_sp,
- }
- # elif defined(VGP_s390x_linux)
- {
-- /* Advertise hardware features "below" TE only. TE and VXRS
-- (and anything above) are not supported by Valgrind. */
-- auxv->u.a_val &= VKI_HWCAP_S390_TE - 1;
-+ /* Advertise hardware features "below" TE and VXRS. TE itself
-+ and anything above VXRS is not supported by Valgrind. */
-+ auxv->u.a_val &= (VKI_HWCAP_S390_TE - 1) | VKI_HWCAP_S390_VXRS;
- }
- # elif defined(VGP_arm64_linux)
- {
---
-2.17.0
-
diff --git a/valgrind-3.14.0-set_AV_CR6.patch b/valgrind-3.14.0-set_AV_CR6.patch
deleted file mode 100644
index 0dc67cd..0000000
--- a/valgrind-3.14.0-set_AV_CR6.patch
+++ /dev/null
@@ -1,145 +0,0 @@
-commit dc1523fb3550b4ed9dd4c178741626daaa474da7
-Author: Mark Wielaard <mark@klomp.org>
-Date: Mon Dec 10 17:18:20 2018 +0100
-
- PR386945 set_AV_CR6 patch
-
- https://bugs.kde.org/show_bug.cgi?id=386945#c62
-
-diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
-index ec2f90a..c3cc6d0 100644
---- a/VEX/priv/guest_ppc_toIR.c
-+++ b/VEX/priv/guest_ppc_toIR.c
-@@ -2062,45 +2062,88 @@ static void set_CR0 ( IRExpr* result )
- static void set_AV_CR6 ( IRExpr* result, Bool test_all_ones )
- {
- /* CR6[0:3] = {all_ones, 0, all_zeros, 0}
-- all_ones = (v[0] && v[1] && v[2] && v[3])
-- all_zeros = ~(v[0] || v[1] || v[2] || v[3])
-+ 32 bit: all_zeros = (v[0] || v[1] || v[2] || v[3]) == 0x0000'0000
-+ all_ones = ~(v[0] && v[1] && v[2] && v[3]) == 0x0000'0000
-+ where v[] denotes 32-bit lanes
-+ or
-+ 64 bit: all_zeros = (v[0] || v[1]) == 0x0000'0000'0000'0000
-+ all_ones = ~(v[0] && v[1]) == 0x0000'0000'0000'0000
-+ where v[] denotes 64-bit lanes
-+
-+ The 32- and 64-bit versions compute the same thing, but the 64-bit one
-+ tries to be a bit more efficient.
- */
-- IRTemp v0 = newTemp(Ity_V128);
-- IRTemp v1 = newTemp(Ity_V128);
-- IRTemp v2 = newTemp(Ity_V128);
-- IRTemp v3 = newTemp(Ity_V128);
-- IRTemp rOnes = newTemp(Ity_I8);
-- IRTemp rZeros = newTemp(Ity_I8);
--
- vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_V128);
-
-- assign( v0, result );
-- assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
-- assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
-- assign( v3, binop(Iop_ShrV128, result, mkU8(96)) );
-+ IRTemp overlappedOred = newTemp(Ity_V128);
-+ IRTemp overlappedAnded = newTemp(Ity_V128);
-+
-+ if (mode64) {
-+ IRTemp v0 = newTemp(Ity_V128);
-+ IRTemp v1 = newTemp(Ity_V128);
-+ assign( v0, result );
-+ assign( v1, binop(Iop_ShrV128, result, mkU8(64)) );
-+ assign(overlappedOred,
-+ binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)));
-+ assign(overlappedAnded,
-+ binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)));
-+ } else {
-+ IRTemp v0 = newTemp(Ity_V128);
-+ IRTemp v1 = newTemp(Ity_V128);
-+ IRTemp v2 = newTemp(Ity_V128);
-+ IRTemp v3 = newTemp(Ity_V128);
-+ assign( v0, result );
-+ assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
-+ assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
-+ assign( v3, binop(Iop_ShrV128, result, mkU8(96)) );
-+ assign(overlappedOred,
-+ binop(Iop_OrV128,
-+ binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)),
-+ binop(Iop_OrV128, mkexpr(v2), mkexpr(v3))));
-+ assign(overlappedAnded,
-+ binop(Iop_AndV128,
-+ binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
-+ binop(Iop_AndV128, mkexpr(v2), mkexpr(v3))));
-+ }
-+
-+ IRTemp rOnes = newTemp(Ity_I8);
-+ IRTemp rZeroes = newTemp(Ity_I8);
-
-- assign( rZeros, unop(Iop_1Uto8,
-- binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
-- unop(Iop_Not32,
-- unop(Iop_V128to32,
-- binop(Iop_OrV128,
-- binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)),
-- binop(Iop_OrV128, mkexpr(v2), mkexpr(v3))))
-- ))) );
-+ if (mode64) {
-+ assign(rZeroes,
-+ unop(Iop_1Uto8,
-+ binop(Iop_CmpEQ64,
-+ mkU64(0),
-+ unop(Iop_V128to64, mkexpr(overlappedOred)))));
-+ assign(rOnes,
-+ unop(Iop_1Uto8,
-+ binop(Iop_CmpEQ64,
-+ mkU64(0),
-+ unop(Iop_Not64,
-+ unop(Iop_V128to64, mkexpr(overlappedAnded))))));
-+ } else {
-+ assign(rZeroes,
-+ unop(Iop_1Uto8,
-+ binop(Iop_CmpEQ32,
-+ mkU32(0),
-+ unop(Iop_V128to32, mkexpr(overlappedOred)))));
-+ assign(rOnes,
-+ unop(Iop_1Uto8,
-+ binop(Iop_CmpEQ32,
-+ mkU32(0),
-+ unop(Iop_Not32,
-+ unop(Iop_V128to32, mkexpr(overlappedAnded))))));
-+ }
-+
-+ // rOnes might not be used below. But iropt will remove it, so there's no
-+ // inefficiency as a result.
-
- if (test_all_ones) {
-- assign( rOnes, unop(Iop_1Uto8,
-- binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
-- unop(Iop_V128to32,
-- binop(Iop_AndV128,
-- binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
-- binop(Iop_AndV128, mkexpr(v2), mkexpr(v3)))
-- ))) );
- putCR321( 6, binop(Iop_Or8,
- binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)),
-- binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) );
-+ binop(Iop_Shl8, mkexpr(rZeroes), mkU8(1))) );
- } else {
-- putCR321( 6, binop(Iop_Shl8, mkexpr(rZeros), mkU8(1)) );
-+ putCR321( 6, binop(Iop_Shl8, mkexpr(rZeroes), mkU8(1)) );
- }
- putCR0( 6, mkU8(0) );
- }
-diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
-index c24db91..7f69ee3 100644
---- a/memcheck/mc_translate.c
-+++ b/memcheck/mc_translate.c
-@@ -8322,6 +8322,9 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure,
- # elif defined(VGA_amd64)
- mce.dlbo.dl_Add64 = DLauto;
- mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive;
-+# elif defined(VGA_ppc64le)
-+ // Needed by (at least) set_AV_CR6() in the front end.
-+ mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive;
- # endif
-
- /* preInstrumentationAnalysis() will allocate &mce.tmpHowUsed and then
diff --git a/valgrind-3.14.0-sigkill.patch b/valgrind-3.14.0-sigkill.patch
deleted file mode 100644
index 36368f0..0000000
--- a/valgrind-3.14.0-sigkill.patch
+++ /dev/null
@@ -1,231 +0,0 @@
-commit 0c701ba2a4b10a5f6f3fae31cb0ec6ca034d51d9
-Author: Mark Wielaard <mark@klomp.org>
-Date: Fri Dec 7 14:01:20 2018 +0100
-
- Fix sigkill.stderr.exp for glibc-2.28.
-
- glibc 2.28 filters out some bad signal numbers and returns
- Invalid argument instead of passing such bad signal numbers
- the kernel sigaction syscall. So we won't see such bad signal
- numbers and won't print "bad signal number" ourselves.
-
- Add a new memcheck/tests/sigkill.stderr.exp-glibc-2.28 to catch
- this case.
-
-diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
-index 76e0e90..2af4dd1 100644
---- a/memcheck/tests/Makefile.am
-+++ b/memcheck/tests/Makefile.am
-@@ -260,7 +260,8 @@ EXTRA_DIST = \
- sh-mem-random.stdout.exp sh-mem-random.vgtest \
- sigaltstack.stderr.exp sigaltstack.vgtest \
- sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-mips32 \
-- sigkill.stderr.exp-solaris sigkill.vgtest \
-+ sigkill.stderr.exp-solaris \
-+ sigkill.stderr.exp-glibc-2.28 sigkill.vgtest \
- signal2.stderr.exp signal2.stdout.exp signal2.vgtest \
- sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \
- static_malloc.stderr.exp static_malloc.vgtest \
-diff --git a/memcheck/tests/sigkill.stderr.exp-glibc-2.28 b/memcheck/tests/sigkill.stderr.exp-glibc-2.28
-new file mode 100644
-index 0000000..0e5f0cb
---- /dev/null
-+++ b/memcheck/tests/sigkill.stderr.exp-glibc-2.28
-@@ -0,0 +1,197 @@
-+
-+setting signal 1: Success
-+getting signal 1: Success
-+
-+setting signal 2: Success
-+getting signal 2: Success
-+
-+setting signal 3: Success
-+getting signal 3: Success
-+
-+setting signal 4: Success
-+getting signal 4: Success
-+
-+setting signal 5: Success
-+getting signal 5: Success
-+
-+setting signal 6: Success
-+getting signal 6: Success
-+
-+setting signal 7: Success
-+getting signal 7: Success
-+
-+setting signal 8: Success
-+getting signal 8: Success
-+
-+setting signal 9: Warning: ignored attempt to set SIGKILL handler in sigaction();
-+ the SIGKILL signal is uncatchable
-+Invalid argument
-+getting signal 9: Success
-+
-+setting signal 10: Success
-+getting signal 10: Success
-+
-+setting signal 11: Success
-+getting signal 11: Success
-+
-+setting signal 12: Success
-+getting signal 12: Success
-+
-+setting signal 13: Success
-+getting signal 13: Success
-+
-+setting signal 14: Success
-+getting signal 14: Success
-+
-+setting signal 15: Success
-+getting signal 15: Success
-+
-+setting signal 16: Success
-+getting signal 16: Success
-+
-+setting signal 17: Success
-+getting signal 17: Success
-+
-+setting signal 18: Success
-+getting signal 18: Success
-+
-+setting signal 19: Warning: ignored attempt to set SIGSTOP handler in sigaction();
-+ the SIGSTOP signal is uncatchable
-+Invalid argument
-+getting signal 19: Success
-+
-+setting signal 20: Success
-+getting signal 20: Success
-+
-+setting signal 21: Success
-+getting signal 21: Success
-+
-+setting signal 22: Success
-+getting signal 22: Success
-+
-+setting signal 23: Success
-+getting signal 23: Success
-+
-+setting signal 24: Success
-+getting signal 24: Success
-+
-+setting signal 25: Success
-+getting signal 25: Success
-+
-+setting signal 26: Success
-+getting signal 26: Success
-+
-+setting signal 27: Success
-+getting signal 27: Success
-+
-+setting signal 28: Success
-+getting signal 28: Success
-+
-+setting signal 29: Success
-+getting signal 29: Success
-+
-+setting signal 30: Success
-+getting signal 30: Success
-+
-+setting signal 31: Success
-+getting signal 31: Success
-+
-+setting signal 34: Success
-+getting signal 34: Success
-+
-+setting signal 35: Success
-+getting signal 35: Success
-+
-+setting signal 36: Success
-+getting signal 36: Success
-+
-+setting signal 37: Success
-+getting signal 37: Success
-+
-+setting signal 38: Success
-+getting signal 38: Success
-+
-+setting signal 39: Success
-+getting signal 39: Success
-+
-+setting signal 40: Success
-+getting signal 40: Success
-+
-+setting signal 41: Success
-+getting signal 41: Success
-+
-+setting signal 42: Success
-+getting signal 42: Success
-+
-+setting signal 43: Success
-+getting signal 43: Success
-+
-+setting signal 44: Success
-+getting signal 44: Success
-+
-+setting signal 45: Success
-+getting signal 45: Success
-+
-+setting signal 46: Success
-+getting signal 46: Success
-+
-+setting signal 47: Success
-+getting signal 47: Success
-+
-+setting signal 48: Success
-+getting signal 48: Success
-+
-+setting signal 49: Success
-+getting signal 49: Success
-+
-+setting signal 50: Success
-+getting signal 50: Success
-+
-+setting signal 51: Success
-+getting signal 51: Success
-+
-+setting signal 52: Success
-+getting signal 52: Success
-+
-+setting signal 53: Success
-+getting signal 53: Success
-+
-+setting signal 54: Success
-+getting signal 54: Success
-+
-+setting signal 55: Success
-+getting signal 55: Success
-+
-+setting signal 56: Success
-+getting signal 56: Success
-+
-+setting signal 57: Success
-+getting signal 57: Success
-+
-+setting signal 58: Success
-+getting signal 58: Success
-+
-+setting signal 59: Success
-+getting signal 59: Success
-+
-+setting signal 60: Success
-+getting signal 60: Success
-+
-+setting signal 61: Success
-+getting signal 61: Success
-+
-+setting signal 62: Success
-+getting signal 62: Success
-+
-+setting signal 65: Invalid argument
-+getting signal 65: Invalid argument
-+
-+
-+HEAP SUMMARY:
-+ in use at exit: ... bytes in ... blocks
-+ total heap usage: ... allocs, ... frees, ... bytes allocated
-+
-+For a detailed leak analysis, rerun with: --leak-check=full
-+
-+For counts of detected and suppressed errors, rerun with: -v
-+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/valgrind-3.14.0-subrange_type-count.patch b/valgrind-3.14.0-subrange_type-count.patch
deleted file mode 100644
index 817d749..0000000
--- a/valgrind-3.14.0-subrange_type-count.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-commit 3528f84037833a799538a2fc48ed30dd09c77b5e
-Author: Mark Wielaard <mark@klomp.org>
-Date: Fri Jan 11 21:52:26 2019 +0100
-
- readdwarf3.c (parse_type_DIE): Accept DW_TAG_subrange_type with DW_AT_count
-
- GCC9 generates a subrange_type with a lower_bound and count, but no
- upper_bound attribute. This simply means the upper bound is lower
- plus count.
-
-diff --git a/coregrind/m_debuginfo/readdwarf3.c b/coregrind/m_debuginfo/readdwarf3.c
-index e9a3816..1b49ba4 100644
---- a/coregrind/m_debuginfo/readdwarf3.c
-+++ b/coregrind/m_debuginfo/readdwarf3.c
-@@ -3610,6 +3610,7 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents,
- Bool have_count = False;
- Long lower = 0;
- Long upper = 0;
-+ Long count = 0;
-
- switch (parser->language) {
- case 'C': have_lower = True; lower = 0; break;
-@@ -3641,7 +3642,7 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents,
- have_upper = True;
- }
- if (attr == DW_AT_count && cts.szB > 0) {
-- /*count = (Long)cts.u.val;*/
-+ count = (Long)cts.u.val;
- have_count = True;
- }
- }
-@@ -3680,6 +3681,11 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents,
- boundE.Te.Bound.knownU = False;
- boundE.Te.Bound.boundL = 0;
- boundE.Te.Bound.boundU = 0;
-+ } else if (have_lower && (!have_upper) && (have_count)) {
-+ boundE.Te.Bound.knownL = True;
-+ boundE.Te.Bound.knownU = True;
-+ boundE.Te.Bound.boundL = lower;
-+ boundE.Te.Bound.boundU = lower + count;
- } else {
- /* FIXME: handle more cases */
- goto_bad_DIE;
diff --git a/valgrind-3.14.0-transform-popcount64-ctznat64.patch b/valgrind-3.14.0-transform-popcount64-ctznat64.patch
deleted file mode 100644
index c8b2ac1..0000000
--- a/valgrind-3.14.0-transform-popcount64-ctznat64.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-commit cb5d7e047598bff6d0f1d707a70d9fb1a1c7f0e2
-Author: Julian Seward <jseward@acm.org>
-Date: Tue Nov 20 11:46:55 2018 +0100
-
- VEX/priv/ir_opt.c
-
- fold_Expr: transform PopCount64(And64(Add64(x,-1),Not64(x))) into CtzNat64(x).
-
- This is part of the fix for bug 386945.
-
-diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c
-index f40870b..23964be 100644
---- a/VEX/priv/ir_opt.c
-+++ b/VEX/priv/ir_opt.c
-@@ -1377,6 +1377,8 @@ static IRExpr* fold_Expr ( IRExpr** env, IRExpr* e )
- case Iex_Unop:
- /* UNARY ops */
- if (e->Iex.Unop.arg->tag == Iex_Const) {
-+
-+ /* cases where the arg is a const */
- switch (e->Iex.Unop.op) {
- case Iop_1Uto8:
- e2 = IRExpr_Const(IRConst_U8(toUChar(
-@@ -1690,8 +1692,56 @@ static IRExpr* fold_Expr ( IRExpr** env, IRExpr* e )
-
- default:
- goto unhandled;
-- }
-- }
-+ } // switch (e->Iex.Unop.op)
-+
-+ } else {
-+
-+ /* other cases (identities, etc) */
-+ switch (e->Iex.Unop.op) {
-+ case Iop_PopCount64: {
-+ // PopCount64( And64( Add64(x,-1), Not64(x) ) ) ==> CtzNat64(x)
-+ // bindings:
-+ // a1:And64( a11:Add64(a111:x,a112:-1), a12:Not64(a121:x) )
-+ IRExpr* a1 = chase(env, e->Iex.Unop.arg);
-+ if (!a1)
-+ goto nomatch;
-+ if (a1->tag != Iex_Binop || a1->Iex.Binop.op != Iop_And64)
-+ goto nomatch;
-+ // a1 is established
-+ IRExpr* a11 = chase(env, a1->Iex.Binop.arg1);
-+ if (!a11)
-+ goto nomatch;
-+ if (a11->tag != Iex_Binop || a11->Iex.Binop.op != Iop_Add64)
-+ goto nomatch;
-+ // a11 is established
-+ IRExpr* a12 = chase(env, a1->Iex.Binop.arg2);
-+ if (!a12)
-+ goto nomatch;
-+ if (a12->tag != Iex_Unop || a12->Iex.Unop.op != Iop_Not64)
-+ goto nomatch;
-+ // a12 is established
-+ IRExpr* a111 = a11->Iex.Binop.arg1;
-+ IRExpr* a112 = chase(env, a11->Iex.Binop.arg2);
-+ IRExpr* a121 = a12->Iex.Unop.arg;
-+ if (!a111 || !a112 || !a121)
-+ goto nomatch;
-+ // a111 and a121 need to be the same temp.
-+ if (!eqIRAtom(a111, a121))
-+ goto nomatch;
-+ // Finally, a112 must be a 64-bit version of -1.
-+ if (!isOnesU(a112))
-+ goto nomatch;
-+ // Match established. Transform.
-+ e2 = IRExpr_Unop(Iop_CtzNat64, a111);
-+ break;
-+ nomatch:
-+ break;
-+ }
-+ default:
-+ break;
-+ } // switch (e->Iex.Unop.op)
-+
-+ } // if (e->Iex.Unop.arg->tag == Iex_Const)
- break;
-
- case Iex_Binop:
diff --git a/valgrind-3.14.0-undef_malloc_args.patch b/valgrind-3.14.0-undef_malloc_args.patch
deleted file mode 100644
index 43db5ab..0000000
--- a/valgrind-3.14.0-undef_malloc_args.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-commit 262275da43425ba2b8c240e47063e36b39167996
-Author: Mark Wielaard <mark@klomp.org>
-Date: Wed Dec 12 13:55:01 2018 +0100
-
- Fix memcheck/tests/undef_malloc_args testcase.
-
-diff --git a/coregrind/m_replacemalloc/vg_replace_malloc.c b/coregrind/m_replacemalloc/vg_replace_malloc.c
-index 28bdb4a..564829a 100644
---- a/coregrind/m_replacemalloc/vg_replace_malloc.c
-+++ b/coregrind/m_replacemalloc/vg_replace_malloc.c
-@@ -216,9 +216,19 @@ static void init(void);
- Apart of allowing memcheck to detect an error, the macro
- TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED has no effect and
- has a minimal cost for other tools replacing malloc functions.
-+
-+ Creating an "artificial" use of _x that works reliably is not entirely
-+ straightforward. Simply comparing it against zero often produces no
-+ warning if _x contains at least one nonzero bit is defined, because
-+ Memcheck knows that the result of the comparison will be defined (cf
-+ expensiveCmpEQorNE).
-+
-+ Really we want to PCast _x, so as to create a value which is entirely
-+ undefined if any bit of _x is undefined. But there's no portable way to do
-+ that.
- */
--#define TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED(x) \
-- if ((ULong)x == 0) __asm__ __volatile__( "" ::: "memory" )
-+#define TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED(_x) \
-+ if ((UWord)(_x) == 0) __asm__ __volatile__( "" ::: "memory" )
-
- /*---------------------- malloc ----------------------*/
-
-@@ -504,7 +514,7 @@ static void init(void);
- void VG_REPLACE_FUNCTION_EZU(10040,soname,fnname) (void *zone, void *p) \
- { \
- DO_INIT; \
-- TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED((UWord) zone); \
-+ TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED((UWord)zone ^ (UWord)p); \
- MALLOC_TRACE(#fnname "(%p, %p)\n", zone, p ); \
- if (p == NULL) \
- return; \
-diff --git a/memcheck/tests/undef_malloc_args.c b/memcheck/tests/undef_malloc_args.c
-index 99e2799..654d70d 100644
---- a/memcheck/tests/undef_malloc_args.c
-+++ b/memcheck/tests/undef_malloc_args.c
-@@ -11,29 +11,29 @@ int main (int argc, char*argv[])
-
- {
- size_t size = def_size;
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size));
- p = malloc(size);
- }
-
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&p, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&p, sizeof(p));
- new_p = realloc(p, def_size);
-
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, sizeof(new_p));
- new_p = realloc(new_p, def_size);
-
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, sizeof(new_p));
- free (new_p);
-
- {
- size_t nmemb = 1;
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&nmemb, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&nmemb, sizeof(nmemb));
- new_p = calloc(nmemb, def_size);
- free (new_p);
- }
- #if 0
- {
- size_t alignment = 1;
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&alignment, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&alignment, sizeof(alignment));
- new_p = memalign(alignment, def_size);
- free(new_p);
- }
-@@ -41,14 +41,14 @@ int main (int argc, char*argv[])
- {
- size_t nmemb = 16;
- size_t size = def_size;
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size));
- new_p = memalign(nmemb, size);
- free(new_p);
- }
-
- {
- size_t size = def_size;
-- (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1);
-+ (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size));
- new_p = valloc(size);
- free (new_p);
- }
diff --git a/valgrind-3.14.0-vbit-test-sec.patch b/valgrind-3.14.0-vbit-test-sec.patch
deleted file mode 100644
index 66eba70..0000000
--- a/valgrind-3.14.0-vbit-test-sec.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From cee6817c2f4637f859829c7caeac168ccbb74850 Mon Sep 17 00:00:00 2001
-From: Mark Wielaard <mark@klomp.org>
-Date: Sun, 23 Dec 2018 13:29:27 +0100
-Subject: [PATCH] Also test memcheck/tests/vbit-test on any secondary arch.
-
-If we are building a secondary arch then also build and run ther
-memcheck vbit-test for that architecture.
----
- memcheck/tests/vbit-test/Makefile.am | 20 ++++++++++++++++++++
- memcheck/tests/vbit-test/vbit-test-sec.stderr.exp | 0
- memcheck/tests/vbit-test/vbit-test-sec.vgtest | 3 +++
- 3 files changed, 23 insertions(+)
- create mode 100644 memcheck/tests/vbit-test/vbit-test-sec.stderr.exp
- create mode 100644 memcheck/tests/vbit-test/vbit-test-sec.vgtest
-
-diff --git a/memcheck/tests/vbit-test/Makefile.am b/memcheck/tests/vbit-test/Makefile.am
-index 371a71b..124e82e 100644
---- a/memcheck/tests/vbit-test/Makefile.am
-+++ b/memcheck/tests/vbit-test/Makefile.am
-@@ -17,6 +17,10 @@ noinst_HEADERS = vtest.h vbits.h
-
- noinst_PROGRAMS = vbit-test
-
-+if VGCONF_HAVE_PLATFORM_SEC
-+noinst_PROGRAMS += vbit-test-sec
-+endif
-+
- if VGCONF_OS_IS_DARWIN
- noinst_DSYMS = $(noinst_PROGRAMS)
- endif
-@@ -41,3 +45,19 @@ vbit_test_CFLAGS = $(AM_CFLAGS_PRI)
- vbit_test_DEPENDENCIES =
- vbit_test_LDADD = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
- vbit_test_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@
-+
-+if VGCONF_HAVE_PLATFORM_SEC
-+vbit_test_sec_SOURCES = $(SOURCES)
-+vbit_test_sec_CPPFLAGS = $(AM_CPPFLAGS_SEC) \
-+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
-+ -I$(top_srcdir)/include \
-+ -I$(top_srcdir)/memcheck \
-+ -I$(top_srcdir)/VEX/pub
-+vbit_test_sec_CFLAGS = $(AM_CFLAGS_SEC) \
-+ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
-+vbit_test_sec_DEPENDENCIES =
-+vbit_test_sec_LDADD = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
-+ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
-+vbit_test_sec_LDFLAGS = $(AM_CFLAGS_SEC) @LIB_UBSAN@ \
-+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
-+endif
-diff --git a/memcheck/tests/vbit-test/vbit-test-sec.stderr.exp b/memcheck/tests/vbit-test/vbit-test-sec.stderr.exp
-new file mode 100644
-index 0000000..e69de29
-diff --git a/memcheck/tests/vbit-test/vbit-test-sec.vgtest b/memcheck/tests/vbit-test/vbit-test-sec.vgtest
-new file mode 100644
-index 0000000..2d3c938
---- /dev/null
-+++ b/memcheck/tests/vbit-test/vbit-test-sec.vgtest
-@@ -0,0 +1,3 @@
-+prog: vbit-test-sec
-+prereq: test -x vbit-test-sec
-+vgopts: -q --expensive-definedness-checks=yes
---
-1.8.3.1
diff --git a/valgrind-3.14.0-wcsncmp.patch b/valgrind-3.14.0-wcsncmp.patch
deleted file mode 100644
index 8940910..0000000
--- a/valgrind-3.14.0-wcsncmp.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-commit 5fdabb72fdcba6bcf788eaa19c1ee557c13b8a7a
-Author: Mark Wielaard <mark@klomp.org>
-Date: Sat Dec 1 23:54:40 2018 +0100
-
- Bug 401627 - Add wcsncmp override and testcase.
-
- glibc 2.28 added an avx2 optimized variant of wstrncmp which memcheck
- cannot proof correct. Add a simple override in vg_replace_strmem.c.
-
-diff --git a/memcheck/tests/wcs.c b/memcheck/tests/wcs.c
-index 15730ad..538304b 100644
---- a/memcheck/tests/wcs.c
-+++ b/memcheck/tests/wcs.c
-@@ -1,5 +1,6 @@
--// Uses various wchar_t * functions that have hand written SSE assembly
--// implementations in glibc. wcslen, wcscpy, wcscmp, wcsrchr, wcschr.
-+// Uses various wchar_t * functions that have hand written SSE and/or AVX2
-+// assembly implementations in glibc.
-+// wcslen, wcscpy, wcscmp, wcsncmp, wcsrchr, wcschr.
-
- #include <stdio.h>
- #include <stdlib.h>
-@@ -18,6 +19,8 @@ int main(int argc, char **argv)
- c = wcscpy (b, a);
-
- fprintf (stderr, "wcscmp equal: %d\n", wcscmp (a, b)); // wcscmp equal: 0
-+ fprintf (stderr,
-+ "wcsncmp equal: %d\n", wcsncmp (a, b, l)); // wcsncmp equal: 0
-
- d = wcsrchr (a, L'd');
- e = wcschr (a, L'd');
-diff --git a/memcheck/tests/wcs.stderr.exp b/memcheck/tests/wcs.stderr.exp
-index 41d74c8..d5b5959 100644
---- a/memcheck/tests/wcs.stderr.exp
-+++ b/memcheck/tests/wcs.stderr.exp
-@@ -1,3 +1,4 @@
- wcslen: 53
- wcscmp equal: 0
-+wcsncmp equal: 0
- wcsrchr == wcschr: 1
-diff --git a/shared/vg_replace_strmem.c b/shared/vg_replace_strmem.c
-index d6927f0..89a7dcc 100644
---- a/shared/vg_replace_strmem.c
-+++ b/shared/vg_replace_strmem.c
-@@ -103,6 +103,7 @@
- 20420 STPNCPY
- 20430 WMEMCHR
- 20440 WCSNLEN
-+ 20450 WSTRNCMP
- */
-
- #if defined(VGO_solaris)
-@@ -1927,6 +1928,36 @@ static inline void my_exit ( int x )
- WCSCMP(VG_Z_LIBC_SONAME, wcscmp)
- #endif
-
-+/*---------------------- wcsncmp ----------------------*/
-+
-+// This is a wchar_t equivalent to strncmp. We don't
-+// have wchar_t available here, but in the GNU C Library
-+// wchar_t is always 32 bits wide and wcsncmp uses signed
-+// comparison, not unsigned as in strncmp function.
-+
-+#define WCSNCMP(soname, fnname) \
-+ int VG_REPLACE_FUNCTION_EZU(20450,soname,fnname) \
-+ ( const Int* s1, const Int* s2, SizeT nmax ); \
-+ int VG_REPLACE_FUNCTION_EZU(20450,soname,fnname) \
-+ ( const Int* s1, const Int* s2, SizeT nmax ) \
-+ { \
-+ SizeT n = 0; \
-+ while (True) { \
-+ if (n >= nmax) return 0; \
-+ if (*s1 == 0 && *s2 == 0) return 0; \
-+ if (*s1 == 0) return -1; \
-+ if (*s2 == 0) return 1; \
-+ \
-+ if (*s1 < *s2) return -1; \
-+ if (*s1 > *s2) return 1; \
-+ \
-+ s1++; s2++; n++; \
-+ } \
-+ }
-+#if defined(VGO_linux)
-+ WCSNCMP(VG_Z_LIBC_SONAME, wcsncmp)
-+#endif
-+
- /*---------------------- wcscpy ----------------------*/
-
- // This is a wchar_t equivalent to strcpy. We don't
diff --git a/valgrind-3.14.0-x86-Iop_Sar64.patch b/valgrind-3.14.0-x86-Iop_Sar64.patch
deleted file mode 100644
index 143f32d..0000000
--- a/valgrind-3.14.0-x86-Iop_Sar64.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From f730da53e59ab25c5b250d7730ead57b6f72fdcf Mon Sep 17 00:00:00 2001
-From: Julian Seward <jseward@acm.org>
-Date: Sun, 23 Dec 2018 21:03:08 +0100
-Subject: [PATCH] Implement Iop_Sar64 in the x86 back end.
-
----
- VEX/priv/host_x86_isel.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 50 insertions(+)
-
-diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c
-index 45aafeb..9ca8a45 100644
---- a/VEX/priv/host_x86_isel.c
-+++ b/VEX/priv/host_x86_isel.c
-@@ -2380,6 +2380,56 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
- return;
- }
-
-+ case Iop_Sar64: {
-+ /* gcc -O2 does the following. I don't know how it works, but it
-+ does work. Don't mess with it. This is hard to test because the
-+ x86 front end doesn't create Iop_Sar64 for any x86 instruction,
-+ so it's impossible to write a test program that feeds values
-+ through Iop_Sar64 and prints their results. The implementation
-+ here was tested by using psrlq on mmx registers -- that generates
-+ Iop_Shr64 -- and temporarily hacking the front end to generate
-+ Iop_Sar64 for that instruction instead.
-+
-+ movl %amount, %ecx
-+ movl %srcHi, %r1
-+ movl %srcLo, %r2
-+
-+ movl %r1, %r3
-+ sarl %cl, %r3
-+ movl %r2, %r4
-+ shrdl %cl, %r1, %r4
-+ movl %r3, %r2
-+ sarl $31, %r2
-+ andl $32, %ecx
-+ cmovne %r3, %r4 // = resLo
-+ cmovne %r2, %r3 // = resHi
-+ */
-+ HReg amount = iselIntExpr_R(env, e->Iex.Binop.arg2);
-+ HReg srcHi = INVALID_HREG, srcLo = INVALID_HREG;
-+ iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Binop.arg1);
-+ HReg r1 = newVRegI(env);
-+ HReg r2 = newVRegI(env);
-+ HReg r3 = newVRegI(env);
-+ HReg r4 = newVRegI(env);
-+ addInstr(env, mk_iMOVsd_RR(amount, hregX86_ECX()));
-+ addInstr(env, mk_iMOVsd_RR(srcHi, r1));
-+ addInstr(env, mk_iMOVsd_RR(srcLo, r2));
-+
-+ addInstr(env, mk_iMOVsd_RR(r1, r3));
-+ addInstr(env, X86Instr_Sh32(Xsh_SAR, 0/*%cl*/, r3));
-+ addInstr(env, mk_iMOVsd_RR(r2, r4));
-+ addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, r1, r4));
-+ addInstr(env, mk_iMOVsd_RR(r3, r2));
-+ addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, r2));
-+ addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(32),
-+ hregX86_ECX()));
-+ addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(r3), r4));
-+ addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(r2), r3));
-+ *rHi = r3;
-+ *rLo = r4;
-+ return;
-+ }
-+
- /* F64 -> I64 */
- /* Sigh, this is an almost exact copy of the F64 -> I32/I16
- case. Unfortunately I see no easy way to avoid the
---
-1.8.3.1
-
diff --git a/valgrind-3.15.0-pkglibexecdir.patch b/valgrind-3.15.0-pkglibexecdir.patch
new file mode 100644
index 0000000..cd52729
--- /dev/null
+++ b/valgrind-3.15.0-pkglibexecdir.patch
@@ -0,0 +1,117 @@
+diff --git a/Makefile.all.am b/Makefile.all.am
+index 3786e34..1befef5 100644
+--- a/Makefile.all.am
++++ b/Makefile.all.am
+@@ -50,20 +50,20 @@ inplace-noinst_DSYMS: build-noinst_DSYMS
+ done
+
+ # This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+-# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
++# "make install". It copies $(noinst_PROGRAMS) into $prefix/libexec/valgrind/.
+ # It needs to be depended on by an 'install-exec-local' rule.
+ install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+- $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
++ $(mkinstalldirs) $(DESTDIR)$(pkglibexecdir); \
+ for f in $(noinst_PROGRAMS); do \
+- $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
++ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibexecdir); \
+ done
+
+ # This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+-# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
++# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/libexec/valgrind/.
+ # It needs to be depended on by an 'uninstall-local' rule.
+ uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+- rm -f $(DESTDIR)$(pkglibdir)/$$f; \
++ rm -f $(DESTDIR)$(pkglibexecdir)/$$f; \
+ done
+
+ # Similar to install-noinst_PROGRAMS.
+@@ -71,15 +71,15 @@ uninstall-noinst_PROGRAMS:
+ # directories. XXX: not sure whether the resulting permissions will be
+ # correct when using 'cp -R'...
+ install-noinst_DSYMS: build-noinst_DSYMS
+- $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
++ $(mkinstalldirs) $(DESTDIR)$(pkglibexecdir); \
+ for f in $(noinst_DSYMS); do \
+- cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
++ cp -R $$f.dSYM $(DESTDIR)$(pkglibexecdir); \
+ done
+
+ # Similar to uninstall-noinst_PROGRAMS.
+ uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+- rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
++ rm -f $(DESTDIR)$(pkglibexecdir)/$$f.dSYM; \
+ done
+
+ # This needs to be depended on by a 'clean-local' rule.
+diff --git a/Makefile.am b/Makefile.am
+index 242b38a..3b7c806 100644
+--- a/Makefile.am
++++ b/Makefile.am
+@@ -58,7 +58,7 @@ DEFAULT_SUPP_FILES = @DEFAULT_SUPP@
+ # default.supp, as it is built from the base .supp files at compile-time.
+ dist_noinst_DATA = $(SUPP_FILES)
+
+-vglibdir = $(pkglibdir)
++vglibdir = $(pkglibexecdir)
+ vglib_DATA = default.supp
+
+ pkgconfigdir = $(libdir)/pkgconfig
+diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am
+index 94030fd..f09763a 100644
+--- a/coregrind/Makefile.am
++++ b/coregrind/Makefile.am
+@@ -11,12 +11,12 @@ include $(top_srcdir)/Makefile.all.am
+
+ AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ += \
+ -I$(top_srcdir)/coregrind \
+- -DVG_LIBDIR="\"$(pkglibdir)"\" \
++ -DVG_LIBDIR="\"$(pkglibexecdir)"\" \
+ -DVG_PLATFORM="\"@VGCONF_ARCH_PRI@-@VGCONF_OS@\""
+ if VGCONF_HAVE_PLATFORM_SEC
+ AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ += \
+ -I$(top_srcdir)/coregrind \
+- -DVG_LIBDIR="\"$(pkglibdir)"\" \
++ -DVG_LIBDIR="\"$(pkglibexecdir)"\" \
+ -DVG_PLATFORM="\"@VGCONF_ARCH_SEC@-@VGCONF_OS@\""
+ endif
+
+@@ -714,7 +714,7 @@ GDBSERVER_XML_FILES = \
+ m_gdbserver/mips64-fpu.xml
+
+ # so as to make sure these get copied into the install tree
+-vglibdir = $(pkglibdir)
++vglibdir = $(pkglibexecdir)
+ vglib_DATA = $(GDBSERVER_XML_FILES)
+
+ # so as to make sure these get copied into the tarball
+diff --git a/mpi/Makefile.am b/mpi/Makefile.am
+index 7ad9a25..471fee0 100644
+--- a/mpi/Makefile.am
++++ b/mpi/Makefile.am
+@@ -18,16 +18,18 @@ EXTRA_DIST = \
+ # libmpiwrap-<platform>.so
+ #----------------------------------------------------------------------------
+
+-noinst_PROGRAMS =
++# These are really real libraries, so they should go to libdir, not libexec.
++mpidir = $(pkglibdir)
++mpi_PROGRAMS =
+ if BUILD_MPIWRAP_PRI
+-noinst_PROGRAMS += libmpiwrap-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so
++mpi_PROGRAMS += libmpiwrap-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so
+ endif
+ if BUILD_MPIWRAP_SEC
+-noinst_PROGRAMS += libmpiwrap-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
++mpi_PROGRAMS += libmpiwrap-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+ endif
+
+ if VGCONF_OS_IS_DARWIN
+-noinst_DSYMS = $(noinst_PROGRAMS)
++mpi_DSYMS = $(mpi_PROGRAMS)
+ endif
+
+
diff --git a/valgrind.spec b/valgrind.spec
index baf3eeb..8943f2e 100644
--- a/valgrind.spec
+++ b/valgrind.spec
@@ -2,8 +2,8 @@
Summary: Tool for finding memory management bugs in programs
Name: %{?scl_prefix}valgrind
-Version: 3.14.0
-Release: 16%{?dist}
+Version: 3.15.0
+Release: 0.1.RC1%{?dist}
Epoch: 1
License: GPLv2+
URL: http://www.valgrind.org/
@@ -68,7 +68,7 @@ URL: http://www.valgrind.org/
# So those will already have their full symbol table.
%undefine _include_minidebuginfo
-Source0: http://www.valgrind.org/downloads/valgrind-%{version}.tar.bz2
+Source0: ftp://sourceware.org/pub/valgrind/valgrind-%{version}.RC1.tar.bz2
# Needs investigation and pushing upstream
Patch1: valgrind-3.9.0-cachegrind-improvements.patch
@@ -79,92 +79,10 @@ Patch2: valgrind-3.9.0-helgrind-race-supp.patch
# Make ld.so supressions slightly less specific.
Patch3: valgrind-3.9.0-ldso-supp.patch
-# KDE#400490 s390x: Fix register allocation for VRs vs FPRs
-Patch4: valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch
-
-# KDE#400491 s390x: Sign-extend immediate operand of LOCHI and friends
-Patch5: valgrind-3.14.0-s390x-sign-extend-lochi.patch
-
-# KDE#397187 s390x: Add vector register support for vgdb
-Patch6: valgrind-3.14.0-s390x-vec-reg-vgdb.patch
-
-# KDE#385411 s390x: z13 vector floating-point instructions not implemented
-Patch7: valgrind-3.14.0-s390x-vec-float-point-code.patch
-Patch8: valgrind-3.14.0-s390x-vec-float-point-tests.patch
-
-# KDE#401277 More bugs in z13 support
-Patch9: valgrind-3.14.0-s390z-more-z13-fixes.patch
-
-# KDE#386945 Bogus memcheck errors on ppc64(le) when using strcmp
-Patch10: valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch
-Patch11: valgrind-3.14.0-new-strlen-IROps.patch
-Patch12: valgrind-3.14.0-ppc-instr-new-IROps.patch
-Patch13: valgrind-3.14.0-memcheck-new-IROps.patch
-Patch14: valgrind-3.14.0-ppc-frontend-new-IROps.patch
-Patch15: valgrind-3.14.0-transform-popcount64-ctznat64.patch
-Patch16: valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch
-
-# KDE#401627 memcheck errors with glibc avx2 optimized wcsncmp
-Patch17: valgrind-3.14.0-wcsncmp.patch
-
-# KDE#402006 mark helper regs defined in final_tidyup before freeres_wrapper
-# Prereq for KDE#386945
-Patch18: valgrind-3.14.0-final_tidyup.patch
-
-# KDE#386945 Bogus memcheck errors on ppc64(le) when using strcmp
-# See also patches 10 to 16 (yes, there are this many...)
-Patch19: valgrind-3.14.0-ppc64-ldbrx.patch
-Patch20: valgrind-3.14.0-ppc64-unaligned-words.patch
-Patch21: valgrind-3.14.0-ppc64-lxvd2x.patch
-Patch22: valgrind-3.14.0-ppc64-unaligned-vecs.patch
-Patch23: valgrind-3.14.0-ppc64-lxvb16x.patch
-Patch24: valgrind-3.14.0-set_AV_CR6.patch
-Patch25: valgrind-3.14.0-undef_malloc_args.patch
-
-# KDE#401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings
-Patch26: valgrind-3.14.0-jm-vmx-constraints.patch
-
-# commit 0c701ba2a Fix sigkill.stderr.exp for glibc-2.28.
-Patch27: valgrind-3.14.0-sigkill.patch
-
-# KDE#402048 Implement minimal ptrace support for ppc64[le]-linux.
-Patch28: valgrind-3.14.0-ppc64-ptrace.patch
-
-# commit 43fe4bc23 arm64: Fix PTRACE_TRACEME
-Patch29: valgrind-3.14.0-arm64-ptrace-traceme.patch
-
-# KDE#402134 - assert fail mc_translate.c (noteTmpUsesIn) Iex_VECRET on arm64
-Patch30: valgrind-3.14.0-mc_translate-vecret.patch
-
-# KDE#402481 vbit-test fails on x86 for Iop_CmpEQ64 iselInt64Expr Sar64
-Patch31: valgrind-3.14.0-vbit-test-sec.patch
-Patch32: valgrind-3.14.0-x86-Iop_Sar64.patch
-
-# KDE#402519 POWER 3.0 addex instruction incorrectly implemented
-Patch33: valgrind-3.14.0-power9-addex.patch
-
-# KDE#402480 Do not use %rsp in clobber list
-Patch34: valgrind-3.14.0-rsp-clobber.patch
-
-# commit 3528f8 Accept DW_TAG_subrange_type with DW_AT_count
-Patch35: valgrind-3.14.0-subrange_type-count.patch
-
-# KDE#403552 s390x: wrong facility bit checked for vector facility
-Patch36: valgrind-3.14.0-s390x-vec-facility-bit.patch
-
-# KDE#404054 powerpc subfe x, x, x initializes x to 0 or -1 based on CA
-Patch37: valgrind-3.14.0-ppc-subfe.patch
-
-# KDE#405079 unhandled ppc64le-linux syscall: 131 (quotactl)
-Patch38: valgrind-3.14.0-ppc64-quotactl.patch
-
-# SW#6399 glibc might implement gettid itself, rename to gettid_sys.
-Patch39: valgrind-3.14.0-gettid.patch
-
# We want all executables and libraries in libexec instead of lib
# so they are only available for valgrind usage itself and so the
# same directory is used independent of arch.
-Patch40: valgrind-3.14.0-pkglibexecdir.patch
+Patch4: valgrind-3.15.0-pkglibexecdir.patch
%if 0%{?fedora} >= 15
@@ -292,48 +210,12 @@ Valgrind User Manual for details.
%endif
%prep
-%setup -q -n %{?scl:%{pkg_name}}%{!?scl:%{name}}-%{version}
+%setup -q -n %{?scl:%{pkg_name}}%{!?scl:%{name}}-%{version}.RC1
%patch1 -p1
%patch2 -p1
%patch3 -p1
%patch4 -p1
-%patch5 -p1
-%patch6 -p1
-%patch7 -p1
-%patch8 -p1
-%patch9 -p1
-%patch10 -p1
-%patch11 -p1
-%patch12 -p1
-%patch13 -p1
-%patch14 -p1
-%patch15 -p1
-%patch16 -p1
-%patch17 -p1
-%patch18 -p1
-%patch19 -p1
-%patch20 -p1
-%patch21 -p1
-%patch22 -p1
-%patch23 -p1
-%patch24 -p1
-%patch25 -p1
-%patch26 -p1
-%patch27 -p1
-%patch28 -p1
-%patch29 -p1
-%patch30 -p1
-%patch31 -p1
-%patch32 -p1
-%patch33 -p1
-%patch34 -p1
-%patch35 -p1
-%patch36 -p1
-%patch37 -p1
-%patch38 -p1
-%patch39 -p1
-%patch40 -p1
%build
CC=gcc
@@ -546,9 +428,11 @@ fi
%endif
%changelog
-* Mon Apr 8 2019 Mark Wielaard <mjw@fedoraproject.org>
+* Mon Apr 8 2019 Mark Wielaard <mjw@fedoraproject.org> - 3.15.0-0.1.RC1
- Remove patches to prebuild files and always ./autogen.sh.
- Only ever build primary arch. Put tools under libexec.
+- Update to upstream 3.15.0-RC1.
+- Drop all upstreamed patches.
* Mon Mar 4 2019 Mark Wielaard <mjw@fedoraproject.org> - 3.14.0-16
- Add valgrind-3.14.0-gettid.patch