From 1af9e5c672ddfc4d4975df43f73f294be91886a3 Mon Sep 17 00:00:00 2001 From: CentOS Sources Date: Apr 10 2018 05:27:46 +0000 Subject: import valgrind-3.13.0-10.el7 --- diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..8c09a8a --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +SOURCES/valgrind-3.13.0.tar.bz2 diff --git a/.valgrind.metadata b/.valgrind.metadata new file mode 100644 index 0000000..03d59c3 --- /dev/null +++ b/.valgrind.metadata @@ -0,0 +1 @@ +ddf13e22dd0ee688bd533fc66b94cf88f75fad86 SOURCES/valgrind-3.13.0.tar.bz2 diff --git a/README.md b/README.md deleted file mode 100644 index 0e7897f..0000000 --- a/README.md +++ /dev/null @@ -1,5 +0,0 @@ -The master branch has no content - -Look at the c7 branch if you are working with CentOS-7, or the c4/c5/c6 branch for CentOS-4, 5 or 6 - -If you find this file in a distro specific branch, it means that no content has been checked in yet diff --git a/SOURCES/valgrind-3.11.0-ppc-fppo.patch b/SOURCES/valgrind-3.11.0-ppc-fppo.patch new file mode 100644 index 0000000..8890e6b --- /dev/null +++ b/SOURCES/valgrind-3.11.0-ppc-fppo.patch @@ -0,0 +1,37 @@ +--- valgrind-3.10.0.BETA1/configure.orig 2014-09-02 13:49:58.125269536 +0200 ++++ valgrind-3.10.0.BETA1/configure 2014-09-02 13:54:08.188701144 +0200 +@@ -8978,9 +8978,8 @@ + fi + rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test x$ac_have_as_ppc_fpPO = xyes ; then +- +-$as_echo "#define HAVE_AS_PPC_FPPO 1" >>confdefs.h +- ++ { $as_echo "$as_me:${as_lineno-$LINENO}: HAVE_AS_PPC_FPPO found, but ignoring." >&5 ++$as_echo "$as_me: HAVE_AS_PPC_FPPO found, but ignoring." >&6;} + fi + + +--- valgrind-3.11.0/config.h.in.orig 2016-04-15 23:51:26.889440687 +0200 ++++ valgrind-3.11.0/config.h.in 2016-04-15 23:51:43.430126014 +0200 +@@ -55,9 +55,6 @@ + /* Define to 1 if as supports fxsave64/fxrstor64. */ + #undef HAVE_AS_AMD64_FXSAVE64 + +-/* Define to 1 if as supports floating point phased out category. */ +-#undef HAVE_AS_PPC_FPPO +- + /* Define to 1 if as supports mtocrf/mfocrf. */ + #undef HAVE_AS_PPC_MFTOCRF + +--- valgrind-3.10.0.BETA1/configure.ac.orig 2014-09-02 14:01:04.443754937 +0200 ++++ valgrind-3.10.0.BETA1/configure.ac 2014-09-02 14:01:16.483727639 +0200 +@@ -2022,7 +2022,7 @@ + AC_MSG_RESULT([no]) + ]) + if test x$ac_have_as_ppc_fpPO = xyes ; then +- AC_DEFINE(HAVE_AS_PPC_FPPO, 1, [Define to 1 if as supports floating point phased out category.]) ++ AC_MSG_NOTICE([HAVE_AS_PPC_FPPO found, but ignoring.]) + fi + + diff --git a/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch b/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch new file mode 100644 index 0000000..c2cef5a --- /dev/null +++ b/SOURCES/valgrind-3.13.0-amd64-eflags-tests.patch @@ -0,0 +1,2104 @@ +commit 4c8c3af18adc0a202d0e342b8ca3731a5b724a1d +Author: Tom Hughes +Date: Wed Aug 30 19:26:37 2017 +0100 + + Fix eflags handling in amd64 instruction tests + + In 64 bit mode there's no way to just save eflags so we save the + whole of rflags but we were doing so to a 32 bit variable! + + Replace that with proper rflags support that knows it is dealing + with the full 64 bit flags word in 64 bit mode. + +diff --git a/none/tests/amd64/gen_insn_test.pl b/none/tests/amd64/gen_insn_test.pl +index 863e560..a144ec4 100644 +--- a/none/tests/amd64/gen_insn_test.pl ++++ b/none/tests/amd64/gen_insn_test.pl +@@ -16,7 +16,7 @@ our %ArgTypes = ( + m32 => "reg32_t", + m64 => "reg64_t", + m128 => "reg128_t", +- eflags => "reg32_t", ++ rflags => "reg64_t", + st => "reg64_t", + fpucw => "reg16_t", + fpusw => "reg16_t" +@@ -222,8 +222,8 @@ while (<>) + + my @presets; + my $presetc = 0; +- my $eflagsmask; +- my $eflagsset; ++ my $rflagsmask; ++ my $rflagsset; + my $fpucwmask; + my $fpucwset; + my $fpuswmask; +@@ -305,7 +305,7 @@ while (<>) + + $presetc++; + } +- elsif ($preset =~ /^(eflags)\[([^\]]+)\]$/) ++ elsif ($preset =~ /^(rflags)\[([^\]]+)\]$/) + { + my $type = $1; + my @values = split(/,/, $2); +@@ -313,8 +313,8 @@ while (<>) + $values[0] = oct($values[0]) if $values[0] =~ /^0/; + $values[1] = oct($values[1]) if $values[1] =~ /^0/; + +- $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff; +- $eflagsset = sprintf "0x%08x", $values[1]; ++ $rflagsmask = sprintf "0x%016x", ~$values[0]; ++ $rflagsset = sprintf "0x%016x", $values[1]; + } + elsif ($preset =~ /^(fpucw)\[([^\]]+)\]$/) + { +@@ -544,7 +544,7 @@ while (<>) + + print qq| $ArgTypes{$type} $name;\n|; + } +- elsif ($result =~ /^eflags\[([^\]]+)\]$/) ++ elsif ($result =~ /^rflags\[([^\]]+)\]$/) + { + my @values = split(/,/, $1); + +@@ -553,19 +553,19 @@ while (<>) + + my $result = { + name => $name, +- type => "eflags", +- subtype => "ud", +- values => [ map { sprintf "0x%08x", $_ } @values ] ++ type => "rflags", ++ subtype => "uq", ++ values => [ map { sprintf "0x%016x", $_ } @values ] + }; + + push @results, $result; + +- print qq| $ArgTypes{eflags} $name;\n|; ++ print qq| $ArgTypes{rflags} $name;\n|; + +- if (!defined($eflagsmask) && !defined($eflagsset)) ++ if (!defined($rflagsmask) && !defined($rflagsset)) + { +- $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff; +- $eflagsset = sprintf "0x%08x", $values[0] & ~$values[1]; ++ $rflagsmask = sprintf "0x%016x", ~$values[0]; ++ $rflagsset = sprintf "0x%016x", $values[0] & ~$values[1]; + } + } + elsif ($result =~ /^fpucw\[([^\]]+)\]$/) +@@ -722,12 +722,11 @@ while (<>) + } + } + +- if (defined($eflagsmask) || defined($eflagsset)) ++ if (defined($rflagsmask) || defined($rflagsset)) + { + print qq| \"pushfq\\n\"\n|; +- print qq| \"andl \$$eflagsmask, (%%rsp)\\n\"\n| if defined($eflagsmask); +- print qq| \"andl \$0, 4(%%rsp)\\n\"\n| if defined($eflagsmask); +- print qq| \"orq \$$eflagsset, (%%rsp)\\n\"\n| if defined($eflagsset); ++ print qq| \"andq \$$rflagsmask, (%%rsp)\\n\"\n| if defined($rflagsmask); ++ print qq| \"orq \$$rflagsset, (%%rsp)\\n\"\n| if defined($rflagsset); + print qq| \"popfq\\n\"\n|; + } + +@@ -747,7 +746,7 @@ while (<>) + + foreach my $arg (@args) + { +- next if $arg->{type} eq "eflags"; ++ next if $arg->{type} eq "rflags"; + + if ($arg->{type} =~ /^(r8|r16|r32|r64|mm|xmm)$/) + { +@@ -815,7 +814,7 @@ while (<>) + { + $fpresults[$RegNums{$result->{register}}] = $result; + } +- elsif ($result->{type} eq "eflags") ++ elsif ($result->{type} eq "rflags") + { + print qq| \"pushfq\\n\"\n|; + print qq| \"popq %$result->{argnum}\\n\"\n|; +@@ -925,9 +924,9 @@ while (<>) + my $suffix = $SubTypeSuffixes{$subtype}; + my @values = @{$result->{values}}; + +- if ($type eq "eflags") ++ if ($type eq "rflags") + { +- print qq|${prefix}\($result->{name}.ud[0] & $values[0]UL\) == $values[1]UL|; ++ print qq|${prefix}\($result->{name}.uq[0] & $values[0]UL\) == $values[1]UL|; + } + elsif ($type =~ /^fpu[cs]w$/) + { +@@ -972,9 +971,9 @@ while (<>) + my $suffix = $SubTypeSuffixes{$subtype}; + my @values = @{$result->{values}}; + +- if ($type eq "eflags") ++ if ($type eq "rflags") + { +- print qq| printf(" eflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|; ++ print qq| printf(" rflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|; + } + elsif ($type =~ /^fpu[cs]w$/) + { +diff --git a/none/tests/amd64/insn_basic.def b/none/tests/amd64/insn_basic.def +index 8b10da1..c3bef75 100644 +--- a/none/tests/amd64/insn_basic.def ++++ b/none/tests/amd64/insn_basic.def +@@ -1,57 +1,57 @@ +-adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47] +-adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46] +-adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47] +-###adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] +-###adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] +-adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] +-adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] +-###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] +-###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913] +-adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912] +-adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913] +-adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] +-adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] +-###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] +-###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000] +-adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] +-adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] +-adcq eflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333] +-adcq eflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334] +-###adcq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999] +-###adcq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000] +-adcq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999] +-adcq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000] +-adcq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999] +-adcq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000] +-adcq eflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] +-adcq eflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] +-adcq eflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999] +-adcq eflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000] +-adcq eflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] +-adcq eflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] ++adcb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47] ++adcb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46] ++adcb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47] ++###adcb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] ++###adcb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] ++adcw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] ++adcw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] ++###adcw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] ++###adcw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913] ++adcw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912] ++adcw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913] ++adcl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] ++adcl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] ++###adcl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] ++###adcl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000] ++adcl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] ++adcl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] ++adcq rflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333] ++adcq rflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334] ++###adcq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999] ++###adcq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000] ++adcq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999] ++adcq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000] ++adcq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999] ++adcq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000] ++adcq rflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] ++adcq rflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] ++adcq rflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999] ++adcq rflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000] ++adcq rflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999] ++adcq rflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000] + addb imm8[12] al.ub[34] => 1.ub[46] + addb imm8[12] bl.ub[34] => 1.ub[46] + addb imm8[12] m8.ub[34] => 1.ub[46] +@@ -123,430 +123,430 @@ bsrq r64.uq[0x1357246813572468] r64.uq[0] => 1.uq[60] + bsrq m64.uq[0x7531864275318642] r64.uq[0] => 1.uq[62] + bswapl r32.ud[0x12345678] => 0.ud[0x78563412] + bswapq r64.uq[0x1234567813572468] => 0.uq[0x6824571378563412] +-btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +-###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +-btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +-btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +-btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001] +-btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000] +-btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +-###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +-btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +-btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +-btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] +-btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001] +-btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000] ++btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001] ++###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000] ++btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001] ++btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000] ++btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001] ++btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000] ++btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001] ++###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000] ++btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001] ++btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000] ++btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] ++btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001] ++btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000] + cbw al.sb[123] : => ax.sw[123] + cbw al.sb[-123] : => ax.sw[-123] + cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678] + cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98] + cdqe eax.ud[0x12345678] : => rax.uq[0x0000000012345678] + cdqe eax.ud[0xfedcba98] : => rax.uq[0xfffffffffedcba98] +-###clc eflags[0x001,0x000] : => eflags[0x001,0x000] +-###clc eflags[0x001,0x001] : => eflags[0x001,0x000] +-cld eflags[0x400,0x000] : => eflags[0x400,0x000] +-cld eflags[0x400,0x400] : => eflags[0x400,0x000] +-###cmc eflags[0x001,0x000] : => eflags[0x001,0x001] +-###cmc eflags[0x001,0x001] : => eflags[0x001,0x000] +-cmpb imm8[3] al.ub[2] => eflags[0x010,0x010] +-cmpb imm8[2] al.ub[3] => eflags[0x010,0x000] +-cmpb imm8[12] al.ub[12] => eflags[0x044,0x044] +-cmpb imm8[12] al.ub[34] => eflags[0x044,0x000] +-cmpb imm8[34] al.ub[12] => eflags[0x081,0x081] +-cmpb imm8[12] al.ub[34] => eflags[0x081,0x000] +-cmpb imm8[100] al.sb[-100] => eflags[0x800,0x800] +-cmpb imm8[50] al.sb[-50] => eflags[0x800,0x000] +-cmpb imm8[-50] al.sb[50] => eflags[0x800,0x000] +-cmpb imm8[-100] al.sb[100] => eflags[0x800,0x800] +-cmpb imm8[3] r8.ub[2] => eflags[0x010,0x010] +-cmpb imm8[2] r8.ub[3] => eflags[0x010,0x000] +-cmpb imm8[12] r8.ub[12] => eflags[0x044,0x044] +-cmpb imm8[12] r8.ub[34] => eflags[0x044,0x000] +-cmpb imm8[34] r8.ub[12] => eflags[0x081,0x081] +-cmpb imm8[12] r8.ub[34] => eflags[0x081,0x000] +-cmpb imm8[100] r8.sb[-100] => eflags[0x800,0x800] +-cmpb imm8[50] r8.sb[-50] => eflags[0x800,0x000] +-cmpb imm8[-50] r8.sb[50] => eflags[0x800,0x000] +-cmpb imm8[-100] r8.sb[100] => eflags[0x800,0x800] +-cmpb imm8[3] m8.ub[2] => eflags[0x010,0x010] +-cmpb imm8[2] m8.ub[3] => eflags[0x010,0x000] +-cmpb imm8[12] m8.ub[12] => eflags[0x044,0x044] +-cmpb imm8[12] m8.ub[34] => eflags[0x044,0x000] +-cmpb imm8[34] m8.ub[12] => eflags[0x081,0x081] +-cmpb imm8[12] m8.ub[34] => eflags[0x081,0x000] +-cmpb imm8[100] m8.sb[-100] => eflags[0x800,0x800] +-cmpb imm8[50] m8.sb[-50] => eflags[0x800,0x000] +-cmpb imm8[-50] m8.sb[50] => eflags[0x800,0x000] +-cmpb imm8[-100] m8.sb[100] => eflags[0x800,0x800] +-cmpb r8.ub[3] r8.ub[2] => eflags[0x010,0x010] +-cmpb r8.ub[2] r8.ub[3] => eflags[0x010,0x000] +-cmpb r8.ub[12] r8.ub[12] => eflags[0x044,0x044] +-cmpb r8.ub[12] r8.ub[34] => eflags[0x044,0x000] +-cmpb r8.ub[34] r8.ub[12] => eflags[0x081,0x081] +-cmpb r8.ub[12] r8.ub[34] => eflags[0x081,0x000] +-cmpb r8.ub[100] r8.sb[-100] => eflags[0x800,0x800] +-cmpb r8.ub[50] r8.sb[-50] => eflags[0x800,0x000] +-cmpb r8.sb[-50] r8.sb[50] => eflags[0x800,0x000] +-cmpb r8.sb[-100] r8.sb[100] => eflags[0x800,0x800] +-cmpb r8.ub[3] m8.ub[2] => eflags[0x010,0x010] +-cmpb r8.ub[2] m8.ub[3] => eflags[0x010,0x000] +-cmpb r8.ub[12] m8.ub[12] => eflags[0x044,0x044] +-cmpb r8.ub[12] m8.ub[34] => eflags[0x044,0x000] +-cmpb r8.ub[34] m8.ub[12] => eflags[0x081,0x081] +-cmpb r8.ub[12] m8.ub[34] => eflags[0x081,0x000] +-cmpb r8.ub[100] m8.sb[-100] => eflags[0x800,0x800] +-cmpb r8.ub[50] m8.sb[-50] => eflags[0x800,0x000] +-cmpb r8.sb[-50] m8.sb[50] => eflags[0x800,0x000] +-cmpb r8.sb[-100] m8.sb[100] => eflags[0x800,0x800] +-cmpb m8.ub[3] r8.ub[2] => eflags[0x010,0x010] +-cmpb m8.ub[2] r8.ub[3] => eflags[0x010,0x000] +-cmpb m8.ub[12] r8.ub[12] => eflags[0x044,0x044] +-cmpb m8.ub[12] r8.ub[34] => eflags[0x044,0x000] +-cmpb m8.ub[34] r8.ub[12] => eflags[0x081,0x081] +-cmpb m8.ub[12] r8.ub[34] => eflags[0x081,0x000] +-cmpb m8.ub[100] r8.sb[-100] => eflags[0x800,0x800] +-cmpb m8.ub[50] r8.sb[-50] => eflags[0x800,0x000] +-cmpb m8.sb[-50] r8.sb[50] => eflags[0x800,0x000] +-cmpb m8.sb[-100] r8.sb[100] => eflags[0x800,0x800] +-cmpw imm8[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw imm8[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw imm8[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw imm8[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw imm8[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw imm8[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw imm8[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm8[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw imm8[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw imm8[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpw imm8[3] m16.uw[2] => eflags[0x010,0x010] +-cmpw imm8[2] m16.uw[3] => eflags[0x010,0x000] +-cmpw imm8[12] m16.uw[12] => eflags[0x044,0x044] +-cmpw imm8[12] m16.uw[34] => eflags[0x044,0x000] +-cmpw imm8[34] m16.uw[12] => eflags[0x081,0x081] +-cmpw imm8[12] m16.uw[34] => eflags[0x081,0x000] +-cmpw imm8[100] m16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm8[50] m16.sw[-50] => eflags[0x800,0x000] +-cmpw imm8[-50] m16.sw[50] => eflags[0x800,0x000] +-cmpw imm8[-100] m16.sw[32700] => eflags[0x800,0x800] +-cmpw imm16[3] ax.uw[2] => eflags[0x010,0x010] +-cmpw imm16[2] ax.uw[3] => eflags[0x010,0x000] +-cmpw imm16[12] ax.uw[12] => eflags[0x044,0x044] +-cmpw imm16[12] ax.uw[34] => eflags[0x044,0x000] +-cmpw imm16[34] ax.uw[12] => eflags[0x081,0x081] +-cmpw imm16[12] ax.uw[34] => eflags[0x081,0x000] +-cmpw imm16[100] ax.sw[-32700] => eflags[0x800,0x800] +-cmpw imm16[50] ax.sw[-50] => eflags[0x800,0x000] +-cmpw imm16[-50] ax.sw[50] => eflags[0x800,0x000] +-cmpw imm16[-100] ax.sw[32700] => eflags[0x800,0x800] +-cmpw imm16[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw imm16[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw imm16[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw imm16[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw imm16[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw imm16[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw imm16[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm16[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw imm16[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw imm16[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpw imm16[3] m16.uw[2] => eflags[0x010,0x010] +-cmpw imm16[2] m16.uw[3] => eflags[0x010,0x000] +-cmpw imm16[12] m16.uw[12] => eflags[0x044,0x044] +-cmpw imm16[12] m16.uw[34] => eflags[0x044,0x000] +-cmpw imm16[34] m16.uw[12] => eflags[0x081,0x081] +-cmpw imm16[12] m16.uw[34] => eflags[0x081,0x000] +-cmpw imm16[100] m16.sw[-32700] => eflags[0x800,0x800] +-cmpw imm16[50] m16.sw[-50] => eflags[0x800,0x000] +-cmpw imm16[-50] m16.sw[50] => eflags[0x800,0x000] +-cmpw imm16[-100] m16.sw[32700] => eflags[0x800,0x800] +-cmpw r16.uw[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw r16.uw[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw r16.uw[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw r16.uw[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw r16.uw[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw r16.uw[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw r16.uw[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw r16.uw[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw r16.sw[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw r16.sw[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpw r16.uw[3] m16.uw[2] => eflags[0x010,0x010] +-cmpw r16.uw[2] m16.uw[3] => eflags[0x010,0x000] +-cmpw r16.uw[12] m16.uw[12] => eflags[0x044,0x044] +-cmpw r16.uw[12] m16.uw[34] => eflags[0x044,0x000] +-cmpw r16.uw[34] m16.uw[12] => eflags[0x081,0x081] +-cmpw r16.uw[12] m16.uw[34] => eflags[0x081,0x000] +-cmpw r16.uw[100] m16.sw[-32700] => eflags[0x800,0x800] +-cmpw r16.uw[50] m16.sw[-50] => eflags[0x800,0x000] +-cmpw r16.sw[-50] m16.sw[50] => eflags[0x800,0x000] +-cmpw r16.sw[-100] m16.sw[32700] => eflags[0x800,0x800] +-cmpw m16.uw[3] r16.uw[2] => eflags[0x010,0x010] +-cmpw m16.uw[2] r16.uw[3] => eflags[0x010,0x000] +-cmpw m16.uw[12] r16.uw[12] => eflags[0x044,0x044] +-cmpw m16.uw[12] r16.uw[34] => eflags[0x044,0x000] +-cmpw m16.uw[34] r16.uw[12] => eflags[0x081,0x081] +-cmpw m16.uw[12] r16.uw[34] => eflags[0x081,0x000] +-cmpw m16.uw[100] r16.sw[-32700] => eflags[0x800,0x800] +-cmpw m16.uw[50] r16.sw[-50] => eflags[0x800,0x000] +-cmpw m16.sw[-50] r16.sw[50] => eflags[0x800,0x000] +-cmpw m16.sw[-100] r16.sw[32700] => eflags[0x800,0x800] +-cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044] +-###cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000] +-cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010] +-cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000] +-cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044] +-cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000] +-cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081] +-cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000] +-cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000] +-cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000] +-cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010] +-cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000] +-cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044] +-cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000] +-cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081] +-cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000] +-cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000] +-cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000] +-cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044] +-cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000] +-cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010] +-cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000] +-cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044] +-cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000] +-cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081] +-cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000] +-cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000] +-cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000] +-cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044] +-cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000] +-cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010] +-cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000] +-cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044] +-cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000] +-cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081] +-cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000] +-cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000] +-cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000] +-cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800] +-cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010] +-cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000] +-cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044] +-cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000] +-cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081] +-cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000] +-cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800] +-cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000] +-cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000] +-###cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800] +-cmpq imm8[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq imm8[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq imm8[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq imm8[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq imm8[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq imm8[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq imm8[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm8[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq imm8[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq imm8[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm8[3] m64.uq[2] => eflags[0x010,0x010] +-cmpq imm8[2] m64.uq[3] => eflags[0x010,0x000] +-cmpq imm8[12] m64.uq[12] => eflags[0x044,0x044] +-cmpq imm8[12] m64.uq[34] => eflags[0x044,0x000] +-cmpq imm8[34] m64.uq[12] => eflags[0x081,0x081] +-cmpq imm8[12] m64.uq[34] => eflags[0x081,0x000] +-cmpq imm8[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm8[50] m64.sq[-50] => eflags[0x800,0x000] +-cmpq imm8[-50] m64.sq[50] => eflags[0x800,0x000] +-cmpq imm8[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[3] rax.uq[2] => eflags[0x010,0x010] +-cmpq imm32[2] rax.uq[3] => eflags[0x010,0x000] +-cmpq imm32[12] rax.uq[12] => eflags[0x044,0x044] +-cmpq imm32[12] rax.uq[34] => eflags[0x044,0x000] +-cmpq imm32[34] rax.uq[12] => eflags[0x081,0x081] +-cmpq imm32[12] rax.uq[34] => eflags[0x081,0x000] +-cmpq imm32[100] rax.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[50] rax.sq[-50] => eflags[0x800,0x000] +-cmpq imm32[-50] rax.sq[50] => eflags[0x800,0x000] +-cmpq imm32[-100] rax.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq imm32[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq imm32[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq imm32[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq imm32[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq imm32[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq imm32[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq imm32[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq imm32[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[3] m64.uq[2] => eflags[0x010,0x010] +-cmpq imm32[2] m64.uq[3] => eflags[0x010,0x000] +-cmpq imm32[12] m64.uq[12] => eflags[0x044,0x044] +-cmpq imm32[12] m64.uq[34] => eflags[0x044,0x000] +-cmpq imm32[34] m64.uq[12] => eflags[0x081,0x081] +-cmpq imm32[12] m64.uq[34] => eflags[0x081,0x000] +-cmpq imm32[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq imm32[50] m64.sq[-50] => eflags[0x800,0x000] +-cmpq imm32[-50] m64.sq[50] => eflags[0x800,0x000] +-cmpq imm32[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq r64.uq[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq r64.uq[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq r64.uq[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq r64.uq[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq r64.uq[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq r64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq r64.sq[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq r64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[3] m64.uq[2] => eflags[0x010,0x010] +-cmpq r64.uq[2] m64.uq[3] => eflags[0x010,0x000] +-cmpq r64.uq[12] m64.uq[12] => eflags[0x044,0x044] +-cmpq r64.uq[12] m64.uq[34] => eflags[0x044,0x000] +-cmpq r64.uq[34] m64.uq[12] => eflags[0x081,0x081] +-cmpq r64.uq[12] m64.uq[34] => eflags[0x081,0x000] +-cmpq r64.uq[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq r64.uq[50] m64.sq[-50] => eflags[0x800,0x000] +-cmpq r64.sq[-50] m64.sq[50] => eflags[0x800,0x000] +-cmpq r64.sq[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800] +-cmpq m64.uq[3] r64.uq[2] => eflags[0x010,0x010] +-cmpq m64.uq[2] r64.uq[3] => eflags[0x010,0x000] +-cmpq m64.uq[12] r64.uq[12] => eflags[0x044,0x044] +-cmpq m64.uq[12] r64.uq[34] => eflags[0x044,0x000] +-cmpq m64.uq[34] r64.uq[12] => eflags[0x081,0x081] +-cmpq m64.uq[12] r64.uq[34] => eflags[0x081,0x000] +-cmpq m64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800] +-cmpq m64.uq[50] r64.sq[-50] => eflags[0x800,0x000] +-cmpq m64.sq[-50] r64.sq[50] => eflags[0x800,0x000] +-cmpq m64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800] +-###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] +-###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] +-###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] +-###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] +-###cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] +-###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] +-cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] +-###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] +-###cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] +-###cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] +-cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] +-cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] +-###cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] +-###cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] +-cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] +-cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] ++###clc rflags[0x001,0x000] : => rflags[0x001,0x000] ++###clc rflags[0x001,0x001] : => rflags[0x001,0x000] ++cld rflags[0x400,0x000] : => rflags[0x400,0x000] ++cld rflags[0x400,0x400] : => rflags[0x400,0x000] ++###cmc rflags[0x001,0x000] : => rflags[0x001,0x001] ++###cmc rflags[0x001,0x001] : => rflags[0x001,0x000] ++cmpb imm8[3] al.ub[2] => rflags[0x010,0x010] ++cmpb imm8[2] al.ub[3] => rflags[0x010,0x000] ++cmpb imm8[12] al.ub[12] => rflags[0x044,0x044] ++cmpb imm8[12] al.ub[34] => rflags[0x044,0x000] ++cmpb imm8[34] al.ub[12] => rflags[0x081,0x081] ++cmpb imm8[12] al.ub[34] => rflags[0x081,0x000] ++cmpb imm8[100] al.sb[-100] => rflags[0x800,0x800] ++cmpb imm8[50] al.sb[-50] => rflags[0x800,0x000] ++cmpb imm8[-50] al.sb[50] => rflags[0x800,0x000] ++cmpb imm8[-100] al.sb[100] => rflags[0x800,0x800] ++cmpb imm8[3] r8.ub[2] => rflags[0x010,0x010] ++cmpb imm8[2] r8.ub[3] => rflags[0x010,0x000] ++cmpb imm8[12] r8.ub[12] => rflags[0x044,0x044] ++cmpb imm8[12] r8.ub[34] => rflags[0x044,0x000] ++cmpb imm8[34] r8.ub[12] => rflags[0x081,0x081] ++cmpb imm8[12] r8.ub[34] => rflags[0x081,0x000] ++cmpb imm8[100] r8.sb[-100] => rflags[0x800,0x800] ++cmpb imm8[50] r8.sb[-50] => rflags[0x800,0x000] ++cmpb imm8[-50] r8.sb[50] => rflags[0x800,0x000] ++cmpb imm8[-100] r8.sb[100] => rflags[0x800,0x800] ++cmpb imm8[3] m8.ub[2] => rflags[0x010,0x010] ++cmpb imm8[2] m8.ub[3] => rflags[0x010,0x000] ++cmpb imm8[12] m8.ub[12] => rflags[0x044,0x044] ++cmpb imm8[12] m8.ub[34] => rflags[0x044,0x000] ++cmpb imm8[34] m8.ub[12] => rflags[0x081,0x081] ++cmpb imm8[12] m8.ub[34] => rflags[0x081,0x000] ++cmpb imm8[100] m8.sb[-100] => rflags[0x800,0x800] ++cmpb imm8[50] m8.sb[-50] => rflags[0x800,0x000] ++cmpb imm8[-50] m8.sb[50] => rflags[0x800,0x000] ++cmpb imm8[-100] m8.sb[100] => rflags[0x800,0x800] ++cmpb r8.ub[3] r8.ub[2] => rflags[0x010,0x010] ++cmpb r8.ub[2] r8.ub[3] => rflags[0x010,0x000] ++cmpb r8.ub[12] r8.ub[12] => rflags[0x044,0x044] ++cmpb r8.ub[12] r8.ub[34] => rflags[0x044,0x000] ++cmpb r8.ub[34] r8.ub[12] => rflags[0x081,0x081] ++cmpb r8.ub[12] r8.ub[34] => rflags[0x081,0x000] ++cmpb r8.ub[100] r8.sb[-100] => rflags[0x800,0x800] ++cmpb r8.ub[50] r8.sb[-50] => rflags[0x800,0x000] ++cmpb r8.sb[-50] r8.sb[50] => rflags[0x800,0x000] ++cmpb r8.sb[-100] r8.sb[100] => rflags[0x800,0x800] ++cmpb r8.ub[3] m8.ub[2] => rflags[0x010,0x010] ++cmpb r8.ub[2] m8.ub[3] => rflags[0x010,0x000] ++cmpb r8.ub[12] m8.ub[12] => rflags[0x044,0x044] ++cmpb r8.ub[12] m8.ub[34] => rflags[0x044,0x000] ++cmpb r8.ub[34] m8.ub[12] => rflags[0x081,0x081] ++cmpb r8.ub[12] m8.ub[34] => rflags[0x081,0x000] ++cmpb r8.ub[100] m8.sb[-100] => rflags[0x800,0x800] ++cmpb r8.ub[50] m8.sb[-50] => rflags[0x800,0x000] ++cmpb r8.sb[-50] m8.sb[50] => rflags[0x800,0x000] ++cmpb r8.sb[-100] m8.sb[100] => rflags[0x800,0x800] ++cmpb m8.ub[3] r8.ub[2] => rflags[0x010,0x010] ++cmpb m8.ub[2] r8.ub[3] => rflags[0x010,0x000] ++cmpb m8.ub[12] r8.ub[12] => rflags[0x044,0x044] ++cmpb m8.ub[12] r8.ub[34] => rflags[0x044,0x000] ++cmpb m8.ub[34] r8.ub[12] => rflags[0x081,0x081] ++cmpb m8.ub[12] r8.ub[34] => rflags[0x081,0x000] ++cmpb m8.ub[100] r8.sb[-100] => rflags[0x800,0x800] ++cmpb m8.ub[50] r8.sb[-50] => rflags[0x800,0x000] ++cmpb m8.sb[-50] r8.sb[50] => rflags[0x800,0x000] ++cmpb m8.sb[-100] r8.sb[100] => rflags[0x800,0x800] ++cmpw imm8[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw imm8[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw imm8[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw imm8[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw imm8[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw imm8[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw imm8[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm8[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw imm8[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw imm8[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpw imm8[3] m16.uw[2] => rflags[0x010,0x010] ++cmpw imm8[2] m16.uw[3] => rflags[0x010,0x000] ++cmpw imm8[12] m16.uw[12] => rflags[0x044,0x044] ++cmpw imm8[12] m16.uw[34] => rflags[0x044,0x000] ++cmpw imm8[34] m16.uw[12] => rflags[0x081,0x081] ++cmpw imm8[12] m16.uw[34] => rflags[0x081,0x000] ++cmpw imm8[100] m16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm8[50] m16.sw[-50] => rflags[0x800,0x000] ++cmpw imm8[-50] m16.sw[50] => rflags[0x800,0x000] ++cmpw imm8[-100] m16.sw[32700] => rflags[0x800,0x800] ++cmpw imm16[3] ax.uw[2] => rflags[0x010,0x010] ++cmpw imm16[2] ax.uw[3] => rflags[0x010,0x000] ++cmpw imm16[12] ax.uw[12] => rflags[0x044,0x044] ++cmpw imm16[12] ax.uw[34] => rflags[0x044,0x000] ++cmpw imm16[34] ax.uw[12] => rflags[0x081,0x081] ++cmpw imm16[12] ax.uw[34] => rflags[0x081,0x000] ++cmpw imm16[100] ax.sw[-32700] => rflags[0x800,0x800] ++cmpw imm16[50] ax.sw[-50] => rflags[0x800,0x000] ++cmpw imm16[-50] ax.sw[50] => rflags[0x800,0x000] ++cmpw imm16[-100] ax.sw[32700] => rflags[0x800,0x800] ++cmpw imm16[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw imm16[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw imm16[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw imm16[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw imm16[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw imm16[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw imm16[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm16[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw imm16[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw imm16[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpw imm16[3] m16.uw[2] => rflags[0x010,0x010] ++cmpw imm16[2] m16.uw[3] => rflags[0x010,0x000] ++cmpw imm16[12] m16.uw[12] => rflags[0x044,0x044] ++cmpw imm16[12] m16.uw[34] => rflags[0x044,0x000] ++cmpw imm16[34] m16.uw[12] => rflags[0x081,0x081] ++cmpw imm16[12] m16.uw[34] => rflags[0x081,0x000] ++cmpw imm16[100] m16.sw[-32700] => rflags[0x800,0x800] ++cmpw imm16[50] m16.sw[-50] => rflags[0x800,0x000] ++cmpw imm16[-50] m16.sw[50] => rflags[0x800,0x000] ++cmpw imm16[-100] m16.sw[32700] => rflags[0x800,0x800] ++cmpw r16.uw[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw r16.uw[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw r16.uw[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw r16.uw[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw r16.uw[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw r16.uw[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw r16.uw[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw r16.uw[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw r16.sw[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw r16.sw[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpw r16.uw[3] m16.uw[2] => rflags[0x010,0x010] ++cmpw r16.uw[2] m16.uw[3] => rflags[0x010,0x000] ++cmpw r16.uw[12] m16.uw[12] => rflags[0x044,0x044] ++cmpw r16.uw[12] m16.uw[34] => rflags[0x044,0x000] ++cmpw r16.uw[34] m16.uw[12] => rflags[0x081,0x081] ++cmpw r16.uw[12] m16.uw[34] => rflags[0x081,0x000] ++cmpw r16.uw[100] m16.sw[-32700] => rflags[0x800,0x800] ++cmpw r16.uw[50] m16.sw[-50] => rflags[0x800,0x000] ++cmpw r16.sw[-50] m16.sw[50] => rflags[0x800,0x000] ++cmpw r16.sw[-100] m16.sw[32700] => rflags[0x800,0x800] ++cmpw m16.uw[3] r16.uw[2] => rflags[0x010,0x010] ++cmpw m16.uw[2] r16.uw[3] => rflags[0x010,0x000] ++cmpw m16.uw[12] r16.uw[12] => rflags[0x044,0x044] ++cmpw m16.uw[12] r16.uw[34] => rflags[0x044,0x000] ++cmpw m16.uw[34] r16.uw[12] => rflags[0x081,0x081] ++cmpw m16.uw[12] r16.uw[34] => rflags[0x081,0x000] ++cmpw m16.uw[100] r16.sw[-32700] => rflags[0x800,0x800] ++cmpw m16.uw[50] r16.sw[-50] => rflags[0x800,0x000] ++cmpw m16.sw[-50] r16.sw[50] => rflags[0x800,0x000] ++cmpw m16.sw[-100] r16.sw[32700] => rflags[0x800,0x800] ++cmpl imm8[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl imm8[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl imm8[12] r32.ud[12] => rflags[0x044,0x044] ++###cmpl imm8[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl imm8[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl imm8[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl imm8[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm8[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl imm8[-50] r32.sd[50] => rflags[0x800,0x000] ++cmpl imm8[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm8[3] m32.ud[2] => rflags[0x010,0x010] ++cmpl imm8[2] m32.ud[3] => rflags[0x010,0x000] ++cmpl imm8[12] m32.ud[12] => rflags[0x044,0x044] ++cmpl imm8[12] m32.ud[34] => rflags[0x044,0x000] ++cmpl imm8[34] m32.ud[12] => rflags[0x081,0x081] ++cmpl imm8[12] m32.ud[34] => rflags[0x081,0x000] ++cmpl imm8[100] m32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm8[50] m32.sd[-50] => rflags[0x800,0x000] ++cmpl imm8[-50] m32.sd[50] => rflags[0x800,0x000] ++cmpl imm8[-100] m32.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm32[3] eax.ud[2] => rflags[0x010,0x010] ++cmpl imm32[2] eax.ud[3] => rflags[0x010,0x000] ++cmpl imm32[12] eax.ud[12] => rflags[0x044,0x044] ++cmpl imm32[12] eax.ud[34] => rflags[0x044,0x000] ++cmpl imm32[34] eax.ud[12] => rflags[0x081,0x081] ++cmpl imm32[12] eax.ud[34] => rflags[0x081,0x000] ++cmpl imm32[100] eax.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm32[50] eax.sd[-50] => rflags[0x800,0x000] ++cmpl imm32[-50] eax.sd[50] => rflags[0x800,0x000] ++cmpl imm32[-100] eax.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm32[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl imm32[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl imm32[12] r32.ud[12] => rflags[0x044,0x044] ++cmpl imm32[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl imm32[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl imm32[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl imm32[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm32[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl imm32[-50] r32.sd[50] => rflags[0x800,0x000] ++cmpl imm32[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpl imm32[3] m32.ud[2] => rflags[0x010,0x010] ++cmpl imm32[2] m32.ud[3] => rflags[0x010,0x000] ++cmpl imm32[12] m32.ud[12] => rflags[0x044,0x044] ++cmpl imm32[12] m32.ud[34] => rflags[0x044,0x000] ++cmpl imm32[34] m32.ud[12] => rflags[0x081,0x081] ++cmpl imm32[12] m32.ud[34] => rflags[0x081,0x000] ++cmpl imm32[100] m32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl imm32[50] m32.sd[-50] => rflags[0x800,0x000] ++cmpl imm32[-50] m32.sd[50] => rflags[0x800,0x000] ++cmpl imm32[-100] m32.sd[2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl r32.ud[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl r32.ud[12] r32.ud[12] => rflags[0x044,0x044] ++cmpl r32.ud[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl r32.ud[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl r32.ud[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl r32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl r32.sd[-50] r32.sd[50] => rflags[0x800,0x000] ++cmpl r32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[3] m32.ud[2] => rflags[0x010,0x010] ++cmpl r32.ud[2] m32.ud[3] => rflags[0x010,0x000] ++cmpl r32.ud[12] m32.ud[12] => rflags[0x044,0x044] ++cmpl r32.ud[12] m32.ud[34] => rflags[0x044,0x000] ++cmpl r32.ud[34] m32.ud[12] => rflags[0x081,0x081] ++cmpl r32.ud[12] m32.ud[34] => rflags[0x081,0x000] ++cmpl r32.ud[100] m32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl r32.ud[50] m32.sd[-50] => rflags[0x800,0x000] ++cmpl r32.sd[-50] m32.sd[50] => rflags[0x800,0x000] ++cmpl r32.sd[-100] m32.sd[2147483600] => rflags[0x800,0x800] ++cmpl m32.ud[3] r32.ud[2] => rflags[0x010,0x010] ++cmpl m32.ud[2] r32.ud[3] => rflags[0x010,0x000] ++cmpl m32.ud[12] r32.ud[12] => rflags[0x044,0x044] ++cmpl m32.ud[12] r32.ud[34] => rflags[0x044,0x000] ++cmpl m32.ud[34] r32.ud[12] => rflags[0x081,0x081] ++cmpl m32.ud[12] r32.ud[34] => rflags[0x081,0x000] ++cmpl m32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800] ++cmpl m32.ud[50] r32.sd[-50] => rflags[0x800,0x000] ++cmpl m32.sd[-50] r32.sd[50] => rflags[0x800,0x000] ++###cmpl m32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800] ++cmpq imm8[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq imm8[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq imm8[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq imm8[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq imm8[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq imm8[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq imm8[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm8[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq imm8[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq imm8[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm8[3] m64.uq[2] => rflags[0x010,0x010] ++cmpq imm8[2] m64.uq[3] => rflags[0x010,0x000] ++cmpq imm8[12] m64.uq[12] => rflags[0x044,0x044] ++cmpq imm8[12] m64.uq[34] => rflags[0x044,0x000] ++cmpq imm8[34] m64.uq[12] => rflags[0x081,0x081] ++cmpq imm8[12] m64.uq[34] => rflags[0x081,0x000] ++cmpq imm8[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm8[50] m64.sq[-50] => rflags[0x800,0x000] ++cmpq imm8[-50] m64.sq[50] => rflags[0x800,0x000] ++cmpq imm8[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[3] rax.uq[2] => rflags[0x010,0x010] ++cmpq imm32[2] rax.uq[3] => rflags[0x010,0x000] ++cmpq imm32[12] rax.uq[12] => rflags[0x044,0x044] ++cmpq imm32[12] rax.uq[34] => rflags[0x044,0x000] ++cmpq imm32[34] rax.uq[12] => rflags[0x081,0x081] ++cmpq imm32[12] rax.uq[34] => rflags[0x081,0x000] ++cmpq imm32[100] rax.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[50] rax.sq[-50] => rflags[0x800,0x000] ++cmpq imm32[-50] rax.sq[50] => rflags[0x800,0x000] ++cmpq imm32[-100] rax.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq imm32[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq imm32[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq imm32[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq imm32[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq imm32[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq imm32[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq imm32[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq imm32[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[3] m64.uq[2] => rflags[0x010,0x010] ++cmpq imm32[2] m64.uq[3] => rflags[0x010,0x000] ++cmpq imm32[12] m64.uq[12] => rflags[0x044,0x044] ++cmpq imm32[12] m64.uq[34] => rflags[0x044,0x000] ++cmpq imm32[34] m64.uq[12] => rflags[0x081,0x081] ++cmpq imm32[12] m64.uq[34] => rflags[0x081,0x000] ++cmpq imm32[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq imm32[50] m64.sq[-50] => rflags[0x800,0x000] ++cmpq imm32[-50] m64.sq[50] => rflags[0x800,0x000] ++cmpq imm32[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq r64.uq[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq r64.uq[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq r64.uq[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq r64.uq[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq r64.uq[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq r64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq r64.sq[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq r64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[3] m64.uq[2] => rflags[0x010,0x010] ++cmpq r64.uq[2] m64.uq[3] => rflags[0x010,0x000] ++cmpq r64.uq[12] m64.uq[12] => rflags[0x044,0x044] ++cmpq r64.uq[12] m64.uq[34] => rflags[0x044,0x000] ++cmpq r64.uq[34] m64.uq[12] => rflags[0x081,0x081] ++cmpq r64.uq[12] m64.uq[34] => rflags[0x081,0x000] ++cmpq r64.uq[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq r64.uq[50] m64.sq[-50] => rflags[0x800,0x000] ++cmpq r64.sq[-50] m64.sq[50] => rflags[0x800,0x000] ++cmpq r64.sq[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800] ++cmpq m64.uq[3] r64.uq[2] => rflags[0x010,0x010] ++cmpq m64.uq[2] r64.uq[3] => rflags[0x010,0x000] ++cmpq m64.uq[12] r64.uq[12] => rflags[0x044,0x044] ++cmpq m64.uq[12] r64.uq[34] => rflags[0x044,0x000] ++cmpq m64.uq[34] r64.uq[12] => rflags[0x081,0x081] ++cmpq m64.uq[12] r64.uq[34] => rflags[0x081,0x000] ++cmpq m64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800] ++cmpq m64.uq[50] r64.sq[-50] => rflags[0x800,0x000] ++cmpq m64.sq[-50] r64.sq[50] => rflags[0x800,0x000] ++cmpq m64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800] ++###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] ++###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] ++###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] ++###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] ++###cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] ++###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] ++cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] ++###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] ++###cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] ++###cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] ++cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] ++cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] ++###cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] ++###cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] ++cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789] ++cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567] + cqo rax.uq[0x0123456789abcdef] : => rdx.uq[0x0000000000000000] rax.uq[0x0123456789abcdef] + cqo rax.uq[0xfedcba9876543210] : => rdx.uq[0xffffffffffffffff] rax.uq[0xfedcba9876543210] + cwd ax.uw[0x1234] : => dx.uw[0x0000] ax.uw[0x1234] +@@ -617,8 +617,8 @@ incl r32.ud[12345678] => 0.ud[12345679] + incl m32.ud[12345678] => 0.ud[12345679] + incq r64.uq[1234567813572468] => 0.uq[1234567813572469] + incq m64.uq[1234567813572468] => 0.uq[1234567813572469] +-###lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] +-###lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] ++###lahf rflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] ++###lahf rflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] + movb imm8[123] r8.ub[0] => 1.ub[123] + movb imm8[123] m8.ub[0] => 1.ub[123] + movb r8.ub[123] r8.ub[0] => 1.ub[123] +@@ -714,54 +714,54 @@ orq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0xffffffff96767779] + orq r64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff] + orq r64.uq[0xeca86420fdb97531] m64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff] + orq m64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff] +-###rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-###rclq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1] +-rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] +-rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] +-rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] +-rcrw eflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0] +-rcrw eflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0] +-rcrw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] +-rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0] +-rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0] +-rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] +-rcrq eflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0] +-rcrq eflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0] +-rcrq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] +-rcrq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] +-rcrq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] +-rcrq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rclw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rcll rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++###rclq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1] ++rcrb rflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0] ++rcrb rflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0] ++rcrb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1] ++rcrw rflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0] ++rcrw rflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0] ++rcrw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1] ++rcrl rflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0] ++rcrl rflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0] ++rcrl rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrl rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrl rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrl rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1] ++rcrq rflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0] ++rcrq rflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0] ++rcrq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] ++rcrq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] ++rcrq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] ++rcrq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1] + rolb r8.ub[0xca] => 0.ub[0x95] + rolb m8.ub[0xca] => 0.ub[0x95] + rolb imm8[2] r8.ub[0xca] => 1.ub[0x2b] +@@ -810,8 +810,8 @@ rorq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] + rorq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] + rorq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] + rorq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00] +-###sahf eflags[0xff,0x28] ah.ub[0xfd] : => eflags[0xfd,0xd5] +-###sahf eflags[0xff,0xfd] ah.ub[0x28] : => eflags[0xfd,0x00] ++###sahf rflags[0xff,0x28] ah.ub[0xfd] : => rflags[0xfd,0xd5] ++###sahf rflags[0xff,0xfd] ah.ub[0x28] : => rflags[0xfd,0x00] + salb r8.ub[0xca] => 0.ub[0x94] + salb m8.ub[0xca] => 0.ub[0x94] + salb imm8[2] r8.ub[0xca] => 1.ub[0x28] +@@ -860,252 +860,252 @@ sarq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] + sarq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] + sarq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] + sarq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00] +-###sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] +-###sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] +-sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22] +-sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21] +-sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22] +-sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21] +-sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22] +-sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21] +-###sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22] +-###sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21] +-###sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] +-###sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] +-sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444] +-sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443] +-###sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] +-###sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443] +-###sbbw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444] +-###sbbw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443] +-sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444] +-sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443] +-sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309] +-sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308] +-###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] +-###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] +-###sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643] +-###sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642] +-sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] +-sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] +-sbbq eflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630] +-sbbq eflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629] +-###sbbq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964] +-###sbbq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963] +-sbbq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964] +-sbbq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963] +-sbbq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964] +-sbbq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963] +-sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] +-sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] +-###sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174] +-###sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173] +-sbbq eflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] +-sbbq eflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] +-seta eflags[0x041,0x000] : r8.ub[123] => 0.ub[1] +-seta eflags[0x041,0x001] : r8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x040] : r8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x041] : r8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x000] : m8.ub[123] => 0.ub[1] +-seta eflags[0x041,0x001] : m8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x040] : m8.ub[123] => 0.ub[0] +-seta eflags[0x041,0x041] : m8.ub[123] => 0.ub[0] +-setae eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] +-setae eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] +-setae eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] +-setae eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] +-setb eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] +-setb eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] +-setb eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] +-setb eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[0] +-setbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[0] +-setbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[1] +-setbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[1] +-setc eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] +-setc eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] +-setc eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] +-setc eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] +-sete eflags[0x040,0x000] : r8.ub[123] => 0.ub[0] +-sete eflags[0x040,0x040] : r8.ub[123] => 0.ub[1] +-sete eflags[0x040,0x000] : m8.ub[123] => 0.ub[0] +-sete eflags[0x040,0x040] : m8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] +-setg eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setg eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] +-setle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x000] : r8.ub[123] => 0.ub[0] +-setna eflags[0x041,0x001] : r8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x040] : r8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x041] : r8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x000] : m8.ub[123] => 0.ub[0] +-setna eflags[0x041,0x001] : m8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x040] : m8.ub[123] => 0.ub[1] +-setna eflags[0x041,0x041] : m8.ub[123] => 0.ub[1] +-setnae eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] +-setnae eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] +-setnae eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] +-setnae eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] +-setnb eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] +-setnb eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] +-setnb eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] +-setnb eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[1] +-setnbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[1] +-setnbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[0] +-setnbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[0] +-setnc eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] +-setnc eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] +-setnc eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] +-setnc eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] +-setne eflags[0x040,0x000] : r8.ub[123] => 0.ub[1] +-setne eflags[0x040,0x040] : r8.ub[123] => 0.ub[0] +-setne eflags[0x040,0x000] : m8.ub[123] => 0.ub[1] +-setne eflags[0x040,0x040] : m8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] +-setng eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setng eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] +-setnge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] +-setnge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] +-setnge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] +-setnge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setnl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setnl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setnl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setnl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] +-setnle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] +-setnle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] +-setno eflags[0x800,0x000] : r8.ub[123] => 0.ub[1] +-setno eflags[0x800,0x800] : r8.ub[123] => 0.ub[0] +-setno eflags[0x800,0x000] : m8.ub[123] => 0.ub[1] +-setno eflags[0x800,0x800] : m8.ub[123] => 0.ub[0] +-setnp eflags[0x004,0x000] : r8.ub[123] => 0.ub[1] +-setnp eflags[0x004,0x004] : r8.ub[123] => 0.ub[0] +-setnp eflags[0x004,0x000] : m8.ub[123] => 0.ub[1] +-setnp eflags[0x004,0x004] : m8.ub[123] => 0.ub[0] +-setns eflags[0x080,0x000] : r8.ub[123] => 0.ub[1] +-setns eflags[0x080,0x080] : r8.ub[123] => 0.ub[0] +-setns eflags[0x080,0x000] : m8.ub[123] => 0.ub[1] +-setns eflags[0x080,0x080] : m8.ub[123] => 0.ub[0] +-setnz eflags[0x040,0x000] : r8.ub[123] => 0.ub[1] +-setnz eflags[0x040,0x040] : r8.ub[123] => 0.ub[0] +-setnz eflags[0x040,0x000] : m8.ub[123] => 0.ub[1] +-setnz eflags[0x040,0x040] : m8.ub[123] => 0.ub[0] +-seto eflags[0x800,0x000] : r8.ub[123] => 0.ub[0] +-seto eflags[0x800,0x800] : r8.ub[123] => 0.ub[1] +-seto eflags[0x800,0x000] : m8.ub[123] => 0.ub[0] +-seto eflags[0x800,0x800] : m8.ub[123] => 0.ub[1] +-setp eflags[0x004,0x000] : r8.ub[123] => 0.ub[0] +-setp eflags[0x004,0x004] : r8.ub[123] => 0.ub[1] +-setp eflags[0x004,0x000] : m8.ub[123] => 0.ub[0] +-setp eflags[0x004,0x004] : m8.ub[123] => 0.ub[1] +-sets eflags[0x080,0x000] : r8.ub[123] => 0.ub[0] +-sets eflags[0x080,0x080] : r8.ub[123] => 0.ub[1] +-sets eflags[0x080,0x000] : m8.ub[123] => 0.ub[0] +-sets eflags[0x080,0x080] : m8.ub[123] => 0.ub[1] +-setz eflags[0x040,0x000] : r8.ub[123] => 0.ub[0] +-setz eflags[0x040,0x040] : r8.ub[123] => 0.ub[1] +-setz eflags[0x040,0x000] : m8.ub[123] => 0.ub[0] +-setz eflags[0x040,0x040] : m8.ub[123] => 0.ub[1] ++###sbbb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] ++###sbbb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] ++sbbb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22] ++sbbb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21] ++sbbb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22] ++sbbb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21] ++sbbb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22] ++sbbb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21] ++###sbbb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22] ++###sbbb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21] ++###sbbb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] ++###sbbb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] ++sbbw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444] ++sbbw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443] ++###sbbw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] ++###sbbw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443] ++###sbbw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444] ++###sbbw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443] ++sbbw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444] ++sbbw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443] ++sbbl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309] ++sbbl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308] ++###sbbl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] ++###sbbl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] ++###sbbl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643] ++###sbbl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642] ++sbbl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] ++sbbl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] ++sbbq rflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630] ++sbbq rflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629] ++###sbbq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964] ++###sbbq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963] ++sbbq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964] ++sbbq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963] ++sbbq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964] ++sbbq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963] ++sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] ++sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] ++###sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174] ++###sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173] ++sbbq rflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] ++sbbq rflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173] ++seta rflags[0x041,0x000] : r8.ub[123] => 0.ub[1] ++seta rflags[0x041,0x001] : r8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x040] : r8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x041] : r8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x000] : m8.ub[123] => 0.ub[1] ++seta rflags[0x041,0x001] : m8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x040] : m8.ub[123] => 0.ub[0] ++seta rflags[0x041,0x041] : m8.ub[123] => 0.ub[0] ++setae rflags[0x001,0x000] : r8.ub[123] => 0.ub[1] ++setae rflags[0x001,0x001] : r8.ub[123] => 0.ub[0] ++setae rflags[0x001,0x000] : m8.ub[123] => 0.ub[1] ++setae rflags[0x001,0x001] : m8.ub[123] => 0.ub[0] ++setb rflags[0x001,0x000] : r8.ub[123] => 0.ub[0] ++setb rflags[0x001,0x001] : r8.ub[123] => 0.ub[1] ++setb rflags[0x001,0x000] : m8.ub[123] => 0.ub[0] ++setb rflags[0x001,0x001] : m8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[0] ++setbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[0] ++setbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[1] ++setbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[1] ++setc rflags[0x001,0x000] : r8.ub[123] => 0.ub[0] ++setc rflags[0x001,0x001] : r8.ub[123] => 0.ub[1] ++setc rflags[0x001,0x000] : m8.ub[123] => 0.ub[0] ++setc rflags[0x001,0x001] : m8.ub[123] => 0.ub[1] ++sete rflags[0x040,0x000] : r8.ub[123] => 0.ub[0] ++sete rflags[0x040,0x040] : r8.ub[123] => 0.ub[1] ++sete rflags[0x040,0x000] : m8.ub[123] => 0.ub[0] ++sete rflags[0x040,0x040] : m8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] ++setg rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setg rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] ++setle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x000] : r8.ub[123] => 0.ub[0] ++setna rflags[0x041,0x001] : r8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x040] : r8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x041] : r8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x000] : m8.ub[123] => 0.ub[0] ++setna rflags[0x041,0x001] : m8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x040] : m8.ub[123] => 0.ub[1] ++setna rflags[0x041,0x041] : m8.ub[123] => 0.ub[1] ++setnae rflags[0x001,0x000] : r8.ub[123] => 0.ub[0] ++setnae rflags[0x001,0x001] : r8.ub[123] => 0.ub[1] ++setnae rflags[0x001,0x000] : m8.ub[123] => 0.ub[0] ++setnae rflags[0x001,0x001] : m8.ub[123] => 0.ub[1] ++setnb rflags[0x001,0x000] : r8.ub[123] => 0.ub[1] ++setnb rflags[0x001,0x001] : r8.ub[123] => 0.ub[0] ++setnb rflags[0x001,0x000] : m8.ub[123] => 0.ub[1] ++setnb rflags[0x001,0x001] : m8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[1] ++setnbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[1] ++setnbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[0] ++setnbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[0] ++setnc rflags[0x001,0x000] : r8.ub[123] => 0.ub[1] ++setnc rflags[0x001,0x001] : r8.ub[123] => 0.ub[0] ++setnc rflags[0x001,0x000] : m8.ub[123] => 0.ub[1] ++setnc rflags[0x001,0x001] : m8.ub[123] => 0.ub[0] ++setne rflags[0x040,0x000] : r8.ub[123] => 0.ub[1] ++setne rflags[0x040,0x040] : r8.ub[123] => 0.ub[0] ++setne rflags[0x040,0x000] : m8.ub[123] => 0.ub[1] ++setne rflags[0x040,0x040] : m8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] ++setng rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setng rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] ++setnge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] ++setnge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] ++setnge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] ++setnge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setnl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setnl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setnl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setnl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] ++setnle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] ++setnle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] ++setno rflags[0x800,0x000] : r8.ub[123] => 0.ub[1] ++setno rflags[0x800,0x800] : r8.ub[123] => 0.ub[0] ++setno rflags[0x800,0x000] : m8.ub[123] => 0.ub[1] ++setno rflags[0x800,0x800] : m8.ub[123] => 0.ub[0] ++setnp rflags[0x004,0x000] : r8.ub[123] => 0.ub[1] ++setnp rflags[0x004,0x004] : r8.ub[123] => 0.ub[0] ++setnp rflags[0x004,0x000] : m8.ub[123] => 0.ub[1] ++setnp rflags[0x004,0x004] : m8.ub[123] => 0.ub[0] ++setns rflags[0x080,0x000] : r8.ub[123] => 0.ub[1] ++setns rflags[0x080,0x080] : r8.ub[123] => 0.ub[0] ++setns rflags[0x080,0x000] : m8.ub[123] => 0.ub[1] ++setns rflags[0x080,0x080] : m8.ub[123] => 0.ub[0] ++setnz rflags[0x040,0x000] : r8.ub[123] => 0.ub[1] ++setnz rflags[0x040,0x040] : r8.ub[123] => 0.ub[0] ++setnz rflags[0x040,0x000] : m8.ub[123] => 0.ub[1] ++setnz rflags[0x040,0x040] : m8.ub[123] => 0.ub[0] ++seto rflags[0x800,0x000] : r8.ub[123] => 0.ub[0] ++seto rflags[0x800,0x800] : r8.ub[123] => 0.ub[1] ++seto rflags[0x800,0x000] : m8.ub[123] => 0.ub[0] ++seto rflags[0x800,0x800] : m8.ub[123] => 0.ub[1] ++setp rflags[0x004,0x000] : r8.ub[123] => 0.ub[0] ++setp rflags[0x004,0x004] : r8.ub[123] => 0.ub[1] ++setp rflags[0x004,0x000] : m8.ub[123] => 0.ub[0] ++setp rflags[0x004,0x004] : m8.ub[123] => 0.ub[1] ++sets rflags[0x080,0x000] : r8.ub[123] => 0.ub[0] ++sets rflags[0x080,0x080] : r8.ub[123] => 0.ub[1] ++sets rflags[0x080,0x000] : m8.ub[123] => 0.ub[0] ++sets rflags[0x080,0x080] : m8.ub[123] => 0.ub[1] ++setz rflags[0x040,0x000] : r8.ub[123] => 0.ub[0] ++setz rflags[0x040,0x040] : r8.ub[123] => 0.ub[1] ++setz rflags[0x040,0x000] : m8.ub[123] => 0.ub[0] ++setz rflags[0x040,0x040] : m8.ub[123] => 0.ub[1] + shlb r8.ub[0xca] => 0.ub[0x94] + shlb m8.ub[0xca] => 0.ub[0x94] + shlb imm8[2] r8.ub[0xca] => 1.ub[0x28] +@@ -1202,10 +1202,10 @@ shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0x7 + shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0x7fff80007f807865] + shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00] + shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00] +-###stc eflags[0x001,0x000] : => eflags[0x001,0x001] +-###stc eflags[0x001,0x001] : => eflags[0x001,0x001] +-std eflags[0x400,0x000] : => eflags[0x400,0x400] +-std eflags[0x400,0x400] : => eflags[0x400,0x400] ++###stc rflags[0x001,0x000] : => rflags[0x001,0x001] ++###stc rflags[0x001,0x001] : => rflags[0x001,0x001] ++std rflags[0x400,0x000] : => rflags[0x400,0x400] ++std rflags[0x400,0x400] : => rflags[0x400,0x400] + subb imm8[12] al.ub[34] => 1.ub[22] + subb imm8[12] bl.ub[34] => 1.ub[22] + subb imm8[12] m8.ub[34] => 1.ub[22] +@@ -1233,106 +1233,106 @@ subq imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964] + subq r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] + subq r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174] + subq m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174] +-testb imm8[0x1a] al.ub[0x1a] => eflags[0x8c5,0x000] +-testb imm8[0x5a] al.ub[0x5a] => eflags[0x8c5,0x004] +-testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044] +-testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080] +-testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084] +-testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000] +-testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004] +-testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044] +-testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080] +-testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084] +-testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000] +-testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004] +-testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044] +-testb imm8[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080] +-testb imm8[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084] +-testb r8.ub[0x1a] r8.ub[0x1a] => eflags[0x8c5,0x000] +-testb r8.ub[0x5a] r8.ub[0x5a] => eflags[0x8c5,0x004] +-testb r8.ub[0x1a] r8.ub[0xa1] => eflags[0x8c5,0x044] +-testb r8.ub[0xa1] r8.ub[0xa1] => eflags[0x8c5,0x080] +-testb r8.ub[0xa5] r8.ub[0xa5] => eflags[0x8c5,0x084] +-testb r8.ub[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000] +-testb r8.ub[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004] +-testb r8.ub[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044] +-testb r8.ub[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080] +-testb r8.ub[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084] +-testw imm16[0x1a1a] ax.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw imm16[0x5a5a] ax.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw imm16[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw imm16[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw r16.uw[0x1a1a] r16.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw r16.uw[0x5a5a] r16.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw r16.uw[0x1a1a] r16.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw r16.uw[0xa1a1] r16.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw r16.uw[0xa5a5] r16.uw[0xa5a5] => eflags[0x8c5,0x084] +-testw r16.uw[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000] +-testw r16.uw[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004] +-testw r16.uw[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044] +-testw r16.uw[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080] +-testw r16.uw[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084] +-testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] +-testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] +-testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080] +-testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084] +-testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080] +-testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084] +-testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => eflags[0x8c5,0x000] +-testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => eflags[0x8c5,0x004] +-testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => eflags[0x8c5,0x044] +-testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080] +-testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000] +-testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044] +-testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080] +-testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000] +-testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004] +-testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044] +-testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080] +-testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084] ++testb imm8[0x1a] al.ub[0x1a] => rflags[0x8c5,0x000] ++testb imm8[0x5a] al.ub[0x5a] => rflags[0x8c5,0x004] ++testb imm8[0x1a] al.ub[0xa1] => rflags[0x8c5,0x044] ++testb imm8[0xa1] al.ub[0xa1] => rflags[0x8c5,0x080] ++testb imm8[0xa5] al.ub[0xa5] => rflags[0x8c5,0x084] ++testb imm8[0x1a] bl.ub[0x1a] => rflags[0x8c5,0x000] ++testb imm8[0x5a] bl.ub[0x5a] => rflags[0x8c5,0x004] ++testb imm8[0x1a] bl.ub[0xa1] => rflags[0x8c5,0x044] ++testb imm8[0xa1] bl.ub[0xa1] => rflags[0x8c5,0x080] ++testb imm8[0xa5] bl.ub[0xa5] => rflags[0x8c5,0x084] ++testb imm8[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000] ++testb imm8[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004] ++testb imm8[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044] ++testb imm8[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080] ++testb imm8[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084] ++testb r8.ub[0x1a] r8.ub[0x1a] => rflags[0x8c5,0x000] ++testb r8.ub[0x5a] r8.ub[0x5a] => rflags[0x8c5,0x004] ++testb r8.ub[0x1a] r8.ub[0xa1] => rflags[0x8c5,0x044] ++testb r8.ub[0xa1] r8.ub[0xa1] => rflags[0x8c5,0x080] ++testb r8.ub[0xa5] r8.ub[0xa5] => rflags[0x8c5,0x084] ++testb r8.ub[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000] ++testb r8.ub[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004] ++testb r8.ub[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044] ++testb r8.ub[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080] ++testb r8.ub[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084] ++testw imm16[0x1a1a] ax.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw imm16[0x5a5a] ax.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw imm16[0x1a1a] ax.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw imm16[0xa1a1] ax.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw imm16[0xa5a5] ax.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw imm16[0x1a1a] bx.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw imm16[0x5a5a] bx.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw imm16[0x1a1a] bx.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw imm16[0xa1a1] bx.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw imm16[0xa5a5] bx.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw imm16[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw imm16[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw imm16[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw imm16[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw imm16[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw r16.uw[0x1a1a] r16.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw r16.uw[0x5a5a] r16.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw r16.uw[0x1a1a] r16.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw r16.uw[0xa1a1] r16.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw r16.uw[0xa5a5] r16.uw[0xa5a5] => rflags[0x8c5,0x084] ++testw r16.uw[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000] ++testw r16.uw[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004] ++testw r16.uw[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044] ++testw r16.uw[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080] ++testw r16.uw[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084] ++testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080] ++testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084] ++testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080] ++testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084] ++testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080] ++testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084] ++testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => rflags[0x8c5,0x000] ++testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => rflags[0x8c5,0x004] ++testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => rflags[0x8c5,0x044] ++testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080] ++testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000] ++testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044] ++testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080] ++testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000] ++testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004] ++testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044] ++testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080] ++testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084] + ###xaddb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[46] + ###xaddb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[46] + ###xaddw r16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[6912] +diff --git a/none/tests/amd64/insn_fpu.def b/none/tests/amd64/insn_fpu.def +index 590f584..525fd1b 100644 +--- a/none/tests/amd64/insn_fpu.def ++++ b/none/tests/amd64/insn_fpu.def +@@ -70,30 +70,30 @@ fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.43 + fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000] + fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[7654321.1234567] fpusw[0x4700,0x0100] + fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[7654321.1234567] fpusw[0x4700,0x4000] +-fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00] +-fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01] +-fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40] +-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00] +-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01] +-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40] +-fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00] +-fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01] +-fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40] +-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00] +-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01] +-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40] +-fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00] +-fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01] +-fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40] +-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00] +-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01] +-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40] +-fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00] +-fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01] +-fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40] +-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00] +-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01] +-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40] ++fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00] ++fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01] ++fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40] ++fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00] ++fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01] ++fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40] ++fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00] ++fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01] ++fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40] ++fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00] ++fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01] ++fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40] ++fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00] ++fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01] ++fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40] ++fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00] ++fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01] ++fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40] ++fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00] ++fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01] ++fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40] ++fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00] ++fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01] ++fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40] + fchs st0.ps[1234.5678] : => st0.ps[-1234.5678] + fchs st0.ps[-1234.5678] : => st0.ps[1234.5678] + fchs st0.pd[12345678.87654321] : => st0.pd[-12345678.87654321] +diff --git a/none/tests/amd64/insn_sse.def b/none/tests/amd64/insn_sse.def +index a9e92a0..277a062 100644 +--- a/none/tests/amd64/insn_sse.def ++++ b/none/tests/amd64/insn_sse.def +@@ -38,12 +38,12 @@ cmpordps xmm.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,23 + cmpordps m128.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,234.5679,234.5677] => 1.ud[0xffffffff,0xffffffff,0xffffffff,0xffffffff] + cmpordss xmm.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5679,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0] + cmpordss m128.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5676,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0] +-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] +-comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] ++comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] ++comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] + cvtpi2ps mm.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4] + cvtpi2ps m64.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4] + cvtps2pi xmm.ps[12.34,56.78,1.11,2.22] mm.sd[1,2] => 1.sd[12,57] +@@ -140,12 +140,12 @@ subps xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66, + subps m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,-23.77,-21.21,-76.65] + subss xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0] + subss m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0] +-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000] +-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001] +-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] +-ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040] ++ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000] ++ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001] ++ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] ++ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040] + unpckhps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65] + unpckhps m128.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65] + unpcklps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[11.22,12.34,33.44,56.78] +diff --git a/none/tests/amd64/insn_sse2.def b/none/tests/amd64/insn_sse2.def +index 3cbdd41..7e0890e 100644 +--- a/none/tests/amd64/insn_sse2.def ++++ b/none/tests/amd64/insn_sse2.def +@@ -38,12 +38,12 @@ cmpnlesd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff, + cmpnlesd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0x0000000000000000,0] + cmpordsd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff,0] + cmpordsd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0xffffffffffffffff,0] +-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] +-comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] ++comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] ++comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] + cvtdq2pd xmm.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0] + cvtdq2pd m128.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0] + cvtdq2ps xmm.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0] +@@ -329,12 +329,12 @@ subpd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4 + subpd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4321] + subsd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0] + subsd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0] +-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] +-ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000] +-ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001] +-ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040] ++ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] ++ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000] ++ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001] ++ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040] + unpckhpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321] + unpckhpd m128.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321] + unpcklpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[1122.3344,1234.5678] diff --git a/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch b/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch new file mode 100644 index 0000000..4b718e3 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-arm-index-hardwire.patch @@ -0,0 +1,86 @@ +diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c +index b8cc022..d54cae7 100644 +--- a/coregrind/m_redir.c ++++ b/coregrind/m_redir.c +@@ -1485,6 +1485,17 @@ void VG_(redir_initialise) ( void ) + (Addr)&VG_(arm_linux_REDIR_FOR_strcmp), + complain_about_stripped_glibc_ldso + ); ++ /* index */ ++ add_hardwired_spec( ++ "ld-linux.so.3", "index", ++ (Addr)&VG_(arm_linux_REDIR_FOR_index), ++ complain_about_stripped_glibc_ldso ++ ); ++ add_hardwired_spec( ++ "ld-linux-armhf.so.3", "index", ++ (Addr)&VG_(arm_linux_REDIR_FOR_index), ++ complain_about_stripped_glibc_ldso ++ ); + } + + # elif defined(VGP_arm64_linux) +diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S +index a532071..0488b54 100644 +--- a/coregrind/m_trampoline.S ++++ b/coregrind/m_trampoline.S +@@ -625,26 +625,26 @@ VG_(arm_linux_REDIR_FOR_strlen): + bx lr + UD2_4 + +-//.global VG_(arm_linux_REDIR_FOR_index) +-//VG_(arm_linux_REDIR_FOR_index): +-// ldrb r3, [r0, #0] @ zero_extendqisi2 +-// and r1, r1, #255 +-// cmp r3, r1 +-// @ lr needed for prologue +-// bne .L9 +-// bx lr +-//.L12: +-// ldrb r3, [r0, #1]! @ zero_extendqisi2 +-// cmp r3, r1 +-// beq .L11 +-//.L9: +-// cmp r3, #0 +-// bne .L12 +-// mov r0, #0 +-// bx lr +-//.L11: +-// bx lr +-// UD2_4 ++.global VG_(arm_linux_REDIR_FOR_index) ++VG_(arm_linux_REDIR_FOR_index): ++ ldrb r3, [r0, #0] @ zero_extendqisi2 ++ and r1, r1, #255 ++ cmp r3, r1 ++ @ lr needed for prologue ++ bne .L9 ++ bx lr ++.L12: ++ ldrb r3, [r0, #1]! @ zero_extendqisi2 ++ cmp r3, r1 ++ beq .L11 ++.L9: ++ cmp r3, #0 ++ bne .L12 ++ mov r0, #0 ++ bx lr ++.L11: ++ bx lr ++ UD2_4 + + .global VG_(arm_linux_REDIR_FOR_memcpy) + VG_(arm_linux_REDIR_FOR_memcpy): +diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h +index 3a9bafe..e29427d 100644 +--- a/coregrind/pub_core_trampoline.h ++++ b/coregrind/pub_core_trampoline.h +@@ -100,7 +100,7 @@ extern Addr VG_(ppctoc_magic_redirect_return_stub); + extern Addr VG_(arm_linux_SUBST_FOR_sigreturn); + extern Addr VG_(arm_linux_SUBST_FOR_rt_sigreturn); + extern UInt VG_(arm_linux_REDIR_FOR_strlen)( void* ); +-//extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int ); ++extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int ); + extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int ); + extern void* VG_(arm_linux_REDIR_FOR_strcmp)( void*, void* ); + #endif diff --git a/SOURCES/valgrind-3.13.0-arm64-hwcap.patch b/SOURCES/valgrind-3.13.0-arm64-hwcap.patch new file mode 100644 index 0000000..8f2a070 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-arm64-hwcap.patch @@ -0,0 +1,17 @@ +diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c +index 30e1f85..387beae 100644 +--- a/coregrind/m_initimg/initimg-linux.c ++++ b/coregrind/m_initimg/initimg-linux.c +@@ -703,6 +703,12 @@ Addr setup_client_stack( void* init_sp, + (and anything above) are not supported by Valgrind. */ + auxv->u.a_val &= VKI_HWCAP_S390_TE - 1; + } ++# elif defined(VGP_arm64_linux) ++ { ++ /* Linux 4.11 started pupulating this for arm64, but we ++ currently don't support any. */ ++ auxv->u.a_val = 0; ++ } + # endif + break; + # if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) diff --git a/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch b/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch new file mode 100644 index 0000000..4f9537a --- /dev/null +++ b/SOURCES/valgrind-3.13.0-disable-vgdb-child.patch @@ -0,0 +1,36 @@ +commit 59af5db9c15d8ea03c1521736fb1f107d66bce08 +Author: philippe +Date: Sun Jun 25 20:25:50 2017 +0000 + + After fork, vgdb activity is polled according to the nr of bbs done : + once the nr of bbs done reaches the next vgdb poll, a check for vgdb + activity is done. + This might lead to the activation of gdbserver after fork. + Such poll is however not expected, unless the children is + to be trace. + This spurious poll in the forked child can cause failures + depending on the nr of bbs done before the fork, and the + nr of bbs done between the fork and the exec. + + => disable vgdb poll in the child in the cleanup after fork + in the child, unless the children have to be traced. + + + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16454 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c +index 87fbce2..648d543 100644 +--- a/coregrind/m_gdbserver/m_gdbserver.c ++++ b/coregrind/m_gdbserver/m_gdbserver.c +@@ -646,6 +646,10 @@ static void gdbserver_cleanup_in_child_after_fork(ThreadId me) + + if (VG_(clo_trace_children)) { + VG_(gdbserver_prerun_action) (me); ++ } else { ++ /* After fork, if we do not trace the children, disable vgdb ++ poll to avoid gdbserver being called unexpectedly. */ ++ VG_(disable_vgdb_poll) (); + } + } + diff --git a/SOURCES/valgrind-3.13.0-epoll_pwait.patch b/SOURCES/valgrind-3.13.0-epoll_pwait.patch new file mode 100644 index 0000000..8a7516b --- /dev/null +++ b/SOURCES/valgrind-3.13.0-epoll_pwait.patch @@ -0,0 +1,68 @@ +commit 79865f0eed7cf0e0ad687ee0a59d59a1d505b514 +Author: mjw +Date: Sat Jun 17 13:49:22 2017 +0000 + + epoll_pwait can have a NULL sigmask. + + According to the epoll_pwait(2) man page: + + The sigmask argument may be specified as NULL, in which case + epoll_pwait() is equivalent to epoll_wait(). + + But doing that under valgrind gives: + + ==13887== Syscall param epoll_pwait(sigmask) points to unaddressable byte(s) + ==13887== at 0x4F2B940: epoll_pwait (epoll_pwait.c:43) + ==13887== by 0x400ADE: main (syscalls-2007.c:89) + ==13887== Address 0x0 is not stack'd, malloc'd or (recently) free'd + + This is because the sys_epoll_pwait wrapper has: + + if (ARG4) + PRE_MEM_READ( "epoll_pwait(sigmask)", ARG5, sizeof(vki_sigset_t) ); + + Which looks like a typo (ARG4 is timeout and ARG5 is sigmask). + + This shows up with newer glibc which translates an epoll_wait call into + an epoll_pwait call with NULL sigmask. + + Fix typo and add a testcase. + + https://bugs.kde.org/show_bug.cgi?id=381289 + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16451 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c +index 26e02fd..4120c1d 100644 +--- a/coregrind/m_syswrap/syswrap-linux.c ++++ b/coregrind/m_syswrap/syswrap-linux.c +@@ -1901,7 +1901,7 @@ PRE(sys_epoll_pwait) + int, maxevents, int, timeout, vki_sigset_t *, sigmask, + vki_size_t, sigsetsize); + PRE_MEM_WRITE( "epoll_pwait(events)", ARG2, sizeof(struct vki_epoll_event)*ARG3); +- if (ARG4) ++ if (ARG5) + PRE_MEM_READ( "epoll_pwait(sigmask)", ARG5, sizeof(vki_sigset_t) ); + } + POST(sys_epoll_pwait) +diff --git a/memcheck/tests/linux/syscalls-2007.c b/memcheck/tests/linux/syscalls-2007.c +index b61c6d5..5494623 100644 +--- a/memcheck/tests/linux/syscalls-2007.c ++++ b/memcheck/tests/linux/syscalls-2007.c +@@ -79,5 +79,16 @@ int main (void) + } + #endif + ++#if defined(HAVE_EPOLL_CREATE) && defined(HAVE_EPOLL_PWAIT) ++ { ++ int fd3; ++ struct epoll_event evs[10]; ++ ++ fd3 = epoll_create (10); ++ /* epoll_pwait can take a NULL sigmask. */ ++ epoll_pwait (fd3, evs, 10, 1, NULL); ++ } ++#endif ++ + return 0; + } diff --git a/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch b/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch new file mode 100644 index 0000000..f34da04 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-gdb-8-testfix.patch @@ -0,0 +1,183 @@ +commit 21788250c945713fa25c16f2683e1f9cd0bb6ccf +Author: philippe +Date: Sun Jun 25 12:40:53 2017 +0000 + + Fix some tests failure with GDB 8.0 + + At the beginning of a Valgrind gdbserver test, + 2 messages are produced when launching the command + target remote | vgdb + + A message output by vgdb: + relaying data between gdb and process + (this message is read by GDB from the vgdb pipe, and re-output + on stderr) + and a message produced by GDB: + Remote debugging using | ./vgdb + + GDB 8.0 changes the order in which the above messages are output. + This causes 2 tests to fail, as the 'relaying' line appears + then in a part of the output deleted by a filter script. + + To avoid this, change the filter scripts to always remove + this 'relaying line', which is not particularly interesting to check. + All the .exp files containining such a 'relaying' line are updated + accordingly. + + This has been tested with various gdb versions (7.5, 7.7, 7.12, 8.0) + on amd64 and/or ppc64. + + Thanks to Mark Wielaard, which helped to investigate this problem + by bisecting the GDB patches in GDB 8.0 causing this change of + behaviour. + + + + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16453 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/gdbserver_tests/filter_gdb b/gdbserver_tests/filter_gdb +index 7177720..ed78cfe 100755 +--- a/gdbserver_tests/filter_gdb ++++ b/gdbserver_tests/filter_gdb +@@ -72,7 +72,7 @@ sed -e '/Remote debugging using/,/vgdb launched process attached/d' + -e '/^Missing separate debuginfo/d' \ + -e '/\/_exit.c: No such file or directory/d' \ + -e '/^Try: zypper install -C/d' \ +- -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../' \ ++ -e '/relaying data between gdb and process/d' \ + -e 's/pid [0-9][0-9]*/pid ..../g' \ + -e 's/Thread [0-9][0-9]*/Thread ..../g' \ + -e '/\[Switching to Thread ....\]/d' \ +diff --git a/gdbserver_tests/filter_vgdb b/gdbserver_tests/filter_vgdb +index 2442ec5..f8028a3 100755 +--- a/gdbserver_tests/filter_vgdb ++++ b/gdbserver_tests/filter_vgdb +@@ -11,7 +11,7 @@ $dir/../tests/filter_addresses | + # pid + # gdb 7.2 sometimes tries to access address 0x0 (same as with standard gdbserver) + # filter a debian 6.0/ppc32 line +-sed -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../' \ ++sed -e '/relaying data between gdb and process/d' \ + -e 's/\(sending command .* to pid \)[0-9][0-9]*/\1..../' \ + -e '/Cannot access memory at address 0x......../d' \ + -e '/^[1-9][0-9]* \.\.\/sysdeps\/powerpc\/powerpc32\/dl-start\.S: No such file or directory\./d' | +diff --git a/gdbserver_tests/hginfo.stderrB.exp b/gdbserver_tests/hginfo.stderrB.exp +index df47f11..669ff92 100644 +--- a/gdbserver_tests/hginfo.stderrB.exp ++++ b/gdbserver_tests/hginfo.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Lock ga 0x........ { + Address 0x........ is 0 bytes inside data symbol "mx" +diff --git a/gdbserver_tests/mcblocklistsearch.stderrB.exp b/gdbserver_tests/mcblocklistsearch.stderrB.exp +index 312d776..1313321 100644 +--- a/gdbserver_tests/mcblocklistsearch.stderrB.exp ++++ b/gdbserver_tests/mcblocklistsearch.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Breakpoint 1 at 0x........: file leak-tree.c, line 42. + Breakpoint 2 at 0x........: file leak-tree.c, line 67. +diff --git a/gdbserver_tests/mcbreak.stderrB.exp b/gdbserver_tests/mcbreak.stderrB.exp +index 65281d2..0f051d1 100644 +--- a/gdbserver_tests/mcbreak.stderrB.exp ++++ b/gdbserver_tests/mcbreak.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + vgdb-error value changed from 999999 to 0 + n_errs_found 1 n_errs_shown 1 (vgdb-error 0) +diff --git a/gdbserver_tests/mcclean_after_fork.stderrB.exp b/gdbserver_tests/mcclean_after_fork.stderrB.exp +index 995b42f..e812b8e 100644 +--- a/gdbserver_tests/mcclean_after_fork.stderrB.exp ++++ b/gdbserver_tests/mcclean_after_fork.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + monitor command request to kill this process + Remote connection closed +diff --git a/gdbserver_tests/mcinfcallWSRU.stderrB.exp b/gdbserver_tests/mcinfcallWSRU.stderrB.exp +index 7789123..a2f2b87 100644 +--- a/gdbserver_tests/mcinfcallWSRU.stderrB.exp ++++ b/gdbserver_tests/mcinfcallWSRU.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Breakpoint 1 at 0x........: file sleepers.c, line 74. + Continuing. +diff --git a/gdbserver_tests/mcleak.stderrB.exp b/gdbserver_tests/mcleak.stderrB.exp +index 7782119..7ed3920 100644 +--- a/gdbserver_tests/mcleak.stderrB.exp ++++ b/gdbserver_tests/mcleak.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + 10 bytes in 1 blocks are still reachable in loss record ... of ... + at 0x........: malloc (vg_replace_malloc.c:...) +diff --git a/gdbserver_tests/mcmain_pic.stderrB.exp b/gdbserver_tests/mcmain_pic.stderrB.exp +index c90e1fa..53ec0ce 100644 +--- a/gdbserver_tests/mcmain_pic.stderrB.exp ++++ b/gdbserver_tests/mcmain_pic.stderrB.exp +@@ -1,2 +1 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 +diff --git a/gdbserver_tests/mcvabits.stderrB.exp b/gdbserver_tests/mcvabits.stderrB.exp +index bdabb1e..f9ced7a 100644 +--- a/gdbserver_tests/mcvabits.stderrB.exp ++++ b/gdbserver_tests/mcvabits.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + Address 0x........ len 10 addressable + Address 0x........ is 0 bytes inside data symbol "undefined" +diff --git a/gdbserver_tests/mssnapshot.stderrB.exp b/gdbserver_tests/mssnapshot.stderrB.exp +index 8bee8fc..e419ce6 100644 +--- a/gdbserver_tests/mssnapshot.stderrB.exp ++++ b/gdbserver_tests/mssnapshot.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + general valgrind monitor commands: + help [debug] : monitor command help. With debug: + debugging commands +diff --git a/gdbserver_tests/nlgone_abrt.stderrB.exp b/gdbserver_tests/nlgone_abrt.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlgone_abrt.stderrB.exp ++++ b/gdbserver_tests/nlgone_abrt.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlgone_exit.stderrB.exp b/gdbserver_tests/nlgone_exit.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlgone_exit.stderrB.exp ++++ b/gdbserver_tests/nlgone_exit.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlgone_return.stderrB.exp b/gdbserver_tests/nlgone_return.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlgone_return.stderrB.exp ++++ b/gdbserver_tests/nlgone_return.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlpasssigalrm.stderrB.exp b/gdbserver_tests/nlpasssigalrm.stderrB.exp +index c90e1fa..53ec0ce 100644 +--- a/gdbserver_tests/nlpasssigalrm.stderrB.exp ++++ b/gdbserver_tests/nlpasssigalrm.stderrB.exp +@@ -1,2 +1 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 +diff --git a/gdbserver_tests/nlself_invalidate.stderrB.exp b/gdbserver_tests/nlself_invalidate.stderrB.exp +index c8b2024..e69de29 100644 +--- a/gdbserver_tests/nlself_invalidate.stderrB.exp ++++ b/gdbserver_tests/nlself_invalidate.stderrB.exp +@@ -1 +0,0 @@ +-relaying data between gdb and process .... +diff --git a/gdbserver_tests/nlsigvgdb.stderrB.exp b/gdbserver_tests/nlsigvgdb.stderrB.exp +index 672fea5..ed5bb61 100644 +--- a/gdbserver_tests/nlsigvgdb.stderrB.exp ++++ b/gdbserver_tests/nlsigvgdb.stderrB.exp +@@ -1,4 +1,3 @@ +-relaying data between gdb and process .... + vgdb-error value changed from 0 to 999999 + gdbserver: continuing in 5000 ms ... + gdbserver: continuing after wait ... diff --git a/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch b/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch new file mode 100644 index 0000000..8356773 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-check-no-vsx.patch @@ -0,0 +1,161 @@ +commit 326d53c8378984c50f29bd124d3f2b4a1242306c +Author: mjw +Date: Fri Jun 16 09:33:35 2017 +0000 + + ppc64 doesn't compile test_isa_2_06_partx.c without VSX support + + The #ifdef HAS_VSX guard is wrongly placed. It makes the standard + include headers not be used. Causing a build failure. Fix by moving + the #ifdef HAS_VSX after the standard includes. + + https://bugs.kde.org/show_bug.cgi?id=381272 + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16450 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/none/tests/ppc32/test_isa_2_06_part1.c b/none/tests/ppc32/test_isa_2_06_part1.c +index 7cd4930..7a14c6d 100644 +--- a/none/tests/ppc32/test_isa_2_06_part1.c ++++ b/none/tests/ppc32/test_isa_2_06_part1.c +@@ -20,13 +20,14 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include ++ ++#ifdef HAS_VSX ++ + #include + + #ifndef __powerpc64__ +diff --git a/none/tests/ppc32/test_isa_2_06_part2.c b/none/tests/ppc32/test_isa_2_06_part2.c +index c7bf4fe..2ee7b53 100644 +--- a/none/tests/ppc32/test_isa_2_06_part2.c ++++ b/none/tests/ppc32/test_isa_2_06_part2.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else +diff --git a/none/tests/ppc32/test_isa_2_06_part3.c b/none/tests/ppc32/test_isa_2_06_part3.c +index 8c74c09..5ebc1a5 100644 +--- a/none/tests/ppc32/test_isa_2_06_part3.c ++++ b/none/tests/ppc32/test_isa_2_06_part3.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else + +diff --git a/none/tests/ppc64/test_isa_2_06_part1.c b/none/tests/ppc64/test_isa_2_06_part1.c +index 7cd4930..7a14c6d 100644 +--- a/none/tests/ppc64/test_isa_2_06_part1.c ++++ b/none/tests/ppc64/test_isa_2_06_part1.c +@@ -20,13 +20,14 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include ++ ++#ifdef HAS_VSX ++ + #include + + #ifndef __powerpc64__ +diff --git a/none/tests/ppc64/test_isa_2_06_part2.c b/none/tests/ppc64/test_isa_2_06_part2.c +index c7bf4fe..2ee7b53 100644 +--- a/none/tests/ppc64/test_isa_2_06_part2.c ++++ b/none/tests/ppc64/test_isa_2_06_part2.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else +diff --git a/none/tests/ppc64/test_isa_2_06_part3.c b/none/tests/ppc64/test_isa_2_06_part3.c +index 8c74c09..5ebc1a5 100644 +--- a/none/tests/ppc64/test_isa_2_06_part3.c ++++ b/none/tests/ppc64/test_isa_2_06_part3.c +@@ -20,17 +20,18 @@ + The GNU General Public License is contained in the file COPYING. + */ + +-#ifdef HAS_VSX +- + #include + #include + #include + #include + #include +-#include + #include + #include // getopt + ++#ifdef HAS_VSX ++ ++#include ++ + #ifndef __powerpc64__ + typedef uint32_t HWord_t; + #else diff --git a/SOURCES/valgrind-3.13.0-ppc64-diag.patch b/SOURCES/valgrind-3.13.0-ppc64-diag.patch new file mode 100644 index 0000000..eba0acb --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-diag.patch @@ -0,0 +1,109 @@ +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index e16e837..a8d4926 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -29356,62 +29356,70 @@ DisResult disInstr_PPC_WRK ( + + decode_noF: + vassert(!allow_F); +- vex_printf("disInstr(ppc): found the Floating Point instruction 0x%x that\n" +- "can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports Floating Point instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Floating Point instruction 0x%x that\n" ++ "can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports Floating Point instructions.\n", ++ theInstr); + goto not_supported; + decode_noV: + vassert(!allow_V); +- vex_printf("disInstr(ppc): found an AltiVec or an e500 instruction 0x%x\n" +- "that can't be handled by Valgrind. If this instruction is an\n" +- "Altivec instruction, Valgrind must be run on a host that supports" +- "AltiVec instructions. If the application was compiled for e500, then\n" +- "unfortunately Valgrind does not yet support e500 instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found an AltiVec or an e500 instruction 0x%x\n" ++ "that can't be handled by Valgrind. If this instruction is an\n" ++ "Altivec instruction, Valgrind must be run on a host that supports" ++ "AltiVec instructions. If the application was compiled for e500, then\n" ++ "unfortunately Valgrind does not yet support e500 instructions.\n", ++ theInstr); + goto not_supported; + decode_noVX: + vassert(!allow_VX); +- vex_printf("disInstr(ppc): found the instruction 0x%x that is defined in the\n" +- "Power ISA 2.06 ABI but can't be handled by Valgrind on this host.\n" +- "This instruction \nrequires a host that supports the ISA 2.06 ABI.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the instruction 0x%x that is defined in the\n" ++ "Power ISA 2.06 ABI but can't be handled by Valgrind on this host.\n" ++ "This instruction \nrequires a host that supports the ISA 2.06 ABI.\n", ++ theInstr); + goto not_supported; + decode_noFX: + vassert(!allow_FX); +- vex_printf("disInstr(ppc): found the General Purpose-Optional instruction 0x%x\n" +- "that can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports the General Purpose-Optional instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the General Purpose-Optional instruction 0x%x\n" ++ "that can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports the General Purpose-Optional instructions.\n", ++ theInstr); + goto not_supported; + decode_noGX: + vassert(!allow_GX); +- vex_printf("disInstr(ppc): found the Graphics-Optional instruction 0x%x\n" +- "that can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports the Graphic-Optional instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Graphics-Optional instruction 0x%x\n" ++ "that can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports the Graphic-Optional instructions.\n", ++ theInstr); + goto not_supported; + decode_noDFP: + vassert(!allow_DFP); +- vex_printf("disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x\n" +- "that can't be handled by Valgrind on this host. This instruction\n" +- "requires a host that supports DFP instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x\n" ++ "that can't be handled by Valgrind on this host. This instruction\n" ++ "requires a host that supports DFP instructions.\n", ++ theInstr); + goto not_supported; + decode_noP8: + vassert(!allow_isa_2_07); +- vex_printf("disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled\n" +- "by Valgrind on this host. This instruction requires a host that\n" +- "supports Power 8 instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled\n" ++ "by Valgrind on this host. This instruction requires a host that\n" ++ "supports Power 8 instructions.\n", ++ theInstr); + goto not_supported; + + decode_noP9: + vassert(!allow_isa_3_0); +- vex_printf("disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled\n" +- "by Valgrind on this host. This instruction requires a host that\n" +- "supports Power 9 instructions.\n", +- theInstr); ++ if (sigill_diag) ++ vex_printf("disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled\n" ++ "by Valgrind on this host. This instruction requires a host that\n" ++ "supports Power 9 instructions.\n", ++ theInstr); + goto not_supported; + + decode_failure: diff --git a/SOURCES/valgrind-3.13.0-ppc64-timebase.patch b/SOURCES/valgrind-3.13.0-ppc64-timebase.patch new file mode 100644 index 0000000..d862b81 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-timebase.patch @@ -0,0 +1,99 @@ +commit 6a55b1e82ccda3f0d663d2cc89eb543ae2d096bf +Author: Carl Love +Date: Tue Oct 31 13:45:28 2017 -0500 + + Fix access to time base register to return 64-bits. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index f63146e7e..4ec37f5f9 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -9419,26 +9419,60 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + putIReg( rD_addr, getGST( PPC_GST_SPRG3_RO ) ); + break; + +- /* Even a lowly PPC7400 can run the associated helper, so no +- obvious need for feature testing at this point. */ +- case 268 /* 0x10C */: +- case 269 /* 0x10D */: { +- UInt arg = SPR==268 ? 0 : 1; +- IRTemp val = newTemp(Ity_I32); +- IRExpr** args = mkIRExprVec_1( mkU32(arg) ); ++ case 268 /* 0x10C TB - 64 bit time base register */: ++ { ++ IRTemp val = newTemp(Ity_I64); ++ IRExpr** args = mkIRExprVec_0(); + IRDirty* d = unsafeIRDirty_1_N( +- val, +- 0/*regparms*/, +- "ppc32g_dirtyhelper_MFSPR_268_269", +- fnptr_to_fnentry +- (vbi, &ppc32g_dirtyhelper_MFSPR_268_269), +- args +- ); ++ val, ++ 0/*regparms*/, ++ "ppcg_dirtyhelper_MFTB", ++ fnptr_to_fnentry(vbi, ++ &ppcg_dirtyhelper_MFTB), ++ args ); ++ /* execute the dirty call, dumping the result in val. */ ++ stmt( IRStmt_Dirty(d) ); ++ putIReg( rD_addr, (mode64) ? mkexpr(val) : ++ unop(Iop_64to32, mkexpr(val)) ); ++ ++ break; ++ } ++ case 269 /* 0x10D TBU - upper 32-bits of time base register */: ++ { ++ DIP("mfspr r%u,%u", rD_addr, SPR); ++ IRTemp val = newTemp(Ity_I64); ++ IRExpr** args = mkIRExprVec_0(); ++ IRDirty* d = unsafeIRDirty_1_N( ++ val, ++ 0/*regparms*/, ++ "ppcg_dirtyhelper_MFTB", ++ fnptr_to_fnentry(vbi, ++ &ppcg_dirtyhelper_MFTB), ++ args ); + /* execute the dirty call, dumping the result in val. */ + stmt( IRStmt_Dirty(d) ); + putIReg( rD_addr, +- mkWidenFrom32(ty, mkexpr(val), False/*unsigned*/) ); ++ mkWidenFrom32(ty, unop(Iop_64HIto32, mkexpr(val)), ++ /* Signed */False) ); ++ break; ++ } ++ case 284 /* 0x1 TBL - lower 32-bits of time base register */: ++ { + DIP("mfspr r%u,%u", rD_addr, SPR); ++ IRTemp val = newTemp(Ity_I64); ++ IRExpr** args = mkIRExprVec_0(); ++ IRDirty* d = unsafeIRDirty_1_N( ++ val, ++ 0/*regparms*/, ++ "ppcg_dirtyhelper_MFTB", ++ fnptr_to_fnentry(vbi, ++ &ppcg_dirtyhelper_MFTB), ++ args ); ++ /* execute the dirty call, dumping the result in val. */ ++ stmt( IRStmt_Dirty(d) ); ++ putIReg( rD_addr, ++ mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(val)), ++ /* Signed */False) ); + break; + } + +@@ -9493,6 +9527,12 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + putIReg( rD_addr, (mode64) ? mkexpr(val) : + unop(Iop_64to32, mkexpr(val)) ); + break; ++ case 284: ++ DIP("mftbl r%u", rD_addr); ++ putIReg( rD_addr, ++ mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(val)), ++ /* Signed */False) ); ++ break; + default: + return False; /* illegal instruction */ + } diff --git a/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch b/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch new file mode 100644 index 0000000..bc41de6 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ppc64-vex-fixes.patch @@ -0,0 +1,5703 @@ +commit 7fce2c5269f82a7d063c87335a25de84fc9acc64 +Author: Carl Love +Date: Tue Oct 3 12:03:22 2017 -0500 + + PPC64, Add support for the Data Stream Control Register (DSCR) + +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index 8230d65..34adf62 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -921,6 +921,7 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state ) + vex_state->guest_TEXASR = 0; + vex_state->guest_PPR = 0x4ULL << 50; // medium priority + vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with ++ vex_state->guest_DSCR = 0; + } + + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index a8d4926..2467f70 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -296,6 +296,7 @@ static Bool OV32_CA32_supported = False; + #define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR) + #define OFFB_PPR offsetofPPCGuestState(guest_PPR) + #define OFFB_PSPB offsetofPPCGuestState(guest_PSPB) ++#define OFFB_DSCR offsetofPPCGuestState(guest_DSCR) + + + /*------------------------------------------------------------*/ +@@ -459,6 +460,7 @@ typedef enum { + * automatically decrement. Could be added later if + * needed. + */ ++ PPC_GST_DSCR, // Data Stream Control Register + PPC_GST_MAX + } PPC_GST; + +@@ -3068,6 +3070,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg ) + case PPC_GST_PSPB: + return IRExpr_Get( OFFB_PSPB, ty ); + ++ case PPC_GST_DSCR: ++ return IRExpr_Get( OFFB_DSCR, ty ); ++ + default: + vex_printf("getGST(ppc): reg = %u", reg); + vpanic("getGST(ppc)"); +@@ -3344,6 +3349,11 @@ static void putGST ( PPC_GST reg, IRExpr* src ) + mkU64( 0x1C000000000000) ) ) ); + break; + } ++ case PPC_GST_DSCR: ++ vassert( ty_src == Ity_I64 ); ++ stmt( IRStmt_Put( OFFB_DSCR, src ) ); ++ break; ++ + default: + vex_printf("putGST(ppc): reg = %u", reg); + vpanic("putGST(ppc)"); +@@ -9407,6 +9417,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ), + /* Signed */False) ); + break; ++ case 0x3: // 131 ++ DIP("mfspr r%u (DSCR)\n", rD_addr); ++ putIReg( rD_addr, getGST( PPC_GST_DSCR) ); ++ break; + case 0x8: + DIP("mflr r%u\n", rD_addr); + putIReg( rD_addr, getGST( PPC_GST_LR ) ); +@@ -9575,6 +9589,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) + DIP("mtxer r%u\n", rS_addr); + putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) ); + break; ++ case 0x3: ++ DIP("mtspr r%u (DSCR)\n", rS_addr); ++ putGST( PPC_GST_DSCR, mkexpr(rS) ); ++ break; + case 0x8: + DIP("mtlr r%u\n", rS_addr); + putGST( PPC_GST_LR, mkexpr(rS) ); +diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h +index 816ef5a..bb48ac5 100644 +--- a/VEX/pub/libvex_guest_ppc32.h ++++ b/VEX/pub/libvex_guest_ppc32.h +@@ -252,8 +252,8 @@ typedef + /* 1388 */ ULong guest_PPR; // Program Priority register + /* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper + /* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register ++ /* 1404 */ ULong guest_DSCR; // Data Stream Control register + /* Padding to make it have an 16-aligned size */ +- /* 1404 */ UInt padding2; + /* 1408 */ UInt padding3; + /* 1412 */ UInt padding4; + } +diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h +index 02c4020..8c01fa6 100644 +--- a/VEX/pub/libvex_guest_ppc64.h ++++ b/VEX/pub/libvex_guest_ppc64.h +@@ -292,11 +292,12 @@ typedef + /* 1686 */ ULong guest_PPR; // Program Priority register + /* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper + /* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register ++ /* 1702 */ ULong guest_DSCR; // Data Stream Control register + + /* Padding to make it have an 16-aligned size */ +- /* 1698 */ UInt padding1; +- /* 1702 UInt padding2; */ +- /* 1706 UInt padding3; */ ++ /* 1710 */ UInt padding1; ++ /* 1714 */ UInt padding2; ++ /* 1718 */ UInt padding3; + + } + VexGuestPPC64State; +diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c +index 3ff7c44..1d57e0c 100644 +--- a/memcheck/mc_machine.c ++++ b/memcheck/mc_machine.c +@@ -194,6 +194,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) + if (o == GOF(TFIAR) && sz == 8) return -1; + if (o == GOF(PPR) && sz == 8) return -1; + if (o == GOF(PSPB) && sz == 8) return -1; ++ if (o == GOF(DSCR) && sz == 8) return -1; + + // With ISA 2.06, the "Vector-Scalar Floating-point" category + // provides facilities to support vector and scalar binary floating- +diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c +index a9a565b..892e503 100644 +--- a/memcheck/mc_main.c ++++ b/memcheck/mc_main.c +@@ -4468,7 +4468,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid, + static void mc_post_reg_write ( CorePart part, ThreadId tid, + PtrdiffT offset, SizeT size) + { +-# define MAX_REG_WRITE_SIZE 1728 ++# define MAX_REG_WRITE_SIZE 1744 + UChar area[MAX_REG_WRITE_SIZE]; + tl_assert(size <= MAX_REG_WRITE_SIZE); + VG_(memset)(area, V_BITS8_DEFINED, size); + +commit acdeb75d2a58f4f3910ddaf9b2bc2ec74378fa3a +Author: Carl Love +Date: Tue Oct 3 12:08:09 2017 -0500 + + PPC64, Replace body of generate_store_FPRF with C helper function. + + The function calculates the floating point condition code values + and stores them into the floating point condition code register. + The function is used by a number of instructions. The calculation + generates a lot of Iops as it much check the operatds for NaN, SNaN, + zero, dnorm, norm and infinity. The large number of Iops exhausts + temporary memory. + +diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h +index fe411f7..f3eb956 100644 +--- a/VEX/priv/guest_ppc_defs.h ++++ b/VEX/priv/guest_ppc_defs.h +@@ -156,6 +156,7 @@ extern ULong convert_to_zoned_helper( ULong src_hi, ULong src_low, + extern ULong convert_to_national_helper( ULong src, ULong return_upper ); + extern ULong convert_from_zoned_helper( ULong src_hi, ULong src_low ); + extern ULong convert_from_national_helper( ULong src_hi, ULong src_low ); ++extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src ); + + + /* --- DIRTY HELPERS --- */ +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index 34adf62..bf2d071 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -216,6 +216,110 @@ IRExpr* guest_ppc64_spechelper ( const HChar* function_name, + } + + ++/* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */ ++#define I16_EXP_MASK 0x7C00 ++#define I16_FRACTION_MASK 0x03FF ++#define I32_EXP_MASK 0x7F800000 ++#define I32_FRACTION_MASK 0x007FFFFF ++#define I64_EXP_MASK 0x7FF0000000000000ULL ++#define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL ++#define V128_EXP_MASK 0x7FFF000000000000ULL ++#define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL /* upper 64-bit fractional mask */ ++ ++ULong generate_C_FPCC_helper( ULong irType, ULong src_hi, ULong src ) ++{ ++ UInt NaN, inf, zero, norm, dnorm, pos; ++ UInt bit0, bit1, bit2, bit3; ++ UInt sign_bit = 0; ++ ULong exp_mask = 0, exp_part = 0, frac_part = 0; ++ ULong fpcc, c; ++ ++ if ( irType == Ity_I16 ) { ++ frac_part = I16_FRACTION_MASK & src; ++ exp_mask = I16_EXP_MASK; ++ exp_part = exp_mask & src; ++ sign_bit = src >> 15; ++ ++ } else if ( irType == Ity_I32 ) { ++ frac_part = I32_FRACTION_MASK & src; ++ exp_mask = I32_EXP_MASK; ++ exp_part = exp_mask & src; ++ sign_bit = src >> 31; ++ ++ } else if ( irType == Ity_I64 ) { ++ frac_part = I64_FRACTION_MASK & src; ++ exp_mask = I64_EXP_MASK; ++ exp_part = exp_mask & src; ++ sign_bit = src >> 63; ++ ++ } else if ( irType == Ity_F128 ) { ++ /* only care if the frac part is zero or non-zero */ ++ frac_part = (V128_FRACTION_MASK & src_hi) | src; ++ exp_mask = V128_EXP_MASK; ++ exp_part = exp_mask & src_hi; ++ sign_bit = src_hi >> 63; ++ } else { ++ vassert(0); // Unknown value of irType ++ } ++ ++ /* NaN: exponene is all ones, fractional part not zero */ ++ if ((exp_part == exp_mask) && (frac_part != 0)) ++ NaN = 1; ++ else ++ NaN = 0; ++ ++ /* inf: exponent all 1's, fraction part is zero */ ++ if ((exp_part == exp_mask) && (frac_part == 0)) ++ inf = 1; ++ else ++ inf = 0; ++ ++ /* zero: exponent is 0, fraction part is zero */ ++ if ((exp_part == 0) && (frac_part == 0)) ++ zero = 1; ++ else ++ zero = 0; ++ ++ /* norm: exponent is not 0, exponent is not all 1's */ ++ if ((exp_part != 0) && (exp_part != exp_mask)) ++ norm = 1; ++ else ++ norm = 0; ++ ++ /* dnorm: exponent is all 0's, fraction is not 0 */ ++ if ((exp_part == 0) && (frac_part != 0)) ++ dnorm = 1; ++ else ++ dnorm = 0; ++ ++ /* pos: MSB is 1 */ ++ if (sign_bit == 0) ++ pos = 1; ++ else ++ pos = 0; ++ ++ /* calculate FPCC */ ++ /* If the result is NaN then must force bits 1, 2 and 3 to zero ++ * to get correct result. ++ */ ++ bit0 = NaN | inf; ++ ++ bit1 = (!NaN) & zero; ++ bit2 = (!NaN) & ((pos & dnorm) | (pos & norm) | (pos & inf)) ++ & ((!zero) & (!NaN)); ++ bit3 = (!NaN) & (((!pos) & dnorm) |((!pos) & norm) | ((!pos) & inf)) ++ & ((!zero) & (!NaN)); ++ ++ fpcc = (bit3 << 3) | (bit2 << 2) | (bit1 << 1) | bit0; ++ ++ /* calculate C */ ++ c = NaN | ((!pos) & dnorm) | ((!pos) & zero) | (pos & dnorm); ++ ++ /* return C in the upper 32-bits and FPCC in the lower 32 bits */ ++ return (c <<32) | fpcc; ++} ++ ++ + /*---------------------------------------------------------------*/ + /*--- Misc BCD clean helpers. ---*/ + /*---------------------------------------------------------------*/ +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 2467f70..0dae368 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -3860,7 +3860,7 @@ static IRExpr * is_Denorm( IRType size, IRTemp src ) + + setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); + +- /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ ++ /* check exponent is all zeros */ + zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) ); + + /* check fractional part is not zero */ +@@ -3871,8 +3871,11 @@ static IRExpr * is_Denorm( IRType size, IRTemp src ) + return mkAND1( zero_exp, not_zero_frac ); + } + ++#if 0 + /* Normalized number has exponent between 1 and max_exp -1, or in other words + the exponent is not zero and not equal to the max exponent value. */ ++ Currently not needed since generate_C_FPCC is now done with a C helper. ++ Keep it around, might be useful in the future. + static IRExpr * is_Norm( IRType size, IRTemp src ) + { + IRExpr *not_zero_exp, *not_max_exp; +@@ -3919,72 +3922,18 @@ static IRExpr * is_Norm( IRType size, IRTemp src ) + + return mkAND1( not_zero_exp, not_max_exp ); + } ++#endif + +- +-static IRExpr * create_FPCC( IRTemp NaN, IRTemp inf, +- IRTemp zero, IRTemp norm, +- IRTemp dnorm, IRTemp pos, +- IRTemp neg ) { +- IRExpr *bit0, *bit1, *bit2, *bit3; +- +- /* If the result is NaN then must force bits 1, 2 and 3 to zero +- * to get correct result. +- */ +- bit0 = unop( Iop_1Uto32, mkOR1( mkexpr( NaN ), mkexpr( inf ) ) ); +- bit1 = unop( Iop_1Uto32, mkAND1( mkNOT1( mkexpr( NaN ) ), mkexpr( zero ) ) ); +- bit2 = unop( Iop_1Uto32, +- mkAND1( mkNOT1( mkexpr( NaN ) ), +- mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( pos ), +- mkexpr( dnorm ) ), +- mkAND1( mkexpr( pos ), +- mkexpr( norm ) ) ), +- mkAND1( mkexpr( pos ), +- mkexpr( inf ) ) ), +- mkAND1( mkNOT1 ( mkexpr( zero ) ), +- mkNOT1( mkexpr( NaN ) ) ) ) ) ); +- bit3 = unop( Iop_1Uto32, +- mkAND1( mkNOT1( mkexpr( NaN ) ), +- mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( neg ), +- mkexpr( dnorm ) ), +- mkAND1( mkexpr( neg ), +- mkexpr( norm ) ) ), +- mkAND1( mkexpr( neg ), +- mkexpr( inf ) ) ), +- mkAND1( mkNOT1 ( mkexpr( zero ) ), +- mkNOT1( mkexpr( NaN ) ) ) ) ) ); +- +- return binop( Iop_Or32, +- binop( Iop_Or32, +- bit0, +- binop( Iop_Shl32, bit1, mkU8( 1 ) ) ), +- binop( Iop_Or32, +- binop( Iop_Shl32, bit2, mkU8( 2 ) ), +- binop( Iop_Shl32, bit3, mkU8( 3 ) ) ) ); +-} +- +-static IRExpr * create_C( IRTemp NaN, IRTemp zero, +- IRTemp dnorm, IRTemp pos, +- IRTemp neg ) +-{ +- +- return unop( Iop_1Uto32, +- mkOR1( mkOR1( mkexpr( NaN ), +- mkAND1( mkexpr( neg ), mkexpr( dnorm ) ) ), +- mkOR1( mkAND1( mkexpr( neg ), mkexpr( zero ) ), +- mkAND1( mkexpr( pos ), mkexpr( dnorm ) ) ) ) ); +-} +- +-static void generate_store_FPRF( IRType size, IRTemp src ) ++static void generate_store_FPRF( IRType size, IRTemp src, ++ const VexAbiInfo* vbi ) + { +- IRExpr *FPCC, *C; +- IRTemp NaN = newTemp( Ity_I1 ), inf = newTemp( Ity_I1 ); +- IRTemp dnorm = newTemp( Ity_I1 ), norm = newTemp( Ity_I1 ); +- IRTemp pos = newTemp( Ity_I1 ), neg = newTemp( Ity_I1 ); +- IRTemp zero = newTemp( Ity_I1 ); + +- IRTemp sign_bit = newTemp( Ity_I1 ); +- IRTemp value; ++ /* This function was originally written using IR code. It has been ++ * replaced with a clean helper due to the large amount of IR code ++ * needed by this function. ++ */ + ++ IRTemp tmp = newTemp( Ity_I64 ); + vassert( ( size == Ity_I16 ) || ( size == Ity_I32 ) + || ( size == Ity_I64 ) || ( size == Ity_F128 ) ); + +@@ -3993,82 +3942,45 @@ static void generate_store_FPRF( IRType size, IRTemp src ) + || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_F128 ) ); + + if( size == Ity_I16 ) { +- /* The 16-bit floating point value is in the lower 16-bits of +- the 32-bit input value */ +- value = newTemp( Ity_I32 ); +- assign( value, mkexpr( src ) ); +- assign( sign_bit, +- unop ( Iop_32to1, +- binop( Iop_And32, +- binop( Iop_Shr32, mkexpr( value ), mkU8( 15 ) ), +- mkU32( 0x1 ) ) ) ); +- ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), mkU64( 0 ), ++ mkexpr( src ) ) ) ); + } else if( size == Ity_I32 ) { +- value = newTemp( size ); +- assign( value, mkexpr( src ) ); +- assign( sign_bit, +- unop ( Iop_32to1, +- binop( Iop_And32, +- binop( Iop_Shr32, mkexpr( value ), mkU8( 31 ) ), +- mkU32( 0x1 ) ) ) ); +- ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), mkU64( 0 ), ++ mkexpr( src ) ) ) ); + } else if( size == Ity_I64 ) { +- value = newTemp( size ); +- assign( value, mkexpr( src ) ); +- assign( sign_bit, +- unop ( Iop_64to1, +- binop( Iop_And64, +- binop( Iop_Shr64, mkexpr( value ), mkU8( 63 ) ), +- mkU64( 0x1 ) ) ) ); +- +- } else { +- /* Move the F128 bit pattern to an integer V128 bit pattern */ +- value = newTemp( Ity_V128 ); +- assign( value, +- binop( Iop_64HLtoV128, +- unop( Iop_ReinterpF64asI64, +- unop( Iop_F128HItoF64, mkexpr( src ) ) ), +- unop( Iop_ReinterpF64asI64, +- unop( Iop_F128LOtoF64, mkexpr( src ) ) ) ) ); +- +- size = Ity_V128; +- assign( sign_bit, +- unop ( Iop_64to1, +- binop( Iop_And64, +- binop( Iop_Shr64, +- unop( Iop_V128HIto64, mkexpr( value ) ), +- mkU8( 63 ) ), +- mkU64( 0x1 ) ) ) ); ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), mkU64( 0 ), ++ mkexpr( src ) ) ) ); ++ } else if( size == Ity_F128 ) { ++ assign( tmp, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "generate_store_C_FPCC_helper", ++ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ), ++ mkIRExprVec_3( mkU64( size ), ++ unop( Iop_ReinterpF64asI64, ++ unop( Iop_F128HItoF64, ++ mkexpr( src ) ) ), ++ unop( Iop_ReinterpF64asI64, ++ unop( Iop_F128LOtoF64, ++ mkexpr( src ) ) ) ) ) ); + } + +- /* Calculate the floating point result field FPRF */ +- assign( NaN, is_NaN( size, value ) ); +- assign( inf, is_Inf( size, value ) ); +- assign( zero, is_Zero( size, value ) ); +- assign( norm, is_Norm( size, value ) ); +- assign( dnorm, is_Denorm( size, value ) ); +- assign( pos, mkAND1( mkNOT1( mkexpr( sign_bit ) ), mkU1( 1 ) ) ); +- assign( neg, mkAND1( mkexpr( sign_bit ), mkU1( 1 ) ) ); +- +- /* create the FPRF bit field +- * +- * FPRF field[4:0] type of value +- * 10001 QNaN +- * 01001 - infininity +- * 01000 - Normalized +- * 11000 - Denormalized +- * 10010 - zero +- * 00010 + zero +- * 10100 + Denormalized +- * 00100 + Normalized +- * 00101 + infinity ++ /* C is in the upper 32-bits, FPCC is in the lower 32-bits of the ++ * value returned by the helper function + */ +- FPCC = create_FPCC( NaN, inf, zero, norm, dnorm, pos, neg ); +- C = create_C( NaN, zero, dnorm, pos, neg ); +- +- /* Write the C and FPCC fields of the FPRF field */ +- putC( C ); +- putFPCC( FPCC ); ++ putC( unop( Iop_64HIto32, mkexpr( tmp) ) ); ++ putFPCC( unop( Iop_64to32, mkexpr( tmp) ) ); + } + + /* This function takes an Ity_I32 input argument interpreted +@@ -18538,7 +18450,8 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) + * Miscellaneous VSX Scalar Instructions + */ + static Bool +-dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 ) ++dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, ++ int allow_isa_3_0 ) + { + #define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL + /* XX3-Form and XX2-Form */ +@@ -18783,7 +18696,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 ) + putVSReg( XT, mkexpr( result ) ); + + assign( value, unop( Iop_V128HIto64, mkexpr( result ) ) ); +- generate_store_FPRF( Ity_I64, value ); ++ generate_store_FPRF( Ity_I64, value, vbi ); + return True; + + } else if (inst_select == 17) { // xscvdphp +@@ -18798,7 +18711,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 ) + assign( value, unop( Iop_64to32, unop( Iop_V128HIto64, + mkexpr( result ) ) ) ); + putVSReg( XT, mkexpr( result ) ); +- generate_store_FPRF( Ity_I16, value ); ++ generate_store_FPRF( Ity_I16, value, vbi ); + return True; + + } else { +@@ -21475,7 +21388,7 @@ dis_vx_store ( UInt theInstr ) + } + + static Bool +-dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) ++dis_vx_Scalar_Round_to_quad_integer( UInt theInstr, const VexAbiInfo* vbi ) + { + /* The ISA 3.0 instructions supported in this function require + * the underlying hardware platform that supports the ISA3.0 +@@ -21514,7 +21427,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) + DIP("xsrqpix %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC); + assign( vT, binop( Iop_F128toI128S, rm, mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + } /* case 0x005 */ + break; + case 0x025: // xsrqpxp VSX Scalar Round Quad-Precision to +@@ -21530,7 +21443,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) + + DIP("xsrqpxp %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC); + assign( vT, binop( Iop_RndF128, rm, mkexpr( vB ) ) ); +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + } /* case 0x025 */ + break; + default: +@@ -21542,7 +21455,8 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr ) + } + + static Bool +-dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) ++dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr, ++ const VexAbiInfo* vbi ) + { + /* The ISA 3.0 instructions supported in this function require + * the underlying hardware platform that supports the ISA 3.0 +@@ -21582,7 +21496,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_AddF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x024: // xsmulqp (VSX Scalar Multiply Quad-Precision[using round to Odd]) +@@ -21600,7 +21514,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_MulF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x184: // xsmaddqp (VSX Scalar Multiply add Quad-Precision[using round to Odd]) +@@ -21625,7 +21539,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_MAddF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x1A4: // xsmsubqp (VSX Scalar Multiply Subtract Quad-Precision[using round to Odd]) +@@ -21649,7 +21563,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_MSubF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x1C4: // xsnmaddqp (VSX Scalar Negative Multiply Add Quad-Precision[using round to Odd]) +@@ -21673,7 +21587,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_NegMAddF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x1E4: // xsmsubqp (VSX Scalar Negatve Multiply Subtract Quad-Precision[using round to Odd]) +@@ -21697,7 +21611,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + qop( Iop_NegMSubF128, set_round_to_Oddmode(), + mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x204: // xssubqp (VSX Scalar Subtract Quad-Precision[using round to Odd]) +@@ -21714,7 +21628,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_SubF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x224: // xsdivqp (VSX Scalar Divide Quad-Precision[using round to Odd]) +@@ -21731,7 +21645,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, triop( Iop_DivF128, set_round_to_Oddmode(), mkexpr( vA ), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 0x324: // xssqrtqp (VSX Scalar Square root Quad-Precision[using round to Odd]) +@@ -21752,7 +21666,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, binop( Iop_SqrtF128, set_round_to_Oddmode(), + mkexpr( vB ) ) ); + } +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } /* end case 27 */ + default: +@@ -21783,7 +21697,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( tmp, unop( Iop_ReinterpF64asI64, + unop( Iop_F128HItoF64, mkexpr( vB ) ) ) ); + assign( vT, unop( Iop_I64UtoF128, mkexpr( tmp ) ) ); +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 9: // xsvqpswz VSX Scalar Truncate & Convert Quad-Precision +@@ -21803,7 +21717,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( tmp, unop( Iop_ReinterpF64asI64, + unop( Iop_F128HItoF64, mkexpr( vB ) ) ) ); + assign( vT, unop( Iop_I64StoF128, mkexpr( tmp ) ) ); +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 17: // xsvqpudz VSX Scalar Truncate & Convert Quad-Precision +@@ -21855,7 +21769,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( tmp, unop( Iop_ReinterpF64asI64, + unop( Iop_F128HItoF64, mkexpr( vT ) ) ) ); + +- generate_store_FPRF( Ity_I64, tmp ); ++ generate_store_FPRF( Ity_I64, tmp, vbi ); + break; + } + case 22: // xscvdpqp VSX Scalar Convert from Double-Precision +@@ -21866,7 +21780,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr ) + assign( vT, unop( Iop_F64toF128, + unop( Iop_F128HItoF64, mkexpr( vB ) ) ) ); + +- generate_store_FPRF( Ity_F128, vT ); ++ generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 25: // xsvqpsdz VSX Scalar Truncate & Convert Quad-Precision +@@ -28199,13 +28113,13 @@ DisResult disInstr_PPC_WRK ( + UInt vsxOpc2; + + if (( opc2hi == 13 ) && ( opc2lo == 5)) { //xvtstdcsp +- if (dis_vxs_misc(theInstr, 0x354, allow_isa_3_0)) ++ if (dis_vxs_misc(theInstr, abiinfo, 0x354, allow_isa_3_0)) + goto decode_success; + goto decode_failure; + } + + if (( opc2hi == 15 ) && ( opc2lo == 5)) { //xvtstdcdp +- if (dis_vxs_misc(theInstr, 0x3D4, allow_isa_3_0)) ++ if (dis_vxs_misc(theInstr, abiinfo, 0x3D4, allow_isa_3_0)) + goto decode_success; + goto decode_failure; + } +@@ -28221,7 +28135,7 @@ DisResult disInstr_PPC_WRK ( + /* This is a special case of the XX1 form where the RA, RB + * fields hold an immediate value. + */ +- if (dis_vxs_misc(theInstr, opc2, allow_isa_3_0)) goto decode_success; ++ if (dis_vxs_misc(theInstr, abiinfo, opc2, allow_isa_3_0)) goto decode_success; + goto decode_failure; + } + +@@ -28231,7 +28145,8 @@ DisResult disInstr_PPC_WRK ( + case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw + case 0x068: case 0xE8: // xxperm, xxpermr + case 0x018: case 0x148: // xxsel, xxspltw +- if (dis_vx_permute_misc(theInstr, vsxOpc2)) goto decode_success; ++ if (dis_vx_permute_misc(theInstr, vsxOpc2 )) ++ goto decode_success; + goto decode_failure; + case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor, + case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc +@@ -28255,7 +28170,7 @@ DisResult disInstr_PPC_WRK ( + case 0x354: // xvtstdcsp + case 0x360:case 0x396: // xviexpsp, xsiexpdp + case 0x3D4: case 0x3E0: // xvtstdcdp, xviexpdp +- if (dis_vxs_misc(theInstr, vsxOpc2, allow_isa_3_0)) ++ if (dis_vxs_misc(theInstr, abiinfo, vsxOpc2, allow_isa_3_0)) + goto decode_success; + goto decode_failure; + case 0x08C: case 0x0AC: // xscmpudp, xscmpodp +@@ -28409,7 +28324,7 @@ DisResult disInstr_PPC_WRK ( + case 0x5: // xsrqpi, xsrqpix + case 0x25: // xsrqpxp + if ( !mode64 || !allow_isa_3_0 ) goto decode_failure; +- if ( dis_vx_Scalar_Round_to_quad_integer( theInstr ) ) ++ if ( dis_vx_Scalar_Round_to_quad_integer( theInstr, abiinfo ) ) + goto decode_success; + goto decode_failure; + default: +@@ -28531,7 +28446,8 @@ DisResult disInstr_PPC_WRK ( + + case 0x324: // xsabsqp, xsxexpqp,xsnabsqp, xsnegqp, xsxsigqp + if ( inst_select == 27 ) { // xssqrtqp +- if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) ) ++ if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr, ++ abiinfo ) ) + goto decode_success; + } + +@@ -28566,7 +28482,8 @@ DisResult disInstr_PPC_WRK ( + case 0x344: // xscvudqp, xscvsdqp, xscvqpdp, xscvqpdpo, xsvqpdp + // xscvqpswz, xscvqpuwz, xscvqpudz, xscvqpsdz + if ( !mode64 || !allow_isa_3_0 ) goto decode_failure; +- if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) ) ++ if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr, ++ abiinfo ) ) + goto decode_success; + goto decode_failure; + + +commit a1d03d0d11c0b31a6d9f57baa4d46317fdd5f6ef +Author: Carl Love +Date: Tue Oct 3 15:09:22 2017 -0500 + + PPC64, Use the vperm code to implement the xxperm inst. + + The current xxperm instruction implementation generates a huge + number of Iops to explicitly do the permutation. The code + was changed to use the Iop_Perm8x16 which is much more efficient + so temporary memory doesn't get exhausted. + + Bugzilla 385208 + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 0dae368..1373d1c 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -22319,15 +22319,17 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + case 0x68: // xxperm (VSX Permute ) + case 0xE8: // xxpermr (VSX Permute right-index ) + { +- int i; +- IRTemp new_Vt[17]; +- IRTemp perm_val[16]; +- IRTemp perm_val_gt16[16]; +- IRTemp tmp_val[16]; +- IRTemp perm_idx[16]; +- IRTemp perm_mask = newTemp( Ity_V128 ); +- IRTemp val_mask = newTemp( Ity_V128 ); +- int dest_shift_amount = 0; ++ ++ /* The xxperm instruction performs the same operation as ++ the vperm except the xxperm operates on the VSR register ++ file. while vperm operates on the VR register file. ++ Lets borrow some code here from vperm. The mapping of ++ the source registers is also a little different. ++ */ ++ IRTemp a_perm = newTemp(Ity_V128); ++ IRTemp b_perm = newTemp(Ity_V128); ++ IRTemp mask = newTemp(Ity_V128); ++ IRTemp perm_val = newTemp(Ity_V128); + + if ( opc2 == 0x68 ) { + DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); +@@ -22337,119 +22339,40 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + DIP("xxpermr v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); + } + +- new_Vt[0] = newTemp( Ity_V128 ); +- + assign( vT, getVSReg( XT ) ); + +- assign( new_Vt[0], binop( Iop_64HLtoV128, +- mkU64( 0x0 ), mkU64( 0x0 ) ) ); +- assign( perm_mask, binop( Iop_64HLtoV128, +- mkU64( 0x0 ), mkU64( 0x1F ) ) ); +- assign( val_mask, binop( Iop_64HLtoV128, +- mkU64( 0x0 ), mkU64( 0xFF ) ) ); +- +- /* For each permute index in XB, the permute list, select the byte +- * from XA indexed by the permute index if the permute index is less +- * then 16. Copy the selected byte to the destination location in +- * the result. +- */ +- for ( i = 0; i < 16; i++ ) { +- perm_val_gt16[i] = newTemp( Ity_V128 ); +- perm_val[i] = newTemp( Ity_V128 ); +- perm_idx[i] = newTemp( Ity_I8 ); +- tmp_val[i] = newTemp( Ity_V128 ); +- new_Vt[i+1] = newTemp( Ity_V128 ); +- +- /* create mask to extract the permute index value from vB, +- * store value in least significant bits of perm_val +- */ +- if ( opc2 == 0x68 ) +- /* xxperm, the perm value is the index value in XB */ +- assign( perm_val[i], binop( Iop_ShrV128, +- binop( Iop_AndV128, +- mkexpr(vB), +- binop( Iop_ShlV128, +- mkexpr( perm_mask ), +- mkU8( (15 - i) * 8 ) ) ), +- mkU8( (15 - i) * 8 ) ) ); ++ if ( opc2 == 0x68 ) // xxperm ++ assign( perm_val, ++ binop( Iop_AndV128, mkexpr( vB ), ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ); + +- else +- /* xxpermr, the perm value is 31 - index value in XB */ +- assign( perm_val[i], +- binop( Iop_Sub8x16, +- binop( Iop_64HLtoV128, +- mkU64( 0 ), mkU64( 31 ) ), +- binop( Iop_ShrV128, +- binop( Iop_AndV128, +- mkexpr( vB ), +- binop( Iop_ShlV128, +- mkexpr( perm_mask ), +- mkU8( ( 15 - i ) * 8 ) ) ), +- mkU8( ( 15 - i ) * 8 ) ) ) ); +- +- /* Determine if the perm_val[] > 16. If it is, then the value +- * will come from xT otherwise it comes from xA. Either way, +- * create the mask to get the value from the source using the +- * lower 3 bits of perm_val[]. Create a 128 bit mask from the +- * upper bit of perm_val[] to be used to select from xT or xA. +- */ +- assign( perm_val_gt16[i], +- binop(Iop_64HLtoV128, +- unop( Iop_1Sto64, +- unop( Iop_64to1, +- unop( Iop_V128to64, +- binop( Iop_ShrV128, +- mkexpr( perm_val[i] ), +- mkU8( 4 ) ) ) ) ), +- unop( Iop_1Sto64, +- unop( Iop_64to1, +- unop( Iop_V128to64, +- binop( Iop_ShrV128, +- mkexpr( perm_val[i] ), +- mkU8( 4 ) ) ) ) ) ) ); +- +- assign( perm_idx[i], +- unop(Iop_32to8, +- binop( Iop_Mul32, +- binop( Iop_Sub32, +- mkU32( 15 ), +- unop( Iop_64to32, +- binop( Iop_And64, +- unop( Iop_V128to64, +- mkexpr( perm_val[i] ) ), +- mkU64( 0xF ) ) ) ), +- mkU32( 8 ) ) ) ); +- +- dest_shift_amount = ( 15 - i )*8; +- +- /* Use perm_val_gt16 to select value from vA or vT */ +- assign( tmp_val[i], +- binop( Iop_ShlV128, +- binop( Iop_ShrV128, +- binop( Iop_OrV128, +- binop( Iop_AndV128, +- mkexpr( vA ), +- binop( Iop_AndV128, +- unop( Iop_NotV128, +- mkexpr( perm_val_gt16[i] ) ), +- binop( Iop_ShlV128, +- mkexpr( val_mask ), +- mkexpr( perm_idx[i] ) ) ) ), +- binop( Iop_AndV128, +- mkexpr( vT ), +- binop( Iop_AndV128, +- mkexpr( perm_val_gt16[i] ), +- binop( Iop_ShlV128, +- mkexpr( val_mask ), +- mkexpr( perm_idx[i] ) ) ) ) ), +- mkexpr( perm_idx[i] ) ), +- mkU8( dest_shift_amount ) ) ); +- +- assign( new_Vt[i+1], binop( Iop_OrV128, +- mkexpr( tmp_val[i] ), +- mkexpr( new_Vt[i] ) ) ); +- } +- putVSReg( XT, mkexpr( new_Vt[16] ) ); ++ else // xxpermr ++ assign( perm_val, ++ binop( Iop_Sub16x8, ++ binop( Iop_64HLtoV128, ++ mkU64( 0x1F1F1F1F1F1F1F1F ), ++ mkU64( 0x1F1F1F1F1F1F1F1F ) ), ++ binop( Iop_AndV128, mkexpr( vB ), ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ ++ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ IR specifies, and also to hide irrelevant bits from ++ memcheck. ++ */ ++ assign( a_perm, ++ binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) ); ++ assign( b_perm, ++ binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) ); ++ assign( mask, binop( Iop_SarN8x16, ++ binop( Iop_ShlN8x16, mkexpr( perm_val ), ++ mkU8( 3 ) ), ++ mkU8( 7 ) ) ); ++ // dst = (a & ~mask) | (b & mask) ++ putVSReg( XT, binop( Iop_OrV128, ++ binop( Iop_AndV128, mkexpr( a_perm ), ++ unop( Iop_NotV128, mkexpr( mask ) ) ), ++ binop( Iop_AndV128, mkexpr( b_perm ), ++ mkexpr( mask ) ) ) ); + break; + } + + +commit b0aef250a74804423341b3ce804355037211e330 +Author: Carl Love +Date: Tue Oct 3 15:18:09 2017 -0500 + + PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16. + + The current implementation will generate a lot of Iops. The number + of generated Iops can lead to Valgrind running out of temporary space. + See bugzilla https://bugs.kde.org/show_bug.cgi?id=385208 as an example + of the issue. Using Iop_Perm8x16 reduces the number of Iops significantly. + + bugzilla 385210 + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 1373d1c..1785959 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -24107,107 +24107,40 @@ static Bool dis_av_permute ( UInt theInstr ) + } + + case 0x3B: { // vpermr (Vector Permute Right-indexed) +- int i; +- IRTemp new_Vt[17]; +- IRTemp tmp[16]; +- IRTemp index[16]; +- IRTemp index_gt16[16]; +- IRTemp mask[16]; +- +- DIP("vpermr v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr); +- +- new_Vt[0] = newTemp( Ity_V128 ); +- assign( new_Vt[0], binop( Iop_64HLtoV128, +- mkU64( 0x0 ), +- mkU64( 0x0 ) ) ); +- +- for ( i = 0; i < 16; i++ ) { +- index_gt16[i] = newTemp( Ity_V128 ); +- mask[i] = newTemp( Ity_V128 ); +- index[i] = newTemp( Ity_I32 ); +- tmp[i] = newTemp( Ity_V128 ); +- new_Vt[i+1] = newTemp( Ity_V128 ); +- +- assign( index[i], +- binop( Iop_Sub32, +- mkU32( 31 ), +- unop( Iop_64to32, +- unop( Iop_V128to64, +- binop( Iop_ShrV128, +- binop( Iop_AndV128, +- binop( Iop_ShlV128, +- binop( Iop_64HLtoV128, +- mkU64( 0x0 ), +- mkU64( 0x3F ) ), +- mkU8( (15 - i) * 8 ) ), +- mkexpr( vC ) ), +- mkU8( (15 - i) * 8 ) ) ) ) ) ); +- +- /* Determine if index < 16, src byte is vA[index], otherwise +- * vB[31-index]. Check if msb of index is 1 or not. +- */ +- assign( index_gt16[i], +- binop( Iop_64HLtoV128, +- unop( Iop_1Sto64, +- unop( Iop_32to1, +- binop( Iop_Shr32, +- mkexpr( index[i] ), +- mkU8( 4 ) ) ) ), +- unop( Iop_1Sto64, +- unop( Iop_32to1, +- binop( Iop_Shr32, +- mkexpr( index[i] ), +- mkU8( 4 ) ) ) ) ) ); +- assign( mask[i], +- binop( Iop_ShlV128, +- binop( Iop_64HLtoV128, +- mkU64( 0x0 ), +- mkU64( 0xFF ) ), +- unop( Iop_32to8, +- binop( Iop_Mul32, +- binop( Iop_Sub32, +- mkU32( 15 ), +- binop( Iop_And32, +- mkexpr( index[i] ), +- mkU32( 0xF ) ) ), +- mkU32( 8 ) ) ) ) ); +- +- /* Extract the indexed byte from vA and vB using the lower 4-bits +- * of the index. Then use the index_gt16 mask to select vA if the +- * index < 16 or vB if index > 15. Put the selected byte in the +- * least significant byte. +- */ +- assign( tmp[i], +- binop( Iop_ShrV128, +- binop( Iop_OrV128, +- binop( Iop_AndV128, +- binop( Iop_AndV128, +- mkexpr( mask[i] ), +- mkexpr( vA ) ), +- unop( Iop_NotV128, +- mkexpr( index_gt16[i] ) ) ), +- binop( Iop_AndV128, +- binop( Iop_AndV128, +- mkexpr( mask[i] ), +- mkexpr( vB ) ), +- mkexpr( index_gt16[i] ) ) ), +- unop( Iop_32to8, +- binop( Iop_Mul32, +- binop( Iop_Sub32, +- mkU32( 15 ), +- binop( Iop_And32, +- mkexpr( index[i] ), +- mkU32( 0xF ) ) ), +- mkU32( 8 ) ) ) ) ); +- +- /* Move the selected byte to the position to store in the result */ +- assign( new_Vt[i+1], binop( Iop_OrV128, +- binop( Iop_ShlV128, +- mkexpr( tmp[i] ), +- mkU8( (15 - i) * 8 ) ), +- mkexpr( new_Vt[i] ) ) ); +- } +- putVReg( vD_addr, mkexpr( new_Vt[16] ) ); ++ /* limited to two args for IR, so have to play games... */ ++ IRTemp a_perm = newTemp( Ity_V128 ); ++ IRTemp b_perm = newTemp( Ity_V128 ); ++ IRTemp mask = newTemp( Ity_V128 ); ++ IRTemp vC_andF = newTemp( Ity_V128 ); ++ ++ DIP( "vpermr v%d,v%d,v%d,v%d\n", ++ vD_addr, vA_addr, vB_addr, vC_addr); ++ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ IR specifies, and also to hide irrelevant bits from ++ memcheck. ++ */ ++ ++ assign( vC_andF, ++ binop( Iop_Sub16x8, ++ binop( Iop_64HLtoV128, ++ mkU64( 0x1F1F1F1F1F1F1F1F ), ++ mkU64( 0x1F1F1F1F1F1F1F1F ) ), ++ binop( Iop_AndV128, mkexpr( vC ), ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ assign( a_perm, ++ binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) ); ++ assign( b_perm, ++ binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) ); ++ // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0 ++ assign( mask, binop(Iop_SarN8x16, ++ binop( Iop_ShlN8x16, mkexpr( vC_andF ), ++ mkU8( 3 ) ), mkU8( 7 ) ) ); ++ // dst = (a & ~mask) | (b & mask) ++ putVReg( vD_addr, binop( Iop_OrV128, ++ binop( Iop_AndV128, mkexpr( a_perm ), ++ unop( Iop_NotV128, mkexpr( mask ) ) ), ++ binop( Iop_AndV128, mkexpr( b_perm ), ++ mkexpr( mask ) ) ) ); + return True; + } + + +commit f0c4da68ca9e8c99f55965d8e074273a33ab916d +Author: Carl Love +Date: Tue Oct 3 10:49:48 2017 -0500 + + PPC64, Fix bug in vperm instruction. + + The ISA says: + + Let the source vector be the concatenation of the + contents of VR[VRA] followed by the contents of + VR[VRB]. + + For each integer value i from 0 to 15, do the following. + Let index be the value specified by bits 3:7 of byte + element i of VR[VRC]. + + So, the index value is 5-bits wide ([3:7]), not 4-bits wide. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 1785959..97664c2 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -24047,12 +24047,12 @@ static Bool dis_av_permute ( UInt theInstr ) + IRTemp vC_andF = newTemp(Ity_V128); + DIP("vperm v%d,v%d,v%d,v%d\n", + vD_addr, vA_addr, vB_addr, vC_addr); +- /* Limit the Perm8x16 steering values to 0 .. 15 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck */ + assign( vC_andF, + binop(Iop_AndV128, mkexpr(vC), +- unop(Iop_Dup8x16, mkU8(0xF))) ); ++ unop(Iop_Dup8x16, mkU8(0x1F))) ); + assign( a_perm, + binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); + assign( b_perm, + +commit 5398a9f9cb9db6805df03e43258e65fa799a7caa +Author: Carl Love +Date: Wed Oct 4 10:24:36 2017 -0500 + + PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions. + + These are Power 9 instructions. + + Add test cases for the new instructions to test_isa_3_0.c + + Bugzilla 385183. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 97664c2..6b2157d 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -3629,18 +3629,22 @@ static IRExpr * fp_exp_part( IRType size, IRTemp src ) + /* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */ + #define I16_EXP_MASK 0x7C00 + #define I16_FRACTION_MASK 0x03FF ++#define I16_MSB_FRACTION_MASK 0x0200 + #define I32_EXP_MASK 0x7F800000 + #define I32_FRACTION_MASK 0x007FFFFF ++#define I32_MSB_FRACTION_MASK 0x00400000 + #define I64_EXP_MASK 0x7FF0000000000000ULL + #define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL ++#define I64_MSB_FRACTION_MASK 0x0008000000000000ULL + #define V128_EXP_MASK 0x7FFF000000000000ULL + #define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL /* upper 64-bit fractional mask */ ++#define V128_MSB_FRACTION_MASK 0x0000800000000000ULL /* upper 64-bit fractional mask */ + + void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask, +- IRTemp *zero ); ++ IRTemp *msb_frac_mask, IRTemp *zero ); + + void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask, +- IRTemp *zero ) { ++ IRTemp *msb_frac_mask, IRTemp *zero ) { + + vassert( ( size == Ity_I16 ) || ( size == Ity_I32 ) + || ( size == Ity_I64 ) || ( size == Ity_V128 ) ); +@@ -3649,37 +3653,45 @@ void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask, + /* The 16-bit floating point value is in the lower 16-bits of + the 32-bit input value */ + *frac_mask = newTemp( Ity_I32 ); ++ *msb_frac_mask = newTemp( Ity_I32 ); + *exp_mask = newTemp( Ity_I32 ); + *zero = newTemp( Ity_I32 ); + assign( *exp_mask, mkU32( I16_EXP_MASK ) ); + assign( *frac_mask, mkU32( I16_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU32( I16_MSB_FRACTION_MASK ) ); + assign( *zero, mkU32( 0 ) ); + + } else if( size == Ity_I32 ) { + *frac_mask = newTemp( Ity_I32 ); ++ *msb_frac_mask = newTemp( Ity_I32 ); + *exp_mask = newTemp( Ity_I32 ); + *zero = newTemp( Ity_I32 ); + assign( *exp_mask, mkU32( I32_EXP_MASK ) ); + assign( *frac_mask, mkU32( I32_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU32( I32_MSB_FRACTION_MASK ) ); + assign( *zero, mkU32( 0 ) ); + + } else if( size == Ity_I64 ) { + *frac_mask = newTemp( Ity_I64 ); ++ *msb_frac_mask = newTemp( Ity_I64 ); + *exp_mask = newTemp( Ity_I64 ); + *zero = newTemp( Ity_I64 ); + assign( *exp_mask, mkU64( I64_EXP_MASK ) ); + assign( *frac_mask, mkU64( I64_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU64( I64_MSB_FRACTION_MASK ) ); + assign( *zero, mkU64( 0 ) ); + + } else { + /* V128 is converted to upper and lower 64 bit values, */ + /* uses 64-bit operators and temps */ + *frac_mask = newTemp( Ity_I64 ); ++ *msb_frac_mask = newTemp( Ity_I64 ); + *exp_mask = newTemp( Ity_I64 ); + *zero = newTemp( Ity_I64 ); + assign( *exp_mask, mkU64( V128_EXP_MASK ) ); + /* upper 64-bit fractional mask */ + assign( *frac_mask, mkU64( V128_FRACTION_MASK ) ); ++ assign( *msb_frac_mask, mkU64( V128_MSB_FRACTION_MASK ) ); + assign( *zero, mkU64( 0 ) ); + } + } +@@ -3801,9 +3813,10 @@ static IRExpr *fractional_part_compare( IRType size, IRTemp src, + static IRExpr * is_Inf( IRType size, IRTemp src ) + { + IRExpr *max_exp, *zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ + max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) ); +@@ -3818,9 +3831,10 @@ static IRExpr * is_Inf( IRType size, IRTemp src ) + static IRExpr * is_Zero( IRType size, IRTemp src ) + { + IRExpr *zero_exp, *zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check the exponent is all zeros, i.e. (exp AND exp_mask) = zero */ + zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) ); +@@ -3837,9 +3851,10 @@ static IRExpr * is_Zero( IRType size, IRTemp src ) + static IRExpr * is_NaN( IRType size, IRTemp src ) + { + IRExpr *max_exp, *not_zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ + max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) ); +@@ -3852,13 +3867,37 @@ static IRExpr * is_NaN( IRType size, IRTemp src ) + return mkAND1( max_exp, not_zero_frac ); + } + ++static IRExpr * is_sNaN( IRType size, IRTemp src ) ++{ ++ IRExpr *max_exp, *not_zero_frac, *msb_zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; ++ ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); ++ ++ /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ ++ max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) ); ++ ++ /* Most significant fractional bit is zero for sNaN */ ++ msb_zero = fractional_part_compare ( size, src, msb_frac_mask, ++ mkexpr( zero ) ); ++ ++ /* check fractional part is not zero */ ++ not_zero_frac = unop( Iop_Not1, ++ fractional_part_compare( size, src, frac_mask, ++ mkexpr( zero ) ) ); ++ ++ return mkAND1( msb_zero, mkAND1( max_exp, not_zero_frac ) ); ++} ++ + /* Denormalized number has a zero exponent and non zero fraction. */ + static IRExpr * is_Denorm( IRType size, IRTemp src ) + { + IRExpr *zero_exp, *not_zero_frac; +- IRTemp exp_mask, frac_mask, zero; ++ IRTemp exp_mask, frac_mask, msb_frac_mask, zero; + +- setup_value_check_args( size, &exp_mask, &frac_mask, &zero ); ++ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask, ++ &zero ); + + /* check exponent is all zeros */ + zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) ); +@@ -19712,6 +19751,216 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, + } + + /* ++ * VSX vector miscellaneous instructions ++ */ ++ ++static Bool ++dis_vx_misc ( UInt theInstr, UInt opc2 ) ++{ ++ /* XX3-Form */ ++ UChar XT = ifieldRegXT ( theInstr ); ++ UChar XA = ifieldRegXA ( theInstr ); ++ UChar XB = ifieldRegXB ( theInstr ); ++ IRTemp vA = newTemp( Ity_V128 ); ++ IRTemp vB = newTemp( Ity_V128 ); ++ IRTemp src1 = newTemp(Ity_I64); ++ IRTemp src2 = newTemp(Ity_I64); ++ IRTemp result_mask = newTemp(Ity_I64); ++ IRTemp cmp_mask = newTemp(Ity_I64); ++ IRTemp nan_mask = newTemp(Ity_I64); ++ IRTemp snan_mask = newTemp(Ity_I64); ++ IRTemp word_result = newTemp(Ity_I64); ++ IRTemp check_result = newTemp(Ity_I64); ++ IRTemp xT = newTemp( Ity_V128 ); ++ IRTemp nan_cmp_value = newTemp(Ity_I64); ++ UInt trap_enabled = 0; /* 0 - trap enabled is False */ ++ ++ assign( vA, getVSReg( XA ) ); ++ assign( vB, getVSReg( XB ) ); ++ assign( xT, getVSReg( XT ) ); ++ ++ assign(src1, unop( Iop_V128HIto64, mkexpr( vA ) ) ); ++ assign(src2, unop( Iop_V128HIto64, mkexpr( vB ) ) ); ++ ++ assign( nan_mask, ++ binop( Iop_Or64, ++ unop( Iop_1Sto64, is_NaN( Ity_I64, src1 ) ), ++ unop( Iop_1Sto64, is_NaN( Ity_I64, src2 ) ) ) ); ++ ++ if ( trap_enabled == 0 ) ++ /* Traps on invalid operation are assumed not enabled, assign ++ result of comparison to xT. ++ */ ++ assign( snan_mask, mkU64( 0 ) ); ++ ++ else ++ assign( snan_mask, ++ binop( Iop_Or64, ++ unop( Iop_1Sto64, is_sNaN( Ity_I64, src1 ) ), ++ unop( Iop_1Sto64, is_sNaN( Ity_I64, src2 ) ) ) ); ++ ++ assign (result_mask, binop( Iop_Or64, ++ mkexpr( snan_mask ), ++ mkexpr( nan_mask ) ) ); ++ ++ switch (opc2) { ++ case 0xC: //xscmpeqdp ++ { ++ DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* extract double-precision floating point source values from ++ double word 0 */ ++ ++ /* result of Iop_CmpF64 is 0x40 if operands are equal, ++ mask is all 1's if equal. */ ++ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop(Iop_32to1, ++ binop(Iop_Shr32, ++ binop( Iop_CmpF64, ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ) ), ++ mkU8( 6 ) ) ) ) ); ++ ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), ++ mkU64( 0xFFFFFFFFFFFFFFFF ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkU64( 0x0 ) ) ) ); ++ assign( nan_cmp_value, mkU64( 0 ) ); ++ break; ++ } ++ ++ case 0x2C: //xscmpgtdp ++ { ++ DIP("xscmpgtdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* Test for src1 > src2 */ ++ ++ /* Result of Iop_CmpF64 is 0x1 if op1 < op2, set mask to all 1's. */ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop(Iop_32to1, ++ binop(Iop_CmpF64, ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ) ) ) ) ); ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), ++ mkU64( 0xFFFFFFFFFFFFFFFF ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkU64( 0x0 ) ) ) ); ++ assign( nan_cmp_value, mkU64( 0 ) ); ++ break; ++ } ++ ++ case 0x4C: //xscmpgedp ++ { ++ DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* compare src 1 >= src 2 */ ++ /* result of Iop_CmpF64 is 0x40 if operands are equal, ++ mask is all 1's if equal. */ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop(Iop_32to1, ++ binop( Iop_Or32, ++ binop( Iop_Shr32, ++ binop(Iop_CmpF64, /* EQ test */ ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ) ), ++ mkU8( 6 ) ), ++ binop(Iop_CmpF64, /* src2 < src 1 test */ ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ) ) ) ) ) ); ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), ++ mkU64( 0xFFFFFFFFFFFFFFFF ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkU64( 0x0 ) ) ) ); ++ assign( nan_cmp_value, mkU64( 0 ) ); ++ break; ++ } ++ ++ case 0x220: //xsmincdp ++ { ++ DIP("xsmincdp v%d,v%d,v%d\n", XT, XA, XB); ++ /* extract double-precision floating point source values from ++ double word 0 */ ++ ++ /* result of Iop_CmpF64 is 0x1 if src1 less then src2, */ ++ assign( cmp_mask, ++ unop( Iop_1Sto64, ++ unop( Iop_32to1, ++ binop(Iop_CmpF64, ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src1 ) ), ++ unop( Iop_ReinterpI64asF64, ++ mkexpr( src2 ) ) ) ) ) ); ++ assign( word_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( cmp_mask ), mkexpr( src1 ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( cmp_mask ) ), ++ mkexpr( src2 ) ) ) ); ++ assign( nan_cmp_value, mkexpr( src2 ) ); ++ break; ++ } ++ ++ default: ++ vex_printf( "dis_vx_misc(ppc)(opc2)\n" ); ++ return False; ++ } ++ ++ /* If either argument is NaN, result is src2. If either argument is ++ SNaN, we are supposed to generate invalid operation exception. ++ Currently don't support generating exceptions. In case of an ++ trap enabled invalid operation (SNaN) XT is not changed. The ++ snan_mask is setup appropriately for trap enabled or not. ++ */ ++ assign( check_result, ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( snan_mask ), ++ unop( Iop_V128HIto64, mkexpr( xT ) ) ), ++ binop( Iop_And64, unop( Iop_Not64, ++ mkexpr( snan_mask ) ), ++ binop( Iop_Or64, ++ binop( Iop_And64, mkexpr( nan_mask ), ++ mkexpr( nan_cmp_value ) ), ++ binop( Iop_And64, ++ unop( Iop_Not64, ++ mkexpr( nan_mask ) ), ++ mkU64( 0 ) ) ) ) ) ); ++ ++ /* If SNaN is true, then the result is unchanged if a trap-enabled ++ Invalid Operation occurs. Result mask already setup for trap-enabled ++ case. ++ */ ++ putVSReg( XT, ++ binop( Iop_64HLtoV128, ++ binop( Iop_Or64, ++ binop( Iop_And64, ++ unop( Iop_Not64, mkexpr( result_mask ) ), ++ mkexpr( word_result ) ), ++ binop( Iop_And64, ++ mkexpr( result_mask ), ++ mkexpr( check_result ) ) ), ++ mkU64( 0 ) ) ); ++ return True; ++} ++ ++/* + * VSX Logical Instructions + */ + static Bool +@@ -27319,12 +27568,15 @@ static struct vsx_insn vsx_xx3[] = { + { 0x0, "xsaddsp" }, + { 0x4, "xsmaddasp" }, + { 0x9, "xsmaddmsp" }, ++ { 0xC, "xscmpeqdp" }, + { 0x20, "xssubsp" }, + { 0x24, "xsmaddmsp" }, ++ { 0x2C, "xscmpgtdp" }, + { 0x3A, "xxpermr" }, + { 0x40, "xsmulsp" }, + { 0x44, "xsmsubasp" }, + { 0x48, "xxmrghw" }, ++ { 0x4C, "xscmpgedp" }, + { 0x60, "xsdivsp" }, + { 0x64, "xsmsubmsp" }, + { 0x68, "xxperm" }, +@@ -27371,6 +27623,7 @@ static struct vsx_insn vsx_xx3[] = { + { 0x1f4, "xvtdivdp" }, + { 0x204, "xsnmaddasp" }, + { 0x208, "xxland" }, ++ { 0x220, "xsmincdp" }, + { 0x224, "xsnmaddmsp" }, + { 0x228, "xxlandc" }, + { 0x244, "xsnmsubasp" }, +@@ -28004,9 +28257,13 @@ DisResult disInstr_PPC_WRK ( + if (dis_vx_permute_misc(theInstr, vsxOpc2 )) + goto decode_success; + goto decode_failure; ++ case 0xC: case 0x2C: case 0x4C: // xscmpeqdp, xscmpgtdp, xscmpgedp ++ case 0x220: //xsmincdp ++ if (dis_vx_misc(theInstr, vsxOpc2)) goto decode_success; ++ goto decode_failure; + case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor, +- case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc +- case 0x2C8: case 0x2E8: // xxlnand, xxleqv ++ case 0x208: case 0x228: // xxland, xxlandc ++ case 0x2A8: case 0x2C8: case 0x2E8: // xxlorc, xxlnand, xxleqv + if (dis_vx_logic(theInstr, vsxOpc2)) goto decode_success; + goto decode_failure; + case 0x0ec: // xscmpexpdp +diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c +index 6e4e7dc..4b07f8b 100644 +--- a/none/tests/ppc64/test_isa_3_0.c ++++ b/none/tests/ppc64/test_isa_3_0.c +@@ -1172,8 +1172,28 @@ static void test_xscmpexpdp(void) { + }; + } + +-static test_list_t testgroup_vector_scalar_compare_exp_double[] = { ++static void test_xscmpeqdp(void) { ++ __asm__ __volatile__ ("xscmpeqdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static void test_xscmpgtdp(void) { ++ __asm__ __volatile__ ("xscmpgtdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static void test_xscmpgedp(void) { ++ __asm__ __volatile__ ("xscmpgedp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static void test_xsmincdp(void) { ++ __asm__ __volatile__ ("xsmincdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb)); ++} ++ ++static test_list_t testgroup_vector_scalar_compare_double[] = { + { &test_xscmpexpdp , "xscmpexpdp " }, ++ { &test_xscmpeqdp , "xscmpeqdp " }, ++ { &test_xscmpgtdp , "xscmpgtdp " }, ++ { &test_xscmpgedp , "xscmpgedp " }, ++ { &test_xsmincdp , "xsmincdp " }, + { NULL , NULL }, + }; + +@@ -2301,8 +2321,8 @@ static test_group_table_t all_tests[] = { + PPC_MISC | PPC_TWO_ARGS, + }, + { +- testgroup_vector_scalar_compare_exp_double, +- "ppc vector scalar compare exponents doubles", ++ testgroup_vector_scalar_compare_double, ++ "ppc vector scalar compare doubles", + PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS, + }, + { +@@ -3125,8 +3145,16 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name, + } + } + ++/* helper macro. Use below to limit output to only dword[0] for the inputs ++ * to the instructions listed here. */ ++#define instruction_only_uses_dword0_inputs(instruction_name) \ ++ ((strncmp(instruction_name, "xscmpeqdp",9) == 0) || \ ++ (strncmp(instruction_name, "xscmpgtdp",9) == 0) || \ ++ (strncmp(instruction_name, "xscmpgedp",9) == 0) || \ ++ (strncmp(instruction_name, "xsmincdp",8) == 0) ) ++ + static void +-testfunction_vector_scalar_compare_exp_double (const char* instruction_name, ++testfunction_vector_scalar_compare_double (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_test_flags){ + int i,j; +@@ -3154,11 +3182,15 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name, + */ + SET_CR_ZERO + SET_FPSCR_ZERO +- +- printf("%s %016lx %016lx %016lx %016lx", +- instruction_name, +- vec_xa[0], vec_xa[1], +- vec_xb[0], vec_xb[1]); ++ if (instruction_only_uses_dword0_inputs(instruction_name)) { ++ printf("%s %016lx %016lx", ++ instruction_name, vec_xa[1], vec_xb[1]); ++ } else { ++ printf("%s %016lx %016lx %016lx %016lx", ++ instruction_name, ++ vec_xa[0], vec_xa[1], ++ vec_xb[0], vec_xb[1]); ++ } + + if (verbose) printf(" cr#%d ", x_index); + +@@ -3166,6 +3198,10 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name, + + (*test_function)(); + ++ if (instruction_only_uses_dword0_inputs(instruction_name)) { ++ printf("%016lx %016lx", vec_xt[0], vec_xt[1]); ++ } ++ + dissect_fpscr(local_fpscr); + dissect_fpscr_result_value_class(local_fpscr); + dissect_cr_rn(local_cr, x_index); +@@ -4094,7 +4130,7 @@ static void do_tests ( insn_sel_flags_t seln_flags) + break; + + case PPC_COMPARE_ARGS: +- group_function = &testfunction_vector_scalar_compare_exp_double; ++ group_function = &testfunction_vector_scalar_compare_double; + break; + + default: +diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE +index c4ad35f..7d3c94c 100644 +--- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE ++++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE +@@ -53311,8 +53311,8 @@ stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0 + 00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ] + + All done. Tested 135 different instructions +-ppc vector scalar compare exponents doubles: +-Test instruction group [ppc vector scalar compare exponents doubles] ++ppc vector scalar compare doubles: ++Test instruction group [ppc vector scalar compare doubles] + xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ) + xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ) + xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ) +@@ -54275,7 +54275,3855 @@ xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 + xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO) + xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO) + +-All done. Tested 136 different instructions ++xscmpeqdp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpeqdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++ ++xscmpgtdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgtdp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++ ++xscmpgedp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 80007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 80007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xscmpgedp fff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++ ++xsmincdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 00007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 7ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 00007fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 0ff07fffffffffff => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff0000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8000000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 00007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 0ff07fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff0000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8000000000000000 => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 80007fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 00007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 0ff07fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8000000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 80007fffffffffff => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 00007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 0ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8000000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 80007fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp 8ff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO) ++ ++All done. Tested 140 different instructions + ppc vector scalar test data class tests: + Test instruction group [ppc vector scalar test data class tests] + xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a +@@ -55453,7 +59301,7 @@ xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 000000000000 + xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000 + xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff + +-All done. Tested 141 different instructions ++All done. Tested 145 different instructions + ppc vector scalar tests against float double two args : + Test instruction group [ppc vector scalar tests against float double two args ] + xsiexpdp r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000 +@@ -56261,4 +60109,4 @@ xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f800 + xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff + xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff + +-All done. Tested 146 different instructions ++All done. Tested 150 different instructions + +commit c618e707d3e24853cd1e0b71deb981f2dc4ae8d4 +Author: Carl Love +Date: Wed Oct 4 10:54:07 2017 -0500 + + PPC64, revert the change to vperm instruction. + + The patch was in my git tree with the patch I intended to apply. + I didn't realize the patch was in the tree. Git applied both + patches. Still investigating the vperm change to see if it is + really needed. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 6b2157d..b5b0d03 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -24296,12 +24296,12 @@ static Bool dis_av_permute ( UInt theInstr ) + IRTemp vC_andF = newTemp(Ity_V128); + DIP("vperm v%d,v%d,v%d,v%d\n", + vD_addr, vA_addr, vB_addr, vC_addr); +- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck */ + assign( vC_andF, + binop(Iop_AndV128, mkexpr(vC), +- unop(Iop_Dup8x16, mkU8(0x1F))) ); ++ unop(Iop_Dup8x16, mkU8(0xF))) ); + assign( a_perm, + binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); + assign( b_perm, + +commit 856d45eb7e3661a61ace32be2cfa10bf198620c8 +Author: Carl Love +Date: Thu Oct 5 12:19:59 2017 -0500 + + PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field + + The implementation of the vpermr, xxperm, xxpermr violate this by + using a mask of 0x1F. Fix the code and the corresponding comments + to met the definition for Iop_Perm8x16. Use Iop_Dup8x16 to generate + vector value for subtraction. + + Bugzilla 385334. + +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index b5b0d03..f63146e 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -22579,6 +22579,7 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + IRTemp b_perm = newTemp(Ity_V128); + IRTemp mask = newTemp(Ity_V128); + IRTemp perm_val = newTemp(Ity_V128); ++ IRTemp vB_adj = newTemp( Ity_V128 ); + + if ( opc2 == 0x68 ) { + DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); +@@ -22591,29 +22592,27 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) + assign( vT, getVSReg( XT ) ); + + if ( opc2 == 0x68 ) // xxperm +- assign( perm_val, +- binop( Iop_AndV128, mkexpr( vB ), +- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ); ++ assign( vB_adj, mkexpr( vB ) ); + + else // xxpermr +- assign( perm_val, ++ assign( vB_adj, + binop( Iop_Sub16x8, +- binop( Iop_64HLtoV128, +- mkU64( 0x1F1F1F1F1F1F1F1F ), +- mkU64( 0x1F1F1F1F1F1F1F1F ) ), +- binop( Iop_AndV128, mkexpr( vB ), +- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ), ++ mkexpr( vB ) ) ); + +- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck. + */ ++ assign( perm_val, ++ binop( Iop_AndV128, mkexpr( vB_adj ), ++ unop( Iop_Dup8x16, mkU8( 0xF ) ) ) ); + assign( a_perm, + binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) ); + assign( b_perm, + binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) ); + assign( mask, binop( Iop_SarN8x16, +- binop( Iop_ShlN8x16, mkexpr( perm_val ), ++ binop( Iop_ShlN8x16, mkexpr( vB_adj ), + mkU8( 3 ) ), + mkU8( 7 ) ) ); + // dst = (a & ~mask) | (b & mask) +@@ -24361,28 +24360,29 @@ static Bool dis_av_permute ( UInt theInstr ) + IRTemp b_perm = newTemp( Ity_V128 ); + IRTemp mask = newTemp( Ity_V128 ); + IRTemp vC_andF = newTemp( Ity_V128 ); ++ IRTemp vC_adj = newTemp( Ity_V128 ); + + DIP( "vpermr v%d,v%d,v%d,v%d\n", + vD_addr, vA_addr, vB_addr, vC_addr); +- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what ++ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what + IR specifies, and also to hide irrelevant bits from + memcheck. + */ + ++ assign( vC_adj, ++ binop( Iop_Sub16x8, ++ unop( Iop_Dup8x16, mkU8( 0x1F ) ), ++ mkexpr( vC ) ) ); + assign( vC_andF, +- binop( Iop_Sub16x8, +- binop( Iop_64HLtoV128, +- mkU64( 0x1F1F1F1F1F1F1F1F ), +- mkU64( 0x1F1F1F1F1F1F1F1F ) ), +- binop( Iop_AndV128, mkexpr( vC ), +- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) ); ++ binop( Iop_AndV128, mkexpr( vC_adj), ++ unop( Iop_Dup8x16, mkU8( 0xF ) ) ) ); + assign( a_perm, + binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) ); + assign( b_perm, + binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) ); + // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0 + assign( mask, binop(Iop_SarN8x16, +- binop( Iop_ShlN8x16, mkexpr( vC_andF ), ++ binop( Iop_ShlN8x16, mkexpr( vC_adj ), + mkU8( 3 ) ), mkU8( 7 ) ) ); + // dst = (a & ~mask) | (b & mask) + putVReg( vD_addr, binop( Iop_OrV128, diff --git a/SOURCES/valgrind-3.13.0-static-tls.patch b/SOURCES/valgrind-3.13.0-static-tls.patch new file mode 100644 index 0000000..578a3c5 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-static-tls.patch @@ -0,0 +1,81 @@ +commit f1ff8597ef9c37ff1a853411b9e3be1696c36d92 +Author: Philippe Waroquiers +Date: Tue Sep 19 23:17:48 2017 +0200 + + Implement static TLS code for more platforms + + gdbserver_tests/hgtls is failing on a number of platforms + as it looks like static tls handling is now needed. + So, omplement static tls for a few more platforms. + The formulas that are platform dependent are somewhat wild guesses + obtained with trial and errors. + Note that arm/arm64/ppc32 are not (yet) done + +diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c +index 10e52fc..1f03c12 100644 +--- a/coregrind/m_gdbserver/target.c ++++ b/coregrind/m_gdbserver/target.c +@@ -712,6 +712,7 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + // Check we can read the modid + CHECK_DEREF(lm+lm_modid_offset, sizeof(unsigned long int), "link_map modid"); + modid = *(unsigned long int *)(lm+lm_modid_offset); ++ dlog (2, "tid %u modid %lu\n", tst->tid, modid); + + // Check we can access the dtv entry for modid + CHECK_DEREF(dtv + 2 * modid, sizeof(CORE_ADDR), "dtv[2*modid]"); +@@ -719,7 +720,6 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + // Compute the base address of the tls block. + *tls_addr = *(dtv + 2 * modid); + +-#if defined(VGA_mips32) || defined(VGA_mips64) + if (*tls_addr & 1) { + /* This means that computed address is not valid, most probably + because given module uses Static TLS. +@@ -731,17 +731,24 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + CORE_ADDR tls_offset_addr; + PtrdiffT tls_offset; + +- dlog(1, "computing tls_addr using static TLS\n"); ++ dlog(2, "tls_addr (%p & 1) => computing tls_addr using static TLS\n", ++ (void*) *tls_addr); + + /* Assumes that tls_offset is placed right before tls_modid. + To check the assumption, start a gdb on none/tests/tls and do: +- p &((struct link_map*)0x0)->l_tls_modid +- p &((struct link_map*)0x0)->l_tls_offset */ ++ p &((struct link_map*)0x0)->l_tls_modid ++ p &((struct link_map*)0x0)->l_tls_offset ++ Instead of assuming this, we could calculate this similarly to ++ lm_modid_offset, by extending getplatformoffset to support querying ++ more than one offset. ++ */ + tls_offset_addr = lm + lm_modid_offset - sizeof(PtrdiffT); + + // Check we can read the tls_offset. + CHECK_DEREF(tls_offset_addr, sizeof(PtrdiffT), "link_map tls_offset"); + tls_offset = *(PtrdiffT *)(tls_offset_addr); ++ dlog(2, "tls_offset_addr %p tls_offset %ld\n", ++ (void*)tls_offset_addr, (long)tls_offset); + + /* Following two values represent platform dependent constants + NO_TLS_OFFSET and FORCED_DYNAMIC_TLS_OFFSET, respectively. */ +@@ -751,9 +758,18 @@ Bool valgrind_get_tls_addr (ThreadState *tst, + } + + // This calculation is also platform dependent. ++#if defined(VGA_mips32) || defined(VGA_mips64) + *tls_addr = ((CORE_ADDR)dtv_loc + 2 * sizeof(CORE_ADDR) + tls_offset); +- } ++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) ++ *tls_addr = ((CORE_ADDR)dtv_loc + sizeof(CORE_ADDR) + tls_offset); ++#elif defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) ++ *tls_addr = (CORE_ADDR)dtv_loc - tls_offset - sizeof(CORE_ADDR); ++#else ++ // ppc32, arm, arm64 ++ dlog(0, "target.c is missing platform code for static TLS\n"); ++ return False; + #endif ++ } + + // Finally, add tls variable offset to tls block base address. + *tls_addr += offset; diff --git a/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch b/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch new file mode 100644 index 0000000..77405fc --- /dev/null +++ b/SOURCES/valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch @@ -0,0 +1,36 @@ +commit 3c3aa1c62767c48ac8f2015df66f04f354dd897b +Author: Mark Wielaard +Date: Tue Oct 17 17:49:26 2017 +0200 + + Suppress _dl_runtime_resolve_avx_slow for memcheck conditional. + + glibc ld.so has an optimization when resolving a symbol that checks + whether or not the upper 128 bits of the ymm registers are zero. If + so it uses "cheaper" instructions to save/restore them using the xmm + registers. If those upper 128 bits contain undefined values memcheck + will issue an Conditional jump or move depends on uninitialised value(s) + warning whenever trying to resolve a symbol. + + This triggers in our sh-mem-vecxxx test cases. Suppress the warning + by default. + +diff --git a/glibc-2.X.supp.in b/glibc-2.X.supp.in +index 8edeb4a..126e8b3 100644 +--- a/glibc-2.X.supp.in ++++ b/glibc-2.X.supp.in +@@ -236,3 +236,15 @@ + Memcheck:Cond + fun:_dl_relocate_object + } ++ ++# glibc ld.so has an optimization when resolving a symbol that checks ++# whether or not the upper 128 bits of the ymm registers are zero. If ++# so it uses "cheaper" instructions to save/restore them using the xmm ++# registers. If those upper 128 bits contain undefined values memcheck ++# will issue an Conditional jump or move depends on uninitialised value(s) ++# warning whenever trying to resolve a symbol. ++{ ++ dl-trampoline-sse-avx ++ Memcheck:Cond ++ fun:_dl_runtime_resolve_avx_slow ++} diff --git a/SOURCES/valgrind-3.13.0-ucontext_t.patch b/SOURCES/valgrind-3.13.0-ucontext_t.patch new file mode 100644 index 0000000..0abcef2 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-ucontext_t.patch @@ -0,0 +1,25 @@ +commit 9b37074f7609cd496c067e88ef8c436981aa7267 +Author: mjw +Date: Thu Jun 29 15:26:30 2017 +0000 + + memcheck/tests: Use ucontext_t instead of struct ucontext + + glibc 2.26 does not expose struct ucontext anymore. + + Signed-off-by: Khem Raj + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16457 a5019735-40e9-0310-863c-91ae7b9d1cf9 + +diff --git a/memcheck/tests/linux/stack_changes.c b/memcheck/tests/linux/stack_changes.c +index a978fc2..7f97b90 100644 +--- a/memcheck/tests/linux/stack_changes.c ++++ b/memcheck/tests/linux/stack_changes.c +@@ -10,7 +10,7 @@ + // This test is checking the libc context calls (setcontext, etc.) and + // checks that Valgrind notices their stack changes properly. + +-typedef struct ucontext mycontext; ++typedef ucontext_t mycontext; + + mycontext ctx1, ctx2, oldc; + int count; diff --git a/SOURCES/valgrind-3.13.0-xml-socket.patch b/SOURCES/valgrind-3.13.0-xml-socket.patch new file mode 100644 index 0000000..e1b79d3 --- /dev/null +++ b/SOURCES/valgrind-3.13.0-xml-socket.patch @@ -0,0 +1,25 @@ +commit 34dd8493de39314033509bb7ad62673f33dcf3db +Author: Ivo Raisr +Date: Thu Aug 3 05:22:01 2017 +0000 + + Fix handling command line option --xml-socket. + Fixes BZ#382998 + Patch by: Orgad Shaneh + + + + git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16467 + +diff --git a/coregrind/m_libcprint.c b/coregrind/m_libcprint.c +index d66c67d..f6ba202 100644 +--- a/coregrind/m_libcprint.c ++++ b/coregrind/m_libcprint.c +@@ -526,7 +526,7 @@ void VG_(init_log_xml_sinks)(VgLogTo log_to, VgLogTo xml_to, + break; + + case VgLogTo_Socket: +- log_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded), ++ xml_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded), + &VG_(xml_output_sink), True); + break; + } diff --git a/SOURCES/valgrind-3.9.0-cachegrind-improvements.patch b/SOURCES/valgrind-3.9.0-cachegrind-improvements.patch new file mode 100644 index 0000000..c2680b1 --- /dev/null +++ b/SOURCES/valgrind-3.9.0-cachegrind-improvements.patch @@ -0,0 +1,54 @@ +--- valgrind-3.8.1/cachegrind/cg_sim.c.jj 2011-10-26 23:24:32.000000000 +0200 ++++ valgrind-3.8.1/cachegrind/cg_sim.c 2011-12-09 17:31:19.256023683 +0100 +@@ -42,27 +42,30 @@ typedef struct { + Int size; /* bytes */ + Int assoc; + Int line_size; /* bytes */ +- Int sets; + Int sets_min_1; + Int line_size_bits; + Int tag_shift; +- HChar desc_line[128]; /* large enough */ + UWord* tags; +-} cache_t2; ++ HChar desc_line[128]; ++} cache_t2 ++#ifdef __GNUC__ ++__attribute__ ((aligned (8 * sizeof (Int)))) ++#endif ++; + + /* By this point, the size/assoc/line_size has been checked. */ + static void cachesim_initcache(cache_t config, cache_t2* c) + { +- Int i; ++ Int sets; + + c->size = config.size; + c->assoc = config.assoc; + c->line_size = config.line_size; + +- c->sets = (c->size / c->line_size) / c->assoc; +- c->sets_min_1 = c->sets - 1; ++ sets = (c->size / c->line_size) / c->assoc; ++ c->sets_min_1 = sets - 1; + c->line_size_bits = VG_(log2)(c->line_size); +- c->tag_shift = c->line_size_bits + VG_(log2)(c->sets); ++ c->tag_shift = c->line_size_bits + VG_(log2)(sets); + + if (c->assoc == 1) { + VG_(sprintf)(c->desc_line, "%d B, %d B, direct-mapped", +@@ -72,11 +75,8 @@ static void cachesim_initcache(cache_t c + c->size, c->line_size, c->assoc); + } + +- c->tags = VG_(malloc)("cg.sim.ci.1", +- sizeof(UWord) * c->sets * c->assoc); +- +- for (i = 0; i < c->sets * c->assoc; i++) +- c->tags[i] = 0; ++ c->tags = VG_(calloc)("cg.sim.ci.1", ++ sizeof(UWord), sets * c->assoc); + } + + /* This attribute forces GCC to inline the function, getting rid of a diff --git a/SOURCES/valgrind-3.9.0-helgrind-race-supp.patch b/SOURCES/valgrind-3.9.0-helgrind-race-supp.patch new file mode 100644 index 0000000..759d151 --- /dev/null +++ b/SOURCES/valgrind-3.9.0-helgrind-race-supp.patch @@ -0,0 +1,15 @@ +--- valgrind/glibc-2.34567-NPTL-helgrind.supp.jj 2009-08-19 15:37:48.000000000 +0200 ++++ valgrind/glibc-2.34567-NPTL-helgrind.supp 2009-10-21 16:46:31.000000000 +0200 +@@ -88,6 +88,12 @@ + obj:*/lib*/libpthread-2.*so* + } + { ++ helgrind-glibc2X-102a ++ Helgrind:Race ++ fun:mythread_wrapper ++ obj:*vgpreload_helgrind*.so ++} ++{ + helgrind-glibc2X-103 + Helgrind:Race + fun:pthread_cond_*@@GLIBC_2.* diff --git a/SOURCES/valgrind-3.9.0-ldso-supp.patch b/SOURCES/valgrind-3.9.0-ldso-supp.patch new file mode 100644 index 0000000..d7a42c7 --- /dev/null +++ b/SOURCES/valgrind-3.9.0-ldso-supp.patch @@ -0,0 +1,28 @@ +--- valgrind/glibc-2.X.supp.in.jj 2011-10-26 23:24:45.000000000 +0200 ++++ valgrind/glibc-2.X.supp.in 2012-05-07 10:55:20.395942656 +0200 +@@ -124,7 +124,7 @@ + glibc-2.5.x-on-SUSE-10.2-(PPC)-2a + Memcheck:Cond + fun:index +- obj:*ld-@GLIBC_VERSION@.*.so ++ obj:*ld-@GLIBC_VERSION@*.so + } + { + glibc-2.5.x-on-SuSE-10.2-(PPC)-2b +@@ -136,14 +136,14 @@ + glibc-2.5.5-on-SuSE-10.2-(PPC)-2c + Memcheck:Addr4 + fun:index +- obj:*ld-@GLIBC_VERSION@.*.so ++ obj:*ld-@GLIBC_VERSION@*.so + } + { + glibc-2.3.5-on-SuSE-10.1-(PPC)-3 + Memcheck:Addr4 + fun:*wordcopy_fwd_dest_aligned* + fun:mem*cpy +- obj:*lib*@GLIBC_VERSION@.*.so ++ obj:*lib*@GLIBC_VERSION@*.so + } + + { diff --git a/SPECS/valgrind.spec b/SPECS/valgrind.spec new file mode 100644 index 0000000..9879ba2 --- /dev/null +++ b/SPECS/valgrind.spec @@ -0,0 +1,1315 @@ +%{?scl:%scl_package valgrind} + +Summary: Tool for finding memory management bugs in programs +Name: %{?scl_prefix}valgrind +Version: 3.13.0 +Release: 10%{?dist} +Epoch: 1 +License: GPLv2+ +URL: http://www.valgrind.org/ +Group: Development/Debuggers + +# Only necessary for RHEL, will be ignored on Fedora +BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) + +# Are we building for a Software Collection? +%{?scl:%global is_scl 1} +%{!?scl:%global is_scl 0} + +# Only arches that are supported upstream as multilib and that the distro +# has multilib builds for should set build_multilib 1. In practice that +# is only x86_64 and ppc64 (but not in fedora 21 and later, and never +# for ppc64le or when building for scl). +%global build_multilib 0 + +%ifarch x86_64 + %global build_multilib 1 +%endif + +%ifarch ppc64 + %if %{is_scl} + %global build_multilib 0 + %else + %if 0%{?rhel} + %global build_multilib 1 + %endif + %if 0%{?fedora} + %global build_multilib (%fedora < 21) + %endif + %endif +%endif + +# Note s390x doesn't have an openmpi port available. +# We never want the openmpi subpackage when building a software collecton +%if %{is_scl} + %global build_openmpi 0 +%else + %ifarch %{ix86} x86_64 ppc ppc64 ppc64le %{arm} aarch64 + %global build_openmpi 1 + %else + %global build_openmpi 0 + %endif +%endif + +# Whether to run the full regtest or only a limited set +# The full regtest includes gdb_server integration tests. +# On arm the gdb integration tests hang for unknown reasons. +# On rhel6 the gdb_server tests hang. +# On rhel7 they hang on ppc64 and ppc64le. +%ifarch %{arm} + %global run_full_regtest 0 +%else + %if 0%{?rhel} == 6 + %global run_full_regtest 0 + %else + %if 0%{?rhel} == 7 + %ifarch ppc64 ppc64le + %global run_full_regtest 0 + %else + %global run_full_regtest 1 + %endif + %else + %global run_full_regtest 1 + %endif + %endif +%endif + +# Generating minisymtabs doesn't really work for the staticly linked +# tools. Note (below) that we don't strip the vgpreload libraries at all +# because valgrind might read and need the debuginfo in those (client) +# libraries for better error reporting and sometimes correctly unwinding. +# So those will already have their full symbol table. +%undefine _include_minidebuginfo + +Source0: ftp://sourceware.org/pub/valgrind/valgrind-%{version}.tar.bz2 + +# Needs investigation and pushing upstream +Patch1: valgrind-3.9.0-cachegrind-improvements.patch + +# KDE#211352 - helgrind races in helgrind's own mythread_wrapper +Patch2: valgrind-3.9.0-helgrind-race-supp.patch + +# Make ld.so supressions slightly less specific. +Patch3: valgrind-3.9.0-ldso-supp.patch + +# KDE#381272 ppc64 doesn't compile test_isa_2_06_partx.c without VSX support +Patch4: valgrind-3.13.0-ppc64-check-no-vsx.patch + +# KDE#381289 epoll_pwait can have a NULL sigmask. +Patch5: valgrind-3.13.0-epoll_pwait.patch + +# KDE#381274 powerpc too chatty even with --sigill-diagnostics=no +Patch6: valgrind-3.13.0-ppc64-diag.patch + +# KDE#381556 arm64: Handle feature registers access on 4.11 Linux kernel +# Workaround that masks CPUID support in HWCAP on aarch64 (#1464211) +Patch7: valgrind-3.13.0-arm64-hwcap.patch + +# RHBZ#1466017 ARM ld.so index warnings. +# KDE#381805 arm32 needs ld.so index hardwire for new glibc security fixes +Patch8: valgrind-3.13.0-arm-index-hardwire.patch + +# KDE#381769 Use ucontext_t instead of struct ucontext +Patch9: valgrind-3.13.0-ucontext_t.patch + +# valgrind svn r16453 Fix some tests failure with GDB 8.0 +Patch10: valgrind-3.13.0-gdb-8-testfix.patch + +# valgrind svn r16454. disable vgdb poll in the child after fork +Patch11: valgrind-3.13.0-disable-vgdb-child.patch + +# KDE#382998 xml-socket doesn't work +Patch12: valgrind-3.13.0-xml-socket.patch + +# KDE#385334 +# PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field +# PPC64, revert the change to vperm instruction. +# KDE#385183 +# PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions +# PPC64, Fix bug in vperm instruction. +# KDE#385210 +# PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16. +# KDE#385208 +# PPC64, Use the vperm code to implement the xxperm inst. +# PPC64, Replace body of generate_store_FPRF with C helper function. +# PPC64, Add support for the Data Stream Control Register (DSCR) +Patch13: valgrind-3.13.0-ppc64-vex-fixes.patch + +# Fix eflags handling in amd64 instruction tests +Patch14: valgrind-3.13.0-amd64-eflags-tests.patch + +# KDE#385868 ld.so _dl_runtime_resolve_avx_slow conditional jump warning +Patch15: valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch + +# Implement static TLS code for more platforms +Patch16: valgrind-3.13.0-static-tls.patch + +# KDE#386397 PPC64 valgrind truncates powerpc timebase to 32-bits. +Patch17: valgrind-3.13.0-ppc64-timebase.patch + +# RHEL7 specific patches. + +# RHBZ#996927 Ignore PPC floating point phased out category. +# The result might differ on ppc vs ppc64 and config.h ends up as +# public header under /usr/include/valgrind causing multilib problems. +# The result would only be used for two test cases. +Patch7001: valgrind-3.11.0-ppc-fppo.patch +%if %{build_multilib} + +# Ensure glibc{,-devel} is installed for both multilib arches +BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so +%endif + +%if 0%{?fedora} >= 15 +BuildRequires: glibc-devel >= 2.14 +%else +%if 0%{?rhel} >= 6 +BuildRequires: glibc-devel >= 2.12 +%else +BuildRequires: glibc-devel >= 2.5 +%endif +%endif + +%if %{build_openmpi} +BuildRequires: openmpi-devel >= 1.3.3 +%endif + +# For %%build and %%check. +# In case of a software collection, pick the matching gdb and binutils. +%if %{run_full_regtest} +BuildRequires: %{?scl_prefix}gdb +%endif +BuildRequires: %{?scl_prefix}binutils + +# gdbserver_tests/filter_make_empty uses ps in test +BuildRequires: procps + +# Some testcases require g++ to build +BuildRequires: gcc-c++ + +# check_headers_and_includes uses Getopt::Long +%if 0%{?fedora} +BuildRequires: perl-generators +%endif +BuildRequires: perl(Getopt::Long) + +%{?scl:Requires:%scl_runtime} + +ExclusiveArch: %{ix86} x86_64 ppc ppc64 ppc64le s390x armv7hl aarch64 +%ifarch %{ix86} +%define valarch x86 +%define valsecarch %{nil} +%endif +%ifarch x86_64 +%define valarch amd64 +%define valsecarch x86 +%endif +%ifarch ppc +%define valarch ppc32 +%define valsecarch %{nil} +%endif +%ifarch ppc64 + %define valarch ppc64be + %if %{build_multilib} + %define valsecarch ppc32 + %else + %define valsecarch %{nil} + %endif +%endif +%ifarch ppc64le +%define valarch ppc64le +%define valsecarch %{nil} +%endif +%ifarch s390x +%define valarch s390x +%define valsecarch %{nil} +%endif +%ifarch armv7hl +%define valarch arm +%define valsecarch %{nil} +%endif +%ifarch aarch64 +%define valarch arm64 +%define valsecarch %{nil} +%endif + +%description +Valgrind is an instrumentation framework for building dynamic analysis +tools. There are Valgrind tools that can automatically detect many +memory management and threading bugs, and profile your programs in +detail. You can also use Valgrind to build new tools. The Valgrind +distribution currently includes six production-quality tools: a memory +error detector (memcheck, the default tool), two thread error +detectors (helgrind and drd), a cache and branch-prediction profiler +(cachegrind), a call-graph generating cache and branch-prediction +profiler (callgrind), and a heap profiler (massif). + +%package devel +Summary: Development files for valgrind +Group: Development/Debuggers +Requires: %{?scl_prefix}valgrind = %{epoch}:%{version}-%{release} +Provides: %{name}-static = %{epoch}:%{version}-%{release} + +%description devel +Header files and libraries for development of valgrind aware programs +or valgrind plugins. + +%if %{build_openmpi} +%package openmpi +Summary: OpenMPI support for valgrind +Group: Development/Debuggers +Requires: %{?scl_prefix}valgrind = %{epoch}:%{version}-%{release} + +%description openmpi +A wrapper library for debugging OpenMPI parallel programs with valgrind. +See the section on Debugging MPI Parallel Programs with Valgrind in the +Valgrind User Manual for details. +%endif + +%prep +%setup -q -n %{?scl:%{pkg_name}}%{!?scl:%{name}}-%{version} + +%patch1 -p1 +%patch2 -p1 +%patch3 -p1 +%patch4 -p1 +%patch5 -p1 +%patch6 -p1 +%patch7 -p1 +%patch8 -p1 +%patch9 -p1 +%patch10 -p1 +%patch11 -p1 +%patch12 -p1 +%patch13 -p1 +%patch14 -p1 +%patch15 -p1 +%patch16 -p1 +%patch17 -p1 + +# RHEL7 specific patches +%patch7001 -p1 + +%build +# We need to use the software collection compiler and binutils if available. +# The configure checks might otherwise miss support for various newer +# assembler instructions. +%{?scl:PATH=%{_bindir}${PATH:+:${PATH}}} + +CC=gcc +%if %{build_multilib} +# Ugly hack - libgcc 32-bit package might not be installed +mkdir -p shared/libgcc/32 +ar r shared/libgcc/32/libgcc_s.a +ar r shared/libgcc/libgcc_s_32.a +CC="gcc -B `pwd`/shared/libgcc/" +%endif + +# Old openmpi-devel has version depended paths for mpicc. +%if %{build_openmpi} +%if 0%{?fedora} >= 13 || 0%{?rhel} >= 6 +%define mpiccpath %{!?scl:%{_libdir}}%{?scl:%{_root_libdir}}/openmpi/bin/mpicc +%else +%define mpiccpath %{!?scl:%{_libdir}}%{?scl:%{_root_libdir}}/openmpi/*/bin/mpicc +%endif +%endif + +# Filter out some flags that cause lots of valgrind test failures. +# Also filter away -O2, valgrind adds it wherever suitable, but +# not for tests which should be -O0, as they aren't meant to be +# compiled with -O2 unless explicitely requested. Same for any -mcpu flag. +# Ideally we will change this to only be done for the non-primary build +# and the test suite. +%undefine _hardened_build +OPTFLAGS="`echo " %{optflags} " | sed 's/ -m\(64\|3[21]\) / /g;s/ -fexceptions / /g;s/ -fstack-protector\([-a-z]*\) / / g;s/ -Wp,-D_FORTIFY_SOURCE=2 / /g;s/ -O2 / /g;s/ -mcpu=\([a-z0-9]\+\) / /g;s/^ //;s/ $//'`" +%configure CC="$CC" CFLAGS="$OPTFLAGS" CXXFLAGS="$OPTFLAGS" \ +%if %{build_openmpi} + --with-mpicc=%{mpiccpath} \ +%endif + GDB=%{_bindir}/gdb + +make %{?_smp_mflags} + +# Ensure there are no unexpected file descriptors open, +# the testsuite otherwise fails. +cat > close_fds.c < +#include +int main (int argc, char *const argv[]) +{ + int i, j = sysconf (_SC_OPEN_MAX); + if (j < 0) + exit (1); + for (i = 3; i < j; ++i) + close (i); + execvp (argv[1], argv + 1); + exit (1); +} +EOF +gcc $RPM_OPT_FLAGS -o close_fds close_fds.c + +%install +rm -rf $RPM_BUILD_ROOT +make DESTDIR=$RPM_BUILD_ROOT install +mkdir docs/installed +mv $RPM_BUILD_ROOT%{_datadir}/doc/valgrind/* docs/installed/ +rm -f docs/installed/*.ps + +# We want the MPI wrapper installed under the openmpi libdir so the script +# generating the MPI library requires picks them up and sets up the right +# openmpi libmpi.so requires. Install symlinks in the original/upstream +# location for backwards compatibility. +%if %{build_openmpi} +pushd $RPM_BUILD_ROOT%{_libdir} +mkdir -p openmpi/valgrind +cd valgrind +mv libmpiwrap-%{valarch}-linux.so ../openmpi/valgrind/ +ln -s ../openmpi/valgrind/libmpiwrap-%{valarch}-linux.so +popd +%endif + +%if "%{valsecarch}" != "" +pushd $RPM_BUILD_ROOT%{_libdir}/valgrind/ +rm -f *-%{valsecarch}-* || : +for i in *-%{valarch}-*; do + j=`echo $i | sed 's/-%{valarch}-/-%{valsecarch}-/'` + ln -sf ../../lib/valgrind/$j $j +done +popd +%endif + +rm -f $RPM_BUILD_ROOT%{_libdir}/valgrind/*.supp.in + +%ifarch %{ix86} x86_64 +# To avoid multilib clashes in between i?86 and x86_64, +# tweak installed a little bit. +for i in HAVE_PTHREAD_CREATE_GLIBC_2_0 HAVE_PTRACE_GETREGS HAVE_AS_AMD64_FXSAVE64 \ +%if 0%{?rhel} == 5 + HAVE_BUILTIN_ATOMIC HAVE_BUILTIN_ATOMIC_CXX \ +%endif + ; do + sed -i -e 's,^\(#define '$i' 1\|/\* #undef '$i' \*/\)$,#ifdef __x86_64__\n# define '$i' 1\n#endif,' \ + $RPM_BUILD_ROOT%{_includedir}/valgrind/config.h +done +%endif + +# We don't want debuginfo generated for the vgpreload libraries. +# Turn off execute bit so they aren't included in the debuginfo.list. +# We'll turn the execute bit on again in %%files. +chmod 644 $RPM_BUILD_ROOT%{_libdir}/valgrind/vgpreload*-%{valarch}-*so + +%check +# Make sure some info about the system is in the build.log +# Add || true because rpm on copr EPEL6 acts weirdly and we don't want +# to break the build. +uname -a +rpm -q glibc gcc %{?scl_prefix}binutils || true +%if %{run_full_regtest} +rpm -q %{?scl_prefix}gdb || true +%endif + +LD_SHOW_AUXV=1 /bin/true +cat /proc/cpuinfo + +# Make sure a basic binary runs. There should be no errors. +./vg-in-place --error-exitcode=1 /bin/true + +# Build the test files with the software collection compiler if available. +%{?scl:PATH=%{_bindir}${PATH:+:${PATH}}} +# Make sure no extra CFLAGS, CXXFLAGS or LDFLAGS leak through, +# the testsuite sets all flags necessary. See also configure above. +make %{?_smp_mflags} CFLAGS="" CXXFLAGS="" LDFLAGS="" check + +# Workaround https://bugzilla.redhat.com/show_bug.cgi?id=1434601 +# for gdbserver tests. +export PYTHONCOERCECLOCALE=0 + +echo ===============TESTING=================== +%if %{run_full_regtest} + ./close_fds make regtest || : +%else + ./close_fds make nonexp-regtest || : +%endif + +# Make sure test failures show up in build.log +# Gather up the diffs (at most the first 20 lines for each one) +MAX_LINES=20 +diff_files=`find . -name '*.diff' | sort` +if [ z"$diff_files" = z ] ; then + echo "Congratulations, all tests passed!" >> diffs +else + for i in $diff_files ; do + echo "=================================================" >> diffs + echo $i >> diffs + echo "=================================================" >> diffs + if [ `wc -l < $i` -le $MAX_LINES ] ; then + cat $i >> diffs + else + head -n $MAX_LINES $i >> diffs + echo "" >> diffs + fi + done +fi +cat diffs +echo ===============END TESTING=============== + +%files +%defattr(-,root,root) +%doc COPYING NEWS README_* +%doc docs/installed/html docs/installed/*.pdf +%{_bindir}/* +%dir %{_libdir}/valgrind +# Install everything in the libdir except the .so and .a files. +# The vgpreload so files might file mode adjustment (see below). +# The libmpiwrap so files go in the valgrind-openmpi package. +# The .a archives go into the valgrind-devel package. +%{_libdir}/valgrind/*[^ao] +# Turn on executable bit again for vgpreload libraries. +# Was disabled in %%install to prevent debuginfo stripping. +%attr(0755,root,root) %{_libdir}/valgrind/vgpreload*-%{valarch}-*so +# And install the symlinks to the secarch files if the exist. +# These are separate from the above because %%attr doesn't work +# on symlinks. +%if "%{valsecarch}" != "" +%{_libdir}/valgrind/vgpreload*-%{valsecarch}-*so +%endif +%{_mandir}/man1/* + +%files devel +%defattr(-,root,root) +%{_includedir}/valgrind +%dir %{_libdir}/valgrind +%{_libdir}/valgrind/*.a +%{_libdir}/pkgconfig/* + +%if %{build_openmpi} +%files openmpi +%defattr(-,root,root) +%dir %{_libdir}/valgrind +%{_libdir}/openmpi/valgrind/libmpiwrap*.so +%{_libdir}/valgrind/libmpiwrap*.so +%endif + +%changelog +* Thu Nov 2 2017 Mark Wielaard - 3.13.0-10 +- Add valgrind-3.13.0-ppc64-timebase.patch (#1508148) + +* Tue Oct 17 2017 Mark Wielaard - 3.13.0-9 +- valgrind 3.13.0 (fedora). +- Update description. +- Drop all upstreamed patches. +- Add valgrind-3.13.0-ppc64-check-no-vsx.patch +- Add valgrind-3.13.0-epoll_pwait.patch (#1462258) +- Add valgrind-3.13.0-ppc64-diag.patch +- Add valgrind-3.13.0-arm64-hwcap.patch (#1464211) +- Add valgrind-3.13.0-arm-index-hardwire.patch (#1466017) +- Add valgrind-3.13.0-ucontext_t.patch +- Add valgrind-3.13.0-gdb-8-testfix.patch +- Add valgrind-3.13.0-disable-vgdb-child.patch +- Add --error-exitcode=1 to /bin/true check. +- Add valgrind-3.13.0-xml-socket.patch +- Add valgrind-3.13.0-ppc64-vex-fixes.patch +- Add valgrind-3.13.0-amd64-eflags-tests.patch +- Add valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch +- Add valgrind-3.13.0-static-tls.patch +- Workaround gdb/python bug in testsuite (#1434601) + +* Thu Sep 21 2017 Mark Wielaard - 3.12.0-9 +- Add valgrind-3.12.0-ll-sc-fallback[1234].patch (#1492753) + +* Tue Mar 28 2017 Mark Wielaard - 3.12.0-8 +- Add valgrind-3.12.0-powerpc-register-pair.patch (#1437030) +- Add valgrind-3.12.0-ppc64-isa-3_00.patch (#1437032) + +* Sat Feb 18 2017 Mark Wielaard - 3.12.0-7 +- Rebase to 3.12.0 fedora backports (#1391217, #1385006, #1368706, #1270889) + +* Thu Jul 21 2016 Mark Wielaard - 3.11.0-24 +- Add valgrind-3.11.0-pcmpxstrx-0x70-0x19.patch (#1354557) + +* Tue Jun 21 2016 Mark Wielaard - 3.11.0-23 +- Update valgrind-3.11.0-ppoll-mask.patch (#1347626) + +* Mon May 30 2016 Mark Wielaard - 3.11.0-22 +- Add valgrind-3.11.0-arm64-handle_at.patch +- Add valgrind-3.11.0-ppc64-syscalls.patch + +* Fri Apr 29 2016 Mark Wielaard - 3.11.0-21 +- Add valgrind-3.11.0-deduppoolalloc.patch (#1328347) +- Add valgrind-3.11.0-ppc-bcd-addsub.patch (#1331738) +- Add valgrind-3.11.0-ppc64-vgdb-vr-regs.patch (#1331774) + +* Fri Apr 15 2016 Mark Wielaard - 3.11.0-20 +- Rebase to fedora 3.11.0 + (#1316512 #1306844 #1305962 #1298888 #1296318 #1271754 #1265566 #1265557) + +* Fri Aug 28 2015 Mark Wielaard - 3.10.0-16 +- Patch both 32 and 64 in valgrind-3.10.1-ppc32-tabortdc.patch (#1257623) + +* Thu Aug 27 2015 Mark Wielaard - 3.10.0-15 +- Add valgrind-3.10.1-ppc32-tabortdc.patch (#1257623) + +* Mon Aug 10 2015 Mark Wielaard - 3.10.0-14 +- Add setuid and setresgid to valgrind-3.10.1-aarch64-syscalls.patch (#1251181) + +* Mon Aug 03 2015 Mark Wielaard - 3.10.0-13 +- Add valgrind-3.10.1-ppc64-hwcap2.patch (#1249381) + +* Wed Jul 29 2015 Mark Wielaard - 3.10.0-12 +- Add valgrind-3.10.1-kernel-4.0.patch (#1247557) + +* Thu Jul 09 2015 Mark Wielaard - 3.10.0-11 +- Add valgrind-3.10.1-s390x-fiebra.patch (#1181993) + +* Tue Jul 07 2015 Mark Wielaard - 3.10.0-10 +- Add valgrind-3.10.1-di_notify_mmap.patch (#1237206) + +* Thu May 28 2015 Mark Wielaard - 3.10.0-9 +- Add valgrind-3.10-1-ppc64-sigpending.patch. (#1225964) + +* Thu May 28 2015 Mark Wielaard - 3.10.0-8 +- Add valgrind-3.10-s390-spechelper.patch. (#1190169) +- Add valgrind-3.10.1-aarch64-syscalls.patch. (#1188622) +- Add accept4 to valgrind-3.10.1-aarch64-syscalls.patch. (#1190660) +- Add valgrind-3.10.1-ppc64-accept4.patch. (#1190660) +- Add valgrind-3.10.1-send-recv-mmsg.patch. (#1192103) +- Add mount and umount2 to valgrind-3.10.1-aarch64-syscalls.patch. (#1193796) + +* Tue Jan 13 2015 Mark Wielaard - 3.10.0-7 +- Add valgrind-3.10.1-mempcpy.patch (#1178813) + +* Wed Nov 19 2014 Mark Wielaard - 3.10.0-6 +- Add getgroups/setgroups to valgrind-3.10.0-aarch64-syscalls.patch + +* Tue Nov 4 2014 Mark Wielaard - 3.10.0-5 +- Merge valgrind-3.10.0-aarch64-times.patch + and valgrind-3.10.0-aarch64-getsetsid.patch + into valgrind-3.10.0-aarch64-syscalls.patch + add fdatasync, msync, pread64, setreuid, setregid, + mknodat, fchdir, chroot, fchownat, fchmod and fchown. +- Add valgrind-3.10.0-aarch64-frint.patch +- Add valgrind-3.10.0-fcvtmu.patch +- Add valgrind-3.10.0-aarch64-fcvta.patch + +* Sat Oct 11 2014 Mark Wielaard - 3.10.0-4 +- Add valgrind-3.10.0-aarch64-times.patch +- Add valgrind-3.10.0-aarch64-getsetsid.patch +- Add valgrind-3.10.0-aarch64-dmb-sy.patch + +* Mon Sep 15 2014 Mark Wielaard - 3.10.0-3 +- Add valgrind-3.10.0-old-ppc32-instr-magic.patch. + +* Fri Sep 12 2014 Mark Wielaard - 3.10.0-2 +- Fix ppc32 multilib handling on ppc64[be]. +- Drop ppc64 secondary for ppc32 primary support. +- Except for armv7hl we don't support any other arm[32] arch. + +* Thu Sep 11 2014 Mark Wielaard - 3.10.0-1 +- Update to 3.10.0 final. +- Don't run dwz or generate minisymtab. +- Remove valgrind-3.9.0-s390x-ld-supp.patch fixed upstream. +- Add valgrind-openmpi for ppc64le. + +* Tue Sep 2 2014 Mark Wielaard - 3.10.0-0.1.BETA1 +- Update to official upstream 3.10.0 BETA1. + - Enables inlined frames in stacktraces. + +* Mon Mar 10 2014 Mark Wielaard - 3.9.0-6 +- Add valgrind-3.9.0-ppc64-priority.patch. (#1073613) + +* Fri Feb 21 2014 Mark Wielaard - 3.9.0-5 +- Add valgrind-3.9.0-s390-dup3.patch. (#1067486) + +* Fri Jan 24 2014 Daniel Mach - 1:3.9.0-4 +- Mass rebuild 2014-01-24 + +* Fri Dec 27 2013 Daniel Mach - 1:3.9.0-3 +- Mass rebuild 2013-12-27 + +* Thu Dec 12 2013 Mark Wielaard +- Add valgrind-3.9.0-manpage-memcheck-options.patch. (#1040914) +- Add valgrind-3.9.0-s390-fpr-pair.patch. (#1036615) + +* Thu Nov 28 2013 Mark Wielaard - 3.9.0-2.2 +- Add valgrind-3.9.0-s390x-ld-supp.patch. (#1032282) +- Add valgrind-3.9.0-xabort.patch. (#1035704) + +* Wed Nov 20 2013 Mark Wielaard - 3.9.0-2.1 +- Add valgrind-3.9.0-dwz-alt-buildid.patch. (#1029875) + +* Thu Nov 7 2013 Mark Wielaard - 3.9.0-1.2 +- Remove unnecessary and unapplied valgrind-3.8.1-movntdqa.patch +- Remove valgrind-3.9.0-s390x-workarounds.patch +- Add valgrind-3.9.0-s390-risbg.patch (#1018325) + +* Fri Nov 1 2013 Mark Wielaard - 3.9.0-1.1 +- Add s390x workarounds. (#1018325) + +* Fri Nov 1 2013 Mark Wielaard - 3.9.0-1 +- Upgrade to valgrind 3.9.0 final. +- Remove support for really ancient GCCs (valgrind-3.9.0-config_h.patch). +- Add valgrind-3.9.0-amd64_gen_insn_test.patch. +- Remove and cleanup fake 32-bit libgcc package. + +* Mon Oct 28 2013 Mark Wielaard - 3.9.0-0.1.TEST1 +- Upgrade to valgrind 3.9.0.TEST1 +- Remove patches that are now upstream: + - valgrind-3.8.1-abbrev-parsing.patch + - valgrind-3.8.1-af-bluetooth.patch + - valgrind-3.8.1-aspacemgr_VG_N_SEGs.patch + - valgrind-3.8.1-avx2-bmi-fma.patch.gz + - valgrind-3.8.1-avx2-prereq.patch + - valgrind-3.8.1-bmi-conf-check.patch + - valgrind-3.8.1-capget.patch + - valgrind-3.8.1-cfi_dw_ops.patch + - valgrind-3.8.1-dwarf-anon-enum.patch + - valgrind-3.8.1-filter_gdb.patch + - valgrind-3.8.1-find-buildid.patch + - valgrind-3.8.1-gdbserver_exit.patch + - valgrind-3.8.1-gdbserver_tests-syscall-template-source.patch + - valgrind-3.8.1-glibc-2.17-18.patch + - valgrind-3.8.1-index-supp.patch + - valgrind-3.8.1-initial-power-isa-207.patch + - valgrind-3.8.1-manpages.patch + - valgrind-3.8.1-memcheck-mc_translate-Iop_8HLto16.patch + - valgrind-3.8.1-mmxext.patch + - valgrind-3.8.1-movntdqa.patch + - valgrind-3.8.1-new-manpages.patch + - valgrind-3.8.1-openat.patch + - valgrind-3.8.1-overlap_memcpy_filter.patch + - valgrind-3.8.1-pie.patch + - valgrind-3.8.1-pkg-config.patch + - valgrind-3.8.1-power-isa-205-deprecation.patch + - valgrind-3.8.1-ppc-32-mode-64-bit-instr.patch + - valgrind-3.8.1-ppc-setxattr.patch + - valgrind-3.8.1-proc-auxv.patch + - valgrind-3.8.1-ptrace-include-configure.patch + - valgrind-3.8.1-ptrace-setgetregset.patch + - valgrind-3.8.1-ptrace-thread-area.patch + - valgrind-3.8.1-regtest-fixlets.patch + - valgrind-3.8.1-s390-STFLE.patch + - valgrind-3.8.1-s390_tsearch_supp.patch + - valgrind-3.8.1-sendmsg-flags.patch + - valgrind-3.8.1-sigill_diag.patch + - valgrind-3.8.1-static-variables.patch + - valgrind-3.8.1-stpncpy.patch + - valgrind-3.8.1-text-segment.patch + - valgrind-3.8.1-wcs.patch + - valgrind-3.8.1-x86_amd64_features-avx.patch + - valgrind-3.8.1-xaddb.patch + - valgrind-3.8.1-zero-size-sections.patch +- Remove special case valgrind-3.8.1-enable-armv5.patch. +- Remove valgrind-3.8.1-x86-backtrace.patch, rely on new upstream fp/cfi + try-cache mechanism. + +* Mon Oct 14 2013 Mark Wielaard - 3.8.1-31 +- Fix multilib issue with HAVE_PTRACE_GETREGS in config.h. + +* Thu Sep 26 2013 Mark Wielaard - 3.8.1-30 +- Add valgrind-3.8.1-index-supp.patch (#1011713) +- Ignore PPC floating point phased out category. (#996927). + +* Wed Sep 25 2013 Mark Wielaard - 3.8.1-29 +- Filter out -mcpu= so tests are compiled with the right flags. (#996927). + +* Mon Sep 23 2013 Mark Wielaard - 3.8.1-28 +- Implement SSE4 MOVNTDQA insn (valgrind-3.8.1-movntdqa.patch) +- Don't BuildRequire /bin/ps, just BuildRequire procps + (procps-ng provides procps). + +* Thu Sep 05 2013 Mark Wielaard - 3.8.1-27 +- Fix power_ISA2_05 testcase (valgrind-3.8.1-power-isa-205-deprecation.patch) +- Fix ppc32 make check build (valgrind-3.8.1-initial-power-isa-207.patch) +- Add valgrind-3.8.1-mmxext.patch + +* Wed Aug 21 2013 Mark Wielaard - 3.8.1-26 +- Allow building against glibc 2.18. (#999169) + +* Thu Aug 15 2013 Mark Wielaard - 3.8.1-25 +- Add valgrind-3.8.1-s390-STFLE.patch + s390 message-security assist (MSA) instruction extension not implemented. + +* Wed Aug 14 2013 Mark Wielaard - 3.8.1-24 +- Add valgrind-3.8.1-power-isa-205-deprecation.patch + Deprecation of some ISA 2.05 POWER6 instructions. +- Fixup auto-foo generation of new manpage doc patch. + +* Wed Aug 14 2013 Mark Wielaard - 3.8.1-23 +- tests/check_isa-2_07_cap should be executable. + +* Tue Aug 13 2013 Mark Wielaard - 3.8.1-22 +- Add valgrind-3.8.1-initial-power-isa-207.patch + Initial ISA 2.07 support for POWER8-tuned libc. + +* Thu Aug 08 2013 Mark Wielaard - 3.8.1-21 +- Don't depend on docdir location and version in openmpi subpackage + description (#993938). +- Enable openmpi subpackage also on arm. + +* Thu Aug 08 2013 Mark Wielaard - 3.8.1-20 +- Add valgrind-3.8.1-ptrace-include-configure.patch (#992847) + +* Sun Aug 04 2013 Fedora Release Engineering - 1:3.8.1-19 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_20_Mass_Rebuild + +* Thu Jul 18 2013 Petr Pisar - 1:3.8.1-18 +- Perl 5.18 rebuild + +* Mon Jul 08 2013 Mark Wielaard - 3.8.1-17 +- Add valgrind-3.8.1-dwarf-anon-enum.patch +- Cleanup valgrind-3.8.1-sigill_diag.patch .orig file changes (#949687). +- Add valgrind-3.8.1-ppc-setxattr.patch +- Add valgrind-3.8.1-new-manpages.patch +- Add valgrind-3.8.1-ptrace-thread-area.patch +- Add valgrind-3.8.1-af-bluetooth.patch + +* Tue May 28 2013 Michael Schwendt - 1:3.8.1-16 +- Provide virtual -static package in -devel subpackage (#609624). + +* Thu Apr 25 2013 Mark Wielaard 3.8.1-15 +- Add valgrind-3.8.1-zero-size-sections.patch. Resolves issues with zero + sized .eh_frame sections on ppc64. + +* Thu Apr 18 2013 Mark Wielaard 3.8.1-14 +- fixup selinux file context when doing a scl build. +- Enable regtest suite on ARM. +- valgrind-3.8.1-abbrev-parsing.patch, drop workaround, enable real fix. +- Fix -Ttext-segment configure check. Enables s390x again. +- BuildRequire ps for testsuite. + +* Tue Apr 02 2013 Mark Wielaard 3.8.1-13 +- Fix quoting in valgrind valgrind-3.8.1-enable-armv5.patch and + remove arm configure hunk from valgrind-3.8.1-text-segment.patch #947440 +- Replace valgrind-3.8.1-text-segment.patch with upstream variant. +- Add valgrind-3.8.1-regtest-fixlets.patch. + +* Wed Mar 20 2013 Mark Wielaard 3.8.1-12 +- Add valgrind-3.8.1-text-segment.patch +- Don't undefine _missing_build_ids_terminate_build. + +* Tue Mar 12 2013 Mark Wielaard 3.8.1-11 +- Add valgrind-3.8.1-manpages.patch + +* Fri Mar 01 2013 Mark Wielaard 3.8.1-10 +- Don't disable -debuginfo package generation, but do undefine + _missing_build_ids_terminate_build. + +* Thu Feb 28 2013 Mark Wielaard 3.8.1-9 +- Replace valgrind-3.8.1-sendmsg-flags.patch with upstream version. + +* Tue Feb 19 2013 Mark Wielaard 3.8.1-8 +- Add valgrind-3.8.1-sendmsg-flags.patch +- Add valgrind-3.8.1-ptrace-setgetregset.patch +- Add valgrind-3.8.1-static-variables.patch + +* Thu Feb 07 2013 Jon Ciesla 1:3.8.1-7 +- Merge review fixes, BZ 226522. + +* Wed Jan 16 2013 Mark Wielaard 3.8.1-6 +- Allow building against glibc-2.17. + +* Sun Nov 4 2012 Mark Wielaard 3.8.1-5 +- Add valgrind-3.8.1-stpncpy.patch (KDE#309427) +- Add valgrind-3.8.1-ppc-32-mode-64-bit-instr.patch (#810992, KDE#308573) +- Add valgrind-3.8.1-sigill_diag.patch (#810992, KDE#309425) + +* Tue Oct 16 2012 Mark Wielaard 3.8.1-4 +- Add valgrind-3.8.1-xaddb.patch (#866793, KDE#307106) + +* Mon Oct 15 2012 Mark Wielaard 3.8.1-3 +- Add valgrind-3.8.1-x86_amd64_features-avx.patch (KDE#307285) +- Add valgrind-3.8.1-gdbserver_tests-syscall-template-source.patch (KDE#307155) +- Add valgrind-3.8.1-overlap_memcpy_filter.patch (KDE#307290) +- Add valgrind-3.8.1-pkg-config.patch (#827219, KDE#307729) +- Add valgrind-3.8.1-proc-auxv.patch (KDE#253519) +- Add valgrind-3.8.1-wcs.patch (#755242, KDE#307828) +- Add valgrind-3.8.1-filter_gdb.patch (KDE#308321) +- Add valgrind-3.8.1-gdbserver_exit.patch (#862795, KDE#308341) +- Add valgrind-3.8.1-aspacemgr_VG_N_SEGs.patch (#730303, KDE#164485) +- Add valgrind-3.8.1-s390_tsearch_supp.patch (#816244, KDE#308427) + +* Fri Sep 21 2012 Mark Wielaard 3.8.1-2 +- Add valgrind-3.8.1-gdbserver_tests-mcinvoke-ppc64.patch +- Replace valgrind-3.8.1-cfi_dw_ops.patch with version as committed upstream. +- Remove erroneous printf change from valgrind-3.8.1-abbrev-parsing.patch. +- Add scalar testcase change to valgrind-3.8.1-capget.patch. + +* Thu Sep 20 2012 Mark Wielaard 3.8.1-1 +- Add partial backport of upstream revision 12884 + valgrind-3.8.0-memcheck-mc_translate-Iop_8HLto16.patch + without it AVX2 VPBROADCASTB insn is broken under memcheck. +- Add valgrind-3.8.0-cfi_dw_ops.patch (KDE#307038) + DWARF2 CFI reader: unhandled DW_OP_ opcode 0x8 (DW_OP_const1u and friends) +- Add valgrind-3.8.0-avx2-prereq.patch. +- Remove accidentially included diffs for gdbserver_tests and helgrind/tests + Makefile.in from valgrind-3.8.0-avx2-bmi-fma.patch.gz +- Remove valgrind-3.8.0-tests.patch tests no longer hang. +- Added SCL macros to support building as part of a Software Collection. +- Upgrade to valgrind 3.8.1. + +* Wed Sep 12 2012 Mark Wielaard 3.8.0-8 +- Add configure fixup valgrind-3.8.0-bmi-conf-check.patch + +* Wed Sep 12 2012 Mark Wielaard 3.8.0-7 +- Add valgrind-3.8.0-avx2-bmi-fma.patch (KDE#305728) + +* Tue Sep 11 2012 Mark Wielaard 3.8.0-6 +- Add valgrind-3.8.0-lzcnt-tzcnt-bugfix.patch (KDE#295808) +- Add valgrind-3.8.0-avx-alignment-check.patch (KDE#305926) + +* Mon Aug 27 2012 Mark Wielaard 3.8.0-5 +- Add valgrind-3.8.0-abbrev-parsing.patch for #849783 (KDE#305513). + +* Sun Aug 19 2012 Mark Wielaard 3.8.0-4 +- Add valgrind-3.8.0-find-buildid.patch workaround bug #849435 (KDE#305431). + +* Wed Aug 15 2012 Jakub Jelinek 3.8.0-3 +- fix up last change + +* Wed Aug 15 2012 Jakub Jelinek 3.8.0-2 +- tweak up to allow simultaneous installation + of valgrind-devel.{i686,x86_64} (#848146) + +* Fri Aug 10 2012 Jakub Jelinek 3.8.0-1 +- update to 3.8.0 release +- from CFLAGS/CXXFLAGS filter just fortification flags, not arch + specific flags +- on i?86 prefer to use CFI over %%ebp unwinding, as GCC 4.6+ + defaults to -fomit-frame-pointer + +* Tue Aug 07 2012 Mark Wielaard 3.8.0-0.1.TEST1.svn12858 +- Update to 3.8.0-TEST1 +- Clear CFLAGS CXXFLAGS LDFLAGS. +- Fix \ line continuation in configure line. + +* Fri Aug 03 2012 Mark Wielaard 3.7.0-7 +- Fixup shadowing warnings valgrind-3.7.0-dwz.patch +- Add valgrind-3.7.0-ref_addr.patch (#842659, KDE#298864) + +* Wed Jul 25 2012 Mark Wielaard 3.7.0-6 +- handle dwz DWARF compressor output (#842659, KDE#302901) +- allow glibc 2.16. + +* Sun Jul 22 2012 Fedora Release Engineering - 1:3.7.0-5 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_18_Mass_Rebuild + +* Mon May 7 2012 Jakub Jelinek 3.7.0-4 +- adjust suppressions so that it works even with ld-2.15.so (#806854) +- handle DW_TAG_unspecified_type and DW_TAG_rvalue_reference_type + (#810284, KDE#278313) +- handle .debug_types sections (#810286, KDE#284124) + +* Sun Mar 4 2012 Peter Robinson 3.7.0-2 +- Fix building on ARM platform + +* Fri Jan 27 2012 Jakub Jelinek 3.7.0-1 +- update to 3.7.0 (#769213, #782910, #772343) +- handle some further SCSI ioctls (#783936) +- handle fcntl F_SETOWN_EX and F_GETOWN_EX (#770746) + +* Wed Aug 17 2011 Adam Jackson 3.6.1-6 +- rebuild for rpm 4.9.1 trailing / bug + +* Thu Jul 21 2011 Jakub Jelinek 3.6.1-5 +- handle PLT unwind info (#723790, KDE#277045) + +* Mon Jun 13 2011 Jakub Jelinek 3.6.1-4 +- fix memcpy/memmove redirection on x86_64 (#705790) + +* Wed Jun 8 2011 Jakub Jelinek 3.6.1-3 +- fix testing against glibc 2.14 + +* Wed Jun 8 2011 Jakub Jelinek 3.6.1-2 +- fix build on ppc64 (#711608) +- don't fail if s390x support patch hasn't been applied, + move testing into %%check (#708522) +- rebuilt against glibc 2.14 + +* Wed Feb 23 2011 Jakub Jelinek 3.6.1-1 +- update to 3.6.1 + +* Mon Feb 07 2011 Fedora Release Engineering - 1:3.6.0-3 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_15_Mass_Rebuild + +* Fri Jan 28 2011 Jakub Jelinek 3.6.0-2 +- rebuilt against glibc 2.13 (#673046) +- hook in pwrite64 syscall on ppc64 (#672858) +- fix PIE handling on ppc/ppc64 (#665289) + +* Fri Nov 12 2010 Jakub Jelinek 3.6.0-1 +- update to 3.6.0 +- add s390x support (#632354) +- provide a replacement for str{,n}casecmp{,_l} (#626470) + +* Tue May 18 2010 Jakub Jelinek 3.5.0-18 +- rebuilt against glibc 2.12 + +* Mon Apr 12 2010 Jakub Jelinek 3.5.0-16 +- change pub_tool_basics.h not to include config.h (#579283) +- add valgrind-openmpi package for OpenMPI support (#565541) +- allow NULL second argument to capget (#450976) + +* Wed Apr 7 2010 Jakub Jelinek 3.5.0-15 +- handle i686 nopw insns with more than one data16 prefix (#574889) +- DWARF4 support +- handle getcpu and splice syscalls + +* Wed Jan 20 2010 Jakub Jelinek 3.5.0-14 +- fix build against latest glibc headers + +* Wed Jan 20 2010 Jakub Jelinek 3.5.0-13 +- DW_OP_mod is unsigned modulus instead of signed +- fix up valgrind.pc (#551277) + +* Mon Dec 21 2009 Jakub Jelinek 3.5.0-12 +- don't require offset field to be set in adjtimex's + ADJ_OFFSET_SS_READ mode (#545866) + +* Wed Dec 2 2009 Jakub Jelinek 3.5.0-10 +- add handling of a bunch of recent syscalls and fix some + other syscall wrappers (Dodji Seketeli) +- handle prelink created split of .bss into .dynbss and .bss + and similarly for .sbss and .sdynbss (#539874) + +* Wed Nov 4 2009 Jakub Jelinek 3.5.0-9 +- rebuilt against glibc 2.11 +- use upstream version of the ifunc support + +* Wed Oct 28 2009 Jakub Jelinek 3.5.0-8 +- add preadv/pwritev syscall support + +* Tue Oct 27 2009 Jakub Jelinek 3.5.0-7 +- add perf_counter_open syscall support (#531271) +- add handling of some sbb/adc insn forms on x86_64 (KDE#211410) + +* Fri Oct 23 2009 Jakub Jelinek 3.5.0-6 +- ppc and ppc64 fixes + +* Thu Oct 22 2009 Jakub Jelinek 3.5.0-5 +- add emulation of 0x67 prefixed loop* insns on x86_64 (#530165) + +* Wed Oct 21 2009 Jakub Jelinek 3.5.0-4 +- handle reading of .debug_frame in addition to .eh_frame +- ignore unknown DWARF3 expressions in evaluate_trivial_GX +- suppress helgrind race errors in helgrind's own mythread_wrapper +- fix compilation of x86 tests on x86_64 and ppc tests + +* Wed Oct 14 2009 Jakub Jelinek 3.5.0-3 +- handle many more DW_OP_* ops that GCC now uses +- handle the more compact form of DW_AT_data_member_location +- don't strip .debug_loc etc. from valgrind binaries + +* Mon Oct 12 2009 Jakub Jelinek 3.5.0-2 +- add STT_GNU_IFUNC support (Dodji Seketeli, #518247) +- wrap inotify_init1 syscall (Dodji Seketeli, #527198) +- fix mmap/mprotect handling in memcheck (KDE#210268) + +* Fri Aug 21 2009 Jakub Jelinek 3.5.0-1 +- update to 3.5.0 + +* Tue Jul 28 2009 Jakub Jelinek 3.4.1-7 +- handle futex ops newly added during last 4 years (#512121) + +* Sun Jul 26 2009 Fedora Release Engineering 3.4.1-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_12_Mass_Rebuild + +* Mon Jul 13 2009 Jakub Jelinek 3.4.1-5 +- add support for DW_CFA_{remember,restore}_state + +* Mon Jul 13 2009 Jakub Jelinek 3.4.1-4 +- handle version 3 .debug_frame, .eh_frame, .debug_info and + .debug_line (#509197) + +* Mon May 11 2009 Jakub Jelinek 3.4.1-3 +- rebuilt against glibc 2.10.1 + +* Wed Apr 22 2009 Jakub Jelinek 3.4.1-2 +- redirect x86_64 ld.so strlen early (#495645) + +* Mon Mar 9 2009 Jakub Jelinek 3.4.1-1 +- update to 3.4.1 + +* Mon Feb 9 2009 Jakub Jelinek 3.4.0-3 +- update to 3.4.0 + +* Wed Apr 16 2008 Jakub Jelinek 3.3.0-3 +- add suppressions for glibc 2.8 +- add a bunch of syscall wrappers (#441709) + +* Mon Mar 3 2008 Jakub Jelinek 3.3.0-2 +- add _dl_start suppression for ppc/ppc64 + +* Mon Mar 3 2008 Jakub Jelinek 3.3.0-1 +- update to 3.3.0 +- split off devel bits into valgrind-devel subpackage + +* Thu Oct 18 2007 Jakub Jelinek 3.2.3-7 +- add suppressions for glibc >= 2.7 + +* Fri Aug 31 2007 Jakub Jelinek 3.2.3-6 +- handle new x86_64 nops (#256801, KDE#148447) +- add support for private futexes (KDE#146781) +- update License tag + +* Fri Aug 3 2007 Jakub Jelinek 3.2.3-5 +- add ppc64-linux symlink in valgrind ppc.rpm, so that when + rpm prefers 32-bit binaries over 64-bit ones 32-bit + /usr/bin/valgrind can find 64-bit valgrind helper binaries + (#249773) +- power5+ and power6 support (#240762) + +* Thu Jun 28 2007 Jakub Jelinek 3.2.3-4 +- pass GDB=%%{_prefix}/gdb to configure to fix default + --db-command (#220840) + +* Wed Jun 27 2007 Jakub Jelinek 3.2.3-3 +- add suppressions for glibc >= 2.6 +- avoid valgrind internal error if io_destroy syscall is + passed a bogus argument + +* Tue Feb 13 2007 Jakub Jelinek 3.2.3-2 +- fix valgrind.pc again + +* Tue Feb 13 2007 Jakub Jelinek 3.2.3-1 +- update to 3.2.3 + +* Wed Nov 8 2006 Jakub Jelinek 3.2.1-7 +- some cachegrind improvements (Ulrich Drepper) + +* Mon Nov 6 2006 Jakub Jelinek 3.2.1-6 +- fix valgrind.pc (#213149) +- handle Intel Core2 cache sizes in cachegrind (Ulrich Drepper) + +* Wed Oct 25 2006 Jakub Jelinek 3.2.1-5 +- fix valgrind on ppc/ppc64 where PAGESIZE is 64K (#211598) + +* Sun Oct 1 2006 Jakub Jelinek 3.2.1-4 +- adjust for glibc-2.5 + +* Wed Sep 27 2006 Jakub Jelinek 3.2.1-3 +- another DW_CFA_set_loc handling fix + +* Tue Sep 26 2006 Jakub Jelinek 3.2.1-2 +- fix openat handling (#208097) +- fix DW_CFA_set_loc handling + +* Tue Sep 19 2006 Jakub Jelinek 3.2.1-1 +- update to 3.2.1 bugfix release + - SSE3 emulation fixes, reduce memcheck false positive rate, + 4 dozens of bugfixes + +* Mon Aug 21 2006 Jakub Jelinek 3.2.0-5 +- handle the new i686/x86_64 nops (#203273) + +* Fri Jul 28 2006 Jeremy Katz - 1:3.2.0-4 +- rebuild to bring ppc back + +* Wed Jul 12 2006 Jesse Keating - 1:3.2.0-3.1 +- rebuild + +* Fri Jun 16 2006 Jakub Jelinek 3.2.0-3 +- handle [sg]et_robust_list syscall on ppc{32,64} + +* Fri Jun 16 2006 Jakub Jelinek 3.2.0-2 +- fix ppc64 symlink to 32-bit valgrind libdir +- handle a few extra ppc64 syscalls + +* Thu Jun 15 2006 Jakub Jelinek 3.2.0-1 +- update to 3.2.0 + - ppc64 support + +* Fri May 26 2006 Jakub Jelinek 3.1.1-3 +- handle [sg]et_robust_list syscalls on i?86/x86_64 +- handle *at syscalls on ppc +- ensure on x86_64 both 32-bit and 64-bit glibc{,-devel} are + installed in the buildroot (#191820) + +* Wed Apr 12 2006 Jakub Jelinek 3.1.1-2 +- handle many syscalls that were unhandled before, especially on ppc + +* Mon Apr 3 2006 Jakub Jelinek 3.1.1-1 +- upgrade to 3.1.1 + - many bugfixes + +* Mon Mar 13 2006 Jakub Jelinek 3.1.0-2 +- add support for DW_CFA_val_offset{,_sf}, DW_CFA_def_cfa_sf + and skip over DW_CFA_val_expression quietly +- adjust libc/ld.so filenames in glibc-2.4.supp for glibc 2.4 + release + +* Mon Jan 9 2006 Jakub Jelinek 3.1.0-1 +- upgrade to 3.1.0 (#174582) + - many bugfixes, ppc32 support + +* Thu Oct 13 2005 Jakub Jelinek 3.0.1-2 +- remove Obsoletes for valgrind-callgrind, as it has been + ported to valgrind 3.0.x already + +* Sun Sep 11 2005 Jakub Jelinek 3.0.1-1 +- upgrade to 3.0.1 + - many bugfixes +- handle xattr syscalls on x86-64 (Ulrich Drepper) + +* Fri Aug 12 2005 Jakub Jelinek 3.0.0-3 +- fix amd64 handling of cwtd instruction +- fix amd64 handling of e.g. sarb $0x4,val(%%rip) +- speedup amd64 insn decoding + +* Fri Aug 12 2005 Jakub Jelinek 3.0.0-2 +- lower x86_64 stage2 base from 112TB down to 450GB, so that + valgrind works even on 2.4.x kernels. Still way better than + 1.75GB that stock valgrind allows + +* Fri Aug 12 2005 Jakub Jelinek 3.0.0-1 +- upgrade to 3.0.0 + - x86_64 support +- temporarily obsolete valgrind-callgrind, as it has not been + ported yet + +* Tue Jul 12 2005 Jakub Jelinek 2.4.0-3 +- build some insn tests with -mmmx, -msse or -msse2 (#161572) +- handle glibc-2.3.90 the same way as 2.3.[0-5] + +* Wed Mar 30 2005 Jakub Jelinek 2.4.0-2 +- resurrect the non-upstreamed part of valgrind_h patch +- remove 2.1.2-4G patch, seems to be upstreamed +- resurrect passing -fno-builtin in memcheck tests + +* Sun Mar 27 2005 Colin Walters 2.4.0-1 +- New upstream version +- Update valgrind-2.2.0-regtest.patch to 2.4.0; required minor + massaging +- Disable valgrind-2.1.2-4G.patch for now; Not going to touch this, + and Fedora does not ship 4G kernel by default anymore +- Remove upstreamed valgrind-2.2.0.ioctls.patch +- Remove obsolete valgrind-2.2.0-warnings.patch; Code is no longer + present +- Remove upstreamed valgrind-2.2.0-valgrind_h.patch +- Remove obsolete valgrind-2.2.0-unnest.patch and + valgrind-2.0.0-pthread-stacksize.patch; valgrind no longer + includes its own pthread library + +* Thu Mar 17 2005 Jakub Jelinek 2.2.0-10 +- rebuilt with GCC 4 + +* Tue Feb 8 2005 Jakub Jelinek 2.2.0-8 +- avoid unnecessary use of nested functions for pthread_once + cleanup + +* Mon Dec 6 2004 Jakub Jelinek 2.2.0-7 +- update URL (#141873) + +* Tue Nov 16 2004 Jakub Jelinek 2.2.0-6 +- act as if NVALGRIND is defined when using + in non-m32/i386 programs (#138923) +- remove weak from VALGRIND_PRINTF*, make it static and + add unused attribute + +* Mon Nov 8 2004 Jakub Jelinek 2.2.0-4 +- fix a printout and possible problem with local variable + usage around setjmp (#138254) + +* Tue Oct 5 2004 Jakub Jelinek 2.2.0-3 +- remove workaround for buggy old makes (#134563) + +* Fri Oct 1 2004 Jakub Jelinek 2.2.0-2 +- handle some more ioctls (Peter Jones, #131967) + +* Thu Sep 2 2004 Jakub Jelinek 2.2.0-1 +- update to 2.2.0 + +* Thu Jul 22 2004 Jakub Jelinek 2.1.2-3 +- fix packaging of documentation + +* Tue Jul 20 2004 Jakub Jelinek 2.1.2-2 +- allow tracing of 32-bit binaries on x86-64 + +* Tue Jul 20 2004 Jakub Jelinek 2.1.2-1 +- update to 2.1.2 +- run make regtest as part of package build +- use glibc-2.3 suppressions instead of glibc-2.2 suppressions + +* Thu Apr 29 2004 Colin Walters 2.0.0-1 +- update to 2.0.0 + +* Tue Feb 25 2003 Jeff Johnson 1.9.4-0.20030228 +- update to 1.9.4 from CVS. +- dwarf patch from Graydon Hoare. +- sysinfo patch from Graydon Hoare, take 1. + +* Fri Feb 14 2003 Jeff Johnson 1.9.3-6.20030207 +- add return codes to syscalls. +- fix: set errno after syscalls. + +* Tue Feb 11 2003 Graydon Hoare 1.9.3-5.20030207 +- add handling for separate debug info (+fix). +- handle blocking readv/writev correctly. +- comment out 4 overly zealous pthread checks. + +* Tue Feb 11 2003 Jeff Johnson 1.9.3-4.20030207 +- move _pthread_desc to vg_include.h. +- implement pthread_mutex_timedlock(). +- implement pthread_barrier_wait(). + +* Mon Feb 10 2003 Jeff Johnson 1.9.3-3.20030207 +- import all(afaik) missing functionality from linuxthreads. + +* Sun Feb 9 2003 Jeff Johnson 1.9.3-2.20030207 +- import more missing functionality from linuxthreads in glibc-2.3.1. + +* Sat Feb 8 2003 Jeff Johnson 1.9.3-1.20030207 +- start fixing nptl test cases. + +* Fri Feb 7 2003 Jeff Johnson 1.9.3-0.20030207 +- build against current 1.9.3 with nptl hacks. + +* Tue Oct 15 2002 Alexander Larsson +- Update to 1.0.4 + +* Fri Aug 9 2002 Alexander Larsson +- Update to 1.0.0 + +* Wed Jul 3 2002 Alexander Larsson +- Update to pre4. + +* Tue Jun 18 2002 Alexander Larsson +- Add threadkeys and extra suppressions patches. Bump epoch. + +* Mon Jun 17 2002 Alexander Larsson +- Updated to 1.0pre1 + +* Tue May 28 2002 Alex Larsson +- Updated to 20020524. Added GLIBC_PRIVATE patch + +* Thu May 9 2002 Jonathan Blandford +- add missing symbol __pthread_clock_settime + +* Wed May 8 2002 Alex Larsson +- Update to 20020508 + +* Mon May 6 2002 Alex Larsson +- Update to 20020503b + +* Thu May 2 2002 Alex Larsson +- update to new snapshot + +* Mon Apr 29 2002 Alex Larsson 20020428-1 +- update to new snapshot + +* Fri Apr 26 2002 Jeremy Katz 20020426-1 +- update to new snapshot + +* Thu Apr 25 2002 Alex Larsson 20020424-5 +- Added stack patch. Commented out other patches. + +* Wed Apr 24 2002 Nalin Dahyabhai 20020424-4 +- filter out GLIBC_PRIVATE requires, add preload patch + +* Wed Apr 24 2002 Alex Larsson 20020424-3 +- Make glibc 2.2 and XFree86 4 the default supressions + +* Wed Apr 24 2002 Alex Larsson 20020424-2 +- Added patch that includes atomic.h + +* Wed Apr 24 2002 Alex Larsson 20020424-1 +- Initial build