From 4f0b04ae746ccb2a848292027defef48873b2598 Mon Sep 17 00:00:00 2001

From: Carl Love <carll@us.ibm.com>

Date: Tue, 8 Jul 2014 10:37:46 -0500

Subject: [PATCH] POWER PC, add initial Little Endian support

The IBM POWER processor now supports both Big Endian and Little Endian.

This patch renames the #defines with the name ppc64 to ppc64be for the BE

specific code.  This patch adds the Little Endian #define ppc64le to the

Additionally, a few functions are renamed to remove BE from the name if the

function is used by BE and LE. Functions that are BE specific have BE put

in the name.

The goals of this patch is to make sure #defines, function names and

variables consistently use PPC64/ppc64 if it refers to BE and LE,

PPC64BE/ppc64be if it is specific to BE, PPC64LE/ppc64le if it is LE

specific.  The patch does not break the code for PPC64 Big Endian.

The patch removes the BASH specific use of "BASH_SOURCE[0]" in

tests/check_isa-2_06_cap and tests/check_isa-2_07 as it is not portable

across other shells.

Signed-off-by: Carl Love <carll@us.ibm.com>

---

 Makefile.all.am                             |  23 +-

 Makefile.tool.am                            |  21 +-

 VEX/priv/guest_ppc_toIR.c                   | 356 ++++++++++++++--------------

 cachegrind/cg_arch.c                        |   2 +-

 cachegrind/cg_branchpred.c                  |   2 +-

 configure.ac                                |  57 ++++-

 coregrind/launcher-darwin.c                 |  10 +-

 coregrind/launcher-linux.c                  |   4 +-

 coregrind/m_aspacemgr/aspacemgr-common.c    |   3 +-

 coregrind/m_cache.c                         |   3 +-

 coregrind/m_coredump/coredump-elf.c         |   4 +-

 coregrind/m_debugger.c                      |   2 +-

 coregrind/m_debuginfo/d3basics.c            |   5 +-

 coregrind/m_debuginfo/debuginfo.c           |  15 +-

 coregrind/m_debuginfo/priv_storage.h        |   2 +-

 coregrind/m_debuginfo/readdwarf.c           |  15 +-

 coregrind/m_debuginfo/readelf.c             |  47 ++--

 coregrind/m_debuginfo/readmacho.c           |   4 +-

 coregrind/m_debuginfo/storage.c             |   2 +-

 coregrind/m_debuglog.c                      |   2 +-

 coregrind/m_dispatch/dispatch-ppc64-linux.S |   6 +-

 coregrind/m_gdbserver/target.c              |   2 +-

 coregrind/m_initimg/initimg-linux.c         |  18 +-

 coregrind/m_libcassert.c                    |   2 +-

 coregrind/m_libcfile.c                      |  25 +-

 coregrind/m_libcproc.c                      |   6 +-

 coregrind/m_libcsetjmp.c                    |   4 +-

 coregrind/m_machine.c                       |  26 +-

 coregrind/m_main.c                          |  19 +-

 coregrind/m_redir.c                         |   2 +-

 coregrind/m_scheduler/scheduler.c           |   4 +-

 coregrind/m_sigframe/sigframe-ppc64-linux.c |   4 +-

 coregrind/m_signals.c                       |   4 +-

 coregrind/m_stacktrace.c                    |  13 +-

 coregrind/m_syscall.c                       |   4 +-

 coregrind/m_syswrap/priv_types_n_macros.h   |   3 +-

 coregrind/m_syswrap/syscall-ppc64-linux.S   |   4 +-

 coregrind/m_syswrap/syswrap-linux.c         |   8 +-

 coregrind/m_syswrap/syswrap-main.c          |  12 +-

 coregrind/m_syswrap/syswrap-ppc64-linux.c   |   4 +-

 coregrind/m_trampoline.S                    |   2 +-

 coregrind/m_translate.c                     |  16 +-

 coregrind/m_ume/elf.c                       |   6 +-

 coregrind/m_ume/macho.c                     |   4 +-

 coregrind/m_vki.c                           |   4 +-

 coregrind/pub_core_aspacemgr.h              |   3 +-

 coregrind/pub_core_basics.h                 |   2 +-

 coregrind/pub_core_debuginfo.h              |   2 +-

 coregrind/pub_core_machine.h                |   8 +-

 coregrind/pub_core_mallocfree.h             |  15 +-

 coregrind/pub_core_threadstate.h            |   2 +-

 coregrind/pub_core_trampoline.h             |   2 +-

 coregrind/pub_core_transtab_asm.h           |   4 +-

 coregrind/vgdb-invoker-ptrace.c             |   6 +-

 drd/drd_bitmap.h                            |   4 +-

 drd/drd_load_store.c                        |   2 +-

 drd/tests/unit_bitmap.c                     |   3 +-

 helgrind/tests/annotate_hbefore.c           |   2 +-

 include/pub_tool_basics.h                   |   7 +-

 include/pub_tool_libcsetjmp.h               |   2 +-

 include/pub_tool_machine.h                  |   2 +-

 include/pub_tool_vkiscnums_asm.h            |   2 +-

 include/valgrind.h                          |  22 +-

 include/vki/vki-linux.h                     |   4 +-

 memcheck/mc_machine.c                       |   7 +-

 memcheck/tests/atomic_incs.c                |   8 +-

 memcheck/tests/unit_libcbase.c              |   3 +-

 tests/Makefile.am                           |   3 +-

 tests/arch_test.c                           |   2 +-

 tests/check_isa-2_06_cap                    |   2 +-

 tests/check_isa-2_07_cap                    |   2 +-

 tests/is_ppc64_BE.c                         |  14 ++

 tests/power_insn_available.c                |   6 +-

 73 files changed, 506 insertions(+), 416 deletions(-)

 create mode 100644 tests/is_ppc64_BE.c

diff --git a/Makefile.all.am b/Makefile.all.am

index 0d30ed5..f0b638d 100644

--- a/Makefile.all.am

+++ b/Makefile.all.am

@@ -229,15 +229,16 @@ if VGCONF_PLATVARIANT_IS_ANDROID

 PRELOAD_LDFLAGS_COMMON_LINUX += -nostdlib

 endif

-PRELOAD_LDFLAGS_X86_LINUX    = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

-PRELOAD_LDFLAGS_AMD64_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

-PRELOAD_LDFLAGS_PPC32_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

-PRELOAD_LDFLAGS_PPC64_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

-PRELOAD_LDFLAGS_ARM_LINUX    = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

-PRELOAD_LDFLAGS_ARM64_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

-PRELOAD_LDFLAGS_X86_DARWIN   = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386

-PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64

-PRELOAD_LDFLAGS_S390X_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

-PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

-PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+PRELOAD_LDFLAGS_X86_LINUX      = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

+PRELOAD_LDFLAGS_AMD64_LINUX    = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+PRELOAD_LDFLAGS_PPC32_LINUX    = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

+PRELOAD_LDFLAGS_PPC64BE_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+PRELOAD_LDFLAGS_PPC64LE_LINUX  = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+PRELOAD_LDFLAGS_ARM_LINUX      = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

+PRELOAD_LDFLAGS_ARM64_LINUX    = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+PRELOAD_LDFLAGS_X86_DARWIN     = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386

+PRELOAD_LDFLAGS_AMD64_DARWIN   = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64

+PRELOAD_LDFLAGS_S390X_LINUX    = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+PRELOAD_LDFLAGS_MIPS32_LINUX   = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@

+PRELOAD_LDFLAGS_MIPS64_LINUX   = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@

diff --git a/Makefile.tool.am b/Makefile.tool.am

index 6e15ce4..458d5ee 100644

--- a/Makefile.tool.am

+++ b/Makefile.tool.am

@@ -46,7 +46,10 @@ TOOL_LDFLAGS_AMD64_LINUX = \

 TOOL_LDFLAGS_PPC32_LINUX = \

 	$(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

-TOOL_LDFLAGS_PPC64_LINUX = \

+TOOL_LDFLAGS_PPC64BE_LINUX = \

+	$(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

+

+TOOL_LDFLAGS_PPC64LE_LINUX = \

 	$(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 TOOL_LDFLAGS_ARM_LINUX = \

@@ -102,8 +105,11 @@ LIBREPLACEMALLOC_AMD64_LINUX = \

 LIBREPLACEMALLOC_PPC32_LINUX = \

 	$(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a

-LIBREPLACEMALLOC_PPC64_LINUX = \

-	$(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a

+LIBREPLACEMALLOC_PPC64BE_LINUX = \

+	$(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64be-linux.a

+

+LIBREPLACEMALLOC_PPC64LE_LINUX = \

+	$(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64le-linux.a

 LIBREPLACEMALLOC_ARM_LINUX = \

 	$(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a

@@ -141,9 +147,14 @@ LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \

 	$(LIBREPLACEMALLOC_PPC32_LINUX) \

 	-Wl,--no-whole-archive

-LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \

+LIBREPLACEMALLOC_LDFLAGS_PPC64BE_LINUX = \

+	-Wl,--whole-archive \

+	$(LIBREPLACEMALLOC_PPC64BE_LINUX) \

+	-Wl,--no-whole-archive

+

+LIBREPLACEMALLOC_LDFLAGS_PPC64LE_LINUX = \

 	-Wl,--whole-archive \

-	$(LIBREPLACEMALLOC_PPC64_LINUX) \

+	$(LIBREPLACEMALLOC_PPC64LE_LINUX) \

 	-Wl,--no-whole-archive

 LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c

index d39debf..e0031a3 100644

--- a/VEX/priv/guest_ppc_toIR.c

+++ b/VEX/priv/guest_ppc_toIR.c

@@ -144,6 +144,7 @@

 #include "guest_ppc_defs.h"

+#define IENDIANESS   Iend_BE

 /*------------------------------------------------------------*/

 /*--- Globals                                              ---*/

 /*------------------------------------------------------------*/

@@ -503,9 +504,9 @@ static ULong extend_s_32to64 ( UInt x )

    return (ULong)((((Long)x) << 32) >> 32);

 }

-/* Do a big-endian load of a 32-bit word, regardless of the endianness

+/* Do a proper-endian load of a 32-bit word, regardless of the endianness

    of the underlying host. */

-static UInt getUIntBigendianly ( UChar* p )

+static UInt getUIntPPCendianly ( UChar* p )

 {

    UInt w = 0;

    w = (w << 8) | p[0];

@@ -526,11 +527,11 @@ static void assign ( IRTemp dst, IRExpr* e )

 }

 /* This generates a normal (non store-conditional) store. */

-static void storeBE ( IRExpr* addr, IRExpr* data )

+static void store ( IRExpr* addr, IRExpr* data )

 {

    IRType tyA = typeOfIRExpr(irsb->tyenv, addr);

    vassert(tyA == Ity_I32 || tyA == Ity_I64);

-   stmt( IRStmt_Store(Iend_BE, addr, data) );

+   stmt( IRStmt_Store(IENDIANESS, addr, data) );

 }

 static IRExpr* unop ( IROp op, IRExpr* a )

@@ -586,9 +587,9 @@ static IRExpr* mkV128 ( UShort i )

 }

 /* This generates a normal (non load-linked) load. */

-static IRExpr* loadBE ( IRType ty, IRExpr* addr )

+static IRExpr* load ( IRType ty, IRExpr* addr )

 {

-   return IRExpr_Load(Iend_BE, ty, addr);

+   return IRExpr_Load(IENDIANESS, ty, addr);

 }

 static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 )

@@ -4758,7 +4759,7 @@ static Bool dis_int_load ( UInt theInstr )

    switch (opc1) {

    case 0x22: // lbz (Load B & Zero, PPC32 p433)

       DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I8, mkexpr(EA));

+      val = load(Ity_I8, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom8(ty, val, False) );

       break;

@@ -4768,14 +4769,14 @@ static Bool dis_int_load ( UInt theInstr )

          return False;

       }

       DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I8, mkexpr(EA));

+      val = load(Ity_I8, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom8(ty, val, False) );

       putIReg( rA_addr, mkexpr(EA) );

       break;

    case 0x2A: // lha (Load HW Alg, PPC32 p445)

       DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I16, mkexpr(EA));

+      val = load(Ity_I16, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom16(ty, val, True) );

       break;

@@ -4785,14 +4786,14 @@ static Bool dis_int_load ( UInt theInstr )

          return False;

       }

       DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I16, mkexpr(EA));

+      val = load(Ity_I16, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom16(ty, val, True) );

       putIReg( rA_addr, mkexpr(EA) );

       break;

    case 0x28: // lhz (Load HW & Zero, PPC32 p450)

       DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I16, mkexpr(EA));

+      val = load(Ity_I16, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom16(ty, val, False) );

       break;

@@ -4802,14 +4803,14 @@ static Bool dis_int_load ( UInt theInstr )

          return False;

       }

       DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I16, mkexpr(EA));

+      val = load(Ity_I16, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom16(ty, val, False) );

       putIReg( rA_addr, mkexpr(EA) );

       break;

    case 0x20: // lwz (Load W & Zero, PPC32 p460)

       DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I32, mkexpr(EA));

+      val = load(Ity_I32, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom32(ty, val, False) );

       break;

@@ -4819,7 +4820,7 @@ static Bool dis_int_load ( UInt theInstr )

          return False;

       }

       DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);

-      val = loadBE(Ity_I32, mkexpr(EA));

+      val = load(Ity_I32, mkexpr(EA));

       putIReg( rD_addr, mkWidenFrom32(ty, val, False) );

       putIReg( rA_addr, mkexpr(EA) );

       break;

@@ -4838,14 +4839,14 @@ static Bool dis_int_load ( UInt theInstr )

             vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n");

             return False;

          }

-         val = loadBE(Ity_I8, mkexpr(EA));

+         val = load(Ity_I8, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom8(ty, val, False) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436)

          DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I8, mkexpr(EA));

+         val = load(Ity_I8, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom8(ty, val, False) );

          break;

@@ -4855,14 +4856,14 @@ static Bool dis_int_load ( UInt theInstr )

             return False;

          }

          DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I16, mkexpr(EA));

+         val = load(Ity_I16, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom16(ty, val, True) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448)

          DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I16, mkexpr(EA));

+         val = load(Ity_I16, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom16(ty, val, True) );

          break;

@@ -4872,14 +4873,14 @@ static Bool dis_int_load ( UInt theInstr )

             return False;

          }

          DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I16, mkexpr(EA));

+         val = load(Ity_I16, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom16(ty, val, False) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453)

          DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I16, mkexpr(EA));

+         val = load(Ity_I16, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom16(ty, val, False) );

          break;

@@ -4889,14 +4890,14 @@ static Bool dis_int_load ( UInt theInstr )

             return False;

          }

          DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I32, mkexpr(EA));

+         val = load(Ity_I32, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom32(ty, val, False) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463)

          DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         val = loadBE(Ity_I32, mkexpr(EA));

+         val = load(Ity_I32, mkexpr(EA));

          putIReg( rD_addr, mkWidenFrom32(ty, val, False) );

          break;

@@ -4908,13 +4909,13 @@ static Bool dis_int_load ( UInt theInstr )

             return False;

          }

          DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );

+         putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x015: // ldx (Load DWord, Indexed, PPC64 p476)

          DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );

+         putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );

          break;

       case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501)

@@ -4924,14 +4925,14 @@ static Bool dis_int_load ( UInt theInstr )

          }

          DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

          putIReg( rD_addr,

-                  unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );

+                  unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502)

          DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

          putIReg( rD_addr,

-                  unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );

+                  unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );

          break;

       default:

@@ -4946,7 +4947,7 @@ static Bool dis_int_load ( UInt theInstr )

       switch ((b1<<1) | b0) {

       case 0x0: // ld (Load DWord, PPC64 p472)

          DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);

-         putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );

+         putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );

          break;

       case 0x1: // ldu (Load DWord, Update, PPC64 p474)

@@ -4955,14 +4956,14 @@ static Bool dis_int_load ( UInt theInstr )

             return False;

          }

          DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);

-         putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );

+         putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );

          putIReg( rA_addr, mkexpr(EA) );

          break;

       case 0x2: // lwa (Load Word Alg, PPC64 p499)

          DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);

          putIReg( rD_addr,

-                  unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );

+                  unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );

          break;

       default:

@@ -4981,17 +4982,17 @@ static Bool dis_int_load ( UInt theInstr )

        */

       // trap if EA misaligned on 16 byte address

       if (mode64) {

-         assign(high, loadBE(ty, mkexpr( EA ) ) );

-         assign(low, loadBE(ty, binop( Iop_Add64,

-                                       mkexpr( EA ),

-                                       mkU64( 8 ) ) ) );

+         assign(high, load(ty, mkexpr( EA ) ) );

+         assign(low, load(ty, binop( Iop_Add64,

+                                     mkexpr( EA ),

+                                     mkU64( 8 ) ) ) );

       } else {

-         assign(high, loadBE(ty, binop( Iop_Add32,

-                                        mkexpr( EA ),

-                                        mkU32( 4 ) ) ) );

-         assign(low, loadBE(ty, binop( Iop_Add32,

-                                        mkexpr( EA ),

-                                        mkU32( 12 ) ) ) );

+         assign(high, load(ty, binop( Iop_Add32,

+                                      mkexpr( EA ),

+                                      mkU32( 4 ) ) ) );

+         assign(low, load(ty, binop( Iop_Add32,

+                                      mkexpr( EA ),

+                                      mkU32( 12 ) ) ) );

       }

       gen_SIGBUS_if_misaligned( EA, 16 );

       putIReg( rD_addr,  mkexpr( high) );

@@ -5046,7 +5047,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

    switch (opc1) {

    case 0x26: // stb (Store B, PPC32 p509)

       DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

-      storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

+      store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

       break;

    case 0x27: // stbu (Store B, Update, PPC32 p510)

@@ -5056,12 +5057,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

       }

       DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

       putIReg( rA_addr, mkexpr(EA) );

-      storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

+      store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

       break;

    case 0x2C: // sth (Store HW, PPC32 p522)

       DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

-      storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

+      store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

       break;

    case 0x2D: // sthu (Store HW, Update, PPC32 p524)

@@ -5071,12 +5072,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

       }

       DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

       putIReg( rA_addr, mkexpr(EA) );

-      storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

+      store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

       break;

    case 0x24: // stw (Store W, PPC32 p530)

       DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

-      storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

+      store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

       break;

    case 0x25: // stwu (Store W, Update, PPC32 p534)

@@ -5086,7 +5087,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

       }

       DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

       putIReg( rA_addr, mkexpr(EA) );

-      storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

+      store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

       break;

    /* X Form : all these use EA_indexed */

@@ -5104,12 +5105,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

          }

          DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          putIReg( rA_addr, mkexpr(EA) );

-         storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

+         store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

          break;

       case 0x0D7: // stbx (Store B Indexed, PPC32 p512)

          DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

-         storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

+         store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );

          break;

       case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525)

@@ -5119,12 +5120,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

          }

          DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          putIReg( rA_addr, mkexpr(EA) );

-         storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

+         store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

          break;

       case 0x197: // sthx (Store HW Indexed, PPC32 p526)

          DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

-         storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

+         store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );

          break;

       case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535)

@@ -5134,12 +5135,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

          }

          DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          putIReg( rA_addr, mkexpr(EA) );

-         storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

+         store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

          break;

       case 0x097: // stwx (Store W Indexed, PPC32 p536)

          DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

-         storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

+         store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );

          break;

@@ -5151,12 +5152,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

          }

          DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          putIReg( rA_addr, mkexpr(EA) );

-         storeBE( mkexpr(EA), mkexpr(rS) );

+         store( mkexpr(EA), mkexpr(rS) );

          break;

       case 0x095: // stdx (Store DWord Indexed, PPC64 p585)

          DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

-         storeBE( mkexpr(EA), mkexpr(rS) );

+         store( mkexpr(EA), mkexpr(rS) );

          break;

       default:

@@ -5174,7 +5175,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

             return False;

          DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

-         storeBE( mkexpr(EA), mkexpr(rS) );

+         store( mkexpr(EA), mkexpr(rS) );

          break;

       case 0x1: // stdu (Store DWord, Update, PPC64 p583)

@@ -5183,7 +5184,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

          DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

          putIReg( rA_addr, mkexpr(EA) );

-         storeBE( mkexpr(EA), mkexpr(rS) );

+         store( mkexpr(EA), mkexpr(rS) );

          break;

       case 0x2: { // stq (Store QuadWord, Update, PPC64 p583)

@@ -5205,9 +5206,9 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )

             assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) );

          }

          putIReg( rA_addr, mkexpr(EA_hi) );

-         storeBE( mkexpr(EA_hi), mkexpr(rS) );

+         store( mkexpr(EA_hi), mkexpr(rS) );

          putIReg( rA_addr, mkexpr( EA_lo) );

-         storeBE( mkexpr(EA_lo), getIReg( rS_addr+1 ) );

+         store( mkexpr(EA_lo), getIReg( rS_addr+1 ) );

          break;

       }

       default:

@@ -5256,7 +5257,7 @@ static Bool dis_int_ldst_mult ( UInt theInstr )

       DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);

       for (r = rD_addr; r <= 31; r++) {

          irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));

-         putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ),

+         putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr ),

                                        False) );

          ea_off += 4;

       }

@@ -5266,7 +5267,7 @@ static Bool dis_int_ldst_mult ( UInt theInstr )

       DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

       for (r = rS_addr; r <= 31; r++) {

          irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));

-         storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) );

+         store( irx_addr, mkNarrowTo32(ty, getIReg(r)) );

          ea_off += 4;

       }

       break;

@@ -5321,8 +5322,9 @@ void generate_lsw_sequence ( IRTemp tNBytes,   // # bytes, :: Ity_I32

                   Iop_Shl32, 

                   unop(

                      Iop_8Uto32, 

-                     loadBE(Ity_I8, 

-                            binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)))

+                     load( Ity_I8,

+                           binop( mkSzOp(ty,Iop_Add8),

+                                  e_EA, mkSzImm(ty,i)))

                   ), 

                   mkU8(toUChar(shift))

                )

@@ -5360,12 +5362,12 @@ void generate_stsw_sequence ( IRTemp tNBytes,   // # bytes, :: Ity_I32

       }

       /* *(EA+i) = 32to8(rS >> shift) */

       vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);

-      storeBE(

-         binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)),

-         unop(Iop_32to8,

-              binop(Iop_Shr32,

-                    mkNarrowTo32(ty, getIReg(rS)),

-                    mkU8(toUChar(shift))))

+      store(

+            binop( mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)),

+            unop( Iop_32to8,

+                  binop( Iop_Shr32,

+                         mkNarrowTo32( ty, getIReg(rS) ),

+                         mkU8( toUChar(shift) )))

       );

       shift -= 8;

    }

@@ -5404,10 +5406,10 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )

          /* Special case hack */

          /* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */

          putIReg( rD_addr,          

-                  loadBE(Ity_I32, mkexpr(t_EA)) );

+                  load(Ity_I32, mkexpr(t_EA)) );

          putIReg( (rD_addr+1) % 32, 

-                  loadBE(Ity_I32,

-                         binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );

+                  load(Ity_I32,

+                       binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );

       } else {

          t_nbytes = newTemp(Ity_I32);

          assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );

@@ -5439,10 +5441,10 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )

       if (NumBytes == 8 && !mode64) {

          /* Special case hack */

          /* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */

-         storeBE( mkexpr(t_EA), 

-                  getIReg(rD_addr) );

-         storeBE( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)), 

-                  getIReg((rD_addr+1) % 32) );

+         store( mkexpr(t_EA),

+                getIReg(rD_addr) );

+         store( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),

+                getIReg((rD_addr+1) % 32) );

       } else {

          t_nbytes = newTemp(Ity_I32);

          assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );

@@ -6145,7 +6147,7 @@ static Bool dis_memsync ( UInt theInstr )

          // and actually do the load

          res = newTemp(Ity_I32);

-         stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) );

+         stmt( IRStmt_LLSC(IENDIANESS, res, mkexpr(EA), NULL/*this is a load*/) );

          putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) );

          break;

@@ -6171,7 +6173,7 @@ static Bool dis_memsync ( UInt theInstr )

          // Do the store, and get success/failure bit into resSC

          resSC = newTemp(Ity_I1);

-         stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) );

+         stmt( IRStmt_LLSC(IENDIANESS, resSC, mkexpr(EA), mkexpr(rS)) );

          // Set CR0[LT GT EQ S0] = 0b000 || XER[SO]  on failure

          // Set CR0[LT GT EQ S0] = 0b001 || XER[SO]  on success

@@ -6238,7 +6240,7 @@ static Bool dis_memsync ( UInt theInstr )

          // and actually do the load

          res = newTemp(Ity_I64);

-         stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) );

+         stmt( IRStmt_LLSC(IENDIANESS, res, mkexpr(EA), NULL/*this is a load*/) );

          putIReg( rD_addr, mkexpr(res) );

          break;

@@ -6264,7 +6266,7 @@ static Bool dis_memsync ( UInt theInstr )

          // Do the store, and get success/failure bit into resSC

          resSC = newTemp(Ity_I1);

-         stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) );

+         stmt( IRStmt_LLSC(IENDIANESS, resSC, mkexpr(EA), mkexpr(rS)) );

          // Set CR0[LT GT EQ S0] = 0b000 || XER[SO]  on failure

          // Set CR0[LT GT EQ S0] = 0b001 || XER[SO]  on success

@@ -6294,16 +6296,16 @@ static Bool dis_memsync ( UInt theInstr )

          // and actually do the load

          if (mode64) {

-            stmt( IRStmt_LLSC( Iend_BE, res_hi,

+            stmt( IRStmt_LLSC( IENDIANESS, res_hi,

                                mkexpr(EA), NULL/*this is a load*/) );

-            stmt( IRStmt_LLSC( Iend_BE, res_lo,

+            stmt( IRStmt_LLSC( IENDIANESS, res_lo,

                                binop(Iop_Add64, mkexpr(EA), mkU64(8) ),

                                NULL/*this is a load*/) );

          } else {

-            stmt( IRStmt_LLSC( Iend_BE, res_hi,

+            stmt( IRStmt_LLSC( IENDIANESS, res_hi,

                                binop( Iop_Add32, mkexpr(EA), mkU32(4) ),

                                NULL/*this is a load*/) );

-            stmt( IRStmt_LLSC( Iend_BE, res_lo,

+            stmt( IRStmt_LLSC( IENDIANESS, res_lo,

                                binop( Iop_Add32, mkexpr(EA), mkU32(12) ),

                                NULL/*this is a load*/) );

          }

@@ -6334,14 +6336,14 @@ static Bool dis_memsync ( UInt theInstr )

          resSC = newTemp(Ity_I1);

          if (mode64) {

-            stmt( IRStmt_LLSC( Iend_BE, resSC, mkexpr(EA), mkexpr(rS_hi) ) );

-            storeBE(binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );

+            stmt( IRStmt_LLSC( IENDIANESS, resSC, mkexpr(EA), mkexpr(rS_hi) ) );

+            store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );

          } else {

-            stmt( IRStmt_LLSC( Iend_BE, resSC, binop( Iop_Add32,

-                                                      mkexpr(EA),

-                                                      mkU32(4) ),

-                                                      mkexpr(rS_hi) ) );

-            storeBE(binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );

+            stmt( IRStmt_LLSC( IENDIANESS, resSC, binop( Iop_Add32,

+                                                         mkexpr(EA),

+                                                         mkU32(4) ),

+                                                         mkexpr(rS_hi) ) );

+            store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );

          }

          // Set CR0[LT GT EQ S0] = 0b000 || XER[SO]  on failure

@@ -6664,7 +6666,7 @@ static Bool dis_int_ldst_rev ( UInt theInstr )

       case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449)

          DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         assign( w1, unop(Iop_16Uto32, loadBE(Ity_I16, mkexpr(EA))) );

+         assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA))) );

          assign( w2, gen_byterev16(w1) );

          putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),

                                          /* Signed */False) );

@@ -6672,7 +6674,7 @@ static Bool dis_int_ldst_rev ( UInt theInstr )

       case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459)

          DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         assign( w1, loadBE(Ity_I32, mkexpr(EA)) );

+         assign( w1, load(Ity_I32, mkexpr(EA)) );

          assign( w2, gen_byterev32(w1) );

          putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),

                                          /* Signed */False) );

@@ -6684,11 +6686,11 @@ static Bool dis_int_ldst_rev ( UInt theInstr )

          IRTemp w3 = newTemp( Ity_I32 );

          IRTemp w4 = newTemp( Ity_I32 );

          DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);

-         assign( w1, loadBE( Ity_I32, mkexpr( EA ) ) );

+         assign( w1, load( Ity_I32, mkexpr( EA ) ) );

          assign( w2, gen_byterev32( w1 ) );

          nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),

                            ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );

-         assign( w3, loadBE( Ity_I32, nextAddr ) );

+         assign( w3, load( Ity_I32, nextAddr ) );

          assign( w4, gen_byterev32( w3 ) );

          putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );

          break;

@@ -6697,13 +6699,13 @@ static Bool dis_int_ldst_rev ( UInt theInstr )

       case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523)

          DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );

-         storeBE( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );

+         store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );

          break;

       case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531)

          DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );

-         storeBE( mkexpr(EA), gen_byterev32(w1) );

+         store( mkexpr(EA), gen_byterev32(w1) );

          break;

       case 0x294: // stdbrx (Store Doubleword Byte-Reverse Indexed)

@@ -6715,8 +6717,9 @@ static Bool dis_int_ldst_rev ( UInt theInstr )

          DIP("stdbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);

          assign(lo, unop(Iop_64HIto32, mkexpr(rS)));

          assign(hi, unop(Iop_64to32, mkexpr(rS)));

-         storeBE( mkexpr( EA ),

-                  binop( Iop_32HLto64, gen_byterev32( hi ), gen_byterev32( lo ) ) );

+         store( mkexpr( EA ),

+                binop( Iop_32HLto64, gen_byterev32( hi ),

+                       gen_byterev32( lo ) ) );

          break;

       }

@@ -7234,7 +7237,7 @@ static Bool dis_cache_manage ( UInt         theInstr,

          for (i = 0; i < clearszB / 8; i++) {

             irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) );

-            storeBE( irx_addr, mkU64(0) );

+            store( irx_addr, mkU64(0) );

          }

       } else {

          /* Round EA down to the start of the containing block. */

@@ -7244,7 +7247,7 @@ static Bool dis_cache_manage ( UInt         theInstr,

          for (i = 0; i < clearszB / 4; i++) {

             irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) );

-            storeBE( irx_addr, mkU32(0) );

+            store( irx_addr, mkU32(0) );

          }

       }

       break;

@@ -7464,7 +7467,7 @@ static Bool dis_fp_load ( UInt theInstr )

       DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);

       assign( EA, ea_rAor0_simm(rA_addr, simm16) );

       putFReg( frD_addr,

-               unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );

+               unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );

       break;

    case 0x31: // lfsu (Load Float Single, Update, PPC32 p442)

@@ -7473,14 +7476,14 @@ static Bool dis_fp_load ( UInt theInstr )

       DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);

       assign( EA, ea_rA_simm(rA_addr, simm16) );

       putFReg( frD_addr,

-               unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );

+               unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );

       putIReg( rA_addr, mkexpr(EA) );

       break;

    case 0x32: // lfd (Load Float Double, PPC32 p437)

       DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);

       assign( EA, ea_rAor0_simm(rA_addr, simm16) );

-      putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );

+      putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );

       break;

    case 0x33: // lfdu (Load Float Double, Update, PPC32 p438)

@@ -7488,7 +7491,7 @@ static Bool dis_fp_load ( UInt theInstr )

          return False;

       DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);

       assign( EA, ea_rA_simm(rA_addr, simm16) );

-      putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );

+      putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );

       putIReg( rA_addr, mkexpr(EA) );

       break;

@@ -7503,7 +7506,7 @@ static Bool dis_fp_load ( UInt theInstr )

          DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);

          assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );

          putFReg( frD_addr, unop( Iop_F32toF64, 

-                                  loadBE(Ity_F32, mkexpr(EA))) );

+                                  load(Ity_F32, mkexpr(EA))) );

          break;

       case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443)

@@ -7512,14 +7515,14 @@ static Bool dis_fp_load ( UInt theInstr )

          DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);

          assign( EA, ea_rA_idxd(rA_addr, rB_addr) );

          putFReg( frD_addr,

-                  unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );

+                  unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );

          putIReg( rA_addr, mkexpr(EA) );

          break;