valgrind svn commit r13494, VEX svn commit r2750

Initial ISA 2.07 support for POWER8-tuned libc

The IBM Power ISA 2.07 has been published on power.org, and IBM's new POWER8

processor is under development to implement that ISA. This patch provides

initial VEX support for running Valgrind on POWER8 systems running a soon-to-be

released Linux distribution. This Linux distro will include a POWER8-tuned

libc that uses a subset of the new instructions from ISA 2.07. Since virtually

all applications link with libc, it would be impossible to run an application

under Valgrind on this distro without adding support for these new instructions

to Valgrind, so that's the intent of this patch. Note that applications built

on this distro will *not* employ new POWER8 instructions by default. There are

roughly 150 new instructions in the Power ISA 2.07, including hardware

transaction management (HTM). Support for these new instructions (modulo the

subset included in this bug) will be added to Valgrind in a phased approach,

similar to what we did for Power ISA 2.06.

Bugzilla 322294

diff -ur valgrind-3.8.1.orig/configure valgrind-3.8.1/configure

--- valgrind-3.8.1.orig/configure	2013-08-13 13:07:12.837887980 +0200

+++ valgrind-3.8.1/configure	2013-08-13 13:28:33.188030564 +0200

@@ -673,6 +673,8 @@

 FLAG_MMMX

 FLAG_M64

 FLAG_M32

+HAS_ISA_2_07_FALSE

+HAS_ISA_2_07_TRUE

 HAVE_PTHREAD_CREATE_GLIBC_2_0_FALSE

 HAVE_PTHREAD_CREATE_GLIBC_2_0_TRUE

 HAS_DFP_FALSE

@@ -7321,6 +7323,47 @@

 rm -f core conftest.err conftest.$ac_objext \

     conftest$ac_exeext conftest.$ac_ext

+# isa 2.07 checking

+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking that assembler knows ISA 2.07 " >&5

+$as_echo_n "checking that assembler knows ISA 2.07 ... " >&6; }

+

+cat confdefs.h - <<_ACEOF >conftest.$ac_ext

+/* end confdefs.h.  */

+

+

+int

+main ()

+{

+

+  __asm__ __volatile__("mtvsrd 1,2 ");

+

+  ;

+  return 0;

+}

+_ACEOF

+if ac_fn_c_try_compile "$LINENO"; then :

+

+ac_asm_have_isa_2_07=yes

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5

+$as_echo "yes" >&6; }

+

+else

+

+ac_asm_have_isa_2_07=no

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5

+$as_echo "no" >&6; }

+

+fi

+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext

+

+ if test x$ac_asm_have_isa_2_07 = xyes; then

+  HAS_ISA_2_07_TRUE=

+  HAS_ISA_2_07_FALSE='#'

+else

+  HAS_ISA_2_07_TRUE='#'

+  HAS_ISA_2_07_FALSE=

+fi

+

 #----------------------------------------------------------------------------

 # Checking for supported compiler flags.

@@ -10411,6 +10454,10 @@

   as_fn_error "conditional \"HAVE_PTHREAD_CREATE_GLIBC_2_0\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5

 fi

+if test -z "${HAS_ISA_2_07_TRUE}" && test -z "${HAS_ISA_2_07_FALSE}"; then

+  as_fn_error "conditional \"HAS_ISA_2_07\" was never defined.

+Usually this means the macro was only invoked conditionally." "$LINENO" 5

+fi

 if test -z "${DWARF4_TRUE}" && test -z "${DWARF4_FALSE}"; then

   as_fn_error "conditional \"DWARF4\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5

diff -ur valgrind-3.8.1.orig/configure.in valgrind-3.8.1/configure.in

--- valgrind-3.8.1.orig/configure.in	2013-08-13 13:07:12.800887713 +0200

+++ valgrind-3.8.1/configure.in	2013-08-13 13:10:17.485219043 +0200

@@ -1303,6 +1303,21 @@

 AC_MSG_RESULT([no])

 ])

+# isa 2.07 checking

+AC_MSG_CHECKING([that assembler knows ISA 2.07 ])

+

+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[

+]], [[

+  __asm__ __volatile__("mtvsrd 1,2 ");

+]])], [

+ac_asm_have_isa_2_07=yes

+AC_MSG_RESULT([yes])

+], [

+ac_asm_have_isa_2_07=no

+AC_MSG_RESULT([no])

+])

+

+AM_CONDITIONAL(HAS_ISA_2_07, test x$ac_asm_have_isa_2_07 = xyes)

 #----------------------------------------------------------------------------

 # Checking for supported compiler flags.

diff -ur valgrind-3.8.1.orig/coregrind/m_machine.c valgrind-3.8.1/coregrind/m_machine.c

--- valgrind-3.8.1.orig/coregrind/m_machine.c	2013-08-13 13:07:12.780887570 +0200

+++ valgrind-3.8.1/coregrind/m_machine.c	2013-08-13 13:10:17.487219057 +0200

@@ -862,6 +862,7 @@

      vki_sigaction_toK_t     tmp_sigill_act,   tmp_sigfpe_act;

      volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP;

+     volatile Bool have_isa_2_07;

      Int r;

      /* This is a kludge.  Really we ought to back-convert saved_act

@@ -956,6 +957,14 @@

         __asm__ __volatile__(".long 0xee4e8005"); /* dadd  FRT,FRA, FRB */

      }

+     /* Check for ISA 2.07 support. */

+     have_isa_2_07 = True;

+     if (VG_MINIMAL_SETJMP(env_unsup_insn)) {

+        have_isa_2_07 = False;

+     } else {

+        __asm__ __volatile__(".long 0x7c000166"); /* mtvsrd XT,RA */

+     }

+

      /* determine dcbz/dcbzl sizes while we still have the signal

       * handlers registered */

      find_ppc_dcbz_sz(&vai;;

@@ -966,9 +975,10 @@

      vg_assert(r == 0);

      r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);

      vg_assert(r == 0);

-     VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d\n",

+     VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d ISA2.07 %d\n",

                     (Int)have_F, (Int)have_V, (Int)have_FX,

-                    (Int)have_GX, (Int)have_VX, (Int)have_DFP);

+                    (Int)have_GX, (Int)have_VX, (Int)have_DFP,

+                    (Int)have_isa_2_07);

      /* Make FP a prerequisite for VMX (bogusly so), and for FX and GX. */

      if (have_V && !have_F)

         have_V = False;

@@ -989,6 +999,7 @@

      if (have_GX) vai.hwcaps |= VEX_HWCAPS_PPC32_GX;

      if (have_VX) vai.hwcaps |= VEX_HWCAPS_PPC32_VX;

      if (have_DFP) vai.hwcaps |= VEX_HWCAPS_PPC32_DFP;

+     if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA2_07;

      /* But we're not done yet: VG_(machine_ppc32_set_clszB) must be

@@ -1004,6 +1015,7 @@

      vki_sigaction_toK_t     tmp_sigill_act,   tmp_sigfpe_act;

      volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP;

+     volatile Bool have_isa_2_07;

      Int r;

      /* This is a kludge.  Really we ought to back-convert saved_act

@@ -1090,6 +1102,14 @@

         __asm__ __volatile__(".long 0xee4e8005"); /* dadd  FRT,FRA, FRB */

      }

+     /* Check for ISA 2.07 support. */

+     have_isa_2_07 = True;

+     if (VG_MINIMAL_SETJMP(env_unsup_insn)) {

+        have_isa_2_07 = False;

+     } else {

+        __asm__ __volatile__(".long 0x7c000166"); /* mtvsrd XT,RA */

+     }

+

      /* determine dcbz/dcbzl sizes while we still have the signal

       * handlers registered */

      find_ppc_dcbz_sz(&vai;;

@@ -1097,9 +1117,10 @@

      VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);

      VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);

      VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);

-     VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d\n",

+     VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d ISA2.07 %d\n",

                     (Int)have_F, (Int)have_V, (Int)have_FX,

-                    (Int)have_GX, (Int)have_VX, (Int)have_DFP);

+                    (Int)have_GX, (Int)have_VX, (Int)have_DFP,

+                    (Int)have_isa_2_07);

      /* on ppc64, if we don't even have FP, just give up. */

      if (!have_F)

         return False;

@@ -1114,6 +1135,7 @@

      if (have_GX) vai.hwcaps |= VEX_HWCAPS_PPC64_GX;

      if (have_VX) vai.hwcaps |= VEX_HWCAPS_PPC64_VX;

      if (have_DFP) vai.hwcaps |= VEX_HWCAPS_PPC64_DFP;

+     if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA2_07;

      /* But we're not done yet: VG_(machine_ppc64_set_clszB) must be

         called before we're ready to go. */

diff -ur valgrind-3.8.1.orig/memcheck/mc_translate.c valgrind-3.8.1/memcheck/mc_translate.c

--- valgrind-3.8.1.orig/memcheck/mc_translate.c	2013-08-13 13:07:12.733887229 +0200

+++ valgrind-3.8.1/memcheck/mc_translate.c	2013-08-13 13:10:17.490219078 +0200

@@ -3223,6 +3223,7 @@

          than a data steering operation. */

       case Iop_NarrowBin32to16x8: 

       case Iop_NarrowBin16to8x16: 

+      case Iop_NarrowBin64to32x4:

          return assignNew('V', mce, Ity_V128, 

                                     binop(op, vatom1, vatom2));

diff -ur valgrind-3.8.1.orig/none/tests/ppc32/Makefile.am valgrind-3.8.1/none/tests/ppc32/Makefile.am

--- valgrind-3.8.1.orig/none/tests/ppc32/Makefile.am	2013-08-13 13:07:12.633886508 +0200

+++ valgrind-3.8.1/none/tests/ppc32/Makefile.am	2013-08-13 13:10:17.493219099 +0200

@@ -35,7 +35,10 @@

 	test_dfp2.stdout.exp_Without_dcffix \

 	test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \

 	test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \

-	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest

+	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \

+	jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \

+	test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest

+

 check_PROGRAMS = \

 	allexec \

@@ -46,7 +49,9 @@

 	test_isa_2_06_part1 \

 	test_isa_2_06_part2 \

 	test_isa_2_06_part3 \

-	test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5

+	test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5 \

+	test_isa_2_07_part1 \

+	test_isa_2_07_part2

 AM_CFLAGS    += @FLAG_M32@

@@ -77,6 +82,14 @@

 DFP_FLAG =

 endif

+if HAS_ISA_2_07

+BUILD_FLAGS_ISA_2_07 = -mcpu=power8

+ISA_2_07_FLAG = -DHAS_ISA_2_07

+else

+BUILD_FLAGS_ISA_2_07 =

+ISA_2_07_FLAG =

+endif

+

 jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \

 			@FLAG_M32@ $(ALTIVEC_FLAG)

@@ -104,3 +117,9 @@

 test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \

 			@FLAG_M32@ $(BUILD_FLAGS_DFP)

+

+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+                        @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)

+

+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+			@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)

diff -ur valgrind-3.8.1.orig/none/tests/ppc32/Makefile.in valgrind-3.8.1/none/tests/ppc32/Makefile.in

--- valgrind-3.8.1.orig/none/tests/ppc32/Makefile.in	2013-08-13 13:07:12.632886501 +0200

+++ valgrind-3.8.1/none/tests/ppc32/Makefile.in	2013-08-13 13:28:32.372024756 +0200

@@ -63,7 +63,8 @@

 	test_isa_2_06_part1$(EXEEXT) test_isa_2_06_part2$(EXEEXT) \

 	test_isa_2_06_part3$(EXEEXT) test_dfp1$(EXEEXT) \

 	test_dfp2$(EXEEXT) test_dfp3$(EXEEXT) test_dfp4$(EXEEXT) \

-	test_dfp5$(EXEEXT)

+	test_dfp5$(EXEEXT) test_isa_2_07_part1$(EXEEXT) \

+	test_isa_2_07_part2$(EXEEXT)

 subdir = none/tests/ppc32

 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4

 am__aclocal_m4_deps = $(top_srcdir)/configure.in

@@ -164,6 +165,18 @@

 test_isa_2_06_part3_LDADD = $(LDADD)

 test_isa_2_06_part3_LINK = $(CCLD) $(test_isa_2_06_part3_CFLAGS) \

 	$(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

+test_isa_2_07_part1_SOURCES = test_isa_2_07_part1.c

+test_isa_2_07_part1_OBJECTS =  \

+	test_isa_2_07_part1-test_isa_2_07_part1.$(OBJEXT)

+test_isa_2_07_part1_LDADD = $(LDADD)

+test_isa_2_07_part1_LINK = $(CCLD) $(test_isa_2_07_part1_CFLAGS) \

+	$(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

+test_isa_2_07_part2_SOURCES = test_isa_2_07_part2.c

+test_isa_2_07_part2_OBJECTS =  \

+	test_isa_2_07_part2-test_isa_2_07_part2.$(OBJEXT)

+test_isa_2_07_part2_LDADD = $(LDADD)

+test_isa_2_07_part2_LINK = $(CCLD) $(test_isa_2_07_part2_CFLAGS) \

+	$(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

 tw_SOURCES = tw.c

 tw_OBJECTS = tw.$(OBJEXT)

 tw_LDADD = $(LDADD)

@@ -187,13 +200,15 @@

 	power6_bcmp.c round.c testVMX.c test_dfp1.c test_dfp2.c \

 	test_dfp3.c test_dfp4.c test_dfp5.c test_fx.c test_gx.c \

 	test_isa_2_06_part1.c test_isa_2_06_part2.c \

-	test_isa_2_06_part3.c tw.c twi.c xlc_dbl_u32.c

+	test_isa_2_06_part3.c test_isa_2_07_part1.c \

+	test_isa_2_07_part2.c tw.c twi.c xlc_dbl_u32.c

 DIST_SOURCES = allexec.c bug129390-ppc32.c bug139050-ppc32.c \

 	jm-insns.c ldstrev.c lsw.c mcrfs.c mftocrf.c power5+_round.c \

 	power6_bcmp.c round.c testVMX.c test_dfp1.c test_dfp2.c \

 	test_dfp3.c test_dfp4.c test_dfp5.c test_fx.c test_gx.c \

 	test_isa_2_06_part1.c test_isa_2_06_part2.c \

-	test_isa_2_06_part3.c tw.c twi.c xlc_dbl_u32.c

+	test_isa_2_06_part3.c test_isa_2_07_part1.c \

+	test_isa_2_07_part2.c tw.c twi.c xlc_dbl_u32.c

 ETAGS = etags

 CTAGS = ctags

 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)

@@ -507,7 +522,9 @@

 	test_dfp2.stdout.exp_Without_dcffix \

 	test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \

 	test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \

-	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest

+	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \

+	jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \

+	test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest

 allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@

 @HAS_ALTIVEC_FALSE@ALTIVEC_FLAG = 

@@ -520,6 +537,10 @@

 @HAS_DFP_TRUE@BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6

 @HAS_DFP_FALSE@DFP_FLAG = 

 @HAS_DFP_TRUE@DFP_FLAG = -DHAS_DFP

+@HAS_ISA_2_07_FALSE@BUILD_FLAGS_ISA_2_07 = 

+@HAS_ISA_2_07_TRUE@BUILD_FLAGS_ISA_2_07 = -mcpu=power8

+@HAS_ISA_2_07_FALSE@ISA_2_07_FLAG = 

+@HAS_ISA_2_07_TRUE@ISA_2_07_FLAG = -DHAS_ISA_2_07

 jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \

 			@FLAG_M32@ $(ALTIVEC_FLAG)

@@ -550,6 +571,12 @@

 test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \

 			@FLAG_M32@ $(BUILD_FLAGS_DFP)

+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+                        @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)

+

+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+			@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)

+

 all: all-am

 .SUFFIXES:

@@ -653,6 +680,12 @@

 test_isa_2_06_part3$(EXEEXT): $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_DEPENDENCIES) 

 	@rm -f test_isa_2_06_part3$(EXEEXT)

 	$(test_isa_2_06_part3_LINK) $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_LDADD) $(LIBS)

+test_isa_2_07_part1$(EXEEXT): $(test_isa_2_07_part1_OBJECTS) $(test_isa_2_07_part1_DEPENDENCIES) 

+	@rm -f test_isa_2_07_part1$(EXEEXT)

+	$(test_isa_2_07_part1_LINK) $(test_isa_2_07_part1_OBJECTS) $(test_isa_2_07_part1_LDADD) $(LIBS)

+test_isa_2_07_part2$(EXEEXT): $(test_isa_2_07_part2_OBJECTS) $(test_isa_2_07_part2_DEPENDENCIES) 

+	@rm -f test_isa_2_07_part2$(EXEEXT)

+	$(test_isa_2_07_part2_LINK) $(test_isa_2_07_part2_OBJECTS) $(test_isa_2_07_part2_LDADD) $(LIBS)

 tw$(EXEEXT): $(tw_OBJECTS) $(tw_DEPENDENCIES) 

 	@rm -f tw$(EXEEXT)

 	$(LINK) $(tw_OBJECTS) $(tw_LDADD) $(LIBS)

@@ -691,6 +724,8 @@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tw.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/twi.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xlc_dbl_u32.Po@am__quote@

@@ -863,6 +898,34 @@

 @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

 @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part3-test_isa_2_06_part3.obj `if test -f 'test_isa_2_06_part3.c'; then $(CYGPATH_W) 'test_isa_2_06_part3.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part3.c'; fi`

+test_isa_2_07_part1-test_isa_2_07_part1.o: test_isa_2_07_part1.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part1-test_isa_2_07_part1.o -MD -MP -MF $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo -c -o test_isa_2_07_part1-test_isa_2_07_part1.o `test -f 'test_isa_2_07_part1.c' || echo '$(srcdir)/'`test_isa_2_07_part1.c

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part1.c' object='test_isa_2_07_part1-test_isa_2_07_part1.o' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part1-test_isa_2_07_part1.o `test -f 'test_isa_2_07_part1.c' || echo '$(srcdir)/'`test_isa_2_07_part1.c

+

+test_isa_2_07_part1-test_isa_2_07_part1.obj: test_isa_2_07_part1.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part1-test_isa_2_07_part1.obj -MD -MP -MF $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo -c -o test_isa_2_07_part1-test_isa_2_07_part1.obj `if test -f 'test_isa_2_07_part1.c'; then $(CYGPATH_W) 'test_isa_2_07_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part1.c'; fi`

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part1.c' object='test_isa_2_07_part1-test_isa_2_07_part1.obj' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part1-test_isa_2_07_part1.obj `if test -f 'test_isa_2_07_part1.c'; then $(CYGPATH_W) 'test_isa_2_07_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part1.c'; fi`

+

+test_isa_2_07_part2-test_isa_2_07_part2.o: test_isa_2_07_part2.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part2-test_isa_2_07_part2.o -MD -MP -MF $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo -c -o test_isa_2_07_part2-test_isa_2_07_part2.o `test -f 'test_isa_2_07_part2.c' || echo '$(srcdir)/'`test_isa_2_07_part2.c

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part2.c' object='test_isa_2_07_part2-test_isa_2_07_part2.o' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part2-test_isa_2_07_part2.o `test -f 'test_isa_2_07_part2.c' || echo '$(srcdir)/'`test_isa_2_07_part2.c

+

+test_isa_2_07_part2-test_isa_2_07_part2.obj: test_isa_2_07_part2.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part2-test_isa_2_07_part2.obj -MD -MP -MF $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo -c -o test_isa_2_07_part2-test_isa_2_07_part2.obj `if test -f 'test_isa_2_07_part2.c'; then $(CYGPATH_W) 'test_isa_2_07_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part2.c'; fi`

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part2.c' object='test_isa_2_07_part2-test_isa_2_07_part2.obj' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part2-test_isa_2_07_part2.obj `if test -f 'test_isa_2_07_part2.c'; then $(CYGPATH_W) 'test_isa_2_07_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part2.c'; fi`

+

 ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)

 	list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \

 	unique=`for i in $$list; do \

diff -ur valgrind-3.8.1.orig/none/tests/ppc64/Makefile.am valgrind-3.8.1/none/tests/ppc64/Makefile.am

--- valgrind-3.8.1.orig/none/tests/ppc64/Makefile.am	2013-08-13 13:07:12.675886811 +0200

+++ valgrind-3.8.1/none/tests/ppc64/Makefile.am	2013-08-13 13:10:17.496219122 +0200

@@ -23,12 +23,16 @@

 	test_dfp2.stdout.exp_Without_dcffix \

 	test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \

 	test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \

-	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest

+	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \

+	jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \

+	test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest

 check_PROGRAMS = \

 	allexec \

-	jm-insns lsw round std_reg_imm twi_tdi tw_td power6_bcmp power6_mf_gpr test_isa_2_06_part1 \

-	test_isa_2_06_part2 test_isa_2_06_part3 test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5

+	jm-insns lsw round std_reg_imm twi_tdi tw_td power6_bcmp \

+	power6_mf_gpr test_isa_2_06_part1 test_isa_2_06_part2 \

+	test_isa_2_06_part3 test_dfp1 test_dfp2 test_dfp3 test_dfp4 \

+	test_dfp5 test_isa_2_07_part1 test_isa_2_07_part2

 AM_CFLAGS    += @FLAG_M64@

 AM_CXXFLAGS  += @FLAG_M64@

@@ -58,6 +62,14 @@

 DFP_FLAG =

 endif

+if HAS_ISA_2_07

+BUILD_FLAGS_ISA_2_07 = -mcpu=power8

+ISA_2_07_FLAG = -DHAS_ISA_2_07

+else

+BUILD_FLAGS_ISA_2_07 =

+ISA_2_07_FLAG =

+endif

+

 test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \

 			@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)

@@ -84,3 +96,8 @@

 test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \

 			@FLAG_M64@ $(BUILD_FLAGS_DFP)

+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+			@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)

+

+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+			@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)

diff -ur valgrind-3.8.1.orig/none/tests/ppc64/Makefile.in valgrind-3.8.1/none/tests/ppc64/Makefile.in

--- valgrind-3.8.1.orig/none/tests/ppc64/Makefile.in	2013-08-13 13:07:12.674886804 +0200

+++ valgrind-3.8.1/none/tests/ppc64/Makefile.in	2013-08-13 13:28:32.460025381 +0200

@@ -60,7 +60,8 @@

 	test_isa_2_06_part1$(EXEEXT) test_isa_2_06_part2$(EXEEXT) \

 	test_isa_2_06_part3$(EXEEXT) test_dfp1$(EXEEXT) \

 	test_dfp2$(EXEEXT) test_dfp3$(EXEEXT) test_dfp4$(EXEEXT) \

-	test_dfp5$(EXEEXT)

+	test_dfp5$(EXEEXT) test_isa_2_07_part1$(EXEEXT) \

+	test_isa_2_07_part2$(EXEEXT)

 subdir = none/tests/ppc64

 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4

 am__aclocal_m4_deps = $(top_srcdir)/configure.in

@@ -138,6 +139,18 @@

 test_isa_2_06_part3_LDADD = $(LDADD)

 test_isa_2_06_part3_LINK = $(CCLD) $(test_isa_2_06_part3_CFLAGS) \

 	$(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

+test_isa_2_07_part1_SOURCES = test_isa_2_07_part1.c

+test_isa_2_07_part1_OBJECTS =  \

+	test_isa_2_07_part1-test_isa_2_07_part1.$(OBJEXT)

+test_isa_2_07_part1_LDADD = $(LDADD)

+test_isa_2_07_part1_LINK = $(CCLD) $(test_isa_2_07_part1_CFLAGS) \

+	$(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

+test_isa_2_07_part2_SOURCES = test_isa_2_07_part2.c

+test_isa_2_07_part2_OBJECTS =  \

+	test_isa_2_07_part2-test_isa_2_07_part2.$(OBJEXT)

+test_isa_2_07_part2_LDADD = $(LDADD)

+test_isa_2_07_part2_LINK = $(CCLD) $(test_isa_2_07_part2_CFLAGS) \

+	$(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

 tw_td_SOURCES = tw_td.c

 tw_td_OBJECTS = tw_td.$(OBJEXT)

 tw_td_LDADD = $(LDADD)

@@ -156,11 +169,13 @@

 SOURCES = allexec.c jm-insns.c lsw.c power6_bcmp.c power6_mf_gpr.c \

 	round.c std_reg_imm.c test_dfp1.c test_dfp2.c test_dfp3.c \

 	test_dfp4.c test_dfp5.c test_isa_2_06_part1.c \

-	test_isa_2_06_part2.c test_isa_2_06_part3.c tw_td.c twi_tdi.c

+	test_isa_2_06_part2.c test_isa_2_06_part3.c \

+	test_isa_2_07_part1.c test_isa_2_07_part2.c tw_td.c twi_tdi.c

 DIST_SOURCES = allexec.c jm-insns.c lsw.c power6_bcmp.c \

 	power6_mf_gpr.c round.c std_reg_imm.c test_dfp1.c test_dfp2.c \

 	test_dfp3.c test_dfp4.c test_dfp5.c test_isa_2_06_part1.c \

-	test_isa_2_06_part2.c test_isa_2_06_part3.c tw_td.c twi_tdi.c

+	test_isa_2_06_part2.c test_isa_2_06_part3.c \

+	test_isa_2_07_part1.c test_isa_2_07_part2.c tw_td.c twi_tdi.c

 ETAGS = etags

 CTAGS = ctags

 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)

@@ -462,7 +477,9 @@

 	test_dfp2.stdout.exp_Without_dcffix \

 	test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \

 	test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \

-	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest

+	test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \

+	jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \

+	test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest

 allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@

 @HAS_ALTIVEC_FALSE@ALTIVEC_FLAG = 

@@ -475,6 +492,10 @@

 @HAS_DFP_TRUE@BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6

 @HAS_DFP_FALSE@DFP_FLAG = 

 @HAS_DFP_TRUE@DFP_FLAG = -DHAS_DFP

+@HAS_ISA_2_07_FALSE@BUILD_FLAGS_ISA_2_07 = 

+@HAS_ISA_2_07_TRUE@BUILD_FLAGS_ISA_2_07 = -mcpu=power8

+@HAS_ISA_2_07_FALSE@ISA_2_07_FLAG = 

+@HAS_ISA_2_07_TRUE@ISA_2_07_FLAG = -DHAS_ISA_2_07

 test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \

 			@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)

@@ -502,6 +523,12 @@

 test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \

 			@FLAG_M64@ $(BUILD_FLAGS_DFP)

+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+			@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)

+

+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \

+			@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)

+

 all: all-am

 .SUFFIXES:

@@ -584,6 +611,12 @@

 test_isa_2_06_part3$(EXEEXT): $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_DEPENDENCIES) 

 	@rm -f test_isa_2_06_part3$(EXEEXT)

 	$(test_isa_2_06_part3_LINK) $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_LDADD) $(LIBS)

+test_isa_2_07_part1$(EXEEXT): $(test_isa_2_07_part1_OBJECTS) $(test_isa_2_07_part1_DEPENDENCIES) 

+	@rm -f test_isa_2_07_part1$(EXEEXT)

+	$(test_isa_2_07_part1_LINK) $(test_isa_2_07_part1_OBJECTS) $(test_isa_2_07_part1_LDADD) $(LIBS)

+test_isa_2_07_part2$(EXEEXT): $(test_isa_2_07_part2_OBJECTS) $(test_isa_2_07_part2_DEPENDENCIES) 

+	@rm -f test_isa_2_07_part2$(EXEEXT)

+	$(test_isa_2_07_part2_LINK) $(test_isa_2_07_part2_OBJECTS) $(test_isa_2_07_part2_LDADD) $(LIBS)

 tw_td$(EXEEXT): $(tw_td_OBJECTS) $(tw_td_DEPENDENCIES) 

 	@rm -f tw_td$(EXEEXT)

 	$(LINK) $(tw_td_OBJECTS) $(tw_td_LDADD) $(LIBS)

@@ -612,6 +645,8 @@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tw_td.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/twi_tdi.Po@am__quote@

@@ -769,6 +804,34 @@

 @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

 @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part3-test_isa_2_06_part3.obj `if test -f 'test_isa_2_06_part3.c'; then $(CYGPATH_W) 'test_isa_2_06_part3.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part3.c'; fi`

+test_isa_2_07_part1-test_isa_2_07_part1.o: test_isa_2_07_part1.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part1-test_isa_2_07_part1.o -MD -MP -MF $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo -c -o test_isa_2_07_part1-test_isa_2_07_part1.o `test -f 'test_isa_2_07_part1.c' || echo '$(srcdir)/'`test_isa_2_07_part1.c

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part1.c' object='test_isa_2_07_part1-test_isa_2_07_part1.o' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part1-test_isa_2_07_part1.o `test -f 'test_isa_2_07_part1.c' || echo '$(srcdir)/'`test_isa_2_07_part1.c

+

+test_isa_2_07_part1-test_isa_2_07_part1.obj: test_isa_2_07_part1.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part1-test_isa_2_07_part1.obj -MD -MP -MF $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo -c -o test_isa_2_07_part1-test_isa_2_07_part1.obj `if test -f 'test_isa_2_07_part1.c'; then $(CYGPATH_W) 'test_isa_2_07_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part1.c'; fi`

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Tpo $(DEPDIR)/test_isa_2_07_part1-test_isa_2_07_part1.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part1.c' object='test_isa_2_07_part1-test_isa_2_07_part1.obj' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part1-test_isa_2_07_part1.obj `if test -f 'test_isa_2_07_part1.c'; then $(CYGPATH_W) 'test_isa_2_07_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part1.c'; fi`

+

+test_isa_2_07_part2-test_isa_2_07_part2.o: test_isa_2_07_part2.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part2-test_isa_2_07_part2.o -MD -MP -MF $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo -c -o test_isa_2_07_part2-test_isa_2_07_part2.o `test -f 'test_isa_2_07_part2.c' || echo '$(srcdir)/'`test_isa_2_07_part2.c

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part2.c' object='test_isa_2_07_part2-test_isa_2_07_part2.o' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part2-test_isa_2_07_part2.o `test -f 'test_isa_2_07_part2.c' || echo '$(srcdir)/'`test_isa_2_07_part2.c

+

+test_isa_2_07_part2-test_isa_2_07_part2.obj: test_isa_2_07_part2.c

+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_07_part2-test_isa_2_07_part2.obj -MD -MP -MF $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo -c -o test_isa_2_07_part2-test_isa_2_07_part2.obj `if test -f 'test_isa_2_07_part2.c'; then $(CYGPATH_W) 'test_isa_2_07_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part2.c'; fi`

+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Tpo $(DEPDIR)/test_isa_2_07_part2-test_isa_2_07_part2.Po

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='test_isa_2_07_part2.c' object='test_isa_2_07_part2-test_isa_2_07_part2.obj' libtool=no @AMDEPBACKSLASH@

+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_07_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_07_part2-test_isa_2_07_part2.obj `if test -f 'test_isa_2_07_part2.c'; then $(CYGPATH_W) 'test_isa_2_07_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_07_part2.c'; fi`

+

 ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)

 	list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \

 	unique=`for i in $$list; do \

diff -ur valgrind-3.8.1.orig/tests/check_isa-2_06_cap valgrind-3.8.1/tests/check_isa-2_06_cap

--- valgrind-3.8.1.orig/tests/check_isa-2_06_cap	2013-08-13 13:07:12.820887858 +0200

+++ valgrind-3.8.1/tests/check_isa-2_06_cap	2013-08-13 13:10:17.500219150 +0200

@@ -1,8 +1,9 @@

 #!/bin/sh

-# We use this script to check whether or not the processor supports Power ISA 2.06.

+# We use this script to check whether or not the processor supports Power ISA 2.06 or later.

+DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"

+LD_SHOW_AUXV=1 $DIR/true | grep  arch_2_06 > /dev/null 2>&1

-LD_SHOW_AUXV=1 /bin/true | grep  arch_2_06 > /dev/null 2>&1

 if [ "$?" -ne "0" ]; then

 	exit 1

 else

diff -ur valgrind-3.8.1.orig/VEX/priv/guest_ppc_toIR.c valgrind-3.8.1/VEX/priv/guest_ppc_toIR.c

--- valgrind-3.8.1.orig/VEX/priv/guest_ppc_toIR.c	2013-08-13 13:07:12.730887208 +0200

+++ valgrind-3.8.1/VEX/priv/guest_ppc_toIR.c	2013-08-13 13:10:17.465218898 +0200

@@ -4918,11 +4918,17 @@

    case 0x3E:

       switch ((b1<<1) | b0) {

       case 0x0: // std (Store DWord, PPC64 p580)

+         if (!mode64)

+            return False;

+

          DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

          storeBE( mkexpr(EA), mkexpr(rS) );

          break;

       case 0x1: // stdu (Store DWord, Update, PPC64 p583)

+         if (!mode64)

+            return False;

+

          DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);

          putIReg( rA_addr, mkexpr(EA) );

          storeBE( mkexpr(EA), mkexpr(rS) );

@@ -6452,7 +6458,7 @@

       }

       /* not decodable */

       return False;

-    

+

    /* XFX-Form */

    case 0x153: // mfspr (Move from Special-Purpose Register, PPC32 p470)

@@ -6620,7 +6626,79 @@

          return False;

       }

       break;

-      

+

+   case 0x33:                // mfvsrd

+   {

+      UChar XS = ifieldRegXS( theInstr );

+      UChar rA_addr = ifieldRegA(theInstr);

+      IRExpr * high64;

+      IRTemp vS = newTemp( Ity_V128 );

+      DIP("mfvsrd r%u,vsr%d\n", rA_addr, (UInt)XS);

+

+      /*  XS = SX || S

+       *  For SX=0, mfvsrd is treated as a Floating-Point

+       *            instruction in terms of resource availability.

+       *  For SX=1, mfvsrd is treated as a Vector instruction in

+       *            terms of resource availability.

+       *NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART

+       */

+      assign( vS, getVSReg( XS ) );

+      high64 = unop( Iop_V128HIto64, mkexpr( vS ) );

+      putIReg( rA_addr, (mode64) ? high64 :

+      unop( Iop_64to32, high64 ) );

+      break;

+   }

+

+   case 0xB3:                // mtvsrd

+   {

+      UChar XT = ifieldRegXT( theInstr );

+      UChar rA_addr = ifieldRegA(theInstr);

+      IRTemp rA = newTemp(ty);

+      DIP("mtvsrd vsr%d,r%u\n", (UInt)XT, rA_addr);

+      /*  XS = SX || S

+       *  For SX=0, mfvsrd is treated as a Floating-Point

+       *            instruction in terms of resource availability.

+       *  For SX=1, mfvsrd is treated as a Vector instruction in

+       *            terms of resource availability.

+       *NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART

+       */

+      assign( rA, getIReg(rA_addr) );

+

+      if (mode64)

+         putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( rA ), mkU64( 0 ) ) );

+      else

+         putVSReg( XT, binop( Iop_64HLtoV128,

+                              binop( Iop_32HLto64,

+                                     mkU32( 0 ),

+                                     mkexpr( rA ) ),

+                                     mkU64( 0 ) ) );

+      break;

+   }

+

+   case 0xD3:                // mtvsrwa

+   {

+      UChar XT = ifieldRegXT( theInstr );

+      UChar rA_addr = ifieldRegA(theInstr);

+      IRTemp rA = newTemp( Ity_I32 );

+      DIP("mtvsrwa vsr%d,r%u\n", (UInt)XT, rA_addr);

+      /*  XS = SX || S

+       *  For SX=0, mtvsrwa is treated as a Floating-Point

+       *            instruction in terms of resource availability.

+       *  For SX=1, mtvsrwa is treated as a Vector instruction in

+       *            terms of resource availability.

+       *NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART

+       */

+      if (mode64)

+         assign( rA, unop( Iop_64to32, getIReg( rA_addr ) ) );

+      else

+         assign( rA, getIReg(rA_addr) );

+

+      putVSReg( XT, binop( Iop_64HLtoV128,

+                           unop( Iop_32Sto64, mkexpr( rA ) ),

+                           mkU64( 0 ) ) );

+      break;

+   }

+

    default:

       vex_printf("dis_proc_ctl(ppc)(opc2)\n");

       return False;

@@ -11635,7 +11713,7 @@

    /* Create and assign temps only as needed for the given instruction. */

    switch (opc2) {

       // scalar double-precision floating point argument

-      case 0x2B0: case 0x0b0: case 0x290: case 0x212: case 0x090:

+      case 0x2B0: case 0x0b0: case 0x290: case 0x212: case 0x216: case 0x090:

          xB = newTemp(Ity_F64);

          assign( xB,

                  unop( Iop_ReinterpI64asF64,

@@ -11677,6 +11755,11 @@

          assign( xB,

                  unop( Iop_64HIto32, unop( Iop_V128HIto64, getVSReg( XB ) ) ) );

          break;

+      case 0x296: // xscvspdpn (non signaling version of xscvpdp)

+         xB = newTemp(Ity_I32);

+         assign( xB,

+                 unop( Iop_64HIto32, unop( Iop_V128HIto64, getVSReg( XB ) ) ) );

+         break;

       /* Certain instructions have their complete implementation in the main switch statement

        * that follows this one; thus we have a "do nothing" case for those instructions here.

@@ -11824,6 +11907,18 @@

                                  mkU32( 0 ) ),

                           mkU64( 0ULL ) ) );

          break;

+      case 0x216: /* xscvdpspn (VSX Scalar convert scalar Single-Precision to

+                              vector single Convert to Single-Precision non-signalling */

+         DIP("xscvdpspn v%u,v%u\n",  (UInt)XT, (UInt)XB);

+         putVSReg( XT,

+                   binop( Iop_64HLtoV128,

+                          binop( Iop_32HLto64,

+                                 unop( Iop_ReinterpF32asI32,

+                                       unop( Iop_TruncF64asF32,

+                                             mkexpr( xB ) ) ),

+                                             mkU32( 0 ) ),

+                                             mkU64( 0ULL ) ) );

+         break;

       case 0x090: // xscvdpuxws (VSX Scalar truncate Double-Precision to integer

                   //             and Convert to Unsigned Integer Word format with Saturate)

          DIP("xscvdpuxws v%u,v%u\n",  (UInt)XT, (UInt)XB);

@@ -11845,6 +11940,15 @@

                                       unop( Iop_ReinterpI32asF32, mkexpr( xB ) ) ) ),

                           mkU64( 0ULL ) ) );

          break;

+      case 0x296: // xscvspdpn (VSX Scalar Convert Single-Precision to Double-Precision format Non signaling)

+         DIP("xscvspdpn v%u,v%u\n",  (UInt)XT, (UInt)XB);

+         putVSReg( XT,

+                   binop( Iop_64HLtoV128,

+                          unop( Iop_ReinterpF64asI64,

+                                unop( Iop_F32toF64,

+                                      unop( Iop_ReinterpI32asF32, mkexpr( xB ) ) ) ),

+                                      mkU64( 0ULL ) ) );

+         break;

       case 0x312: // xvcvdpsp (VSX Vector round Double-Precision to single-precision

                   //           and Convert to Single-Precision format)

          DIP("xvcvdpsp v%u,v%u\n",  (UInt)XT, (UInt)XB);

@@ -14552,6 +14656,11 @@

       putVReg( vD_addr, binop(Iop_Add32x4, mkexpr(vA), mkexpr(vB)) );

       break;

+   case 0x0C0: // vaddudm (Add Unsigned Double Word Modulo)

+      DIP("vaddudm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);

+      putVReg( vD_addr, binop(Iop_Add64x2, mkexpr(vA), mkexpr(vB)) );

+      break;

+

    case 0x200: // vaddubs (Add Unsigned Byte Saturate, AV p142)

       DIP("vaddubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);

       putVReg( vD_addr, binop(Iop_QAdd8Ux16, mkexpr(vA), mkexpr(vB)) );

@@ -15824,6 +15933,12 @@

       return True;

    }

+   case 0x44E: // vpkudum (Pack Unsigned Double Word Unsigned Modulo)

+      DIP("vpkudum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);

+      putVReg( vD_addr,

+               binop(Iop_NarrowBin64to32x4, mkexpr(vA), mkexpr(vB)) );

+      return True;

+

    default:

       break; // Fall through...

    }

@@ -16356,6 +16471,7 @@

       { 0x1f4, "xvtdivdp" },

       { 0x208, "xxland" },

       { 0x212, "xscvdpsp" },

+      { 0x216, "xscvdpspn" },

       { 0x228, "xxlandc" },

       { 0x248 , "xxlor" },

       { 0x268, "xxlxor" },

@@ -16364,6 +16480,7 @@

       { 0x288, "xxlnor" },

       { 0x290, "xscvdpuxds" },

       { 0x292, "xscvspdp" },

+      { 0x296, "xscvspdpn" },

       { 0x2a0, "xsmindp" },

       { 0x2a4, "xsnmaddmdp" },

       { 0x2b0, "xscvdpsxds" },

@@ -16412,7 +16529,8 @@

       { 0x3f0, "xvcvsxddp" },

       { 0x3f2, "xvnegdp" }

 };

-#define VSX_ALL_LEN 135

+#define VSX_ALL_LEN (sizeof vsx_all / sizeof *vsx_all)

+

 // ATTENTION: This search function assumes vsx_all array is sorted.

 static Int findVSXextOpCode(UInt opcode)

@@ -16490,6 +16608,7 @@

    Bool      allow_GX = False;

    Bool      allow_VX = False;  // Equates to "supports Power ISA 2.06

    Bool      allow_DFP = False;

+   Bool      allow_isa_2_07 = False;

    UInt      hwcaps = archinfo->hwcaps;

    Long      delta;

@@ -16501,6 +16620,7 @@

       allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC64_GX));

       allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC64_VX));

       allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC64_DFP));

+      allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA2_07));

    } else {

       allow_F  = (0 != (hwcaps & VEX_HWCAPS_PPC32_F));

       allow_V  = (0 != (hwcaps & VEX_HWCAPS_PPC32_V));

@@ -16508,6 +16628,7 @@

       allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC32_GX));

       allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC32_VX));

       allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC32_DFP));

+      allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA2_07));

    }

    /* The running delta */

@@ -16928,8 +17049,9 @@

          case 0x2B0: case 0x2F0: // xscvdpsxds, xscvsxddp

          case 0x1b0: case 0x130: // xvcvdpsxws, xvcvspsxws

          case 0x0b0: case 0x290: // xscvdpsxws, xscvdpuxds

-         case 0x212: // xscvdpsp

-         case 0x292: case 0x312: // xscvspdp, xvcvdpsp

+         case 0x212: case 0x216: // xscvdpsp, xscvdpspn

+         case 0x292: case 0x296: // xscvspdp, xscvspdpn

+         case 0x312: // xvcvdpsp

          case 0x390: case 0x190: // xvcvdpuxds, xvcvdpuxws

          case 0x3B0: case 0x310: // xvcvdpsxds, xvcvspuxds

          case 0x392: case 0x330: // xvcvspdp, xvcvspsxds

@@ -16973,7 +17095,6 @@

    /* 64bit Integer Stores */

    case 0x3E:  // std, stdu

-      if (!mode64) goto decode_failure;

       if (dis_int_store( theInstr, abiinfo )) goto decode_success;

       goto decode_failure;

@@ -17008,7 +17129,7 @@

          if (!allow_GX) goto decode_noGX;

          if (dis_fp_arith(theInstr)) goto decode_success;