commit 3950c5d661ee09526cddcf24daf5fc22bc83f70c

Author: Carl Love <cel@us.ibm.com>

Date:   Mon Nov 1 11:18:32 2021 -0500

    Valgrind Add powerpc R=1 tests

    Contributed by Will Schmidt <will_schmidt@vnet.ibm.com>

    This includes updates and adjustments as suggested by Carl.

    Add tests that exercise PCRelative instructions.

    These instructions are encoded with R==1, which indicate that

    the memory accessed by the instruction is at a location

    relative to the currently executing instruction.

    These tests are built using -Wl,-text and -Wl,-bss

    options to ensure the location of the target array is at a

    location with a specific offset from the currently

    executing instruction.

    The write instructions are aimed at a large buffer in

    the bss section; which is checked for updates at the

    completion of each test.

    In order to ensure consistent output across assorted

    systems, the tests have been padded with ori, nop instructions

    and align directives.

    Detailed changes:

     * Makefile.am: Add test_isa_3_1_R1_RT and test_isa_3_1_R1_XT tests.

     * isa_3_1_helpers.h: Add identify_instruction_by_func_name() helper function

       to indicate if the test is for R==1.

       Add helpers to initialize and print changes to the pcrelative_write_target

       array.

       Add #define to help pad code with a series of eyecatcher ORI instructions.

         * test_isa_3_1_R1_RT.c: New test.

         * test_isa_3_1_R1_XT.c: New test.

         * test_isa_3_1_R1_XT.stdout.exp: New expected output.

         * test_isa_3_1_R1_XT.stdout.exp: New expected output.

         * test_isa_3_1_R1_RT.stderr.exp: New expected output.

         * test_isa_3_1_R1_RT.stderr.exp: New expected output.

         * test_isa_3_1_R1_RT.vgtest: New test handler.

         * test_isa_3_1_R1_XT.vgtest: New test handler.

         * test_isa_3_1_common.c: Add indicators (updates_byte,updates_halfword,

           updates_word) indicators to control the output from the R==1 tests.

           Add helper check for "_R1" to indicate if instruction is coded with R==1.

           Add init and print helpers for the pcrelative_write_target array.

diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am

index b709f3ef4..f8eab9fc0 100644

--- a/none/tests/ppc64/Makefile.am

+++ b/none/tests/ppc64/Makefile.am

@@ -61,6 +61,8 @@ EXTRA_DIST = \

 	test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp \

 	test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp \

 	test_isa_3_1_AT.vgtest test_isa_3_1_AT.stderr.exp test_isa_3_1_AT.stdout.exp \

+	test_isa_3_1_R1_RT.vgtest test_isa_3_1_R1_RT.stderr.exp test_isa_3_1_R1_RT.stdout.exp \

+	test_isa_3_1_R1_XT.vgtest test_isa_3_1_R1_XT.stderr.exp test_isa_3_1_R1_XT.stdout.exp \

 	subnormal_test.stderr.exp  subnormal_test.stdout.exp \

 	subnormal_test.vgtest test_darn_inst.stderr.exp \

 	test_darn_inst.stdout.exp test_darn_inst.vgtest \

@@ -68,8 +70,8 @@ EXTRA_DIST = \

 	test_copy_paste.stderr.exp test_copy_paste.stdout.exp \

 	test_copy_paste.vgtest \

 	test_mcrxrx.vgtest test_mcrxrx.stderr.exp test_mcrxrx.stdout.exp \

-	test_lxvx_stxvx.vgtest test_lxvx_stxvx.stderr.exp test_lxvx_stxvx.stdout.exp-p8  test_lxvx_stxvx.stdout.exp-p9

-

+	test_lxvx_stxvx.vgtest test_lxvx_stxvx.stderr.exp \

+	test_lxvx_stxvx.stdout.exp-p8  test_lxvx_stxvx.stdout.exp-p9

 check_PROGRAMS = \

 	allexec \

@@ -80,11 +82,12 @@ check_PROGRAMS = \

 	test_isa_3_0 test_mod_instructions \

 	test_isa_3_1_RT test_isa_3_1_XT test_isa_3_1_VRT \

 	test_isa_3_1_Misc test_isa_3_1_AT \

+	test_isa_3_1_R1_RT test_isa_3_1_R1_XT \

 	subnormal_test test_darn_inst test_copy_paste \

 	test_tm test_touch_tm data-cache-instructions \

 	std_reg_imm \

 	twi_tdi tw_td power6_bcmp scv_test \

-	test_mcrxrx  test_lxvx_stxvx

+	test_mcrxrx test_lxvx_stxvx

 # lmw, stmw, lswi, lswx, stswi, stswx compile (and run) only on big endian.

 if VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX

@@ -106,6 +109,8 @@ test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c

 test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c

 test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c

 test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c

+test_isa_3_1_R1_XT_SOURCES = test_isa_3_1_R1_XT.c test_isa_3_1_common.c

+test_isa_3_1_R1_RT_SOURCES = test_isa_3_1_R1_RT.c test_isa_3_1_common.c

 test_darn_inst_SOURCES = test_darn_inst.c

 if HAS_ALTIVEC

@@ -224,6 +229,11 @@ test_isa_3_1_VRT_CFLAGS = $(test_isa_3_1_CFLAGS)

 test_isa_3_1_Misc_CFLAGS = $(test_isa_3_1_CFLAGS)

 test_isa_3_1_AT_CFLAGS = $(test_isa_3_1_CFLAGS)

+# The _R1_foo tests exercise pc-relative instructions, so require the bss and text sections

+# exist at known offsets with respect to each other.

+test_isa_3_1_R1_RT_CFLAGS = $(test_isa_3_1_CFLAGS) -Wl,-Tbss,0x20000 -Wl,-Ttext,0x40000

+test_isa_3_1_R1_XT_CFLAGS = $(test_isa_3_1_CFLAGS) -Wl,-Tbss,0x20000 -Wl,-Ttext,0x40000

+

 subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \

 			@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06)

diff --git a/none/tests/ppc64/isa_3_1_helpers.h b/none/tests/ppc64/isa_3_1_helpers.h

index 338f55526..716a6277b 100644

--- a/none/tests/ppc64/isa_3_1_helpers.h

+++ b/none/tests/ppc64/isa_3_1_helpers.h

@@ -43,6 +43,9 @@ extern void debug_show_current_iteration();

 extern void debug_dump_buffer();

 extern void identify_form_components(const char *, const char *);

+extern void identify_instruction_by_func_name(const char *);

+extern void init_pcrelative_write_target();

+extern void print_pcrelative_write_target();

 extern void dump_vsxargs();

 extern void generic_prologue();

 extern void build_args_table();

@@ -58,6 +61,21 @@ extern void initialize_source_registers();

 extern void set_up_iterators();

 extern void initialize_buffer(int);

+/* This (TEXT_BSS_DELTA) is the relative distance between those

+   sections as set by the linker options for the R==1 tests. */

+#define TEXT_BSS_DELTA 0x20000

+#define RELOC_BUFFER_SIZE 0x1000

+extern unsigned long long pcrelative_buff_addr(int);

+#define PAD_ORI	\

+	__asm__ __volatile__ ("ori 21,21,21"); \

+	__asm__ __volatile__ ("ori 22,22,22");\

+	__asm__ __volatile__ ("ori 23,23,23");\

+	__asm__ __volatile__ ("ori 24,24,24");\

+	__asm__ __volatile__ ("ori 25,25,25");\

+	__asm__ __volatile__ ("ori 26,26,26");\

+	__asm__ __volatile__ ("ori 27,27,27");\

+	__asm__ __volatile__ ("ori 28,28,28");

+

 extern int verbose;

 #define debug_printf(X) if (verbose>0) printf(X);

 #define debug_show_labels (verbose>0)

diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.c b/none/tests/ppc64/test_isa_3_1_R1_RT.c

new file mode 100644

index 000000000..d73b84b10

--- /dev/null

+++ b/none/tests/ppc64/test_isa_3_1_R1_RT.c

@@ -0,0 +1,624 @@

+/*

+ * Valgrind testcase for PowerPC ISA 3.1

+ *

+ * Copyright (C) 2019-2020 Will Schmidt <will_schmidt@vnet.ibm.com>

+ *

+ * 64bit build:

+ *    gcc -Winline -Wall -g -O -mregnames -maltivec -m64

+ */

+

+/*

+ *   This program is free software; you can redistribute it and/or

+ *   modify it under the terms of the GNU General Public License as

+ *   published by the Free Software Foundation; either version 2 of the

+ *   License, or (at your option) any later version.

+ *

+ *   This program is distributed in the hope that it will be useful,

+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of

+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+ *   GNU General Public License for more details.

+ *

+ *   You should have received a copy of the GNU General Public License

+ *   along with this program; if not, write to the Free Software

+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

+ */

+

+#include <stdio.h>

+#ifdef HAS_ISA_3_1

+#include <stdint.h>

+#include <assert.h>

+#include <stdlib.h>

+#include <string.h>

+#include <unistd.h>

+#include <altivec.h>

+#include <malloc.h>

+

+#include <string.h>

+#include <signal.h>

+#include <setjmp.h>

+

+/* Condition Register fields.

+   These are used to capture the condition register values immediately after

+   the instruction under test is executed. This is done to help prevent other

+   test overhead (switch statements, result compares, etc) from disturbing

+   the test case results.  */

+unsigned long current_cr;

+unsigned long current_fpscr;

+

+struct test_list_t current_test;

+

+#include "isa_3_1_helpers.h"

+

+static void test_plxvp_off0_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plxvp 20, +0(0),1"  );

+	PAD_ORI

+}

+static void test_plxvp_off8_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plxvp 20, +8(0),1" );

+	PAD_ORI

+}

+static void test_plxvp_off16_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plxvp 20, +16(0),1" );

+	PAD_ORI

+}

+static void test_plxvp_off24_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plxvp 20, +24(0),1" );

+	PAD_ORI

+}

+static void test_plxvp_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plxvp 20, +32(0),1" );

+	PAD_ORI

+}

+static void test_plbz_off0_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plbz %0, +0(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plbz_off8_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plbz %0, +8(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plbz_off16_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plbz %0, +16(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plbz_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plbz %0, +32(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plbz_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plbz %0, +64(0), 1" : "=r" (rt) );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_plhz_off0_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plhz %0, +0(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plhz_off8_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plhz %0, +8(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plhz_off16_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plhz %0, +16(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plhz_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plhz %0, +32(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plhz_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plhz %0, +64(0), 1" : "=r" (rt) );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_plha_off0_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plha %0, +0(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plha_off8_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plha %0, +8(0), 1" : "=r" (rt)  );

+	PAD_ORI

+}

+static void test_plha_off16_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plha %0, +16(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plha_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plha %0, +32(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plha_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plha %0, +64(0), 1" : "=r" (rt) );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_plwz_off0_R1 (void) {

+  __asm__ __volatile__ ("plwz %0, +0(0), 1" : "=r" (rt)  );

+}

+static void test_plwz_off8_R1 (void) {

+  __asm__ __volatile__ ("plwz %0, +8(0), 1" : "=r" (rt) );

+}

+static void test_plwz_off16_R1 (void) {

+  __asm__ __volatile__ ("plwz %0, +16(0), 1" : "=r" (rt) );

+}

+static void test_plwz_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plwz %0, +32(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plwz_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plwz %0, +64(0), 1" : "=r" (rt) );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_plwa_off0_R1 (void) {

+  __asm__ __volatile__ ("plwa %0, +0(0), 1" : "=r" (rt)  );

+}

+static void test_plwa_off8_R1 (void) {

+  __asm__ __volatile__ ("plwa %0, +8(0), 1" : "=r" (rt)  );

+}

+static void test_plwa_off16_R1 (void) {

+  __asm__ __volatile__ ("plwa %0, +16(0), 1" : "=r" (rt) );

+}

+static void test_plwa_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plwa %0, +32(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_plwa_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plwa %0, +64(0), 1" : "=r" (rt) );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_pld_off0_R1 (void) {

+  __asm__ __volatile__ ("pld %0, +0(0), 1" : "=r" (rt)  );

+}

+static void test_pld_off8_R1 (void) {

+  __asm__ __volatile__ ("pld %0, +8(0), 1" : "=r" (rt)  );

+}

+static void test_pld_off16_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("pld %0, +16(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_pld_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("pld %0, +32(0), 1" : "=r" (rt) );

+	PAD_ORI

+}

+static void test_pld_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("pld %0, +64(0), 1" : "=r" (rt) );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_pstb_off0_R1 (void) {

+  __asm__ __volatile__ ("pstb %0, -0x1f400+0(0), 1" :: "r" (rs) );

+}

+static void test_pstb_off8_R1 (void) {

+  __asm__ __volatile__ ("pstb %0, -0x1f400+8(0), 1" :: "r" (rs) );

+}

+static void test_pstb_off16_R1 (void) {

+  __asm__ __volatile__ ("pstb %0, -0x1f400+16(0), 1" :: "r" (rs) );

+}

+static void test_pstb_off32_R1 (void) {

+  __asm__ __volatile__ ("pstb %0, -0x1f400+32(0), 1" :: "r" (rs) );

+}

+static void test_psth_off0_R1 (void) {

+  __asm__ __volatile__ ("psth %0, -0x1f400+0(0), 1" :: "r" (rs) );

+}

+static void test_psth_off8_R1 (void) {

+  __asm__ __volatile__ ("psth %0, -0x1f400+8(0), 1" :: "r" (rs) );

+}

+static void test_psth_off16_R1 (void) {

+  __asm__ __volatile__ ("psth %0, -0x1f400+16(0), 1" :: "r" (rs) );

+}

+static void test_psth_off32_R1 (void) {

+  __asm__ __volatile__ ("psth %0, -0x1f400+32(0), 1" :: "r" (rs) );

+}

+static void test_pstw_off0_R1 (void) {

+  __asm__ __volatile__ ("pstw %0, -0x1f400+0(0), 1" :: "r" (rs) );

+}

+static void test_pstw_off8_R1 (void) {

+  __asm__ __volatile__ ("pstw %0, -0x1f400+8(0), 1" :: "r" (rs) );

+}

+static void test_pstw_off16_R1 (void) {

+  __asm__ __volatile__ ("pstw %0, -0x1f400+16(0), 1" :: "r" (rs) );

+}

+static void test_pstw_off32_R1 (void) {

+  __asm__ __volatile__ ("pstw %0, -0x1f400+32(0), 1" :: "r" (rs) );

+}

+static void test_pstd_off0_R1 (void) {

+  __asm__ __volatile__ ("pstd %0, -0x1f400+0(0), 1" :: "r" (rs) );

+}

+static void test_pstd_off8_R1 (void) {

+  __asm__ __volatile__ ("pstd %0, -0x1f400+8(0), 1" :: "r" (rs) );

+}

+static void test_pstd_off16_R1 (void) {

+  __asm__ __volatile__ ("pstd %0, -0x1f400+16(0), 1" :: "r" (rs) );

+}

+static void test_pstd_off32_R1 (void) {

+  __asm__ __volatile__ ("pstd %0, -0x1f400+32(0), 1" :: "r" (rs) );

+}

+  /* For the paddi tests; although we can get close to a read/write target

+     due to forcing where the .text and .bss sections are placed, there is

+     still enough codegen variability that having a raw value in the exp

+     file will not be determinative for these instructions.

+     Thus, compromise and just ensure that the generated value is an

+     address that lands within the reloc buffer, and use quasi magic

+     eyecatcher values in the return to indicate success.  */

+static void test_paddi_0_R1 (void) {

+  __asm__ __volatile__ ("paddi %0, 0, 0+0, 1" : "=r" (rt)  );

+  rt = rt - TEXT_BSS_DELTA;

+  if (rt > pcrelative_buff_addr(0) &&

+		  rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE))

+	  rt = 0xffff0000;

+}

+static void test_paddi_12_R1 (void) {

+  __asm__ __volatile__ ("paddi %0, 0, 0+12, 1" : "=r" (rt)  );

+  rt = rt - TEXT_BSS_DELTA;

+  if (rt > pcrelative_buff_addr(0) &&

+		  rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE))

+	  rt = 0xffff0012;

+}

+static void test_paddi_48_R1 (void) {

+  __asm__ __volatile__ ("paddi %0, 0, 0+48, 1" : "=r" (rt)  );

+  rt = rt - TEXT_BSS_DELTA;

+  if (rt > pcrelative_buff_addr(0) &&

+		  rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE))

+	  rt = 0xffff0048;

+}

+static void test_paddi_98_R1 (void) {

+  __asm__ __volatile__ ("paddi %0, 0, 0+98, 1" : "=r" (rt) );

+  rt = rt - TEXT_BSS_DELTA;

+  if (rt > pcrelative_buff_addr(0) &&

+		  rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE))

+	  rt = 0xffff0098;

+}

+static void test_plq_off0_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plq 26, +0(0), 1"  );

+	PAD_ORI

+}

+static void test_plq_off8_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plq 26, +8(0), 1"  );

+	PAD_ORI

+}

+static void test_plq_off16_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plq 26, +16(0), 1"  );

+	PAD_ORI

+}

+static void test_plq_off32_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plq 26, +32(0), 1"  );

+	PAD_ORI

+}

+static void test_plq_off48_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plq 26, +48(0), 1"  );

+	PAD_ORI

+}

+static void test_plq_off64_R1 (void) {

+	PAD_ORI

+  __asm__ __volatile__ ("plq 26, +64(0), 1"  );

+	PAD_ORI

+	PAD_ORI

+}

+static void test_pstq_off0_R1 (void) {

+  __asm__ __volatile__ ("pstq 24, -0x1f400+0(0), 1"  );

+}

+static void test_pstq_off8_R1 (void) {

+  __asm__ __volatile__ ("pstq 24, -0x1f400+8(0), 1"  );

+}

+static void test_pstq_off16_R1 (void) {

+  __asm__ __volatile__ ("pstq 24, -0x1f400+16(0), 1"  );

+}

+static void test_pstq_off32_R1 (void) {

+  __asm__ __volatile__ ("pstq 24, -0x1f400+32(0), 1"  );

+}

+static void test_pstq_off64_R1 (void) {

+  __asm__ __volatile__ ("pstq 24, -0x1f400+64(0), 1"  );

+}

+

+static test_list_t testgroup_generic[] = {

+  { &test_paddi_0_R1, "paddi 0_R1", "RT,RA,SI,R"}, /* bcwp */

+  { &test_paddi_12_R1, "paddi 12_R1", "RT,RA,SI,R"}, /* bcwp */

+  { &test_paddi_48_R1, "paddi 48_R1", "RT,RA,SI,R"}, /* bcwp */

+  { &test_paddi_98_R1, "paddi 98_R1", "RT,RA,SI,R"}, /* bcwp */

+  { &test_plbz_off0_R1, "plbz off0_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plbz_off8_R1, "plbz off8_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plbz_off16_R1, "plbz off16_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plbz_off32_R1, "plbz off32_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plbz_off64_R1, "plbz off64_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_pld_off0_R1, "pld off0_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_pld_off8_R1, "pld off8_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_pld_off16_R1, "pld off16_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_pld_off32_R1, "pld off32_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_pld_off64_R1, "pld off64_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plha_off0_R1, "plha off0_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plha_off8_R1, "plha off8_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plha_off16_R1, "plha off16_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plha_off32_R1, "plha off32_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plha_off64_R1, "plha off64_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plhz_off0_R1, "plhz off0_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plhz_off8_R1, "plhz off8_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plhz_off16_R1, "plhz off16_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plhz_off32_R1, "plhz off32_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plhz_off64_R1, "plhz off64_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plq_off0_R1, "plq off0_R1", "RTp,D(RA),R"}, /* bcwp */

+  { &test_plq_off8_R1, "plq off8_R1", "RTp,D(RA),R"}, /* bcwp */

+  { &test_plq_off16_R1, "plq off16_R1", "RTp,D(RA),R"}, /* bcwp */

+  { &test_plq_off32_R1, "plq off32_R1", "RTp,D(RA),R"}, /* bcwp */

+  { &test_plq_off48_R1, "plq off48_R1", "RTp,D(RA),R"}, /* bcwp */

+  { &test_plq_off64_R1, "plq off64_R1", "RTp,D(RA),R"}, /* bcwp */

+  { &test_plwa_off0_R1, "plwa off0_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwa_off8_R1, "plwa off8_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwa_off16_R1, "plwa off16_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwa_off32_R1, "plwa off32_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwa_off64_R1, "plwa off64_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwz_off0_R1, "plwz off0_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwz_off8_R1, "plwz off8_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwz_off16_R1, "plwz off16_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwz_off32_R1, "plwz off32_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plwz_off64_R1, "plwz off64_R1", "RT,D(RA),R"}, /* bcwp */

+  { &test_plxvp_off0_R1, "plxvp off0_R1", "XTp,D(RA),R"}, /* bcwp */

+  { &test_plxvp_off8_R1, "plxvp off8_R1", "XTp,D(RA),R"}, /* bcwp */

+  { &test_plxvp_off16_R1, "plxvp off16_R1", "XTp,D(RA),R"}, /* bcwp */

+  { &test_plxvp_off24_R1, "plxvp off24_R1", "XTp,D(RA),R"}, /* bcwp */

+  { &test_plxvp_off32_R1, "plxvp off32_R1", "XTp,D(RA),R"}, /* bcwp */

+  { &test_pstb_off0_R1, "pstb off0_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstb_off8_R1, "pstb off8_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstb_off16_R1, "pstb off16_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstb_off32_R1, "pstb off32_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstd_off0_R1, "pstd off0_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstd_off8_R1, "pstd off8_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstd_off16_R1, "pstd off16_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstd_off32_R1, "pstd off32_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_psth_off0_R1, "psth off0_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_psth_off8_R1, "psth off8_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_psth_off16_R1, "psth off16_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_psth_off32_R1, "psth off32_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstq_off0_R1, "pstq off0_R1", "RSp,D(RA),R"}, /* bcwp */

+  { &test_pstq_off8_R1, "pstq off8_R1", "RSp,D(RA),R"}, /* bcwp */

+  { &test_pstq_off16_R1, "pstq off16_R1", "RSp,D(RA),R"}, /* bcwp */

+  { &test_pstq_off32_R1, "pstq off32_R1", "RSp,D(RA),R"}, /* bcwp */

+  { &test_pstq_off64_R1, "pstq off64_R1", "RSp,D(RA),R"}, /* bcwp */

+  { &test_pstw_off0_R1, "pstw off0_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstw_off8_R1, "pstw off8_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstw_off16_R1, "pstw off16_R1", "RS,D(RA),R"}, /* bcwp */

+  { &test_pstw_off32_R1, "pstw off32_R1", "RS,D(RA),R"}, /* bcwp */

+	{ NULL, 	    NULL },

+};

+

+/*  Allow skipping of tests. */

+unsigned long test_count=0xffff;

+unsigned long skip_count=0;

+unsigned long setup_only=0;

+

+/*  Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs.  */

+static jmp_buf mybuf;

+

+/* This (testfunction_generic) is meant to handle all of the instruction

+   variations.  The helpers set up the register and iterator values

+   as is appropriate for the instruction being tested.  */

+static void testfunction_generic (const char* instruction_name,

+				  test_func_t test_function,

+				  unsigned int ignore_flags,

+				  char * cur_form) {

+

+   identify_form_components (instruction_name , cur_form);

+   debug_show_form (instruction_name, cur_form);

+   set_up_iterators ();

+   debug_show_iter_ranges ();

+   initialize_buffer (0);

+   init_pcrelative_write_target ();

+   debug_dump_buffer ();

+

+   for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) {

+      for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) {

+	 for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) {

+	    for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) {

+		CHECK_OVERRIDES

+		debug_show_current_iteration ();

+		// Be sure to initialize the target registers first.

+		initialize_target_registers ();

+		initialize_source_registers ();

+		printf ("%s", instruction_name);

+		print_register_header ();

+		printf( " =>"); fflush (stdout);

+		if (!setup_only) {

+		  if (enable_setjmp) {

+		   if ( setjmp ( mybuf ) ) {

+		     printf("signal tripped. (FIXME)\n");

+		     continue;

+		   }

+		  }

+		  (*test_function) ();

+		}

+		print_register_footer ();

+		print_result_buffer ();

+		print_pcrelative_write_target ();

+		printf ("\n");

+	    }

+	 }

+      }

+   }

+}

+

+void mykillhandler ( int x ) { longjmp (mybuf, 1); }

+void mysegvhandler ( int x ) { longjmp (mybuf, 1); }

+

+static void do_tests ( void )

+{

+   int groupcount;

+   char * cur_form;

+   test_group_t group_function = &testfunction_generic;

+   test_list_t *tests = testgroup_generic;

+

+   struct sigaction kill_action, segv_action;

+   struct sigaction old_kill_action, old_segv_action;

+   if (enable_setjmp) {

+      kill_action.sa_handler = mykillhandler;

+      segv_action.sa_handler = mysegvhandler;

+      sigemptyset ( &kill_action.sa_mask );

+      sigemptyset ( &segv_action.sa_mask );

+      kill_action.sa_flags = SA_NODEFER;

+      segv_action.sa_flags = SA_NODEFER;

+      sigaction ( SIGILL, &kill_action, &old_kill_action);

+      sigaction ( SIGSEGV, &segv_action, &old_segv_action);

+   }

+

+   for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) {

+	cur_form = strdup(tests[groupcount].form);

+	current_test = tests[groupcount];

+	identify_instruction_by_func_name (current_test.name);

+	if (groupcount < skip_count) continue;

+	if (verbose) printf("Test #%d ,", groupcount);

+	if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose);

+	(*group_function) (current_test.name, current_test.func, 0, cur_form );

+	printf ("\n");

+	if (groupcount >= (skip_count+test_count)) break;

+   }

+   if (debug_show_labels) printf("\n");

+   printf ("All done. Tested %d different instruction groups\n", groupcount);

+}

+

+static void usage (void)

+{

+   fprintf(stderr,

+      "Usage: test_isa_XXX [OPTIONS]\n"

+      "\t-h: display this help and exit\n"

+      "\t-v: increase verbosity\n"

+      "\t-a <foo> : limit number of a-iterations to <foo>\n"

+      "\t-b <foo> : limit number of b-iterations to <foo>\n"

+      "\t-c <foo> : limit number of c-iterations to <foo>\n"

+      "\t-n <foo> : limit to this number of tests.\n"

+      "\t-r <foo>: run only test # <foo> \n"

+      "\t\n"

+      "\t-j :enable setjmp to recover from illegal insns. \n"

+      "\t-m :(dev only?) lock VRM value to zero.\n"

+      "\t-z :(dev only?) lock MC value to zero.\n"

+      "\t-p :(dev only?) disable prefix instructions\n"

+      "\t-s <foo>: skip <foo> tests \n"

+      "\t-c <foo>: stop after running <foo> # of tests \n"

+      "\t-f : Do the test setup but do not actually execute the test instruction. \n"

+   );

+}

+

+int main (int argc, char **argv)

+{

+   int c;

+   while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) {

+      switch (c) {

+	 case 'h':

+	    usage();

+	    return 0;

+

+	 case 'v':

+	    verbose++;

+	    break;

+

+	 /* Options related to limiting the test iterations.  */

+	 case 'a':

+	    a_limit=atoi (optarg);

+	    printf ("limiting a-iters to %ld.\n", a_limit);

+	    break;

+	 case 'b':

+	    b_limit=atoi (optarg);

+	    printf ("limiting b-iters to %ld.\n", b_limit);

+	    break;

+	 case 'c':

+	    c_limit=atoi (optarg);

+	    printf ("limiting c-iters to %ld.\n", c_limit);

+	    break;

+	 case 'n': // run this number of tests.

+	    test_count=atoi (optarg);

+	    printf ("limiting to %ld tests\n", test_count);

+	    break;

+	 case 'r': // run just test #<foo>.

+	    skip_count=atoi (optarg);

+	    test_count=0;

+	    if (verbose) printf("Running test number %ld\n", skip_count);

+	    break;

+	 case 's': // skip this number of tests.

+	    skip_count=atoi (optarg);

+	    printf ("skipping %ld tests\n", skip_count);

+	    break;

+

+	 /* debug options.  */

+	 case 'd':

+	    dump_tables=1;

+	    printf("DEBUG:dump_tables.\n");

+	    break;

+	 case 'f':

+	    setup_only=1;

+	    printf("DEBUG:setup_only.\n");

+	    break;

+	 case 'j':

+	    enable_setjmp=1;

+	    printf ("DEBUG:setjmp enabled.\n");

+	    break;

+	 case 'm':

+	    vrm_override=1;

+	    printf ("DEBUG:vrm override enabled.\n");

+	    break;

+	 case 'p':

+	    prefix_override=1;

+	    printf ("DEBUG:prefix override enabled.\n");

+	    break;

+	 case 'z':

+	    mc_override=1;

+	    printf ("DEBUG:MC override enabled.\n");

+	    break;

+	 default:

+	    usage();

+	    fprintf(stderr, "Unknown argument: '%c'\n", c);

+	   }

+	}

+

+	generic_prologue ();

+	build_vsx_table ();

+	build_args_table ();

+	build_float_vsx_tables ();

+

+	if (dump_tables) {

+	   dump_float_vsx_tables ();

+	   dump_vsxargs ();

+	}

+

+	do_tests ();

+

+	return 0;

+}

+

+#else	   // HAS_ISA_3_1

+int main (int argc, char **argv)

+{

+   printf("NO ISA 3.1 SUPPORT\n");

+   return 0;

+}

+#endif

diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp b/none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp

new file mode 100644

index 000000000..139597f9c

--- /dev/null

+++ b/none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp

@@ -0,0 +1,2 @@

+

+

diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp

new file mode 100644

index 000000000..87594748f

--- /dev/null

+++ b/none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp

@@ -0,0 +1,138 @@

+paddi 0_R1 =>         ffff0000

+

+paddi 12_R1 =>         ffff0012

+

+paddi 48_R1 =>         ffff0048

+

+paddi 98_R1 =>         ffff0098

+

+plbz off0_R1 =>               1a

+

+plbz off8_R1 =>               1f

+

+plbz off16_R1 =>               1f

+

+plbz off32_R1 =>               1b

+

+plbz off64_R1 =>               1b

+

+pld off0_R1 => e740000004100000

+

+pld off8_R1 =>         4e800020

+

+pld off16_R1 => 6318001862f7001f

+

+pld off32_R1 => 639c001c637b001b

+

+pld off64_R1 => 639c001c637b001b

+

+plha off0_R1 =>               1a

+

+plha off8_R1 =>               1f

+

+plha off16_R1 =>               1f

+

+plha off32_R1 =>               1b

+

+plha off64_R1 =>               1b

+

+plhz off0_R1 =>               1a

+

+plhz off8_R1 =>               1f

+

+plhz off16_R1 =>               1f

+

+plhz off32_R1 =>               1b

+

+plhz off64_R1 =>               1b

+

+plq off0_R1 => e34000000410001a 62d6001662b5001f

+

+plq off8_R1 => 62d6001662b5001f 6318001862f7001f

+

+plq off16_R1 => 6318001862f7001f 635a001a6339001b

+

+plq off32_R1 => 639c001c637b001b         4e80003b

+

+plq off48_R1 =>               1a 62d6001662b5001f

+

+plq off64_R1 => 639c001c637b001b         4e80003b

+

+plwa off0_R1 =>          4100000

+

+plwa off8_R1 =>         4e800020

+

+plwa off16_R1 =>                0

+

+plwa off32_R1 =>         637b001b

+

+plwa off64_R1 =>         637b001b

+

+plwz off0_R1 =>          6100000

+

+plwz off8_R1 =>         4e800020

+

+plwz off16_R1 =>                0

+

+plwz off32_R1 =>         637b001b

+

+plwz off64_R1 =>         637b001b

+

+plxvp off0_R1 => 6318001862f70017 635a001a63390019 ea80000004100000 62d6001662b50015

+

+plxvp off8_R1 => 635a001a63390019 639c001c637b001b 62d6001662b50015 6318001862f70017

+

+plxvp off16_R1 => 639c001c637b001b 000000004e800020 6318001862f70017 635a001a63390019

+

+plxvp off24_R1 => 000000004e800020 0000000000000000 635a001a63390019 639c001c637b001b

+

+plxvp off32_R1 => 0000000000000000 62d6001662b50015 639c001c637b001b 000000004e800020

+