From 3fbde55a5696c9273084ee2c44daca752e407597 Mon Sep 17 00:00:00 2001

From: Andreas Arnez <arnez@linux.ibm.com>

Date: Tue, 26 Jan 2021 15:06:47 +0100

Subject: [PATCH 01/13] s390x: Misc-insn-3, bitwise logical 3-way instructions

Add support for the instructions NCRK, NCGRK, NNRK, NNGRK, NORK, NOGRK,

NXRK, NXGRK, OCRK, and OCGRK.  Introduce a common helper and use it for

the existing instructions NRK, NGRK, XRK, XGRK, ORK, and OGRK as well.

---

 VEX/priv/guest_s390_toIR.c | 154 ++++++++++++++++++++++++++-----------

 1 file changed, 109 insertions(+), 45 deletions(-)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c

index a73dcfb14..f8afd5b96 100644

--- a/VEX/priv/guest_s390_toIR.c

+++ b/VEX/priv/guest_s390_toIR.c

@@ -5022,8 +5022,12 @@ s390_irgen_NGR(UChar r1, UChar r2)

    return "ngr";

 }

+/* Helper for bitwise logical instructions with two 32-bit input operands and a

+   32-bit output operand.  `inv3' and `inv' indicate whether to invert (build

+   bitwise complement of) operand 3 or the result, respectively. */

 static const HChar *

-s390_irgen_NRK(UChar r3, UChar r1, UChar r2)

+s390_irgen_logicalK32(UChar r3, UChar r1, UChar r2,

+                      const HChar *mnem, IROp op, Bool inv3, Bool inv)

 {

    IRTemp op2 = newTemp(Ity_I32);

    IRTemp op3 = newTemp(Ity_I32);

@@ -5031,15 +5035,19 @@ s390_irgen_NRK(UChar r3, UChar r1, UChar r2)

    assign(op2, get_gpr_w1(r2));

    assign(op3, get_gpr_w1(r3));

-   assign(result, binop(Iop_And32, mkexpr(op2), mkexpr(op3)));

+   IRExpr* tmp = binop(op, mkexpr(op2),

+                       inv3 ? unop(Iop_Not32, mkexpr(op3)) : mkexpr(op3));

+   assign(result, inv ? unop(Iop_Not32, tmp) : tmp);

    s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result);

    put_gpr_w1(r1, mkexpr(result));

-   return "nrk";

+   return mnem;

 }

+/* Same as s390_irgen_logicalK32, but for 64-bit operands. */

 static const HChar *

-s390_irgen_NGRK(UChar r3, UChar r1, UChar r2)

+s390_irgen_logicalK64(UChar r3, UChar r1, UChar r2,

+                      const HChar *mnem, IROp op, Bool inv3, Bool inv)

 {

    IRTemp op2 = newTemp(Ity_I64);

    IRTemp op3 = newTemp(Ity_I64);

@@ -5047,11 +5055,49 @@ s390_irgen_NGRK(UChar r3, UChar r1, UChar r2)

    assign(op2, get_gpr_dw0(r2));

    assign(op3, get_gpr_dw0(r3));

-   assign(result, binop(Iop_And64, mkexpr(op2), mkexpr(op3)));

+   IRExpr* tmp = binop(op, mkexpr(op2),

+                       inv3 ? unop(Iop_Not64, mkexpr(op3)) : mkexpr(op3));

+   assign(result, inv ? unop(Iop_Not64, tmp) : tmp);

    s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result);

    put_gpr_dw0(r1, mkexpr(result));

-   return "ngrk";

+   return mnem;

+}

+

+static const HChar *

+s390_irgen_NRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK32(r3, r1, r2, "nrk", Iop_And32, False, False);

+}

+

+static const HChar *

+s390_irgen_NGRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK64(r3, r1, r2, "ngrk", Iop_And64, False, False);

+}

+

+static const HChar *

+s390_irgen_NCRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK32(r3, r1, r2, "ncrk", Iop_And32, True, False);

+}

+

+static const HChar *

+s390_irgen_NCGRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK64(r3, r1, r2, "ncgrk", Iop_And64, True, False);

+}

+

+static const HChar *

+s390_irgen_NNRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK32(r3, r1, r2, "nnrk", Iop_And32, False, True);

+}

+

+static const HChar *

+s390_irgen_NNGRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK64(r3, r1, r2, "nngrk", Iop_And64, False, True);

 }

 static const HChar *

@@ -7071,33 +7117,25 @@ s390_irgen_XGR(UChar r1, UChar r2)

 static const HChar *

 s390_irgen_XRK(UChar r3, UChar r1, UChar r2)

 {

-   IRTemp op2 = newTemp(Ity_I32);

-   IRTemp op3 = newTemp(Ity_I32);

-   IRTemp result = newTemp(Ity_I32);

-

-   assign(op2, get_gpr_w1(r2));

-   assign(op3, get_gpr_w1(r3));

-   assign(result, binop(Iop_Xor32, mkexpr(op2), mkexpr(op3)));

-   s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result);

-   put_gpr_w1(r1, mkexpr(result));

-

-   return "xrk";

+   return s390_irgen_logicalK32(r3, r1, r2, "xrk", Iop_Xor32, False, False);

 }

 static const HChar *

 s390_irgen_XGRK(UChar r3, UChar r1, UChar r2)

 {

-   IRTemp op2 = newTemp(Ity_I64);

-   IRTemp op3 = newTemp(Ity_I64);

-   IRTemp result = newTemp(Ity_I64);

+   return s390_irgen_logicalK64(r3, r1, r2, "xgrk", Iop_Xor64, False, False);

+}

-   assign(op2, get_gpr_dw0(r2));

-   assign(op3, get_gpr_dw0(r3));

-   assign(result, binop(Iop_Xor64, mkexpr(op2), mkexpr(op3)));

-   s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result);

-   put_gpr_dw0(r1, mkexpr(result));

+static const HChar *

+s390_irgen_NXRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK32(r3, r1, r2, "nxrk", Iop_Xor32, False, True);

+}

-   return "xgrk";

+static const HChar *

+s390_irgen_NXGRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK64(r3, r1, r2, "nxgrk", Iop_Xor64, False, True);

 }

 static const HChar *

@@ -8920,33 +8958,37 @@ s390_irgen_OGR(UChar r1, UChar r2)

 static const HChar *

 s390_irgen_ORK(UChar r3, UChar r1, UChar r2)

 {

-   IRTemp op2 = newTemp(Ity_I32);

-   IRTemp op3 = newTemp(Ity_I32);

-   IRTemp result = newTemp(Ity_I32);

+   return s390_irgen_logicalK32(r3, r1, r2, "ork", Iop_Or32, False, False);

+}

-   assign(op2, get_gpr_w1(r2));

-   assign(op3, get_gpr_w1(r3));

-   assign(result, binop(Iop_Or32, mkexpr(op2), mkexpr(op3)));

-   s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result);

-   put_gpr_w1(r1, mkexpr(result));

+static const HChar *

+s390_irgen_OGRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK64(r3, r1, r2, "ogrk", Iop_Or64, False, False);

+}

-   return "ork";

+static const HChar *

+s390_irgen_OCRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK32(r3, r1, r2, "ocrk", Iop_Or32, True, False);

 }

 static const HChar *

-s390_irgen_OGRK(UChar r3, UChar r1, UChar r2)

+s390_irgen_OCGRK(UChar r3, UChar r1, UChar r2)

 {

-   IRTemp op2 = newTemp(Ity_I64);

-   IRTemp op3 = newTemp(Ity_I64);

-   IRTemp result = newTemp(Ity_I64);

+   return s390_irgen_logicalK64(r3, r1, r2, "ocgrk", Iop_Or64, True, False);

+}

-   assign(op2, get_gpr_dw0(r2));

-   assign(op3, get_gpr_dw0(r3));

-   assign(result, binop(Iop_Or64, mkexpr(op2), mkexpr(op3)));

-   s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result);

-   put_gpr_dw0(r1, mkexpr(result));

+static const HChar *

+s390_irgen_NORK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK32(r3, r1, r2, "nork", Iop_Or32, False, True);

+}

-   return "ogrk";

+static const HChar *

+s390_irgen_NOGRK(UChar r3, UChar r1, UChar r2)

+{

+   return s390_irgen_logicalK64(r3, r1, r2, "nogrk", Iop_Or64, False, True);

 }

 static const HChar *

@@ -20031,12 +20073,28 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb961: s390_format_RRF_U0RR(s390_irgen_CLGRT, RRF2_m3(ovl),

                                      RRF2_r1(ovl), RRF2_r2(ovl),

                                      S390_XMNM_CAB); goto ok;

+   case 0xb964: s390_format_RRF_R0RR2(s390_irgen_NNGRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

+   case 0xb965: s390_format_RRF_R0RR2(s390_irgen_OCGRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

+   case 0xb966: s390_format_RRF_R0RR2(s390_irgen_NOGRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

+   case 0xb967: s390_format_RRF_R0RR2(s390_irgen_NXGRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

    case 0xb972: s390_format_RRF_U0RR(s390_irgen_CRT, RRF2_m3(ovl),

                                      RRF2_r1(ovl), RRF2_r2(ovl),

                                      S390_XMNM_CAB); goto ok;

    case 0xb973: s390_format_RRF_U0RR(s390_irgen_CLRT, RRF2_m3(ovl),

                                      RRF2_r1(ovl), RRF2_r2(ovl),

                                      S390_XMNM_CAB); goto ok;

+   case 0xb974: s390_format_RRF_R0RR2(s390_irgen_NNRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

+   case 0xb975: s390_format_RRF_R0RR2(s390_irgen_OCRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

+   case 0xb976: s390_format_RRF_R0RR2(s390_irgen_NORK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

+   case 0xb977: s390_format_RRF_R0RR2(s390_irgen_NXRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;

    case 0xb980: s390_format_RRE_RR(s390_irgen_NGR, RRE_r1(ovl),

                                    RRE_r2(ovl));  goto ok;

    case 0xb981: s390_format_RRE_RR(s390_irgen_OGR, RRE_r1(ovl),

@@ -20148,6 +20206,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb9e4: s390_format_RRF_R0RR2(s390_irgen_NGRK, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

+   case 0xb9e5: s390_format_RRF_R0RR2(s390_irgen_NCGRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl));

+                                      goto ok;

    case 0xb9e6: s390_format_RRF_R0RR2(s390_irgen_OGRK, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

@@ -20178,6 +20239,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb9f4: s390_format_RRF_R0RR2(s390_irgen_NRK, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

+   case 0xb9f5: s390_format_RRF_R0RR2(s390_irgen_NCRK, RRF4_r3(ovl),

+                                      RRF4_r1(ovl), RRF4_r2(ovl));

+                                      goto ok;

    case 0xb9f6: s390_format_RRF_R0RR2(s390_irgen_ORK, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

-- 

2.23.0

From 748421b31ab6b15cc849bd6b9588ad759b807324 Mon Sep 17 00:00:00 2001

From: Andreas Arnez <arnez@linux.ibm.com>

Date: Wed, 27 Jan 2021 18:11:06 +0100

Subject: [PATCH 02/13] s390x: Misc-insn-3, "select" instructions

Add support for the instructions SELR, SELGR, and SELFHR.

---

 VEX/priv/guest_s390_toIR.c | 43 ++++++++++++++++++++++++++++++++++++++

 1 file changed, 43 insertions(+)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c

index f8afd5b96..41265631b 100644

--- a/VEX/priv/guest_s390_toIR.c

+++ b/VEX/priv/guest_s390_toIR.c

@@ -3113,6 +3113,16 @@ s390_format_RRF_FUFF2(const HChar *(*irgen)(UChar, UChar, UChar, UChar),

       s390_disasm(ENC5(MNM, FPR, FPR, FPR, UINT), mnm, r1, r2, r3, m4);

 }

+static void

+s390_format_RRF_RURR(const HChar *(*irgen)(UChar, UChar, UChar, UChar),

+                     UChar r3, UChar m4, UChar r1, UChar r2)

+{

+   const HChar *mnm = irgen(r3, m4, r1, r2);

+

+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))

+      s390_disasm(ENC5(MNM, GPR, GPR, GPR, UINT), mnm, r1, r3, r2, m4);

+}

+

 static void

 s390_format_RRF_R0RR2(const HChar *(*irgen)(UChar r3, UChar r1, UChar r2),

                       UChar r3, UChar r1, UChar r2)

@@ -19254,6 +19264,30 @@ s390_irgen_VBPERM(UChar v1, UChar v2, UChar v3)

    return "vbperm";

 }

+static const HChar *

+s390_irgen_SELR(UChar r3, UChar m4, UChar r1, UChar r2)

+{

+   IRExpr* cond = binop(Iop_CmpNE32, s390_call_calculate_cond(m4), mkU32(0));

+   put_gpr_w1(r1, mkite(cond, get_gpr_w1(r2), get_gpr_w1(r3)));

+   return "selr";

+}

+

+static const HChar *

+s390_irgen_SELGR(UChar r3, UChar m4, UChar r1, UChar r2)

+{

+   IRExpr* cond = binop(Iop_CmpNE32, s390_call_calculate_cond(m4), mkU32(0));

+   put_gpr_dw0(r1, mkite(cond, get_gpr_dw0(r2), get_gpr_dw0(r3)));

+   return "selgr";

+}

+

+static const HChar *

+s390_irgen_SELFHR(UChar r3, UChar m4, UChar r1, UChar r2)

+{

+   IRExpr* cond = binop(Iop_CmpNE32, s390_call_calculate_cond(m4), mkU32(0));

+   put_gpr_w0(r1, mkite(cond, get_gpr_w0(r2), get_gpr_w0(r3)));

+   return "selfhr";

+}

+

 /* New insns are added here.

    If an insn is contingent on a facility being installed also

    check whether the list of supported facilities in function

@@ -20163,6 +20197,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb9bd: /* TRTRE */ goto unimplemented;

    case 0xb9be: /* SRSTU */ goto unimplemented;

    case 0xb9bf: /* TRTE */ goto unimplemented;

+   case 0xb9c0: s390_format_RRF_RURR(s390_irgen_SELFHR, RRF4_r3(ovl),

+                                     RRF4_m4(ovl), RRF4_r1(ovl),

+                                     RRF4_r2(ovl)); goto ok;

    case 0xb9c8: s390_format_RRF_R0RR2(s390_irgen_AHHHR, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

@@ -20203,6 +20240,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb9e2: s390_format_RRF_U0RR(s390_irgen_LOCGR, RRF3_r3(ovl),

                                      RRF3_r1(ovl), RRF3_r2(ovl),

                                      S390_XMNM_LOCGR);  goto ok;

+   case 0xb9e3: s390_format_RRF_RURR(s390_irgen_SELGR, RRF4_r3(ovl),

+                                     RRF4_m4(ovl), RRF4_r1(ovl),

+                                     RRF4_r2(ovl)); goto ok;

    case 0xb9e4: s390_format_RRF_R0RR2(s390_irgen_NGRK, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

@@ -20233,6 +20273,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb9ed: s390_format_RRF_R0RR2(s390_irgen_MSGRKC, RRF4_r3(ovl),

                                       RRF4_r1(ovl), RRF4_r2(ovl));

                                       goto ok;

+   case 0xb9f0: s390_format_RRF_RURR(s390_irgen_SELR, RRF4_r3(ovl),

+                                     RRF4_m4(ovl), RRF4_r1(ovl),

+                                     RRF4_r2(ovl)); goto ok;

    case 0xb9f2: s390_format_RRF_U0RR(s390_irgen_LOCR, RRF3_r3(ovl),

                                      RRF3_r1(ovl), RRF3_r2(ovl),

                                      S390_XMNM_LOCR);  goto ok;

-- 

2.23.0

From 31cbd583e858f47a86ada087d21a6abc13ba04f2 Mon Sep 17 00:00:00 2001

From: Andreas Arnez <arnez@linux.ibm.com>

Date: Thu, 28 Jan 2021 19:47:00 +0100

Subject: [PATCH 03/13] s390x: Misc-insn-3, new POPCNT variant

Add support for the new POPCNT variant that has bit 0 of the M3 field set

and yields the total number of one bits in its 64-bit operand.

---

 VEX/priv/guest_s390_toIR.c | 44 ++++++++++++++++++++++++++------------

 1 file changed, 30 insertions(+), 14 deletions(-)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c

index 41265631b..ca9e6dc03 100644

--- a/VEX/priv/guest_s390_toIR.c

+++ b/VEX/priv/guest_s390_toIR.c

@@ -3073,6 +3073,20 @@ s390_format_RRF_U0RR(const HChar *(*irgen)(UChar m3, UChar r1, UChar r2),

       s390_disasm(ENC3(XMNM, GPR, GPR), xmnm_kind, m3, r1, r2);

 }

+static void

+s390_format_RRFa_U0RR(const HChar *(*irgen)(UChar m3, UChar r1, UChar r2),

+                      UChar m3, UChar r1, UChar r2)

+{

+   const HChar *mnm = irgen(m3, r1, r2);

+

+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) {

+      if (m3 != 0)

+         s390_disasm(ENC4(MNM, GPR, GPR, UINT), mnm, r1, r2, m3);

+      else

+         s390_disasm(ENC3(MNM, GPR, GPR), mnm, r1, r2);

+   }

+}

+

 static void

 s390_format_RRF_F0FF2(const HChar *(*irgen)(UChar, UChar, UChar),

                       UChar r3, UChar r1, UChar r2)

@@ -15112,30 +15126,32 @@ s390_irgen_FLOGR(UChar r1, UChar r2)

 }

 static const HChar *

-s390_irgen_POPCNT(UChar r1, UChar r2)

+s390_irgen_POPCNT(UChar m3, UChar r1, UChar r2)

 {

-   Int i;

+   s390_insn_assert("popcnt", (m3 & 7) == 0);

+

+   static const ULong masks[] = {

+      0x5555555555555555, 0x3333333333333333, 0x0F0F0F0F0F0F0F0F,

+      0x00FF00FF00FF00FF, 0x0000FFFF0000FFFF, 0x00000000FFFFFFFF,

+   };

+   Int i, n;

    IRTemp val = newTemp(Ity_I64);

-   IRTemp mask[3];

    assign(val, get_gpr_dw0(r2));

-   for (i = 0; i < 3; i++) {

-      mask[i] = newTemp(Ity_I64);

-   }

-   assign(mask[0], mkU64(0x5555555555555555ULL));

-   assign(mask[1], mkU64(0x3333333333333333ULL));

-   assign(mask[2], mkU64(0x0F0F0F0F0F0F0F0FULL));

-   for (i = 0; i < 3; i++) {

+   n = (m3 & 8) ? 6 : 3;

+   for (i = 0; i < n; i++) {

+      IRTemp mask = newTemp(Ity_I64);

       IRTemp tmp = newTemp(Ity_I64);

+      assign (mask, mkU64(masks[i]));

       assign(tmp,

              binop(Iop_Add64,

                    binop(Iop_And64,

                          mkexpr(val),

-                         mkexpr(mask[i])),

+                         mkexpr(mask)),

                    binop(Iop_And64,

                          binop(Iop_Shr64, mkexpr(val), mkU8(1 << i)),

-                         mkexpr(mask[i]))));

+                         mkexpr(mask))));

       val = tmp;

    }

    s390_cc_thunk_putZ(S390_CC_OP_BITWISE, val);

@@ -20235,8 +20251,8 @@ s390_decode_4byte_and_irgen(const UChar *bytes)

    case 0xb9e0: s390_format_RRF_U0RR(s390_irgen_LOCFHR, RRF3_r3(ovl),

                                      RRF3_r1(ovl), RRF3_r2(ovl),

                                      S390_XMNM_LOCFHR);  goto ok;

-   case 0xb9e1: s390_format_RRE_RR(s390_irgen_POPCNT, RRE_r1(ovl),

-                                   RRE_r2(ovl));  goto ok;

+   case 0xb9e1: s390_format_RRFa_U0RR(s390_irgen_POPCNT, RRF3_r3(ovl),

+                                      RRF3_r1(ovl), RRF3_r2(ovl));  goto ok;

    case 0xb9e2: s390_format_RRF_U0RR(s390_irgen_LOCGR, RRF3_r3(ovl),

                                      RRF3_r1(ovl), RRF3_r2(ovl),

                                      S390_XMNM_LOCGR);  goto ok;

-- 

2.23.0

From 64352d57f93711ce76fd481558dcf6d65e26b19f Mon Sep 17 00:00:00 2001

From: Andreas Arnez <arnez@linux.ibm.com>

Date: Fri, 29 Jan 2021 20:13:05 +0100

Subject: [PATCH 04/13] s390x: Misc-insn-3, MVCRL

Add support for the "move right to left" instruction MVCRL.

---

 VEX/priv/guest_s390_toIR.c | 47 ++++++++++++++++++++++++++++++++++++++

 1 file changed, 47 insertions(+)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c

index ca9e6dc03..9f7d98f8c 100644

--- a/VEX/priv/guest_s390_toIR.c

+++ b/VEX/priv/guest_s390_toIR.c

@@ -3562,6 +3562,25 @@ s390_format_SS_L0RDRD(const HChar *(*irgen)(UChar, IRTemp, IRTemp),

       s390_disasm(ENC3(MNM, UDLB, UDXB), mnm, d1, l, b1, d2, 0, b2);

 }

+static void

+s390_format_SSE_RDRD(const HChar *(*irgen)(IRTemp, IRTemp),

+                     UChar b1, UShort d1, UChar b2, UShort d2)

+{

+   const HChar *mnm;

+   IRTemp op1addr = newTemp(Ity_I64);

+   IRTemp op2addr = newTemp(Ity_I64);

+

+   assign(op1addr, binop(Iop_Add64, mkU64(d1), b1 != 0 ? get_gpr_dw0(b1) :

+          mkU64(0)));

+   assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) :

+          mkU64(0)));

+

+   mnm = irgen(op1addr, op2addr);

+

+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))

+      s390_disasm(ENC2(UDXB, UDXB), mnm, d1, 0, b1, d2, 0, b2);

+}

+

 static void

 s390_format_SIL_RDI(const HChar *(*irgen)(UShort i2, IRTemp op1addr),

                     UChar b1, UShort d1, UShort i2)

@@ -13667,6 +13686,31 @@ s390_irgen_MVCIN(UChar length, IRTemp start1, IRTemp start2)

    return "mvcin";

 }

+static const HChar *

+s390_irgen_MVCRL(IRTemp op1addr, IRTemp op2addr)

+{

+   IRTemp counter = newTemp(Ity_I64);

+   IRTemp offset = newTemp(Ity_I64);

+

+   assign(counter, get_counter_dw0());

+   /* offset = length - 1 - counter, where length-1 is specified in r0 */

+   assign(offset,

+          binop(Iop_Sub64,

+                unop(Iop_16Uto64,

+                     binop(Iop_And16, get_gpr_hw3(0), mkU16(0xfff))),

+                mkexpr(counter)));

+

+   store(binop(Iop_Add64, mkexpr(op1addr), mkexpr(offset)),

+         load(Ity_I8, binop(Iop_Add64, mkexpr(op2addr), mkexpr(offset))));

+

+   /* Check for end of field */

+   put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));

+   iterate_if(binop(Iop_CmpNE64, mkexpr(offset), mkU64(0)));

+   put_counter_dw0(mkU64(0));

+

+   return "mvcrl";

+}

+

 static const HChar *

 s390_irgen_MVCL(UChar r1, UChar r2)

 {

@@ -22217,6 +22261,9 @@ s390_decode_6byte_and_irgen(const UChar *bytes)

    case 0xe500ULL: /* LASP */ goto unimplemented;

    case 0xe501ULL: /* TPROT */ goto unimplemented;

    case 0xe502ULL: /* STRAG */ goto unimplemented;

+   case 0xe50aULL: s390_format_SSE_RDRD(s390_irgen_MVCRL,

+                                        SS_b1(ovl), SS_d1(ovl),

+                                        SS_b2(ovl), SS_d2(ovl));  goto ok;

    case 0xe50eULL: /* MVCSK */ goto unimplemented;

    case 0xe50fULL: /* MVCDK */ goto unimplemented;

    case 0xe544ULL: s390_format_SIL_RDI(s390_irgen_MVHHI, SIL_b1(ovl),

-- 

2.23.0

From 6cc4d66cc3a999253d9a57e2b5c75aeb67f77918 Mon Sep 17 00:00:00 2001

From: Andreas Arnez <arnez@linux.ibm.com>

Date: Tue, 2 Feb 2021 20:15:02 +0100

Subject: [PATCH 05/13] s390x: Misc-insn-3, test case

Add a test case for the new instructions in the miscellaneous instruction

extensions facitility 3.

---

 .gitignore                        |   1 +

 none/tests/s390x/Makefile.am      |   3 +-

 none/tests/s390x/misc3.c          | 182 ++++++++++++++++++++++++++++++

 none/tests/s390x/misc3.stderr.exp |   2 +

 none/tests/s390x/misc3.stdout.exp | 103 +++++++++++++++++

 none/tests/s390x/misc3.vgtest     |   1 +

 6 files changed, 291 insertions(+), 1 deletion(-)

 create mode 100644 none/tests/s390x/misc3.c

 create mode 100644 none/tests/s390x/misc3.stderr.exp

 create mode 100644 none/tests/s390x/misc3.stdout.exp

 create mode 100644 none/tests/s390x/misc3.vgtest

diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am

index a0fb92ef5..2fd45ec1e 100644

--- a/none/tests/s390x/Makefile.am

+++ b/none/tests/s390x/Makefile.am

@@ -19,7 +19,8 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \

 	     spechelper-ltr spechelper-or   \

 	     spechelper-icm-1  spechelper-icm-2 spechelper-tmll \

 	     spechelper-tm laa vector lsc2 ppno vector_string vector_integer \

-	     vector_float add-z14 sub-z14 mul-z14 bic

+	     vector_float add-z14 sub-z14 mul-z14 bic \

+	     misc3

 if BUILD_DFP_TESTS

   INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo

diff --git a/none/tests/s390x/misc3.c b/none/tests/s390x/misc3.c

new file mode 100644

index 000000000..ae6e8d4c2

--- /dev/null

+++ b/none/tests/s390x/misc3.c

@@ -0,0 +1,182 @@

+#include <stdio.h>

+

+/* -- Logical instructions -- */

+

+#define TEST_GENERATE(opcode,insn)                              \

+   static void test_##insn(unsigned long a, unsigned long b)    \

+   {                                                            \

+      unsigned long out = 0xdecaffee42424242;                   \

+      int cc;                                                   \

+                                                                \

+      __asm__(                                                  \

+         "cr    0,0\n\t"               /* Clear CC */           \

+         ".insn rrf,0x" #opcode "0000,%[out],%[a],%[b],0\n\t"   \

+         "ipm   %[cc]\n\t"                                      \

+         "srl   %[cc],28\n"                                     \

+         : [out] "+d" (out),                                    \

+           [cc] "=d" (cc)                                       \

+         : [a] "d" (a),                                         \

+           [b] "d" (b)                                          \

+         : "cc");                                               \

+                                                                \

+      printf("\t%016lx %016lx -> %016lx cc=%d\n",               \

+             a, b, out, cc);                                    \

+   }

+

+#define TEST_EXEC(opcode,insn)                             \

+   do {                                                    \

+      puts(#insn);                                         \

+      test_##insn(0, 0);                                   \

+      test_##insn(0, -1);                                  \

+      test_##insn(-1, 0);                                  \

+      test_##insn(-1, -1);                                 \

+      test_##insn(0x012345678abcdef, 0);                   \

+      test_##insn(0x012345678abcdef, -1);                  \

+      test_##insn(0x55555555aaaaaaaa, 0xaaaaaaaa55555555); \

+   } while (0)

+

+#define INSNS                                    \

+   XTEST(b9f5,ncrk);                             \

+   XTEST(b9e5,ncgrk);                            \

+   XTEST(b974,nnrk);                             \

+   XTEST(b964,nngrk);                            \

+   XTEST(b976,nork);                             \

+   XTEST(b966,nogrk);                            \

+   XTEST(b977,nxrk);                             \

+   XTEST(b967,nxgrk);                            \

+   XTEST(b975,ocrk);                             \

+   XTEST(b965,ocgrk);

+

+#define XTEST TEST_GENERATE

+INSNS

+#undef XTEST

+

+static void test_all_logical_insns()

+{

+#define XTEST TEST_EXEC

+   INSNS

+#undef XTEST

+}

+#undef INSNS

+#undef TEST_GENERATE

+#undef TEST_EXEC

+

+

+/* -- Full population count -- */

+

+static void test_popcnt(unsigned long op2)

+{

+   unsigned long result;

+   int cc;

+

+   __asm__(".insn   rrf,0xb9e10000,%[result],%[op2],8,0\n\t"

+           "ipm     %[cc]\n\t"

+           "srl     %[cc],28\n"

+           : [result]"=d" (result),

+             [cc]"=d" (cc)

+           : [op2]"d" (op2)

+           : "cc");

+   printf("\t%016lx -> %2lu cc=%d\n", op2, result, cc);

+}

+

+static int test_all_popcnt()

+{

+   puts("popcnt");

+   test_popcnt(0);

+   test_popcnt(1);

+   test_popcnt(0x8000000000000000);

+   test_popcnt(-1UL);

+   test_popcnt(0xff427e3800556bcd);

+   return 0;

+}

+

+/* -- Select -- */

+

+#define TEST_GENERATE(opcode,insn)                              \

+   static void test_##insn(unsigned long a, unsigned long b)    \

+   {                                                            \

+      unsigned long out0 = 0x0cafebad0badcafe;                  \

+      unsigned long out1 = 0x0badcafe0cafebad;                  \

+                                                                \

+      __asm__(                                                  \

+         "cr    0,0\n\t"               /* Clear CC */           \

+         ".insn rrf,0x" #opcode "0000,%[out0],%[a],%[b],8\n\t"  \

+         ".insn rrf,0x" #opcode "0000,%[out1],%[a],%[b],7\n\t"  \

+         : [out0] "+d" (out0),                                  \

+           [out1] "+d" (out1)                                   \

+         : [a] "d" (a),                                         \

+           [b] "d" (b)                                          \

+         : );                                                   \

+                                                                \

+      printf("\t%016lx %016lx -> %016lx %016lx\n",              \

+             a, b, out0, out1);                                 \

+   }

+

+#define TEST_EXEC(opcode,insn)                             \

+   do {                                                    \

+      puts(#insn);                                         \

+      test_##insn(-1, 0);                                  \

+      test_##insn(0, -1);                                  \

+      test_##insn(0x1234567890abcdef, 0xfedcba9876543210); \

+   } while (0)

+

+#define INSNS                                    \

+   XTEST(b9f0,selr);                             \

+   XTEST(b9e3,selgr);                            \

+   XTEST(b9c0,selfhr);

+

+#define XTEST TEST_GENERATE

+INSNS

+#undef XTEST

+

+static void test_all_select()

+{

+#define XTEST TEST_EXEC

+   INSNS

+#undef XTEST

+}

+#undef INSNS

+#undef TEST_GENERATE

+#undef TEST_EXEC

+

+

+/* -- Move right to left -- */

+

+static void test_mvcrl(void *to, void *from, size_t len)

+{

+   len -= 1;

+   __asm__("lgr    0,%[len]\n\t"

+           ".insn  sse,0xe50a00000000,%[to],%[from]\n\t"

+           : [to] "+Q" (*(struct { char c[len]; } *) to)

+           : [from] "Q" (*(struct { char c[len]; } *) from),

+             [len] "d" (len)

+           : );

+}

+

+static void test_all_mvcrl()

+{

+   static const char pattern[] =

+      "abcdefghijklmnopqrstuvwxyz-0123456789.ABCDEFGHIJKLMNOPQRSTUVWXYZ";

+   char buf[4 * sizeof(pattern) - 2];

+

+   test_mvcrl(buf, (char *) pattern, sizeof(pattern));

+   test_mvcrl(buf + sizeof(pattern) - 1, buf, sizeof(pattern));

+   test_mvcrl(buf + 2 * sizeof(pattern) - 2, buf, 2 * sizeof(pattern) - 1);

+   test_mvcrl(buf + 32, buf + 10, 63);

+   test_mvcrl(buf + 2, buf + 1, 256);

+   test_mvcrl(buf + 254, buf + 256, 2);

+   puts("mvcrl");

+   for (int i = 0; i < 256; i += 64) {

+      printf("\t%.64s\n", buf + i);

+   }

+}

+

+

+int main()

+{

+   test_all_logical_insns();

+   test_all_popcnt();

+   test_all_select();

+   test_all_mvcrl();

+   return 0;

+}

diff --git a/none/tests/s390x/misc3.stderr.exp b/none/tests/s390x/misc3.stderr.exp

new file mode 100644

index 000000000..139597f9c

--- /dev/null

+++ b/none/tests/s390x/misc3.stderr.exp

@@ -0,0 +1,2 @@

+

+

diff --git a/none/tests/s390x/misc3.stdout.exp b/none/tests/s390x/misc3.stdout.exp

new file mode 100644

index 000000000..caaba4960

--- /dev/null

+++ b/none/tests/s390x/misc3.stdout.exp

@@ -0,0 +1,103 @@

+ncrk

+	0000000000000000 0000000000000000 -> decaffee00000000 cc=0

+	0000000000000000 ffffffffffffffff -> decaffee00000000 cc=0

+	ffffffffffffffff 0000000000000000 -> decaffeeffffffff cc=1

+	ffffffffffffffff ffffffffffffffff -> decaffee00000000 cc=0

+	0012345678abcdef 0000000000000000 -> decaffee78abcdef cc=1

+	0012345678abcdef ffffffffffffffff -> decaffee00000000 cc=0

+	55555555aaaaaaaa aaaaaaaa55555555 -> decaffeeaaaaaaaa cc=1

+ncgrk

+	0000000000000000 0000000000000000 -> 0000000000000000 cc=0

+	0000000000000000 ffffffffffffffff -> 0000000000000000 cc=0

+	ffffffffffffffff 0000000000000000 -> ffffffffffffffff cc=1

+	ffffffffffffffff ffffffffffffffff -> 0000000000000000 cc=0

+	0012345678abcdef 0000000000000000 -> 0012345678abcdef cc=1

+	0012345678abcdef ffffffffffffffff -> 0000000000000000 cc=0

+	55555555aaaaaaaa aaaaaaaa55555555 -> 55555555aaaaaaaa cc=1

+nnrk

+	0000000000000000 0000000000000000 -> decaffeeffffffff cc=1

+	0000000000000000 ffffffffffffffff -> decaffeeffffffff cc=1

+	ffffffffffffffff 0000000000000000 -> decaffeeffffffff cc=1

+	ffffffffffffffff ffffffffffffffff -> decaffee00000000 cc=0

+	0012345678abcdef 0000000000000000 -> decaffeeffffffff cc=1

+	0012345678abcdef ffffffffffffffff -> decaffee87543210 cc=1

+	55555555aaaaaaaa aaaaaaaa55555555 -> decaffeeffffffff cc=1

+nngrk

+	0000000000000000 0000000000000000 -> ffffffffffffffff cc=1

+	0000000000000000 ffffffffffffffff -> ffffffffffffffff cc=1

+	ffffffffffffffff 0000000000000000 -> ffffffffffffffff cc=1

+	ffffffffffffffff ffffffffffffffff -> 0000000000000000 cc=0

+	0012345678abcdef 0000000000000000 -> ffffffffffffffff cc=1

+	0012345678abcdef ffffffffffffffff -> ffedcba987543210 cc=1

+	55555555aaaaaaaa aaaaaaaa55555555 -> ffffffffffffffff cc=1

+nork

+	0000000000000000 0000000000000000 -> decaffeeffffffff cc=1

+	0000000000000000 ffffffffffffffff -> decaffee00000000 cc=0

+	ffffffffffffffff 0000000000000000 -> decaffee00000000 cc=0

+	ffffffffffffffff ffffffffffffffff -> decaffee00000000 cc=0

+	0012345678abcdef 0000000000000000 -> decaffee87543210 cc=1

+	0012345678abcdef ffffffffffffffff -> decaffee00000000 cc=0

+	55555555aaaaaaaa aaaaaaaa55555555 -> decaffee00000000 cc=0

+nogrk

+	0000000000000000 0000000000000000 -> ffffffffffffffff cc=1

+	0000000000000000 ffffffffffffffff -> 0000000000000000 cc=0

+	ffffffffffffffff 0000000000000000 -> 0000000000000000 cc=0

+	ffffffffffffffff ffffffffffffffff -> 0000000000000000 cc=0

+	0012345678abcdef 0000000000000000 -> ffedcba987543210 cc=1

+	0012345678abcdef ffffffffffffffff -> 0000000000000000 cc=0

+	55555555aaaaaaaa aaaaaaaa55555555 -> 0000000000000000 cc=0

+nxrk

+	0000000000000000 0000000000000000 -> decaffeeffffffff cc=1

+	0000000000000000 ffffffffffffffff -> decaffee00000000 cc=0

+	ffffffffffffffff 0000000000000000 -> decaffee00000000 cc=0

+	ffffffffffffffff ffffffffffffffff -> decaffeeffffffff cc=1

+	0012345678abcdef 0000000000000000 -> decaffee87543210 cc=1

+	0012345678abcdef ffffffffffffffff -> decaffee78abcdef cc=1

+	55555555aaaaaaaa aaaaaaaa55555555 -> decaffee00000000 cc=0

+nxgrk

+	0000000000000000 0000000000000000 -> ffffffffffffffff cc=1

+	0000000000000000 ffffffffffffffff -> 0000000000000000 cc=0

+	ffffffffffffffff 0000000000000000 -> 0000000000000000 cc=0

+	ffffffffffffffff ffffffffffffffff -> ffffffffffffffff cc=1

+	0012345678abcdef 0000000000000000 -> ffedcba987543210 cc=1

+	0012345678abcdef ffffffffffffffff -> 0012345678abcdef cc=1

+	55555555aaaaaaaa aaaaaaaa55555555 -> 0000000000000000 cc=0

+ocrk

+	0000000000000000 0000000000000000 -> decaffeeffffffff cc=1

+	0000000000000000 ffffffffffffffff -> decaffee00000000 cc=0

+	ffffffffffffffff 0000000000000000 -> decaffeeffffffff cc=1

+	ffffffffffffffff ffffffffffffffff -> decaffeeffffffff cc=1

+	0012345678abcdef 0000000000000000 -> decaffeeffffffff cc=1

+	0012345678abcdef ffffffffffffffff -> decaffee78abcdef cc=1

+	55555555aaaaaaaa aaaaaaaa55555555 -> decaffeeaaaaaaaa cc=1

+ocgrk

+	0000000000000000 0000000000000000 -> ffffffffffffffff cc=1

+	0000000000000000 ffffffffffffffff -> 0000000000000000 cc=0

+	ffffffffffffffff 0000000000000000 -> ffffffffffffffff cc=1

+	ffffffffffffffff ffffffffffffffff -> ffffffffffffffff cc=1

+	0012345678abcdef 0000000000000000 -> ffffffffffffffff cc=1

+	0012345678abcdef ffffffffffffffff -> 0012345678abcdef cc=1

+	55555555aaaaaaaa aaaaaaaa55555555 -> 55555555aaaaaaaa cc=1

+popcnt

+	0000000000000000 ->  0 cc=0

+	0000000000000001 ->  1 cc=1

+	8000000000000000 ->  1 cc=1

+	ffffffffffffffff -> 64 cc=1

+	ff427e3800556bcd -> 33 cc=1

+selr

+	ffffffffffffffff 0000000000000000 -> 0cafebadffffffff 0badcafe00000000

+	0000000000000000 ffffffffffffffff -> 0cafebad00000000 0badcafeffffffff

+	1234567890abcdef fedcba9876543210 -> 0cafebad90abcdef 0badcafe76543210

+selgr

+	ffffffffffffffff 0000000000000000 -> ffffffffffffffff 0000000000000000

+	0000000000000000 ffffffffffffffff -> 0000000000000000 ffffffffffffffff

+	1234567890abcdef fedcba9876543210 -> 1234567890abcdef fedcba9876543210

+selfhr

+	ffffffffffffffff 0000000000000000 -> ffffffff0badcafe 000000000cafebad

+	0000000000000000 ffffffffffffffff -> 000000000badcafe ffffffff0cafebad

+	1234567890abcdef fedcba9876543210 -> 123456780badcafe fedcba980cafebad

+mvcrl

+	abbcdefghijklmnopqrstuvwxyz-01234klmnopqrstuvwxyz-0123456789.ABC

+	DEFGHIJKLMNOPQRSTUVWXYZabcdefghi456789.ABCDEFGHIJKLMNOPQRSTUVWXY

+	Zabcdefghijklmnopqrstuvwxyz-0123456789.ABCDEFGHIJKLMNOPQRSTUVWXY

+	Zabcdefghijklmnopqrstuvwxyz-0123456789.ABCDEFGHIJKLMNOPQRSTUVWZ

diff --git a/none/tests/s390x/misc3.vgtest b/none/tests/s390x/misc3.vgtest

new file mode 100644

index 000000000..d051a06bd

--- /dev/null

+++ b/none/tests/s390x/misc3.vgtest