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commit 4c8c3af18adc0a202d0e342b8ca3731a5b724a1d
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Author: Tom Hughes <tom@compton.nu>
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Date:   Wed Aug 30 19:26:37 2017 +0100
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    Fix eflags handling in amd64 instruction tests
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    In 64 bit mode there's no way to just save eflags so we save the
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    whole of rflags but we were doing so to a 32 bit variable!
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    Replace that with proper rflags support that knows it is dealing
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    with the full 64 bit flags word in 64 bit mode.
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diff --git a/none/tests/amd64/gen_insn_test.pl b/none/tests/amd64/gen_insn_test.pl
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index 863e560..a144ec4 100644
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--- a/none/tests/amd64/gen_insn_test.pl
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+++ b/none/tests/amd64/gen_insn_test.pl
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@@ -16,7 +16,7 @@ our %ArgTypes = (
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                  m32 => "reg32_t",
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                  m64 => "reg64_t",
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                  m128 => "reg128_t",
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-                 eflags => "reg32_t",
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+                 rflags => "reg64_t",
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                  st => "reg64_t",
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                  fpucw => "reg16_t",
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                  fpusw => "reg16_t"
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@@ -222,8 +222,8 @@ while (<>)
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     my @presets;
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     my $presetc = 0;
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-    my $eflagsmask;
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-    my $eflagsset;
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+    my $rflagsmask;
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+    my $rflagsset;
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     my $fpucwmask;
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     my $fpucwset;
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     my $fpuswmask;
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@@ -305,7 +305,7 @@ while (<>)
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             $presetc++;
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         }
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-        elsif ($preset =~ /^(eflags)\[([^\]]+)\]$/)
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+        elsif ($preset =~ /^(rflags)\[([^\]]+)\]$/)
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         {
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             my $type = $1;
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             my @values = split(/,/, $2);
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@@ -313,8 +313,8 @@ while (<>)
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             $values[0] = oct($values[0]) if $values[0] =~ /^0/;
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             $values[1] = oct($values[1]) if $values[1] =~ /^0/;
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-            $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff;
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-            $eflagsset = sprintf "0x%08x", $values[1];
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+            $rflagsmask = sprintf "0x%016x", ~$values[0];
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+            $rflagsset = sprintf "0x%016x", $values[1];
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         }
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         elsif ($preset =~ /^(fpucw)\[([^\]]+)\]$/)
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         {
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@@ -544,7 +544,7 @@ while (<>)
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             print qq|   $ArgTypes{$type} $name;\n|;
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         }
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-        elsif ($result =~ /^eflags\[([^\]]+)\]$/)
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+        elsif ($result =~ /^rflags\[([^\]]+)\]$/)
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         {
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             my @values = split(/,/, $1);
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@@ -553,19 +553,19 @@ while (<>)
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             my $result = {
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                 name => $name,
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-                type => "eflags",
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-                subtype => "ud",
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-                values => [ map { sprintf "0x%08x", $_ } @values ]
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+                type => "rflags",
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+                subtype => "uq",
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+                values => [ map { sprintf "0x%016x", $_ } @values ]
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             };
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             push @results, $result;
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-            print qq|   $ArgTypes{eflags} $name;\n|;
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+            print qq|   $ArgTypes{rflags} $name;\n|;
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-            if (!defined($eflagsmask) && !defined($eflagsset))
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+            if (!defined($rflagsmask) && !defined($rflagsset))
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             {
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-                $eflagsmask = sprintf "0x%08x", $values[0] ^ 0xffffffff;
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-                $eflagsset = sprintf "0x%08x", $values[0] & ~$values[1];
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+                $rflagsmask = sprintf "0x%016x", ~$values[0];
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+                $rflagsset = sprintf "0x%016x", $values[0] & ~$values[1];
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             }
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         }
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         elsif ($result =~ /^fpucw\[([^\]]+)\]$/)
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@@ -722,12 +722,11 @@ while (<>)
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         }
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     }
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-    if (defined($eflagsmask) || defined($eflagsset))
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+    if (defined($rflagsmask) || defined($rflagsset))
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     {
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         print qq|         \"pushfq\\n\"\n|;
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-        print qq|         \"andl \$$eflagsmask, (%%rsp)\\n\"\n| if defined($eflagsmask);
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-        print qq|         \"andl \$0, 4(%%rsp)\\n\"\n| if defined($eflagsmask);
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-        print qq|         \"orq \$$eflagsset, (%%rsp)\\n\"\n| if defined($eflagsset);
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+        print qq|         \"andq \$$rflagsmask, (%%rsp)\\n\"\n| if defined($rflagsmask);
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+        print qq|         \"orq \$$rflagsset, (%%rsp)\\n\"\n| if defined($rflagsset);
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         print qq|         \"popfq\\n\"\n|;
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     }
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@@ -747,7 +746,7 @@ while (<>)
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     foreach my $arg (@args)
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     {
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-        next if $arg->{type} eq "eflags";
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+        next if $arg->{type} eq "rflags";
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         if ($arg->{type} =~ /^(r8|r16|r32|r64|mm|xmm)$/)
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         {
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@@ -815,7 +814,7 @@ while (<>)
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         {
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             $fpresults[$RegNums{$result->{register}}] = $result;
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         }
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-        elsif ($result->{type} eq "eflags")
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+        elsif ($result->{type} eq "rflags")
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         {
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             print qq|         \"pushfq\\n\"\n|;
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             print qq|         \"popq %$result->{argnum}\\n\"\n|;
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@@ -925,9 +924,9 @@ while (<>)
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             my $suffix = $SubTypeSuffixes{$subtype};
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             my @values = @{$result->{values}};
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-            if ($type eq "eflags")
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+            if ($type eq "rflags")
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             {
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-                print qq|${prefix}\($result->{name}.ud[0] & $values[0]UL\) == $values[1]UL|;
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+                print qq|${prefix}\($result->{name}.uq[0] & $values[0]UL\) == $values[1]UL|;
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             }
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             elsif ($type =~ /^fpu[cs]w$/)
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             {
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@@ -972,9 +971,9 @@ while (<>)
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             my $suffix = $SubTypeSuffixes{$subtype};
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             my @values = @{$result->{values}};
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-            if ($type eq "eflags")
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+            if ($type eq "rflags")
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             {
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-                print qq|         printf("  eflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|;
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+                print qq|         printf("  rflags & 0x%lx = 0x%lx (expected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, $values[1]UL);\n|;
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             }
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             elsif ($type =~ /^fpu[cs]w$/)
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             {
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diff --git a/none/tests/amd64/insn_basic.def b/none/tests/amd64/insn_basic.def
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index 8b10da1..c3bef75 100644
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--- a/none/tests/amd64/insn_basic.def
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+++ b/none/tests/amd64/insn_basic.def
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@@ -1,57 +1,57 @@
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-adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
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-adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
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-adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
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-adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
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-adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
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-adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
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-adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46]
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-adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47]
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-adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46]
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-adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47]
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-###adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46]
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-###adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47]
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-adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
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-adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
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-###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
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-###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
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-adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
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-adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
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-adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
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-adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
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-adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912]
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-adcw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913]
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-adcw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912]
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-adcw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913]
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-adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912]
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-adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913]
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-adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
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-adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
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-###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
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-###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
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-adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
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-adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
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-adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
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-adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
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-adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
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-adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
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-adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
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-adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
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-adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
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-adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
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-adcq eflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333]
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-adcq eflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334]
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-###adcq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999]
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-###adcq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000]
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-adcq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999]
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-adcq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000]
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-adcq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999]
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-adcq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000]
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-adcq eflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
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-adcq eflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
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-adcq eflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999]
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-adcq eflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000]
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-adcq eflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
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-adcq eflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
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+adcb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
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+adcb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
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+adcb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
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+adcb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
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+adcb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
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+adcb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
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+adcb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46]
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+adcb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47]
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+adcb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46]
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+adcb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47]
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+###adcb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46]
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+###adcb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47]
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+adcw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
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+adcw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
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+###adcw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
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+###adcw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
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+adcw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
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+adcw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
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+adcw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
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+adcw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
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+adcw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912]
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+adcw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913]
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+adcw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912]
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+adcw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913]
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+adcw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912]
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+adcw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913]
Mark Wielaard d6679b
+adcl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
Mark Wielaard d6679b
+adcl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
Mark Wielaard d6679b
+###adcl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
Mark Wielaard d6679b
+###adcl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
Mark Wielaard d6679b
+adcl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
Mark Wielaard d6679b
+adcl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
Mark Wielaard d6679b
+adcl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
Mark Wielaard d6679b
+adcl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
Mark Wielaard d6679b
+adcl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
Mark Wielaard d6679b
+adcl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
Mark Wielaard d6679b
+adcl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
Mark Wielaard d6679b
+adcl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
Mark Wielaard d6679b
+adcl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
Mark Wielaard d6679b
+adcl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
Mark Wielaard d6679b
+adcq rflags[0x1,0x0] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654333]
Mark Wielaard d6679b
+adcq rflags[0x1,0x1] : imm8[12] r64.uq[8765432187654321] => 1.uq[8765432187654334]
Mark Wielaard d6679b
+###adcq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999]
Mark Wielaard d6679b
+###adcq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000]
Mark Wielaard d6679b
+adcq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999]
Mark Wielaard d6679b
+adcq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000]
Mark Wielaard d6679b
+adcq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999]
Mark Wielaard d6679b
+adcq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000]
Mark Wielaard d6679b
+adcq rflags[0x1,0x0] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
Mark Wielaard d6679b
+adcq rflags[0x1,0x1] : r64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
Mark Wielaard d6679b
+adcq rflags[0x1,0x0] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[9999999999999999]
Mark Wielaard d6679b
+adcq rflags[0x1,0x1] : r64.uq[1234567812345678] m64.uq[8765432187654321] => 1.uq[10000000000000000]
Mark Wielaard d6679b
+adcq rflags[0x1,0x0] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[9999999999999999]
Mark Wielaard d6679b
+adcq rflags[0x1,0x1] : m64.uq[1234567812345678] r64.uq[8765432187654321] => 1.uq[10000000000000000]
Mark Wielaard d6679b
 addb imm8[12] al.ub[34] => 1.ub[46]
Mark Wielaard d6679b
 addb imm8[12] bl.ub[34] => 1.ub[46]
Mark Wielaard d6679b
 addb imm8[12] m8.ub[34] => 1.ub[46]
Mark Wielaard d6679b
@@ -123,430 +123,430 @@ bsrq r64.uq[0x1357246813572468] r64.uq[0] => 1.uq[60]
Mark Wielaard d6679b
 bsrq m64.uq[0x7531864275318642] r64.uq[0] => 1.uq[62]
Mark Wielaard d6679b
 bswapl r32.ud[0x12345678] => 0.ud[0x78563412]
Mark Wielaard d6679b
 bswapq r64.uq[0x1234567813572468] => 0.uq[0x6824571378563412]
Mark Wielaard d6679b
-btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] eflags[0x001,0x001]
Mark Wielaard d6679b
-btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
Mark Wielaard d6679b
-###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
-btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] eflags[0x001,0x001]
Mark Wielaard d6679b
-btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] eflags[0x001,0x000]
Mark Wielaard d6679b
+btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btcq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btcq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btrq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681356] rflags[0x001,0x001]
Mark Wielaard d6679b
+btrq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+###btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] rflags[0x001,0x001]
Mark Wielaard d6679b
+###btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsq imm8[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsq imm8[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsq imm8[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsq imm8[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsq r64.uq[0] r64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsq r64.uq[48] r64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
+btsq r64.uq[0] m64.uq[0x8642753124681357] => 1.uq[0x8642753124681357] rflags[0x001,0x001]
Mark Wielaard d6679b
+btsq r64.uq[48] m64.uq[0x8642753124681357] => 1.uq[0x8643753124681357] rflags[0x001,0x000]
Mark Wielaard d6679b
 cbw al.sb[123] : => ax.sw[123]
Mark Wielaard d6679b
 cbw al.sb[-123] : => ax.sw[-123]
Mark Wielaard d6679b
 cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678]
Mark Wielaard d6679b
 cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98]
Mark Wielaard d6679b
 cdqe eax.ud[0x12345678] : => rax.uq[0x0000000012345678]
Mark Wielaard d6679b
 cdqe eax.ud[0xfedcba98] : => rax.uq[0xfffffffffedcba98]
Mark Wielaard d6679b
-###clc eflags[0x001,0x000] : => eflags[0x001,0x000]
Mark Wielaard d6679b
-###clc eflags[0x001,0x001] : => eflags[0x001,0x000]
Mark Wielaard d6679b
-cld eflags[0x400,0x000] : => eflags[0x400,0x000]
Mark Wielaard d6679b
-cld eflags[0x400,0x400] : => eflags[0x400,0x000]
Mark Wielaard d6679b
-###cmc eflags[0x001,0x000] : => eflags[0x001,0x001]
Mark Wielaard d6679b
-###cmc eflags[0x001,0x001] : => eflags[0x001,0x000]
Mark Wielaard d6679b
-cmpb imm8[3] al.ub[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpb imm8[2] al.ub[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpb imm8[12] al.ub[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpb imm8[12] al.ub[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpb imm8[34] al.ub[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpb imm8[12] al.ub[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpb imm8[100] al.sb[-100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb imm8[50] al.sb[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb imm8[-50] al.sb[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb imm8[-100] al.sb[100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb imm8[3] r8.ub[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpb imm8[2] r8.ub[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpb imm8[12] r8.ub[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpb imm8[12] r8.ub[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpb imm8[34] r8.ub[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpb imm8[12] r8.ub[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpb imm8[100] r8.sb[-100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb imm8[50] r8.sb[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb imm8[-50] r8.sb[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb imm8[-100] r8.sb[100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb imm8[3] m8.ub[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpb imm8[2] m8.ub[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpb imm8[12] m8.ub[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpb imm8[12] m8.ub[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpb imm8[34] m8.ub[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpb imm8[12] m8.ub[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpb imm8[100] m8.sb[-100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb imm8[50] m8.sb[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb imm8[-50] m8.sb[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb imm8[-100] m8.sb[100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb r8.ub[3] r8.ub[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpb r8.ub[2] r8.ub[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpb r8.ub[12] r8.ub[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpb r8.ub[12] r8.ub[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpb r8.ub[34] r8.ub[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpb r8.ub[12] r8.ub[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpb r8.ub[100] r8.sb[-100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb r8.ub[50] r8.sb[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb r8.sb[-50] r8.sb[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb r8.sb[-100] r8.sb[100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb r8.ub[3] m8.ub[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpb r8.ub[2] m8.ub[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpb r8.ub[12] m8.ub[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpb r8.ub[12] m8.ub[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpb r8.ub[34] m8.ub[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpb r8.ub[12] m8.ub[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpb r8.ub[100] m8.sb[-100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb r8.ub[50] m8.sb[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb r8.sb[-50] m8.sb[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb r8.sb[-100] m8.sb[100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb m8.ub[3] r8.ub[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpb m8.ub[2] r8.ub[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpb m8.ub[12] r8.ub[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpb m8.ub[12] r8.ub[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpb m8.ub[34] r8.ub[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpb m8.ub[12] r8.ub[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpb m8.ub[100] r8.sb[-100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpb m8.ub[50] r8.sb[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb m8.sb[-50] r8.sb[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpb m8.sb[-100] r8.sb[100] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm8[3] r16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw imm8[2] r16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw imm8[12] r16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw imm8[12] r16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw imm8[34] r16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw imm8[12] r16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw imm8[100] r16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm8[50] r16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm8[-50] r16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm8[-100] r16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm8[3] m16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw imm8[2] m16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw imm8[12] m16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw imm8[12] m16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw imm8[34] m16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw imm8[12] m16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw imm8[100] m16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm8[50] m16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm8[-50] m16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm8[-100] m16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm16[3] ax.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw imm16[2] ax.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw imm16[12] ax.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw imm16[12] ax.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw imm16[34] ax.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw imm16[12] ax.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw imm16[100] ax.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm16[50] ax.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm16[-50] ax.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm16[-100] ax.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm16[3] r16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw imm16[2] r16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw imm16[12] r16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw imm16[12] r16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw imm16[34] r16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw imm16[12] r16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw imm16[100] r16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm16[50] r16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm16[-50] r16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm16[-100] r16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm16[3] m16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw imm16[2] m16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw imm16[12] m16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw imm16[12] m16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw imm16[34] m16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw imm16[12] m16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw imm16[100] m16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw imm16[50] m16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm16[-50] m16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw imm16[-100] m16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw r16.uw[3] r16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw r16.uw[2] r16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw r16.uw[12] r16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw r16.uw[12] r16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw r16.uw[34] r16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw r16.uw[12] r16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw r16.uw[100] r16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw r16.uw[50] r16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw r16.sw[-50] r16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw r16.sw[-100] r16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw r16.uw[3] m16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw r16.uw[2] m16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw r16.uw[12] m16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw r16.uw[12] m16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw r16.uw[34] m16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw r16.uw[12] m16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw r16.uw[100] m16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw r16.uw[50] m16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw r16.sw[-50] m16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw r16.sw[-100] m16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw m16.uw[3] r16.uw[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpw m16.uw[2] r16.uw[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpw m16.uw[12] r16.uw[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpw m16.uw[12] r16.uw[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpw m16.uw[34] r16.uw[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpw m16.uw[12] r16.uw[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpw m16.uw[100] r16.sw[-32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpw m16.uw[50] r16.sw[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw m16.sw[-50] r16.sw[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpw m16.sw[-100] r16.sw[32700] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-###cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-###cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm8[3] r64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq imm8[2] r64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq imm8[12] r64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq imm8[12] r64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq imm8[34] r64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq imm8[12] r64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq imm8[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm8[50] r64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm8[-50] r64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm8[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm8[3] m64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq imm8[2] m64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq imm8[12] m64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq imm8[12] m64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq imm8[34] m64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq imm8[12] m64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq imm8[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm8[50] m64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm8[-50] m64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm8[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm32[3] rax.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq imm32[2] rax.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq imm32[12] rax.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq imm32[12] rax.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq imm32[34] rax.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq imm32[12] rax.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq imm32[100] rax.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm32[50] rax.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm32[-50] rax.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm32[-100] rax.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm32[3] r64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq imm32[2] r64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq imm32[12] r64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq imm32[12] r64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq imm32[34] r64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq imm32[12] r64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq imm32[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm32[50] r64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm32[-50] r64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm32[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm32[3] m64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq imm32[2] m64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq imm32[12] m64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq imm32[12] m64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq imm32[34] m64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq imm32[12] m64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq imm32[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq imm32[50] m64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm32[-50] m64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq imm32[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq r64.uq[3] r64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq r64.uq[2] r64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq r64.uq[12] r64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq r64.uq[12] r64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq r64.uq[34] r64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq r64.uq[12] r64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq r64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq r64.uq[50] r64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq r64.sq[-50] r64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq r64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq r64.uq[3] m64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq r64.uq[2] m64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq r64.uq[12] m64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq r64.uq[12] m64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq r64.uq[34] m64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq r64.uq[12] m64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq r64.uq[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq r64.uq[50] m64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq r64.sq[-50] m64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq r64.sq[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq m64.uq[3] r64.uq[2] => eflags[0x010,0x010]
Mark Wielaard d6679b
-cmpq m64.uq[2] r64.uq[3] => eflags[0x010,0x000]
Mark Wielaard d6679b
-cmpq m64.uq[12] r64.uq[12] => eflags[0x044,0x044]
Mark Wielaard d6679b
-cmpq m64.uq[12] r64.uq[34] => eflags[0x044,0x000]
Mark Wielaard d6679b
-cmpq m64.uq[34] r64.uq[12] => eflags[0x081,0x081]
Mark Wielaard d6679b
-cmpq m64.uq[12] r64.uq[34] => eflags[0x081,0x000]
Mark Wielaard d6679b
-cmpq m64.uq[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-cmpq m64.uq[50] r64.sq[-50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq m64.sq[-50] r64.sq[50] => eflags[0x800,0x000]
Mark Wielaard d6679b
-cmpq m64.sq[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
Mark Wielaard d6679b
-###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
Mark Wielaard d6679b
-###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
Mark Wielaard d6679b
-###cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
Mark Wielaard d6679b
-###cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
Mark Wielaard d6679b
-###cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
Mark Wielaard d6679b
-###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
Mark Wielaard d6679b
-cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
Mark Wielaard d6679b
-###cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
Mark Wielaard d6679b
-###cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
Mark Wielaard d6679b
-###cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
Mark Wielaard d6679b
-cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
Mark Wielaard d6679b
-cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
Mark Wielaard d6679b
-###cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
Mark Wielaard d6679b
-###cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
Mark Wielaard d6679b
-cmpxchgq eflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => eflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
Mark Wielaard d6679b
-cmpxchgq eflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => eflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
Mark Wielaard d6679b
+###clc rflags[0x001,0x000] : => rflags[0x001,0x000]
Mark Wielaard d6679b
+###clc rflags[0x001,0x001] : => rflags[0x001,0x000]
Mark Wielaard d6679b
+cld rflags[0x400,0x000] : => rflags[0x400,0x000]
Mark Wielaard d6679b
+cld rflags[0x400,0x400] : => rflags[0x400,0x000]
Mark Wielaard d6679b
+###cmc rflags[0x001,0x000] : => rflags[0x001,0x001]
Mark Wielaard d6679b
+###cmc rflags[0x001,0x001] : => rflags[0x001,0x000]
Mark Wielaard d6679b
+cmpb imm8[3] al.ub[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpb imm8[2] al.ub[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpb imm8[12] al.ub[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpb imm8[12] al.ub[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpb imm8[34] al.ub[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpb imm8[12] al.ub[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpb imm8[100] al.sb[-100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb imm8[50] al.sb[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb imm8[-50] al.sb[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb imm8[-100] al.sb[100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb imm8[3] r8.ub[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpb imm8[2] r8.ub[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpb imm8[12] r8.ub[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpb imm8[12] r8.ub[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpb imm8[34] r8.ub[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpb imm8[12] r8.ub[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpb imm8[100] r8.sb[-100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb imm8[50] r8.sb[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb imm8[-50] r8.sb[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb imm8[-100] r8.sb[100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb imm8[3] m8.ub[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpb imm8[2] m8.ub[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpb imm8[12] m8.ub[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpb imm8[12] m8.ub[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpb imm8[34] m8.ub[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpb imm8[12] m8.ub[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpb imm8[100] m8.sb[-100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb imm8[50] m8.sb[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb imm8[-50] m8.sb[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb imm8[-100] m8.sb[100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb r8.ub[3] r8.ub[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpb r8.ub[2] r8.ub[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpb r8.ub[12] r8.ub[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpb r8.ub[12] r8.ub[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpb r8.ub[34] r8.ub[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpb r8.ub[12] r8.ub[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpb r8.ub[100] r8.sb[-100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb r8.ub[50] r8.sb[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb r8.sb[-50] r8.sb[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb r8.sb[-100] r8.sb[100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb r8.ub[3] m8.ub[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpb r8.ub[2] m8.ub[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpb r8.ub[12] m8.ub[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpb r8.ub[12] m8.ub[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpb r8.ub[34] m8.ub[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpb r8.ub[12] m8.ub[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpb r8.ub[100] m8.sb[-100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb r8.ub[50] m8.sb[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb r8.sb[-50] m8.sb[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb r8.sb[-100] m8.sb[100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb m8.ub[3] r8.ub[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpb m8.ub[2] r8.ub[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpb m8.ub[12] r8.ub[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpb m8.ub[12] r8.ub[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpb m8.ub[34] r8.ub[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpb m8.ub[12] r8.ub[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpb m8.ub[100] r8.sb[-100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpb m8.ub[50] r8.sb[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb m8.sb[-50] r8.sb[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpb m8.sb[-100] r8.sb[100] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm8[3] r16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw imm8[2] r16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw imm8[12] r16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw imm8[12] r16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw imm8[34] r16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw imm8[12] r16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw imm8[100] r16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm8[50] r16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm8[-50] r16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm8[-100] r16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm8[3] m16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw imm8[2] m16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw imm8[12] m16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw imm8[12] m16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw imm8[34] m16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw imm8[12] m16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw imm8[100] m16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm8[50] m16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm8[-50] m16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm8[-100] m16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm16[3] ax.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw imm16[2] ax.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw imm16[12] ax.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw imm16[12] ax.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw imm16[34] ax.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw imm16[12] ax.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw imm16[100] ax.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm16[50] ax.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm16[-50] ax.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm16[-100] ax.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm16[3] r16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw imm16[2] r16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw imm16[12] r16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw imm16[12] r16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw imm16[34] r16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw imm16[12] r16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw imm16[100] r16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm16[50] r16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm16[-50] r16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm16[-100] r16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm16[3] m16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw imm16[2] m16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw imm16[12] m16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw imm16[12] m16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw imm16[34] m16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw imm16[12] m16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw imm16[100] m16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw imm16[50] m16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm16[-50] m16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw imm16[-100] m16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw r16.uw[3] r16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw r16.uw[2] r16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw r16.uw[12] r16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw r16.uw[12] r16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw r16.uw[34] r16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw r16.uw[12] r16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw r16.uw[100] r16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw r16.uw[50] r16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw r16.sw[-50] r16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw r16.sw[-100] r16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw r16.uw[3] m16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw r16.uw[2] m16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw r16.uw[12] m16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw r16.uw[12] m16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw r16.uw[34] m16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw r16.uw[12] m16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw r16.uw[100] m16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw r16.uw[50] m16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw r16.sw[-50] m16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw r16.sw[-100] m16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw m16.uw[3] r16.uw[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpw m16.uw[2] r16.uw[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpw m16.uw[12] r16.uw[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpw m16.uw[12] r16.uw[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpw m16.uw[34] r16.uw[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpw m16.uw[12] r16.uw[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpw m16.uw[100] r16.sw[-32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpw m16.uw[50] r16.sw[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw m16.sw[-50] r16.sw[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpw m16.sw[-100] r16.sw[32700] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm8[3] r32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl imm8[2] r32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl imm8[12] r32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+###cmpl imm8[12] r32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl imm8[34] r32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl imm8[12] r32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl imm8[100] r32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm8[50] r32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm8[-50] r32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm8[-100] r32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm8[3] m32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl imm8[2] m32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl imm8[12] m32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl imm8[12] m32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl imm8[34] m32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl imm8[12] m32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl imm8[100] m32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm8[50] m32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm8[-50] m32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm8[-100] m32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm32[3] eax.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl imm32[2] eax.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl imm32[12] eax.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl imm32[12] eax.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl imm32[34] eax.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl imm32[12] eax.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl imm32[100] eax.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm32[50] eax.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm32[-50] eax.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm32[-100] eax.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm32[3] r32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl imm32[2] r32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl imm32[12] r32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl imm32[12] r32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl imm32[34] r32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl imm32[12] r32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl imm32[100] r32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm32[50] r32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm32[-50] r32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm32[-100] r32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm32[3] m32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl imm32[2] m32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl imm32[12] m32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl imm32[12] m32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl imm32[34] m32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl imm32[12] m32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl imm32[100] m32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl imm32[50] m32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm32[-50] m32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl imm32[-100] m32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl r32.ud[3] r32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl r32.ud[2] r32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl r32.ud[12] r32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl r32.ud[12] r32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl r32.ud[34] r32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl r32.ud[12] r32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl r32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl r32.ud[50] r32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl r32.sd[-50] r32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl r32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl r32.ud[3] m32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl r32.ud[2] m32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl r32.ud[12] m32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl r32.ud[12] m32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl r32.ud[34] m32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl r32.ud[12] m32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl r32.ud[100] m32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl r32.ud[50] m32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl r32.sd[-50] m32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl r32.sd[-100] m32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl m32.ud[3] r32.ud[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpl m32.ud[2] r32.ud[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpl m32.ud[12] r32.ud[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpl m32.ud[12] r32.ud[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpl m32.ud[34] r32.ud[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpl m32.ud[12] r32.ud[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpl m32.ud[100] r32.sd[-2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpl m32.ud[50] r32.sd[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpl m32.sd[-50] r32.sd[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+###cmpl m32.sd[-100] r32.sd[2147483600] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm8[3] r64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq imm8[2] r64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq imm8[12] r64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq imm8[12] r64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq imm8[34] r64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq imm8[12] r64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq imm8[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm8[50] r64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm8[-50] r64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm8[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm8[3] m64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq imm8[2] m64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq imm8[12] m64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq imm8[12] m64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq imm8[34] m64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq imm8[12] m64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq imm8[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm8[50] m64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm8[-50] m64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm8[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm32[3] rax.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq imm32[2] rax.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq imm32[12] rax.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq imm32[12] rax.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq imm32[34] rax.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq imm32[12] rax.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq imm32[100] rax.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm32[50] rax.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm32[-50] rax.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm32[-100] rax.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm32[3] r64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq imm32[2] r64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq imm32[12] r64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq imm32[12] r64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq imm32[34] r64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq imm32[12] r64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq imm32[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm32[50] r64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm32[-50] r64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm32[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm32[3] m64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq imm32[2] m64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq imm32[12] m64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq imm32[12] m64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq imm32[34] m64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq imm32[12] m64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq imm32[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq imm32[50] m64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm32[-50] m64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq imm32[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq r64.uq[3] r64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq r64.uq[2] r64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq r64.uq[12] r64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq r64.uq[12] r64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq r64.uq[34] r64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq r64.uq[12] r64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq r64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq r64.uq[50] r64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq r64.sq[-50] r64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq r64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq r64.uq[3] m64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq r64.uq[2] m64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq r64.uq[12] m64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq r64.uq[12] m64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq r64.uq[34] m64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq r64.uq[12] m64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq r64.uq[100] m64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq r64.uq[50] m64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq r64.sq[-50] m64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq r64.sq[-100] m64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq m64.uq[3] r64.uq[2] => rflags[0x010,0x010]
Mark Wielaard d6679b
+cmpq m64.uq[2] r64.uq[3] => rflags[0x010,0x000]
Mark Wielaard d6679b
+cmpq m64.uq[12] r64.uq[12] => rflags[0x044,0x044]
Mark Wielaard d6679b
+cmpq m64.uq[12] r64.uq[34] => rflags[0x044,0x000]
Mark Wielaard d6679b
+cmpq m64.uq[34] r64.uq[12] => rflags[0x081,0x081]
Mark Wielaard d6679b
+cmpq m64.uq[12] r64.uq[34] => rflags[0x081,0x000]
Mark Wielaard d6679b
+cmpq m64.uq[100] r64.sq[-9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+cmpq m64.uq[50] r64.sq[-50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq m64.sq[-50] r64.sq[50] => rflags[0x800,0x000]
Mark Wielaard d6679b
+cmpq m64.sq[-100] r64.sq[9223372036854775800] => rflags[0x800,0x800]
Mark Wielaard d6679b
+###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] r8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
Mark Wielaard d6679b
+###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
Mark Wielaard d6679b
+###cmpxchgb rflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => rflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
Mark Wielaard d6679b
+###cmpxchgb rflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => rflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
Mark Wielaard d6679b
+###cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
Mark Wielaard d6679b
+###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
Mark Wielaard d6679b
+cmpxchgw rflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => rflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
Mark Wielaard d6679b
+###cmpxchgw rflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => rflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
Mark Wielaard d6679b
+###cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
Mark Wielaard d6679b
+###cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
Mark Wielaard d6679b
+cmpxchgl rflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => rflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
Mark Wielaard d6679b
+cmpxchgl rflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => rflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
Mark Wielaard d6679b
+###cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] r64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
Mark Wielaard d6679b
+###cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] r64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
Mark Wielaard d6679b
+cmpxchgq rflags[0x40,0x00] rax.uq[12345] : r64.uq[56789] m64.uq[12345] => rflags[0x40,0x40] rax.uq[12345] 0.uq[56789] 1.uq[56789]
Mark Wielaard d6679b
+cmpxchgq rflags[0x40,0x40] rax.uq[12345] : r64.uq[56789] m64.uq[34567] => rflags[0x40,0x00] rax.uq[34567] 0.uq[56789] 1.uq[34567]
Mark Wielaard d6679b
 cqo rax.uq[0x0123456789abcdef] : => rdx.uq[0x0000000000000000] rax.uq[0x0123456789abcdef]
Mark Wielaard d6679b
 cqo rax.uq[0xfedcba9876543210] : => rdx.uq[0xffffffffffffffff] rax.uq[0xfedcba9876543210]
Mark Wielaard d6679b
 cwd ax.uw[0x1234] : => dx.uw[0x0000] ax.uw[0x1234]
Mark Wielaard d6679b
@@ -617,8 +617,8 @@ incl r32.ud[12345678] => 0.ud[12345679]
Mark Wielaard d6679b
 incl m32.ud[12345678] => 0.ud[12345679]
Mark Wielaard d6679b
 incq r64.uq[1234567813572468] => 0.uq[1234567813572469]
Mark Wielaard d6679b
 incq m64.uq[1234567813572468] => 0.uq[1234567813572469]
Mark Wielaard d6679b
-###lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7]
Mark Wielaard d6679b
-###lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02]
Mark Wielaard d6679b
+###lahf rflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7]
Mark Wielaard d6679b
+###lahf rflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02]
Mark Wielaard d6679b
 movb imm8[123] r8.ub[0] => 1.ub[123]
Mark Wielaard d6679b
 movb imm8[123] m8.ub[0] => 1.ub[123]
Mark Wielaard d6679b
 movb r8.ub[123] r8.ub[0] => 1.ub[123]
Mark Wielaard d6679b
@@ -714,54 +714,54 @@ orq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0xffffffff96767779]
Mark Wielaard d6679b
 orq r64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff]
Mark Wielaard d6679b
 orq r64.uq[0xeca86420fdb97531] m64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff]
Mark Wielaard d6679b
 orq m64.uq[0xeca86420fdb97531] r64.uq[0x0123456789abcdef] => 1.uq[0xedab6567fdbbfdff]
Mark Wielaard d6679b
-###rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclq eflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclq eflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
Mark Wielaard d6679b
-###rclq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrw eflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrw eflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrq eflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrq eflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] eflags[0x1,0x0]
Mark Wielaard d6679b
-rcrq eflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrq eflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrq eflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
Mark Wielaard d6679b
-rcrq eflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] eflags[0x1,0x1]
Mark Wielaard d6679b
+###rclb rflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclb rflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclw rflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclw rflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rcll rflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rcll rflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rcll rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rcll rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rcll rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rcll rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclq rflags[0x1,0x0] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclq rflags[0x1,0x0] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xfffe0001fe01e194] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
Mark Wielaard d6679b
+###rclq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0x0000ff00f0ca7fff] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrb rflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrb rflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrb rflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrb rflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrb rflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrb rflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrw rflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrw rflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrw rflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrw rflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrw rflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrw rflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrl rflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrl rflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrl rflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrl rflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrl rflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrl rflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrq rflags[0x1,0x1] : r64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrq rflags[0x1,0x1] : m64.uq[0xffff0000ff00f0ca] => 0.uq[0xffff80007f807865] rflags[0x1,0x0]
Mark Wielaard d6679b
+rcrq rflags[0x1,0x0] : imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrq rflags[0x1,0x0] : imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrq rflags[0x1,0x0] : cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
Mark Wielaard d6679b
+rcrq rflags[0x1,0x0] : cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xe194ffff0000ff00] rflags[0x1,0x1]
Mark Wielaard d6679b
 rolb r8.ub[0xca] => 0.ub[0x95]
Mark Wielaard d6679b
 rolb m8.ub[0xca] => 0.ub[0x95]
Mark Wielaard d6679b
 rolb imm8[2] r8.ub[0xca] => 1.ub[0x2b]
Mark Wielaard d6679b
@@ -810,8 +810,8 @@ rorq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
Mark Wielaard d6679b
 rorq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
Mark Wielaard d6679b
 rorq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
Mark Wielaard d6679b
 rorq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xf0caffff0000ff00]
Mark Wielaard d6679b
-###sahf eflags[0xff,0x28] ah.ub[0xfd] : => eflags[0xfd,0xd5]
Mark Wielaard d6679b
-###sahf eflags[0xff,0xfd] ah.ub[0x28] : => eflags[0xfd,0x00]
Mark Wielaard d6679b
+###sahf rflags[0xff,0x28] ah.ub[0xfd] : => rflags[0xfd,0xd5]
Mark Wielaard d6679b
+###sahf rflags[0xff,0xfd] ah.ub[0x28] : => rflags[0xfd,0x00]
Mark Wielaard d6679b
 salb r8.ub[0xca] => 0.ub[0x94]
Mark Wielaard d6679b
 salb m8.ub[0xca] => 0.ub[0x94]
Mark Wielaard d6679b
 salb imm8[2] r8.ub[0xca] => 1.ub[0x28]
Mark Wielaard d6679b
@@ -860,252 +860,252 @@ sarq imm8[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
Mark Wielaard d6679b
 sarq imm8[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
Mark Wielaard d6679b
 sarq cl.ub[16] r64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
Mark Wielaard d6679b
 sarq cl.ub[16] m64.uq[0xffff0000ff00f0ca] => 1.uq[0xffffffff0000ff00]
Mark Wielaard d6679b
-###sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22]
Mark Wielaard d6679b
-###sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21]
Mark Wielaard d6679b
-sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22]
Mark Wielaard d6679b
-sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21]
Mark Wielaard d6679b
-sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
-sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
-sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
-sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
-###sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
-###sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
-###sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
-###sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443]
Mark Wielaard d6679b
-###sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
-###sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
-###sbbw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
-###sbbw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
-sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
Mark Wielaard d6679b
-###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
-###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
-###sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
-###sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
-sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629]
Mark Wielaard d6679b
-###sbbq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964]
Mark Wielaard d6679b
-###sbbq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
Mark Wielaard d6679b
-###sbbq eflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174]
Mark Wielaard d6679b
-###sbbq eflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
Mark Wielaard d6679b
-sbbq eflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
Mark Wielaard d6679b
-seta eflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-seta eflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seta eflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seta eflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seta eflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-seta eflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seta eflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seta eflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setae eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setae eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setae eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setae eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setb eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setb eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setb eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setb eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setc eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setc eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setc eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setc eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-sete eflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-sete eflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-sete eflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-sete eflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setg eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setna eflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setna eflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setna eflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setna eflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setna eflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setna eflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setna eflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setna eflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnae eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnae eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnae eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnae eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnb eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnb eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnb eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnb eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnc eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnc eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnc eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnc eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setne eflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setne eflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setne eflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setne eflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setng eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setno eflags[0x800,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setno eflags[0x800,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setno eflags[0x800,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setno eflags[0x800,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnp eflags[0x004,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnp eflags[0x004,0x004] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnp eflags[0x004,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnp eflags[0x004,0x004] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setns eflags[0x080,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setns eflags[0x080,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setns eflags[0x080,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setns eflags[0x080,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnz eflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnz eflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setnz eflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setnz eflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seto eflags[0x800,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seto eflags[0x800,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-seto eflags[0x800,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-seto eflags[0x800,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setp eflags[0x004,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setp eflags[0x004,0x004] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setp eflags[0x004,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setp eflags[0x004,0x004] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-sets eflags[0x080,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-sets eflags[0x080,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-sets eflags[0x080,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-sets eflags[0x080,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setz eflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setz eflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
-setz eflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
-setz eflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+###sbbb rflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22]
Mark Wielaard d6679b
+###sbbb rflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21]
Mark Wielaard d6679b
+sbbb rflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22]
Mark Wielaard d6679b
+sbbb rflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21]
Mark Wielaard d6679b
+sbbb rflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
+sbbb rflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
+sbbb rflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
+sbbb rflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
+###sbbb rflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
+###sbbb rflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
+###sbbb rflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
+###sbbb rflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443]
Mark Wielaard d6679b
+###sbbw rflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
+###sbbw rflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
+###sbbw rflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
+###sbbw rflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444]
Mark Wielaard d6679b
+sbbw rflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
Mark Wielaard d6679b
+###sbbl rflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
+###sbbl rflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
+###sbbl rflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
+###sbbl rflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
Mark Wielaard d6679b
+sbbl rflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x0] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318630]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x1] : imm8[12] r64.uq[8765432175318642] => 1.uq[8765432175318629]
Mark Wielaard d6679b
+###sbbq rflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964]
Mark Wielaard d6679b
+###sbbq rflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
Mark Wielaard d6679b
+###sbbq rflags[0x1,0x0] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174]
Mark Wielaard d6679b
+###sbbq rflags[0x1,0x1] : r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746173]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x0] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
Mark Wielaard d6679b
+sbbq rflags[0x1,0x1] : m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746173]
Mark Wielaard d6679b
+seta rflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+seta rflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seta rflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seta rflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seta rflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+seta rflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seta rflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seta rflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setae rflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setae rflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setae rflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setae rflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setb rflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setb rflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setb rflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setb rflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setc rflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setc rflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setc rflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setc rflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+sete rflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+sete rflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+sete rflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+sete rflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setg rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setna rflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setna rflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setna rflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setna rflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setna rflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setna rflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setna rflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setna rflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnae rflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnae rflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnae rflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnae rflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnb rflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnb rflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnb rflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnb rflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnbe rflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnc rflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnc rflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnc rflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnc rflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setne rflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setne rflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setne rflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setne rflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setng rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnge rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnl rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnle rflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setno rflags[0x800,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setno rflags[0x800,0x800] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setno rflags[0x800,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setno rflags[0x800,0x800] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnp rflags[0x004,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnp rflags[0x004,0x004] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnp rflags[0x004,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnp rflags[0x004,0x004] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setns rflags[0x080,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setns rflags[0x080,0x080] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setns rflags[0x080,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setns rflags[0x080,0x080] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnz rflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnz rflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setnz rflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setnz rflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seto rflags[0x800,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seto rflags[0x800,0x800] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+seto rflags[0x800,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+seto rflags[0x800,0x800] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setp rflags[0x004,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setp rflags[0x004,0x004] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setp rflags[0x004,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setp rflags[0x004,0x004] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+sets rflags[0x080,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+sets rflags[0x080,0x080] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+sets rflags[0x080,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+sets rflags[0x080,0x080] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setz rflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setz rflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
+setz rflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
Mark Wielaard d6679b
+setz rflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
Mark Wielaard d6679b
 shlb r8.ub[0xca] => 0.ub[0x94]
Mark Wielaard d6679b
 shlb m8.ub[0xca] => 0.ub[0x94]
Mark Wielaard d6679b
 shlb imm8[2] r8.ub[0xca] => 1.ub[0x28]
Mark Wielaard d6679b
@@ -1202,10 +1202,10 @@ shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0x7
Mark Wielaard d6679b
 shrdq cl.ub[1] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0x7fff80007f807865]
Mark Wielaard d6679b
 shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] r64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00]
Mark Wielaard d6679b
 shrdq cl.ub[16] r64.uq[0xffff0000ff00f0ca] m64.uq[0xffff0000ff00f0ca] => 2.uq[0xf0caffff0000ff00]
Mark Wielaard d6679b
-###stc eflags[0x001,0x000] : => eflags[0x001,0x001]
Mark Wielaard d6679b
-###stc eflags[0x001,0x001] : => eflags[0x001,0x001]
Mark Wielaard d6679b
-std eflags[0x400,0x000] : => eflags[0x400,0x400]
Mark Wielaard d6679b
-std eflags[0x400,0x400] : => eflags[0x400,0x400]
Mark Wielaard d6679b
+###stc rflags[0x001,0x000] : => rflags[0x001,0x001]
Mark Wielaard d6679b
+###stc rflags[0x001,0x001] : => rflags[0x001,0x001]
Mark Wielaard d6679b
+std rflags[0x400,0x000] : => rflags[0x400,0x400]
Mark Wielaard d6679b
+std rflags[0x400,0x400] : => rflags[0x400,0x400]
Mark Wielaard d6679b
 subb imm8[12] al.ub[34] => 1.ub[22]
Mark Wielaard d6679b
 subb imm8[12] bl.ub[34] => 1.ub[22]
Mark Wielaard d6679b
 subb imm8[12] m8.ub[34] => 1.ub[22]
Mark Wielaard d6679b
@@ -1233,106 +1233,106 @@ subq imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
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 subq r64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
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 subq r64.uq[1234567813572468] m64.uq[8765432175318642] => 1.uq[7530864361746174]
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 subq m64.uq[1234567813572468] r64.uq[8765432175318642] => 1.uq[7530864361746174]
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-testb imm8[0x1a] al.ub[0x1a] => eflags[0x8c5,0x000]
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-testb imm8[0x5a] al.ub[0x5a] => eflags[0x8c5,0x004]
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-testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044]
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-testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080]
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-testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084]
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-testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000]
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-testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004]
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-testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044]
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-testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080]
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-testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084]
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-testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
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-testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
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-testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
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-testb imm8[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080]
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-testb imm8[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084]
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-testb r8.ub[0x1a] r8.ub[0x1a] => eflags[0x8c5,0x000]
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-testb r8.ub[0x5a] r8.ub[0x5a] => eflags[0x8c5,0x004]
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-testb r8.ub[0x1a] r8.ub[0xa1] => eflags[0x8c5,0x044]
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-testb r8.ub[0xa1] r8.ub[0xa1] => eflags[0x8c5,0x080]
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-testb r8.ub[0xa5] r8.ub[0xa5] => eflags[0x8c5,0x084]
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-testb r8.ub[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
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-testb r8.ub[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
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-testb r8.ub[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
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-testb r8.ub[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080]
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-testb r8.ub[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084]
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-testw imm16[0x1a1a] ax.uw[0x1a1a] => eflags[0x8c5,0x000]
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-testw imm16[0x5a5a] ax.uw[0x5a5a] => eflags[0x8c5,0x004]
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-testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044]
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-testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080]
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-testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084]
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-testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000]
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-testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004]
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-testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044]
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-testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080]
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-testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084]
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-testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
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-testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
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-testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
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-testw imm16[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080]
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-testw imm16[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084]
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-testw r16.uw[0x1a1a] r16.uw[0x1a1a] => eflags[0x8c5,0x000]
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-testw r16.uw[0x5a5a] r16.uw[0x5a5a] => eflags[0x8c5,0x004]
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-testw r16.uw[0x1a1a] r16.uw[0xa1a1] => eflags[0x8c5,0x044]
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-testw r16.uw[0xa1a1] r16.uw[0xa1a1] => eflags[0x8c5,0x080]
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-testw r16.uw[0xa5a5] r16.uw[0xa5a5] => eflags[0x8c5,0x084]
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-testw r16.uw[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
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-testw r16.uw[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
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-testw r16.uw[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
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-testw r16.uw[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080]
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-testw r16.uw[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084]
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-testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
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-testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
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-testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
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-testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
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-testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
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-testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
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-testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
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-testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
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-testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
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-testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
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-testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
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-testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
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-testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
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-testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
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-testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
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-testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
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-testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
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-testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
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-testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
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-testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000]
Mark Wielaard d6679b
-testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004]
Mark Wielaard d6679b
-testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044]
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-testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080]
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-testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084]
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-testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => eflags[0x8c5,0x000]
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-testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => eflags[0x8c5,0x004]
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-testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x044]
Mark Wielaard d6679b
-testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => eflags[0x8c5,0x080]
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-testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => eflags[0x8c5,0x084]
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+testb imm8[0x1a] al.ub[0x1a] => rflags[0x8c5,0x000]
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+testb imm8[0x5a] al.ub[0x5a] => rflags[0x8c5,0x004]
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+testb imm8[0x1a] al.ub[0xa1] => rflags[0x8c5,0x044]
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+testb imm8[0xa1] al.ub[0xa1] => rflags[0x8c5,0x080]
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+testb imm8[0xa5] al.ub[0xa5] => rflags[0x8c5,0x084]
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+testb imm8[0x1a] bl.ub[0x1a] => rflags[0x8c5,0x000]
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+testb imm8[0x5a] bl.ub[0x5a] => rflags[0x8c5,0x004]
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+testb imm8[0x1a] bl.ub[0xa1] => rflags[0x8c5,0x044]
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+testb imm8[0xa1] bl.ub[0xa1] => rflags[0x8c5,0x080]
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+testb imm8[0xa5] bl.ub[0xa5] => rflags[0x8c5,0x084]
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+testb imm8[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000]
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+testb imm8[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004]
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+testb imm8[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044]
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+testb imm8[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080]
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+testb imm8[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084]
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+testb r8.ub[0x1a] r8.ub[0x1a] => rflags[0x8c5,0x000]
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+testb r8.ub[0x5a] r8.ub[0x5a] => rflags[0x8c5,0x004]
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+testb r8.ub[0x1a] r8.ub[0xa1] => rflags[0x8c5,0x044]
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+testb r8.ub[0xa1] r8.ub[0xa1] => rflags[0x8c5,0x080]
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+testb r8.ub[0xa5] r8.ub[0xa5] => rflags[0x8c5,0x084]
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+testb r8.ub[0x1a] m8.ub[0x1a] => rflags[0x8c5,0x000]
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+testb r8.ub[0x5a] m8.ub[0x5a] => rflags[0x8c5,0x004]
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+testb r8.ub[0x1a] m8.ub[0xa1] => rflags[0x8c5,0x044]
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+testb r8.ub[0xa1] m8.ub[0xa1] => rflags[0x8c5,0x080]
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+testb r8.ub[0xa5] m8.ub[0xa5] => rflags[0x8c5,0x084]
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+testw imm16[0x1a1a] ax.uw[0x1a1a] => rflags[0x8c5,0x000]
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+testw imm16[0x5a5a] ax.uw[0x5a5a] => rflags[0x8c5,0x004]
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+testw imm16[0x1a1a] ax.uw[0xa1a1] => rflags[0x8c5,0x044]
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+testw imm16[0xa1a1] ax.uw[0xa1a1] => rflags[0x8c5,0x080]
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+testw imm16[0xa5a5] ax.uw[0xa5a5] => rflags[0x8c5,0x084]
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+testw imm16[0x1a1a] bx.uw[0x1a1a] => rflags[0x8c5,0x000]
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+testw imm16[0x5a5a] bx.uw[0x5a5a] => rflags[0x8c5,0x004]
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+testw imm16[0x1a1a] bx.uw[0xa1a1] => rflags[0x8c5,0x044]
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+testw imm16[0xa1a1] bx.uw[0xa1a1] => rflags[0x8c5,0x080]
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+testw imm16[0xa5a5] bx.uw[0xa5a5] => rflags[0x8c5,0x084]
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+testw imm16[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000]
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+testw imm16[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004]
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+testw imm16[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044]
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+testw imm16[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080]
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+testw imm16[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084]
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+testw r16.uw[0x1a1a] r16.uw[0x1a1a] => rflags[0x8c5,0x000]
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+testw r16.uw[0x5a5a] r16.uw[0x5a5a] => rflags[0x8c5,0x004]
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+testw r16.uw[0x1a1a] r16.uw[0xa1a1] => rflags[0x8c5,0x044]
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+testw r16.uw[0xa1a1] r16.uw[0xa1a1] => rflags[0x8c5,0x080]
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+testw r16.uw[0xa5a5] r16.uw[0xa5a5] => rflags[0x8c5,0x084]
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+testw r16.uw[0x1a1a] m16.uw[0x1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testw r16.uw[0x5a5a] m16.uw[0x5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testw r16.uw[0x1a1a] m16.uw[0xa1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testw r16.uw[0xa1a1] m16.uw[0xa1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testw r16.uw[0xa5a5] m16.uw[0xa5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testq r64.uq[0x5a5a5a5a5a5a5a5a] r64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testq r64.uq[0x1a1a1a1a1a1a1a1a] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testq r64.uq[0xa1a1a1a1a1a1a1a1] r64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testq r64.uq[0xa5a5a5a5a5a5a5a5] r64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
+testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0x1a1a1a1a1a1a1a1a] => rflags[0x8c5,0x000]
Mark Wielaard d6679b
+testq r64.uq[0x5a5a5a5a5a5a5a5a] m64.uq[0x5a5a5a5a5a5a5a5a] => rflags[0x8c5,0x004]
Mark Wielaard d6679b
+testq r64.uq[0x1a1a1a1a1a1a1a1a] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x044]
Mark Wielaard d6679b
+testq r64.uq[0xa1a1a1a1a1a1a1a1] m64.uq[0xa1a1a1a1a1a1a1a1] => rflags[0x8c5,0x080]
Mark Wielaard d6679b
+testq r64.uq[0xa5a5a5a5a5a5a5a5] m64.uq[0xa5a5a5a5a5a5a5a5] => rflags[0x8c5,0x084]
Mark Wielaard d6679b
 ###xaddb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[46]
Mark Wielaard d6679b
 ###xaddb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[46]
Mark Wielaard d6679b
 ###xaddw r16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[6912]
Mark Wielaard d6679b
diff --git a/none/tests/amd64/insn_fpu.def b/none/tests/amd64/insn_fpu.def
Mark Wielaard d6679b
index 590f584..525fd1b 100644
Mark Wielaard d6679b
--- a/none/tests/amd64/insn_fpu.def
Mark Wielaard d6679b
+++ b/none/tests/amd64/insn_fpu.def
Mark Wielaard d6679b
@@ -70,30 +70,30 @@ fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.43
Mark Wielaard d6679b
 fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000]
Mark Wielaard d6679b
 fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[7654321.1234567] fpusw[0x4700,0x0100]
Mark Wielaard d6679b
 fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[7654321.1234567] fpusw[0x4700,0x4000]
Mark Wielaard d6679b
-fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00]
Mark Wielaard d6679b
-fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01]
Mark Wielaard d6679b
-fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40]
Mark Wielaard d6679b
-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00]
Mark Wielaard d6679b
-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01]
Mark Wielaard d6679b
-fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40]
Mark Wielaard d6679b
-fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00]
Mark Wielaard d6679b
-fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01]
Mark Wielaard d6679b
-fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40]
Mark Wielaard d6679b
-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00]
Mark Wielaard d6679b
-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01]
Mark Wielaard d6679b
-fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40]
Mark Wielaard d6679b
-fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00]
Mark Wielaard d6679b
-fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01]
Mark Wielaard d6679b
-fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40]
Mark Wielaard d6679b
-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] eflags[0x45,0x00]
Mark Wielaard d6679b
-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] eflags[0x45,0x01]
Mark Wielaard d6679b
-fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] eflags[0x45,0x40]
Mark Wielaard d6679b
-fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] eflags[0x45,0x00]
Mark Wielaard d6679b
-fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] eflags[0x45,0x01]
Mark Wielaard d6679b
-fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] eflags[0x45,0x40]
Mark Wielaard d6679b
-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] eflags[0x45,0x00]
Mark Wielaard d6679b
-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] eflags[0x45,0x01]
Mark Wielaard d6679b
-fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] eflags[0x45,0x40]
Mark Wielaard d6679b
+fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00]
Mark Wielaard d6679b
+fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01]
Mark Wielaard d6679b
+fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40]
Mark Wielaard d6679b
+fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00]
Mark Wielaard d6679b
+fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01]
Mark Wielaard d6679b
+fcomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40]
Mark Wielaard d6679b
+fcomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00]
Mark Wielaard d6679b
+fcomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01]
Mark Wielaard d6679b
+fcomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40]
Mark Wielaard d6679b
+fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00]
Mark Wielaard d6679b
+fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01]
Mark Wielaard d6679b
+fcomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40]
Mark Wielaard d6679b
+fucomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] rflags[0x45,0x00]
Mark Wielaard d6679b
+fucomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] rflags[0x45,0x01]
Mark Wielaard d6679b
+fucomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] rflags[0x45,0x40]
Mark Wielaard d6679b
+fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st0.pd[1234567.7654322] st2.pd[1234567.7654321] rflags[0x45,0x00]
Mark Wielaard d6679b
+fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st0.pd[1234567.7654320] st2.pd[1234567.7654321] rflags[0x45,0x01]
Mark Wielaard d6679b
+fucomi st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st0.pd[1234567.7654321] st2.pd[1234567.7654321] rflags[0x45,0x40]
Mark Wielaard d6679b
+fucomip st2.ps[1234.5678] st0.ps[1234.5679] => st1.ps[1234.5679] rflags[0x45,0x00]
Mark Wielaard d6679b
+fucomip st2.ps[1234.5678] st0.ps[1234.5676] => st1.ps[1234.5676] rflags[0x45,0x01]
Mark Wielaard d6679b
+fucomip st2.ps[1234.5678] st0.ps[1234.5678] => st1.ps[1234.5678] rflags[0x45,0x40]
Mark Wielaard d6679b
+fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654322] => st1.pd[1234567.7654321] rflags[0x45,0x00]
Mark Wielaard d6679b
+fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654320] => st1.pd[1234567.7654321] rflags[0x45,0x01]
Mark Wielaard d6679b
+fucomip st2.pd[1234567.7654321] st0.pd[1234567.7654321] => st1.pd[1234567.7654321] rflags[0x45,0x40]
Mark Wielaard d6679b
 fchs st0.ps[1234.5678] : => st0.ps[-1234.5678]
Mark Wielaard d6679b
 fchs st0.ps[-1234.5678] : => st0.ps[1234.5678]
Mark Wielaard d6679b
 fchs st0.pd[12345678.87654321] : => st0.pd[-12345678.87654321]
Mark Wielaard d6679b
diff --git a/none/tests/amd64/insn_sse.def b/none/tests/amd64/insn_sse.def
Mark Wielaard d6679b
index a9e92a0..277a062 100644
Mark Wielaard d6679b
--- a/none/tests/amd64/insn_sse.def
Mark Wielaard d6679b
+++ b/none/tests/amd64/insn_sse.def
Mark Wielaard d6679b
@@ -38,12 +38,12 @@ cmpordps xmm.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,23
Mark Wielaard d6679b
 cmpordps m128.ps[234.5678,234.5678,234.5678,234.5678] xmm.ps[234.5679,234.5677,234.5679,234.5677] => 1.ud[0xffffffff,0xffffffff,0xffffffff,0xffffffff]
Mark Wielaard d6679b
 cmpordss xmm.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5679,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0]
Mark Wielaard d6679b
 cmpordss m128.ps[1234.5678,0.0,0.0,0.0] xmm.ps[1234.5676,0.0,0.0,0.0] => 1.ud[0xffffffff,0,0,0]
Mark Wielaard d6679b
-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
-comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
+comiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+comiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+comiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+comiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+comiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
+comiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
 cvtpi2ps mm.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4]
Mark Wielaard d6679b
 cvtpi2ps m64.sd[1234,5678] xmm.ps[1.1,2.2,3.3,4.4] => 1.ps[1234.0,5678.0,3.3,4.4]
Mark Wielaard d6679b
 cvtps2pi xmm.ps[12.34,56.78,1.11,2.22] mm.sd[1,2] => 1.sd[12,57]
Mark Wielaard d6679b
@@ -140,12 +140,12 @@ subps xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,
Mark Wielaard d6679b
 subps m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,-23.77,-21.21,-76.65]
Mark Wielaard d6679b
 subss xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
Mark Wielaard d6679b
 subss m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
Mark Wielaard d6679b
-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
-ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
+ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+ucomiss m32.ps[234.5678] xmm.ps[234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+ucomiss m32.ps[234.5678] xmm.ps[234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+ucomiss xmm.ps[234.5678,0.0] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
+ucomiss m32.ps[234.5678] xmm.ps[234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
 unpckhps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65]
Mark Wielaard d6679b
 unpckhps m128.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[55.66,43.21,77.88,87.65]
Mark Wielaard d6679b
 unpcklps xmm.ps[12.34,56.78,43.21,87.65] xmm.ps[11.22,33.44,55.66,77.88] => 1.ps[11.22,12.34,33.44,56.78]
Mark Wielaard d6679b
diff --git a/none/tests/amd64/insn_sse2.def b/none/tests/amd64/insn_sse2.def
Mark Wielaard d6679b
index 3cbdd41..7e0890e 100644
Mark Wielaard d6679b
--- a/none/tests/amd64/insn_sse2.def
Mark Wielaard d6679b
+++ b/none/tests/amd64/insn_sse2.def
Mark Wielaard d6679b
@@ -38,12 +38,12 @@ cmpnlesd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff,
Mark Wielaard d6679b
 cmpnlesd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0x0000000000000000,0]
Mark Wielaard d6679b
 cmpordsd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => 1.uq[0xffffffffffffffff,0]
Mark Wielaard d6679b
 cmpordsd m128.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => 1.uq[0xffffffffffffffff,0]
Mark Wielaard d6679b
-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
-comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
+comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+comisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
+comisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+comisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+comisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
 cvtdq2pd xmm.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0]
Mark Wielaard d6679b
 cvtdq2pd m128.sd[1234,5678,0,0] xmm.pd[0.0,0.0] => 1.pd[1234.0,5678.0]
Mark Wielaard d6679b
 cvtdq2ps xmm.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0]
Mark Wielaard d6679b
@@ -329,12 +329,12 @@ subpd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4
Mark Wielaard d6679b
 subpd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,-7654.4321]
Mark Wielaard d6679b
 subsd xmm.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0]
Mark Wielaard d6679b
 subsd m128.pd[1234.5678,8765.4321] xmm.pd[2222.0,1111.0] => 1.pd[987.4322,1111.0]
Mark Wielaard d6679b
-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
-ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => eflags[0x8d5,0x000]
Mark Wielaard d6679b
-ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => eflags[0x8d5,0x001]
Mark Wielaard d6679b
-ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => eflags[0x8d5,0x040]
Mark Wielaard d6679b
+ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+ucomisd xmm.pd[1234.5678,0.0] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
+ucomisd m64.pd[1234.5678] xmm.pd[1234.5679,0.0] => rflags[0x8d5,0x000]
Mark Wielaard d6679b
+ucomisd m64.pd[1234.5678] xmm.pd[1234.5677,0.0] => rflags[0x8d5,0x001]
Mark Wielaard d6679b
+ucomisd m64.pd[1234.5678] xmm.pd[1234.5678,0.0] => rflags[0x8d5,0x040]
Mark Wielaard d6679b
 unpckhpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321]
Mark Wielaard d6679b
 unpckhpd m128.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[5566.7788,8765.4321]
Mark Wielaard d6679b
 unpcklpd xmm.pd[1234.5678,8765.4321] xmm.pd[1122.3344,5566.7788] => 1.pd[1122.3344,1234.5678]