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Mark Wielaard |
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commit 85d259b468099f38b5241241b92fee07530b53d9
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Mark Wielaard |
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Author: carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Mark Wielaard |
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Date: Wed Sep 16 22:26:59 2015 +0000
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Mark Wielaard |
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Add support for the Power PC Program Priority Register
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Added the Program Priority Register (PPR), support to read and write it
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via the mfspr and mtspr instructions as well as the special OR instruction
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No Op instructions. The setting of the PPR is dependent on the value in
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the Problem State Priority Boost register. Basic support for this register
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was added. Not all of the PSPB register functionality was added.
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This patch fixes bugzilla 352769.
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git-svn-id: svn://svn.valgrind.org/vex/trunk@3189 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
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index 00137e4..08a0753 100644
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--- a/VEX/priv/guest_ppc_helpers.c
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+++ b/VEX/priv/guest_ppc_helpers.c
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@@ -521,6 +521,8 @@ void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state )
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vex_state->guest_IP_AT_SYSCALL = 0;
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vex_state->guest_SPRG3_RO = 0;
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+ vex_state->guest_PPR = 0x4ULL << 50; // medium priority
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+ vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
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vex_state->padding1 = 0;
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vex_state->padding2 = 0;
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@@ -691,6 +693,8 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
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vex_state->guest_TFHAR = 0;
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vex_state->guest_TFIAR = 0;
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vex_state->guest_TEXASR = 0;
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+ vex_state->guest_PPR = 0x4ULL << 50; // medium priority
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+ vex_state->guest_PSPB = 0x00; // an arbitrary non-zero value to start with
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}
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diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
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index bc0bdcb..a0ee34a 100644
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--- a/VEX/priv/guest_ppc_toIR.c
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+++ b/VEX/priv/guest_ppc_toIR.c
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@@ -288,6 +288,8 @@ static void* fnptr_to_fnentry( const VexAbiInfo* vbi, void* f )
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#define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR)
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#define OFFB_TEXASRU offsetofPPCGuestState(guest_TEXASRU)
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#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
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+#define OFFB_PPR offsetofPPCGuestState(guest_PPR)
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+#define OFFB_PSPB offsetofPPCGuestState(guest_PSPB)
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/*------------------------------------------------------------*/
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@@ -438,6 +440,14 @@ typedef enum {
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PPC_GST_TFIAR, // Transactional Failure Instruction Address Register
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PPC_GST_TEXASR, // Transactional EXception And Summary Register
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PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper
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+ PPC_GST_PPR, // Program Priority register
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+ PPC_GST_PPR32, // Upper 32-bits of Program Priority register
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+ PPC_GST_PSPB, /* Problem State Priority Boost register, Note, the
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+ * register is initialized to a non-zero value. Currently
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+ * Valgrind is not supporting the register value to
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+ * automatically decrement. Could be added later if
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+ * needed.
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+ */
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PPC_GST_MAX
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} PPC_GST;
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@@ -2747,6 +2757,15 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
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case PPC_GST_TFIAR:
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return IRExpr_Get( OFFB_TFIAR, ty );
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+ case PPC_GST_PPR:
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+ return IRExpr_Get( OFFB_PPR, ty );
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+
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+ case PPC_GST_PPR32:
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+ return unop( Iop_64HIto32, IRExpr_Get( OFFB_PPR, ty ) );
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+
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+ case PPC_GST_PSPB:
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+ return IRExpr_Get( OFFB_PSPB, ty );
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+
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default:
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vex_printf("getGST(ppc): reg = %u", reg);
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vpanic("getGST(ppc)");
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@@ -2926,6 +2945,95 @@ static void putGST ( PPC_GST reg, IRExpr* src )
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vassert( ty_src == Ity_I64 );
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stmt( IRStmt_Put( OFFB_TFHAR, src ) );
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break;
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+
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+ case PPC_GST_PPR32:
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+ case PPC_GST_PPR:
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+ {
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+ /* The Program Priority Register (PPR) stores the priority in
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+ * bits [52:50]. The user setable priorities are:
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+ *
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+ * 001 very low
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+ * 010 low
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+ * 011 medium low
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+ * 100 medium
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+ * 101 medium high
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+ *
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+ * If the argument is not between 0b001 and 0b100 the priority is set
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+ * to 0b100. The priority can only be set to 0b101 if the the Problem
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+ * State Boost Register is non-zero. The value of the PPR is not
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+ * changed if the input is not valid.
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+ */
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+
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+ IRTemp not_valid = newTemp(Ity_I64);
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+ IRTemp has_perm = newTemp(Ity_I64);
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+ IRTemp new_src = newTemp(Ity_I64);
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+ IRTemp PSPB_val = newTemp(Ity_I64);
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+ IRTemp value = newTemp(Ity_I64);
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+
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+ vassert(( ty_src == Ity_I64 ) || ( ty_src == Ity_I32 ));
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+ assign( PSPB_val, binop( Iop_32HLto64,
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+ mkU32( 0 ),
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+ IRExpr_Get( OFFB_PSPB, Ity_I32 ) ) );
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+ if( reg == PPC_GST_PPR32 ) {
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+ vassert( ty_src == Ity_I32 );
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+ assign( value, binop( Iop_32HLto64,
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+ mkU32(0),
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+ binop( Iop_And32,
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+ binop( Iop_Shr32, src, mkU8( 18 ) ),
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+ mkU32( 0x7 ) ) ) );
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+ } else {
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+ vassert( ty_src == Ity_I64 );
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+ assign( value, binop( Iop_And64,
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+ binop( Iop_Shr64, src, mkU8( 50 ) ),
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+ mkU64( 0x7 ) ) );
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+ }
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+ assign( has_perm,
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+ binop( Iop_And64,
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+ unop( Iop_1Sto64,
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+ binop( Iop_CmpEQ64,
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+ mkexpr( PSPB_val ),
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+ mkU64( 0 ) ) ),
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+ unop( Iop_1Sto64,
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+ binop( Iop_CmpEQ64,
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+ mkU64( 0x5 ),
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+ mkexpr( value ) ) ) ) );
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+ assign( not_valid,
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+ binop( Iop_Or64,
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+ unop( Iop_1Sto64,
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+ binop( Iop_CmpEQ64,
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+ mkexpr( value ),
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+ mkU64( 0 ) ) ),
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+ unop( Iop_1Sto64,
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+ binop( Iop_CmpLT64U,
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+ mkU64( 0x5 ),
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+ mkexpr( value ) ) ) ) );
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+ assign( new_src,
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+ binop( Iop_Or64,
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+ binop( Iop_And64,
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+ unop( Iop_Not64,
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+ mkexpr( not_valid ) ),
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+ src ),
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+ binop( Iop_And64,
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+ mkexpr( not_valid ),
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+ binop( Iop_Or64,
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+ binop( Iop_And64,
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+ mkexpr( has_perm),
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+ binop( Iop_Shl64,
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+ mkexpr( value ),
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+ mkU8( 50 ) ) ),
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+ binop( Iop_And64,
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+ IRExpr_Get( OFFB_PPR, ty ),
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+ unop( Iop_Not64,
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+ mkexpr( has_perm )
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+ ) ) ) ) ) );
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+
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+ /* make sure we only set the valid bit field [52:50] */
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+ stmt( IRStmt_Put( OFFB_PPR,
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+ binop( Iop_And64,
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+ mkexpr( new_src ),
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+ mkU64( 0x1C000000000000) ) ) );
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+ break;
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+ }
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default:
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vex_printf("putGST(ppc): reg = %u", reg);
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vpanic("putGST(ppc)");
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@@ -7131,6 +7239,18 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
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DIP("mfspr r%u (TEXASRU)\n", rD_addr);
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putIReg( rD_addr, getGST( PPC_GST_TEXASRU) );
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break;
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+ case 0x9F: // 159
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+ DIP("mfspr r%u (PSPB)\n", rD_addr);
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+ putIReg( rD_addr, getGST( PPC_GST_PSPB) );
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+ break;
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+ case 0x380: // 896
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+ DIP("mfspr r%u (PPR)\n", rD_addr);
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+ putIReg( rD_addr, getGST( PPC_GST_PPR) );
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Mark Wielaard |
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+ break;
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+ case 0x382: // 898
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+ DIP("mfspr r%u (PPR)32\n", rD_addr);
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+ putIReg( rD_addr, getGST( PPC_GST_PPR32) );
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+ break;
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case 0x100:
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DIP("mfvrsave r%u\n", rD_addr);
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putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ),
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@@ -7287,6 +7407,18 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
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DIP("mtspr r%u (TEXASR)\n", rS_addr);
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Mark Wielaard |
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putGST( PPC_GST_TEXASR, mkexpr(rS) );
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Mark Wielaard |
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break;
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Mark Wielaard |
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+ case 0x9F: // 159
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+ DIP("mtspr r%u (PSPB)\n", rS_addr);
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Mark Wielaard |
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+ putGST( PPC_GST_PSPB, mkexpr(rS) );
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Mark Wielaard |
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+ break;
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+ case 0x380: // 896
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+ DIP("mtspr r%u (PPR)\n", rS_addr);
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Mark Wielaard |
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+ putGST( PPC_GST_PPR, mkexpr(rS) );
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Mark Wielaard |
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+ break;
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+ case 0x382: // 898
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+ DIP("mtspr r%u (PPR32)\n", rS_addr);
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+ putGST( PPC_GST_PPR32, mkexpr(rS) );
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Mark Wielaard |
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+ break;
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default:
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vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR);
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return False;
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diff --git a/pub/libvex_guest_ppc32.h b/pub/libvex_guest_ppc32.h
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Mark Wielaard |
5f750d |
index 2489d55..5bebef8 100644
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Mark Wielaard |
5f750d |
--- a/VEX/pub/libvex_guest_ppc32.h
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Mark Wielaard |
5f750d |
+++ b/VEX/pub/libvex_guest_ppc32.h
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5f750d |
@@ -241,11 +241,12 @@ typedef
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Mark Wielaard |
5f750d |
/* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
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Mark Wielaard |
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/* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
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Mark Wielaard |
5f750d |
/* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
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Mark Wielaard |
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- /* 1384 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
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Mark Wielaard |
5f750d |
-
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5f750d |
+ /* 1384 */ ULong guest_PPR; // Program Priority register
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Mark Wielaard |
5f750d |
+ /* 1392 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
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Mark Wielaard |
5f750d |
+ /* 1396 */ UInt guest_PSPB; // Problem State Priority Boost register
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Mark Wielaard |
5f750d |
/* Padding to make it have an 16-aligned size */
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Mark Wielaard |
5f750d |
- /* 1388 */ UInt padding2;
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Mark Wielaard |
5f750d |
-
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Mark Wielaard |
5f750d |
+ /* 1400 */ UInt padding2;
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Mark Wielaard |
5f750d |
+ /* 1404 */ UInt padding3;
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Mark Wielaard |
5f750d |
}
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Mark Wielaard |
5f750d |
VexGuestPPC32State;
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Mark Wielaard |
5f750d |
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Mark Wielaard |
5f750d |
diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
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Mark Wielaard |
5f750d |
index dea2bba..f3310cb 100644
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Mark Wielaard |
5f750d |
--- a/VEX/pub/libvex_guest_ppc64.h
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Mark Wielaard |
5f750d |
+++ b/VEX/pub/libvex_guest_ppc64.h
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Mark Wielaard |
5f750d |
@@ -282,12 +282,14 @@ typedef
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Mark Wielaard |
5f750d |
/* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
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Mark Wielaard |
5f750d |
/* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
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Mark Wielaard |
5f750d |
/* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
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Mark Wielaard |
5f750d |
- /* 1680 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
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Mark Wielaard |
5f750d |
+ /* 1680 */ ULong guest_PPR; // Program Priority register
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|
Mark Wielaard |
5f750d |
+ /* 1688 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
|
|
Mark Wielaard |
5f750d |
+ /* 1692 */ UInt guest_PSPB; // Problem State Priority Boost register
|
|
Mark Wielaard |
5f750d |
|
|
Mark Wielaard |
5f750d |
/* Padding to make it have an 16-aligned size */
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|
Mark Wielaard |
5f750d |
- /* 1684 */ UInt padding1;
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|
Mark Wielaard |
5f750d |
- /* 1688 */ UInt padding2;
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Mark Wielaard |
5f750d |
- /* 1692 */ UInt padding3;
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|
Mark Wielaard |
5f750d |
+ /* 1696 UInt padding1; currently not needed */
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|
Mark Wielaard |
5f750d |
+ /* 1700 UInt padding2; currently not needed */
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Mark Wielaard |
5f750d |
+ /* 1708 UInt padding3; currently not needed */
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|
Mark Wielaard |
5f750d |
|
|
Mark Wielaard |
5f750d |
}
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|
Mark Wielaard |
5f750d |
VexGuestPPC64State;
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