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commit ae8c6de01417023e78763de145b1c0e6ddd87277
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Author: Carl Love <cel@us.ibm.com>
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Date: Wed Oct 20 20:40:13 2021 +0000
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Fix for the prefixed stq instruction in PC relative mode.
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The pstq instruction for R=1, was not using the correct effective address.
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The EA_hi and EA_lo should have been based on the value of EA as calculated
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by the function calculate_prefix_EA. Unfortuanely, the EA_hi and EA_lo
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addresses were still using the previous code (not PC relative) to calculate
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the address from the contants of RA plus the offset.
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diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
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index 8afd77490..543fa9574 100644
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--- a/VEX/priv/guest_ppc_toIR.c
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+++ b/VEX/priv/guest_ppc_toIR.c
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@@ -9838,23 +9838,24 @@ static Bool dis_int_store_ds_prefix ( UInt prefix,
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if (host_endness == VexEndnessBE) {
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/* upper 64-bits */
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- assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val ) );
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+ assign( EA_hi, mkexpr(EA));
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/* lower 64-bits */
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- assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val+8 ) );
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+ assign( EA_lo, binop(Iop_Add64, mkexpr(EA), mkU64(8)));
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+
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} else {
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/* upper 64-bits */
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- assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val+8 ) );
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+ assign( EA_hi, binop(Iop_Add64, mkexpr(EA), mkU64(8)));
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/* lower 64-bits */
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- assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val ) );
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+ assign( EA_lo, mkexpr(EA));
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}
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} else {
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/* upper half of upper 64-bits */
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- assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val+4 ) );
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+ assign( EA_hi, binop(Iop_Add32, mkexpr(EA), mkU32(4)));
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/* lower half of upper 64-bits */
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- assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val+12 ) );
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+ assign( EA_lo, binop(Iop_Add32, mkexpr(EA), mkU32(12)));
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}
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/* Note, the store order for stq instruction is the same for BE
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