|
 |
e9c5e8 |
commit fb6f7abcbc92506d302fb18a2c5fc853d2929248
|
|
|
e9c5e8 |
Author: Carl Love <cel@us.ibm.com>
|
|
|
e9c5e8 |
Date: Tue Jun 9 10:42:03 2020 -0500
|
|
|
e9c5e8 |
|
|
|
e9c5e8 |
Power PC Fix extraction of the L field for sync instruction
|
|
|
e9c5e8 |
|
|
|
e9c5e8 |
The L field is currently a two bit[22:21] field in ISA 3.0. The size of the
|
|
|
e9c5e8 |
L field has changed over time.
|
|
|
e9c5e8 |
|
|
|
e9c5e8 |
Currently the ISA 3.0 Valgrind sync instruction support code sets the
|
|
|
e9c5e8 |
flag_L for the instruction L field to a five bit value that includes bits
|
|
|
e9c5e8 |
that are marked reserved the sync instruction. This patch fixes the issue for ISA 3.0
|
|
|
e9c5e8 |
to only setting flag_L the specified two bits.
|
|
|
e9c5e8 |
|
|
|
e9c5e8 |
Valgrind bugzilla: https://bugs.kde.org/show_bug.cgi?id=422677
|
|
|
e9c5e8 |
|
|
|
e9c5e8 |
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
|
|
|
e9c5e8 |
index 582c59ec0..c4965a19e 100644
|
|
|
e9c5e8 |
--- a/VEX/priv/guest_ppc_toIR.c
|
|
|
e9c5e8 |
+++ b/VEX/priv/guest_ppc_toIR.c
|
|
|
e9c5e8 |
@@ -8777,7 +8777,7 @@ static Bool dis_memsync ( UInt theInstr )
|
|
|
e9c5e8 |
/* X-Form, XL-Form */
|
|
|
e9c5e8 |
UChar opc1 = ifieldOPC(theInstr);
|
|
|
e9c5e8 |
UInt b11to25 = IFIELD(theInstr, 11, 15);
|
|
|
e9c5e8 |
- UChar flag_L = ifieldRegDS(theInstr);
|
|
|
e9c5e8 |
+ UChar flag_L = IFIELD(theInstr, 21, 2); //ISA 3.0
|
|
|
e9c5e8 |
UInt b11to20 = IFIELD(theInstr, 11, 10);
|
|
|
e9c5e8 |
UInt M0 = IFIELD(theInstr, 11, 5);
|
|
|
e9c5e8 |
UChar rD_addr = ifieldRegDS(theInstr);
|