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7a6b42 |
From 2c1f016e634bf79faf45e81c14c955c711bc202f Mon Sep 17 00:00:00 2001
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From: Mark Wielaard <mark@klomp.org>
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Date: Mon, 31 Dec 2018 22:26:31 +0100
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Subject: [PATCH] Bug 402519 - POWER 3.0 addex instruction incorrectly
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7a6b42 |
implemented
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7a6b42 |
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addex uses OV as carry in and carry out. For all other instructions
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OV is the signed overflow flag. And instructions like adde use CA
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as carry.
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Replace set_XER_OV_OV32 with set_XER_OV_OV32_ADDEX, which will
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call calculate_XER_CA_64 and calculate_XER_CA_32, but with OV
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as input, and sets OV and OV32.
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7a6b42 |
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Enable test_addex in none/tests/ppc64/test_isa_3_0.c and update
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the expected output. test_addex would fail to match the expected
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output before this patch.
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---
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NEWS | 1 +
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VEX/priv/guest_ppc_toIR.c | 52 ++++++++++++++---------
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none/tests/ppc64/test_isa_3_0.c | 3 +-
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none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE | 36 ++++++++++------
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4 files changed, 58 insertions(+), 34 deletions(-)
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diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
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index 18df822..d685383 100644
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--- a/VEX/priv/guest_ppc_toIR.c
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+++ b/VEX/priv/guest_ppc_toIR.c
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@@ -2645,21 +2645,6 @@ static void copy_OV_to_OV32( void ) {
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putXER_OV32( getXER_OV() );
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}
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-static void set_XER_OV_OV32 ( IRType ty, UInt op, IRExpr* res,
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- IRExpr* argL, IRExpr* argR )
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-{
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- if (ty == Ity_I32) {
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- set_XER_OV_OV32_32( op, res, argL, argR );
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- } else {
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- IRExpr* xer_ov_32;
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- set_XER_OV_64( op, res, argL, argR );
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- xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
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- unop(Iop_64to32, argL),
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- unop(Iop_64to32, argR));
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- putXER_OV32( unop(Iop_32to8, xer_ov_32) );
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- }
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-}
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-
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static void set_XER_OV_OV32_SO ( IRType ty, UInt op, IRExpr* res,
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IRExpr* argL, IRExpr* argR )
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{
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@@ -3005,6 +2990,33 @@ static void set_XER_CA_CA32 ( IRType ty, UInt op, IRExpr* res,
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}
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}
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+/* Used only by addex instruction, which uses and sets OV as carry. */
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+static void set_XER_OV_OV32_ADDEX ( IRType ty, IRExpr* res,
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+ IRExpr* argL, IRExpr* argR,
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+ IRExpr* old_ov )
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+{
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+ if (ty == Ity_I32) {
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+ IRTemp xer_ov = newTemp(Ity_I32);
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+ assign ( xer_ov, unop(Iop_32to8,
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+ calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
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+ res, argL, argR, old_ov ) ) );
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+ putXER_OV( mkexpr (xer_ov) );
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+ putXER_OV32( mkexpr (xer_ov) );
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+ } else {
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+ IRExpr *xer_ov;
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+ IRExpr* xer_ov_32;
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+ xer_ov = calculate_XER_CA_64( PPCG_FLAG_OP_ADDE,
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+ res, argL, argR, old_ov );
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+ putXER_OV( unop(Iop_32to8, xer_ov) );
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+ xer_ov_32 = calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
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+ unop(Iop_64to32, res),
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+ unop(Iop_64to32, argL),
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+ unop(Iop_64to32, argR),
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+ unop(Iop_64to32, old_ov) );
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+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
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+ }
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+}
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+
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/*------------------------------------------------------------*/
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@@ -5094,16 +5106,18 @@ static Bool dis_int_arith ( UInt theInstr )
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}
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case 0xAA: {// addex (Add Extended alternate carry bit Z23-form)
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+ IRTemp old_xer_ov = newTemp(ty);
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DIP("addex r%u,r%u,r%u,%d\n", rD_addr, rA_addr, rB_addr, (Int)flag_OE);
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+ assign( old_xer_ov, mkWidenFrom32(ty, getXER_OV_32(), False) );
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assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
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binop( mkSzOp(ty, Iop_Add8), mkexpr(rB),
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- mkWidenFrom8( ty, getXER_OV(), False ) ) ) );
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+ mkexpr(old_xer_ov) ) ) );
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/* CY bit is same as OE bit */
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if (flag_OE == 0) {
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- /* Exception, do not set SO bit */
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- set_XER_OV_OV32( ty, PPCG_FLAG_OP_ADDE,
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- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
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+ /* Exception, do not set SO bit and set OV from carry. */
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+ set_XER_OV_OV32_ADDEX( ty, mkexpr(rD), mkexpr(rA), mkexpr(rB),
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+ mkexpr(old_xer_ov) );
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} else {
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/* CY=1, 2 and 3 (AKA flag_OE) are reserved */
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vex_printf("addex instruction, CY = %d is reserved.\n", flag_OE);
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diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
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index 2d13505..1c2cda3 100644
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--- a/none/tests/ppc64/test_isa_3_0.c
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+++ b/none/tests/ppc64/test_isa_3_0.c
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@@ -286,7 +286,7 @@ static test_list_t testgroup_ia_ops_two[] = {
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{ &test_moduw, "moduw" },
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{ &test_modsd, "modsd" },
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{ &test_modud, "modud" },
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- //{ &test_addex, "addex" },
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+ { &test_addex, "addex" },
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{ NULL , NULL },
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};
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@@ -2741,7 +2741,6 @@ static void testfunction_gpr_vector_logical_one (const char* instruction_name,
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* rt, xa
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*/
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int i;
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- int t;
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volatile HWord_t res;
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VERBOSE_FUNCTION_CALLOUT
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diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
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index 152ff28..cc0e88e 100644
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--- a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
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+++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
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@@ -40,7 +40,17 @@ modud ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
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modud ffffffffffffffff, 0000001cbe991def => 000000043eb0c0b2 (00000000)
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modud ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
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-All done. Tested 4 different instructions
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+addex 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
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+addex 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
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+addex 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
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+addex 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000)
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+addex 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000) OV32
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+addex 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000) OV OV32
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+addex ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000) OV OV32
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+addex ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000) OV OV32
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+addex ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000) OV OV32
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+
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+All done. Tested 5 different instructions
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ppc one argument plus shift:
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Test instruction group [ppc one argument plus shift]
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extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
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@@ -85,7 +95,7 @@ extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaa
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extswsli. 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
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extswsli. 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
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-All done. Tested 6 different instructions
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+All done. Tested 7 different instructions
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ppc three parameter ops:
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Test instruction group [ppc three parameter ops]
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maddhd 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
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@@ -172,7 +182,7 @@ maddld ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 000000000000000
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maddld ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000)
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maddld ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
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-All done. Tested 9 different instructions
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+All done. Tested 10 different instructions
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ppc count zeros:
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Test instruction group [ppc count zeros]
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cnttzw 0000000000000000 => 0000000000000020
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@@ -197,7 +207,7 @@ cnttzd. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (200
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cnttzd. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
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7a6b42 |
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7a6b42 |
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7a6b42 |
-All done. Tested 13 different instructions
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+All done. Tested 14 different instructions
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7a6b42 |
ppc set boolean:
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7a6b42 |
Test instruction group [ppc set boolean]
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setb cr_field:0 cr_value::00000000 => 0000000000000000
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7a6b42 |
@@ -265,7 +275,7 @@ setb cr_field:7 cr_value::00000005 => 0000000000000001
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setb cr_field:7 cr_value::00000006 => 0000000000000001
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setb cr_field:7 cr_value::00000007 => 0000000000000001
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7a6b42 |
-All done. Tested 14 different instructions
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+All done. Tested 15 different instructions
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7a6b42 |
ppc char compare:
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7a6b42 |
Test instruction group [ppc char compare]
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cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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@@ -1711,7 +1721,7 @@ cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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7a6b42 |
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7a6b42 |
-All done. Tested 17 different instructions
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+All done. Tested 18 different instructions
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7a6b42 |
ppc vector scalar move to/from:
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7a6b42 |
Test instruction group [ppc vector scalar move to/from]
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7a6b42 |
mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
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7a6b42 |
@@ -1777,7 +1787,7 @@ mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 113377cc113377cc
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mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
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7a6b42 |
mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
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7a6b42 |
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7a6b42 |
-All done. Tested 20 different instructions
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7a6b42 |
+All done. Tested 21 different instructions
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7a6b42 |
ppc dfp significance:
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7a6b42 |
Test instruction group [ppc dfp significance]
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7a6b42 |
dtstsfi significance(0x00) +Finite 0 * 10 ^ -12 (GT) (4)
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7a6b42 |
@@ -1862,7 +1872,7 @@ dtstsfiq significance(0x20) -inf (GT) (4)
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7a6b42 |
dtstsfiq significance(0x30) -inf (GT) (4)
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7a6b42 |
dtstsfiq significance(0x3f) -inf (GT) (4)
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7a6b42 |
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7a6b42 |
-All done. Tested 22 different instructions
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7a6b42 |
+All done. Tested 23 different instructions
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7a6b42 |
ppc bcd misc:
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7a6b42 |
Test instruction group [ppc bcd misc]
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7a6b42 |
bcdadd. p0 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000000000000c (+|0) => (EQ) (2) xt:0000000000000000 000000000000000c(+|0)
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7a6b42 |
@@ -33338,12 +33348,12 @@ bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:9999999999999999 99999
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7a6b42 |
bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000001234567d ( - ) => (GT) (4) xt:0000000000000000 000000305419901f(+|0)
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7a6b42 |
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7a6b42 |
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7a6b42 |
-All done. Tested 51 different instructions
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7a6b42 |
+All done. Tested 52 different instructions
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7a6b42 |
ppc noop misc:
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7a6b42 |
Test instruction group [ppc noop misc]
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7a6b42 |
wait =>
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7a6b42 |
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7a6b42 |
-All done. Tested 52 different instructions
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7a6b42 |
+All done. Tested 53 different instructions
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7a6b42 |
ppc addpc_misc:
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7a6b42 |
Test instruction group [ppc addpc_misc]
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7a6b42 |
addpcis 0000000000000000 => 0000000000000000
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7a6b42 |
@@ -33380,7 +33390,7 @@ subpcis 000000000000000d => 0000000000000000
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7a6b42 |
subpcis 000000000000000e => 0000000000000000
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7a6b42 |
subpcis 000000000000000f => 0000000000000000
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7a6b42 |
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7a6b42 |
-All done. Tested 54 different instructions
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7a6b42 |
+All done. Tested 55 different instructions
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7a6b42 |
ppc mffpscr:
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7a6b42 |
Test instruction group [ppc mffpscr]
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7a6b42 |
mffsce => 000000000.000000
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7a6b42 |
@@ -33395,7 +33405,7 @@ mffs => 000000000.000000
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7a6b42 |
fpscr: f14
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7a6b42 |
local_fpscr:
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7a6b42 |
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7a6b42 |
-All done. Tested 57 different instructions
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7a6b42 |
+All done. Tested 58 different instructions
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7a6b42 |
ppc mffpscr:
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7a6b42 |
Test instruction group [ppc mffpscr]
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7a6b42 |
mffscdrni 0 => 0X0
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7a6b42 |
@@ -33426,4 +33436,4 @@ mffscrn f15 0X1 => 0X200000000
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7a6b42 |
mffscrn f15 0X2 => 0X200000000
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7a6b42 |
fpscr: f14 local_fpscr: 30-DRN1 RN-bit62
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7a6b42 |
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7a6b42 |
-All done. Tested 61 different instructions
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7a6b42 |
+All done. Tested 62 different instructions
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7a6b42 |
--
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7a6b42 |
1.8.3.1
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7a6b42 |
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