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commit f9fae2ab83f7263f8d58f83ddd58921cd5d1dca8
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Author: sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Date: Thu Oct 30 23:10:45 2014 +0000
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Implement FCVTAS W_S and FCVTAU W_S. Fixes #340509.
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git-svn-id: svn://svn.valgrind.org/vex/trunk@2984 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index 2677211..acfdc02 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -12189,6 +12189,7 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn)
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/* 31 30 29 28 23 21 20 18 15 9 4
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sf 0 0 11110 type 1 rmode opcode 000000 n d
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The first 3 bits are really "sf 0 S", but S is always zero.
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+ Decode fields: sf,type,rmode,opcode
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*/
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# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
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if (INSN(30,29) != BITS2(0,0)
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@@ -12205,7 +12206,7 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn)
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UInt dd = INSN(4,0);
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// op = 000, 001
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- /* -------- FCVT{N,P,M,Z}{S,U} (scalar, integer) -------- */
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+ /* -------- FCVT{N,P,M,Z,A}{S,U} (scalar, integer) -------- */
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/* 30 23 20 18 15 9 4
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sf 00 11110 0x 1 00 000 000000 n d FCVTNS Rd, Fn (round to
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sf 00 11110 0x 1 00 001 000000 n d FCVTNU Rd, Fn nearest)
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@@ -12213,23 +12214,38 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn)
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---------------- 10 -------------- FCVTM-------- (round to -inf)
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---------------- 11 -------------- FCVTZ-------- (round to zero)
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+ ---------------- 00 100 ---------- FCVTAS------- (nearest, ties away)
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+ ---------------- 00 101 ---------- FCVTAU------- (nearest, ties away)
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+
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Rd is Xd when sf==1, Wd when sf==0
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Fn is Dn when x==1, Sn when x==0
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20:19 carry the rounding mode, using the same encoding as FPCR
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*/
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- if (ty <= X01 && (op == BITS3(0,0,0) || op == BITS3(0,0,1))) {
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+ if (ty <= X01
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+ && ( ((op == BITS3(0,0,0) || op == BITS3(0,0,1)) && True)
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+ || ((op == BITS3(1,0,0) || op == BITS3(1,0,1)) && rm == BITS2(0,0))
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+ )
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+ ) {
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Bool isI64 = bitSF == 1;
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Bool isF64 = (ty & 1) == 1;
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Bool isU = (op & 1) == 1;
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/* Decide on the IR rounding mode to use. */
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IRRoundingMode irrm = 8; /*impossible*/
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HChar ch = '?';
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- switch (rm) {
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- case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break;
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- case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break;
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- case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break;
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- case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break;
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- default: vassert(0);
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+ if (op == BITS3(0,0,0) || op == BITS3(0,0,1)) {
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+ switch (rm) {
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+ case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break;
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+ case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break;
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+ case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break;
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+ case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break;
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+ default: vassert(0);
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+ }
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+ } else {
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+ vassert(op == BITS3(1,0,0) || op == BITS3(1,0,1));
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+ switch (rm) {
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+ case BITS2(0,0): ch = 'a'; irrm = Irrm_NEAREST; break;
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+ default: vassert(0);
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+ }
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}
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vassert(irrm != 8);
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/* Decide on the conversion primop, based on the source size,
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@@ -12254,9 +12270,11 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn)
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(iop == Iop_F32toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Sn */
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|| (iop == Iop_F32toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Sn */
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|| (iop == Iop_F32toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Sn */
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+ || (iop == Iop_F32toI32S && irrm == Irrm_NEAREST)/* FCVT{A,N}S W,S */
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/* F32toI32U */
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|| (iop == Iop_F32toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Sn */
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|| (iop == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */
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+ || (iop == Iop_F32toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,S */
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/* F32toI64S */
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|| (iop == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */
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/* F32toI64U */
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commit 9f69352a36003c35cfe8ffe01ba8ef0f830b4198
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Author: mjw <mjw@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Date: Tue Nov 4 15:30:42 2014 +0000
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Bug 340632 arm64: unhandled instruction fcvtas
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git-svn-id: svn://svn.valgrind.org/vex/trunk@2987 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index 4229d6a..1426d00 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -12304,6 +12304,7 @@ Bool dis_AdvSIMD_fp_to_from_int_conv(/*MB_OUT*/DisResult* dres, UInt insn)
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|| (iop == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */
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|| (iop == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */
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|| (iop == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */
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+ || (iop == Iop_F64toI64S && irrm == Irrm_NEAREST) /* FCVT{A,N}S Xd,Dn */
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/* F64toI64U */
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|| (iop == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */
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|| (iop == Iop_F64toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Dn */
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