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From cd0d8ef86151d72a246d565844d4c0470feb6b20 Mon Sep 17 00:00:00 2001
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From: Ruediger Meier <ruediger.meier@ga-group.nl>
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Date: Wed, 16 Mar 2016 13:18:18 +0100
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Subject: [PATCH 68/84] lscpu: use cpu and revision tag if available
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Avoid ifdef which does not work with --sysroot. Our existing test
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dumps produce even better output now for ppc and sparc.
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The logic moved to the printing section.
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Upstream: http://github.com/karelzak/util-linux/commit/641350fe822e7f1ac10873dad9a364bdeaba8083
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Upstream: http://github.com/karelzak/util-linux/commit/86c4817e0ea02656ddb62fe27757a9fd4f13b2d3
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Upstream: http://github.com/karelzak/util-linux/commit/c95e3889725389e9d7e24d29c2a71b015959575f
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Addresses: http://bugzilla.redhat.com/show_bug.cgi?id=1326615
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CC: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Signed-off-by: Ruediger Meier <ruediger.meier@ga-group.nl>
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Signed-off-by: Karel Zak <kzak@redhat.com>
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---
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sys-utils/lscpu.c | 17 ++++++++---------
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tests/expected/lscpu/lscpu-ppc64-POWER7 | 3 ++-
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tests/expected/lscpu/lscpu-ppc64-POWER7-64cpu | 3 ++-
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3 files changed, 12 insertions(+), 11 deletions(-)
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diff --git a/sys-utils/lscpu.c b/sys-utils/lscpu.c
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index 68b15af..7a00636 100644
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--- a/sys-utils/lscpu.c
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+++ b/sys-utils/lscpu.c
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@@ -141,6 +141,8 @@ struct lscpu_desc {
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char *family;
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char *model;
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char *modelname;
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+ char *revision; /* alternative for model (ppc) */
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+ char *cpu; /* alternative for modelname (ppc, sparc) */
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char *virtflag; /* virtualization flag (vmx, svm) */
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char *hypervisor; /* hypervisor software */
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int hyper; /* hypervisor vendor ID */
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@@ -355,13 +357,8 @@ read_basicinfo(struct lscpu_desc *desc, struct lscpu_modifier *mod)
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else if (lookup(buf, "vendor_id", &desc->vendor)) ;
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else if (lookup(buf, "family", &desc->family)) ;
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else if (lookup(buf, "cpu family", &desc->family)) ;
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-#if defined(__powerpc__) || defined(__powerpc64__)
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- else if (lookup(buf, "revision", &desc->model)) ;
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- else if (lookup(buf, "cpu", &desc->modelname)) ;
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-#else
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else if (lookup(buf, "model", &desc->model)) ;
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else if (lookup(buf, "model name", &desc->modelname)) ;
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-#endif
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else if (lookup(buf, "stepping", &desc->stepping)) ;
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else if (lookup(buf, "cpu MHz", &desc->mhz)) ;
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else if (lookup(buf, "flags", &desc->flags)) ; /* x86 */
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@@ -369,6 +366,8 @@ read_basicinfo(struct lscpu_desc *desc, struct lscpu_modifier *mod)
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else if (lookup(buf, "type", &desc->flags)) ; /* sparc64 */
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else if (lookup(buf, "bogomips", &desc->bogomips)) ;
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else if (lookup(buf, "bogomips per cpu", &desc->bogomips)) ; /* s390 */
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+ else if (lookup(buf, "cpu", &desc->cpu)) ;
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+ else if (lookup(buf, "revision", &desc->revision)) ;
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else
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continue;
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}
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@@ -1264,10 +1263,10 @@ print_summary(struct lscpu_desc *desc, struct lscpu_modifier *mod)
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print_s(_("Vendor ID:"), desc->vendor);
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if (desc->family)
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print_s(_("CPU family:"), desc->family);
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- if (desc->model)
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- print_s(_("Model:"), desc->model);
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- if (desc->modelname)
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- print_s(_("Model name:"), desc->modelname);
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+ if (desc->model || desc->revision)
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+ print_s(_("Model:"), desc->revision ? desc->revision : desc->model);
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+ if (desc->modelname || desc->cpu)
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+ print_s(_("Model name:"), desc->cpu ? desc->cpu : desc->modelname);
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if (desc->stepping)
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print_s(_("Stepping:"), desc->stepping);
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if (desc->mhz)
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diff --git a/tests/expected/lscpu/lscpu-ppc64-POWER7 b/tests/expected/lscpu/lscpu-ppc64-POWER7
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index 0d6c5ba..9a3c0c9 100644
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--- a/tests/expected/lscpu/lscpu-ppc64-POWER7
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+++ b/tests/expected/lscpu/lscpu-ppc64-POWER7
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@@ -4,7 +4,8 @@ Thread(s) per core: 4
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Core(s) per socket: 1
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Socket(s): 4
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NUMA node(s): 1
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-Model: IBM,8233-E8B
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+Model: 2.1 (pvr 003f 0201)
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+Model name: POWER7 (architected), altivec supported
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L1d cache: 32K
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L1i cache: 32K
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NUMA node0 CPU(s): 0-15
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diff --git a/tests/expected/lscpu/lscpu-ppc64-POWER7-64cpu b/tests/expected/lscpu/lscpu-ppc64-POWER7-64cpu
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index 40e2736..d4ae6c1 100644
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--- a/tests/expected/lscpu/lscpu-ppc64-POWER7-64cpu
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+++ b/tests/expected/lscpu/lscpu-ppc64-POWER7-64cpu
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@@ -4,7 +4,8 @@ Thread(s) per core: 4
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Core(s) per socket: 1
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Socket(s): 16
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NUMA node(s): 2
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-Model: IBM,8231-E2B
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+Model: 2.1 (pvr 003f 0201)
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+Model name: POWER7 (architected), altivec supported
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L1d cache: 32K
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L1i cache: 32K
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NUMA node0 CPU(s): 0-63
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--
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2.7.4
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