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From 64181e8938e1ebb31375bfb5372190a2f3f1ad60 Mon Sep 17 00:00:00 2001
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From: Marcel Apfelbaum <marcel@redhat.com>
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Date: Thu, 31 Mar 2016 16:19:03 +0200
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Subject: [PATCH] fw/pci: add Q35 S3 support
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RH-Author: Marcel Apfelbaum <marcel@redhat.com>
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Message-id: <1459441143-24378-1-git-send-email-marcel@redhat.com>
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Patchwork-id: 69965
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O-Subject: [RHEL-7.3 seabios PATCH] fw/pci: add Q35 S3 support
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Bugzilla: 1185721
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Acked-by: Gerd Hoffmann <kraxel@redhat.com>
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Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs
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between OS sleeps and use them to re-configure the
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corresponding registers.
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Tested-by: Gal Hammer <ghammer@redhat.com>
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Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
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(cherry picked from commit dce99e01b6bfc51175bdf32612fd4f2738e5c3c8)
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Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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src/fw/pciinit.c | 73 +++++++++++++++++++++++++++++++++++++++++++-------------
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1 file changed, 56 insertions(+), 17 deletions(-)
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diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
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index c31c2fa..7896600 100644
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--- a/src/fw/pciinit.c
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+++ b/src/fw/pciinit.c
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@@ -149,6 +149,22 @@ static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
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dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
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}
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+static void mch_isa_lpc_setup(u16 bdf)
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+{
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+ /* pm io base */
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+ pci_config_writel(bdf, ICH9_LPC_PMBASE,
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+ acpi_pm_base | ICH9_LPC_PMBASE_RTE);
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+
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+ /* acpi enable, SCI: IRQ9 000b = irq9*/
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+ pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
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+
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+ /* set root complex register block BAR */
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+ pci_config_writel(bdf, ICH9_LPC_RCBA,
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+ ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
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+}
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+
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+static int ICH9LpcBDF = -1;
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+
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/* ICH9 LPC PCI to ISA bridge */
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/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
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static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
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@@ -176,16 +192,10 @@ static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
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outb(elcr[1], ICH9_LPC_PORT_ELCR2);
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dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
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- /* pm io base */
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- pci_config_writel(bdf, ICH9_LPC_PMBASE,
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- acpi_pm_base | ICH9_LPC_PMBASE_RTE);
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+ ICH9LpcBDF = bdf;
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- /* acpi enable, SCI: IRQ9 000b = irq9*/
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- pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
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+ mch_isa_lpc_setup(bdf);
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- /* set root complex register block BAR */
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- pci_config_writel(bdf, ICH9_LPC_RCBA,
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- ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
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e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
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acpi_pm1a_cnt = acpi_pm_base + 0x04;
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@@ -244,11 +254,8 @@ static void piix4_pm_setup(struct pci_device *pci, void *arg)
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pmtimer_setup(acpi_pm_base + 0x08);
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}
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-/* ICH9 SMBUS */
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-/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
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-static void ich9_smbus_setup(struct pci_device *dev, void *arg)
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+static void ich9_smbus_enable(u16 bdf)
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{
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- u16 bdf = dev->bdf;
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/* map smbus into io space */
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pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
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(acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
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@@ -257,6 +264,17 @@ static void ich9_smbus_setup(struct pci_device *dev, void *arg)
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pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
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}
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+static int ICH9SmbusBDF = -1;
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+
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+/* ICH9 SMBUS */
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+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
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+static void ich9_smbus_setup(struct pci_device *dev, void *arg)
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+{
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+ ICH9SmbusBDF = dev->bdf;
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+
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+ ich9_smbus_enable(dev->bdf);
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+}
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+
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static const struct pci_device_id pci_device_tbl[] = {
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/* PIIX3/PIIX4 PCI to ISA bridge */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
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@@ -293,6 +311,9 @@ static const struct pci_device_id pci_device_tbl[] = {
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PCI_DEVICE_END,
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};
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+static int MCHMmcfgBDF = -1;
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+static void mch_mmconfig_setup(u16 bdf);
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+
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void pci_resume(void)
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{
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if (!CONFIG_QEMU) {
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@@ -302,6 +323,18 @@ void pci_resume(void)
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if (PiixPmBDF >= 0) {
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piix4_pm_config_setup(PiixPmBDF);
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}
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+
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+ if (ICH9LpcBDF >= 0) {
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+ mch_isa_lpc_setup(ICH9LpcBDF);
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+ }
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+
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+ if (ICH9SmbusBDF >= 0) {
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+ ich9_smbus_enable(ICH9SmbusBDF);
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+ }
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+
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+ if(MCHMmcfgBDF >= 0) {
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+ mch_mmconfig_setup(MCHMmcfgBDF);
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+ }
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}
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static void pci_bios_init_device(struct pci_device *pci)
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@@ -388,18 +421,24 @@ static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
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pci_slot_get_irq = piix_pci_slot_get_irq;
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}
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-static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
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+static void mch_mmconfig_setup(u16 bdf)
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{
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u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
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- u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
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-
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- /* setup mmconfig */
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- u16 bdf = dev->bdf;
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u32 upper = addr >> 32;
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u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
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pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
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pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
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pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
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+}
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+
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+static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
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+{
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+ u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
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+ u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
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+
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+ /* setup mmconfig */
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+ MCHMmcfgBDF = dev->bdf;
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+ mch_mmconfig_setup(dev->bdf);
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e820_add(addr, size, E820_RESERVED);
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/* setup pci i/o window (above mmconfig) */
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--
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1.8.3.1
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