From 2e11a1b041c82158b65dd6f9ca7f64040a32c482 Mon Sep 17 00:00:00 2001 From: CentOS Sources Date: Aug 01 2017 03:38:52 +0000 Subject: import rasdaemon-0.4.1-28.el7 --- diff --git a/SOURCES/0063-add_support_for_knights_mill.patch b/SOURCES/0063-add_support_for_knights_mill.patch new file mode 100644 index 0000000..5362ea0 --- /dev/null +++ b/SOURCES/0063-add_support_for_knights_mill.patch @@ -0,0 +1,63 @@ +--- + mce-intel.c | 3 +++ + ras-mce-handler.c | 5 +++++ + ras-mce-handler.h | 1 + + 3 files changed, 9 insertions(+) + +--- rasdaemon-0.4.1.orig/mce-intel.c 2017-05-30 12:04:54.440167730 -0400 ++++ rasdaemon-0.4.1/mce-intel.c 2017-05-30 12:06:51.705755469 -0400 +@@ -399,6 +399,7 @@ if (test_prefix(11, (e->status & 0xffffL + hsw_decode_model(ras, e); + break; + case CPU_KNIGHTS_LANDING: ++ case CPU_KNIGHTS_MILL: + knl_decode_model(ras, e); + break; + case CPU_BROADWELL_DE: +@@ -470,6 +471,8 @@ int set_intel_imc_log(enum cputype cputy + case CPU_SANDY_BRIDGE_EP: + case CPU_IVY_BRIDGE_EPEX: + case CPU_HASWELL_EPEX: ++ case CPU_KNIGHTS_LANDING: ++ case CPU_KNIGHTS_MILL: + msr = 0x17f; /* MSR_ERROR_CONTROL */ + bit = 0x2; /* MemError Log Enable */ + break; +--- rasdaemon-0.4.1.orig/ras-mce-handler.c 2017-05-30 12:04:54.440167730 -0400 ++++ rasdaemon-0.4.1/ras-mce-handler.c 2017-05-30 12:07:59.850934779 -0400 +@@ -53,6 +53,7 @@ [CPU_XEON75XX] = "Intel Xeon 7500 series + [CPU_BROADWELL_DE] = "Broadwell DE", + [CPU_BROADWELL_EPEX] = "Broadwell EP/EX", + [CPU_KNIGHTS_LANDING] = "Knights Landing", ++ [CPU_KNIGHTS_MILL] = "Knights Mill", + }; + + static enum cputype select_intel_cputype(struct ras_events *ras) +@@ -100,6 +101,8 @@ else if (mce->model == 0x3d) + return CPU_BROADWELL; + else if (mce->model == 0x57) + return CPU_KNIGHTS_LANDING; ++ else if (mce->model == 0x85) ++ return CPU_KNIGHTS_MILL; + + if (mce->model > 0x1a) { + log(ALL, LOG_INFO, +@@ -228,6 +231,8 @@ int register_mce_handler(struct ras_even + case CPU_SANDY_BRIDGE_EP: + case CPU_IVY_BRIDGE_EPEX: + case CPU_HASWELL_EPEX: ++ case CPU_KNIGHTS_LANDING: ++ case CPU_KNIGHTS_MILL: + set_intel_imc_log(mce->cputype, ncpus); + default: + break; +--- rasdaemon-0.4.1.orig/ras-mce-handler.h 2017-05-30 12:04:54.440167730 -0400 ++++ rasdaemon-0.4.1/ras-mce-handler.h 2017-05-30 12:04:58.976113103 -0400 +@@ -48,6 +48,7 @@ enum cputype { + CPU_BROADWELL_DE, + CPU_BROADWELL_EPEX, + CPU_KNIGHTS_LANDING, ++ CPU_KNIGHTS_MILL, + }; + + struct mce_event { diff --git a/SOURCES/0064-add_support_for_skylake.patch b/SOURCES/0064-add_support_for_skylake.patch new file mode 100644 index 0000000..d6666c9 --- /dev/null +++ b/SOURCES/0064-add_support_for_skylake.patch @@ -0,0 +1,344 @@ +commit f9a5724021d8bc9f38cee3a0a71eb4032da1ec66 +Author: Aristeu Rozanski +Date: Mon Sep 19 15:28:33 2016 -0400 + + rasdaemon: add support for Skylake client and server + + Base on upstream mcelog commits + 6c07f906dadfe2c4bb7a21e5fc60dc2f34056bf0 + e4aca6312aee03066ab45632a7bee23dc892a425 + + Signed-off-by: Aristeu Rozanski + +--- + Makefile.am | 2 + mce-intel-skx.c | 257 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ + mce-intel.c | 3 + ras-mce-handler.c | 6 + + ras-mce-handler.h | 3 + 5 files changed, 270 insertions(+), 1 deletion(-) + +--- rasdaemon-0.4.1.orig/Makefile.am 2017-05-30 12:43:11.975591485 -0400 ++++ rasdaemon-0.4.1/Makefile.am 2017-05-30 12:43:16.948531592 -0400 +@@ -30,7 +30,7 @@ if WITH_MCE + mce-intel-dunnington.c mce-intel-tulsa.c \ + mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c \ + mce-intel-knl.c mce-intel-broadwell-de.c \ +- mce-intel-broadwell-epex.c ++ mce-intel-broadwell-epex.c mce-intel-skx.c + endif + if WITH_EXTLOG + rasdaemon_SOURCES += ras-extlog-handler.c +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ rasdaemon-0.4.1/mce-intel-skx.c 2017-05-30 12:43:16.948531592 -0400 +@@ -0,0 +1,257 @@ ++/* ++ * The code below came from Tony Luck mcelog code, ++ * released under GNU Public General License, v.2 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA ++*/ ++ ++#include ++#include ++ ++#include "ras-mce-handler.h" ++#include "bitfield.h" ++ ++ ++/* See IA32 SDM Vol3B Table 16-27 */ ++ ++static char *pcu_1[] = { ++ [0x00] = "No Error", ++ [0x0d] = "MCA_DMI_TRAINING_TIMEOUT", ++ [0x0f] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT", ++ [0x10] = "MCA_MORE_THAN_ONE_LT_AGENT", ++ [0x1e] = "MCA_BIOS_RST_CPL_INVALID_SEQ", ++ [0x1f] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG", ++ [0x25] = "MCA_MESSAGE_CHANNEL_TIMEOUT", ++ [0x27] = "MCA_MSGCH_PMREQ_CMP_TIMEOUT", ++ [0x30] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT", ++ [0x31] = "MCA_PKGC_INVALID_RSP_PCH", ++ [0x33] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN", ++ [0x34] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP", ++ [0x38] = "MCA_PKGC_WATCHDOG_HANG_C3_UP_SF", ++ [0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE", ++ [0x41] = "MCA_SVID_COMMAND_TIMEOUT", ++ [0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE", ++ [0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR", ++ [0x44] = "MCA_SVID_CRITICAL_VR_FAILED", ++ [0x45] = "MCA_SVID_SA_ITD_ERROR", ++ [0x46] = "MCA_SVID_READ_REG_FAILED", ++ [0x47] = "MCA_SVID_WRITE_REG_FAILED", ++ [0x48] = "MCA_SVID_PKGC_INIT_FAILED", ++ [0x49] = "MCA_SVID_PKGC_CONFIG_FAILED", ++ [0x4a] = "MCA_SVID_PKGC_REQUEST_FAILED", ++ [0x4b] = "MCA_SVID_IMON_REQUEST_FAILED", ++ [0x4c] = "MCA_SVID_ALERT_REQUEST_FAILED", ++ [0x4d] = "MCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERROR", ++ [0x4e] = "MCA_SVID_UNEXPECTED_MCP_VR_DETECTED", ++ [0x51] = "MCA_FIVR_CATAS_OVERVOL_FAULT", ++ [0x52] = "MCA_FIVR_CATAS_OVERCUR_FAULT", ++ [0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SLAVE", ++ [0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MASTER", ++ [0x5a] = "MCA_WATCHDOG_TIMEOUT_PKGS_MASTER", ++ [0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT", ++ [0x63] = "MCA_PKGS_INVALID_REQ_PCH", ++ [0x64] = "MCA_PKGS_INVALID_REQ_INTERNAL", ++ [0x65] = "MCA_PKGS_INVALID_RSP_INTERNAL", ++ [0x6b] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT", ++ [0x81] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT", ++}; ++ ++static struct field pcu_mc4[] = { ++ FIELD(24, pcu_1), ++ {} ++}; ++ ++/* See IA32 SDM Vol3B Table 16-28 */ ++ ++static char *qpi[] = { ++ [0x00] = "UC Phy Initialization Failure", ++ [0x01] = "UC Phy detected drift buffer alarm", ++ [0x02] = "UC Phy detected latency buffer rollover", ++ [0x10] = "UC LL Rx detected CRC error: unsuccessful LLR: entered abort state", ++ [0x11] = "UC LL Rx unsupported or undefined packet", ++ [0x12] = "UC LL or Phy control error", ++ [0x13] = "UC LL Rx parameter exchange exception", ++ [0x1F] = "UC LL detected control error from the link-mesh interface", ++ [0x20] = "COR Phy initialization abort", ++ [0x21] = "COR Phy reset", ++ [0x22] = "COR Phy lane failure, recovery in x8 width", ++ [0x23] = "COR Phy L0c error corrected without Phy reset", ++ [0x24] = "COR Phy L0c error triggering Phy Reset", ++ [0x25] = "COR Phy L0p exit error corrected with Phy reset", ++ [0x30] = "COR LL Rx detected CRC error - successful LLR without Phy Reinit", ++ [0x31] = "COR LL Rx detected CRC error - successful LLR with Phy Reinit", ++}; ++ ++static struct field qpi_mc[] = { ++ FIELD(16, qpi), ++ {} ++}; ++ ++/* These apply to MSCOD 0x12 "UC LL or Phy control error" */ ++static struct field qpi_0x12[] = { ++ SBITFIELD(22, "Phy Control Error"), ++ SBITFIELD(23, "Unexpected Retry.Ack flit"), ++ SBITFIELD(24, "Unexpected Retry.Req flit"), ++ SBITFIELD(25, "RF parity error"), ++ SBITFIELD(26, "Routeback Table error"), ++ SBITFIELD(27, "unexpected Tx Protocol flit (EOP, Header or Data)"), ++ SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"), ++ SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"), ++ SBITFIELD(30, "Link Layer reset initiated while protocol traffic not idle"), ++ SBITFIELD(31, "Link Layer Tx Parity Error"), ++ {} ++}; ++ ++/* See IA32 SDM Vol3B Table 16-29 */ ++ ++static struct field mc_bits[] = { ++ SBITFIELD(16, "Address parity error"), ++ SBITFIELD(17, "HA write data parity error"), ++ SBITFIELD(18, "HA write byte enable parity error"), ++ SBITFIELD(19, "Corrected patrol scrub error"), ++ SBITFIELD(20, "Uncorrected patrol scrub error"), ++ SBITFIELD(21, "Corrected spare error"), ++ SBITFIELD(22, "Uncorrected spare error"), ++ SBITFIELD(23, "Any HA read error"), ++ SBITFIELD(24, "WDB read parity error"), ++ SBITFIELD(25, "DDR4 command address parity error"), ++ SBITFIELD(26, "Uncorrected address parity error"), ++ {} ++}; ++ ++static char *mc_0x8xx[] = { ++ [0x0] = "Unrecognized request type", ++ [0x1] = "Read response to an invalid scoreboard entry", ++ [0x2] = "Unexpected read response", ++ [0x3] = "DDR4 completion to an invalid scoreboard entry", ++ [0x4] = "Completion to an invalid scoreboard entry", ++ [0x5] = "Completion FIFO overflow", ++ [0x6] = "Correctable parity error", ++ [0x7] = "Uncorrectable error", ++ [0x8] = "Interrupt received while outstanding interrupt was not ACKed", ++ [0x9] = "ERID FIFO overflow", ++ [0xa] = "Error on Write credits", ++ [0xb] = "Error on Read credits", ++ [0xc] = "Scheduler error", ++ [0xd] = "Error event", ++}; ++ ++static struct field memctrl_mc13[] = { ++ FIELD(16, mc_0x8xx), ++ {} ++}; ++ ++/* See IA32 SDM Vol3B Table 16-30 */ ++ ++static struct field m2m[] = { ++ SBITFIELD(16, "MscodDataRdErr"), ++ SBITFIELD(17, "Reserved"), ++ SBITFIELD(18, "MscodPtlWrErr"), ++ SBITFIELD(19, "MscodFullWrErr"), ++ SBITFIELD(20, "MscodBgfErr"), ++ SBITFIELD(21, "MscodTimeout"), ++ SBITFIELD(22, "MscodParErr"), ++ SBITFIELD(23, "MscodBucket1Err"), ++ {} ++}; ++ ++void skylake_xeon_decode_model(struct ras_events *ras, struct mce_event *e) ++{ ++ uint64_t status = e->status; ++ uint32_t mca = status & 0xffff; ++ unsigned rank0 = -1, rank1 = -1, chan; ++ ++ switch (e->bank) { ++ case 4: ++ switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) { ++ case 0x402: case 0x403: ++ mce_snprintf(e->mcastatus_msg, "Internal errors "); ++ break; ++ case 0x406: ++ mce_snprintf(e->mcastatus_msg, "Intel TXT errors "); ++ break; ++ case 0x407: ++ mce_snprintf(e->mcastatus_msg, "Other UBOX Internal errors "); ++ break; ++ } ++ if (EXTRACT(status, 16, 19)) ++ mce_snprintf(e->mcastatus_msg, "PCU internal error "); ++ decode_bitfield(e, status, pcu_mc4); ++ break; ++ case 5: ++ case 12: ++ case 19: ++ mce_snprintf(e->mcastatus_msg, "QPI: "); ++ decode_bitfield(e, status, qpi_mc); ++ if ((EXTRACT(status, 16, 21) == 0x12)) ++ decode_bitfield(e, status, qpi_0x12); ++ break; ++ case 7: ++ case 8: ++ mce_snprintf(e->mcastatus_msg, "M2M: "); ++ decode_bitfield(e, status, m2m); ++ break; ++ case 13: ++ case 14: ++ case 15: ++ case 16: ++ mce_snprintf(e->mcastatus_msg, "MemCtrl: "); ++ if (EXTRACT(status, 27, 27)) ++ decode_bitfield(e, status, memctrl_mc13); ++ else ++ decode_bitfield(e, status, mc_bits); ++ break; ++ } ++ ++ /* ++ * Memory error specific code. Returns if the error is not a MC one ++ */ ++ ++ /* Check if the error is at the memory controller */ ++ if ((mca >> 7) != 1) ++ return; ++ ++ /* Ignore unless this is an corrected extended error from an iMC bank */ ++ if (e->bank < 9 || e->bank > 16 || (status & MCI_STATUS_UC) || ++ !test_prefix(7, status & 0xefff)) ++ return; ++ ++ /* ++ * Parse the reported channel and ranks ++ */ ++ ++ chan = EXTRACT(status, 0, 3); ++ if (chan == 0xf) ++ return; ++ ++ mce_snprintf(e->mc_location, "memory_channel=%d", chan); ++ ++ if (EXTRACT(e->misc, 62, 62)) { ++ rank0 = EXTRACT(e->misc, 46, 50); ++ if (EXTRACT(e->misc, 63, 63)) ++ rank1 = EXTRACT(e->misc, 51, 55); ++ } ++ ++ /* ++ * FIXME: The conversion from rank to dimm requires to parse the ++ * DMI tables and call failrank2dimm(). ++ */ ++ if (rank0 != -1 && rank1 != -1) ++ mce_snprintf(e->mc_location, "ranks=%d and %d", ++ rank0, rank1); ++ else if (rank0 != -1) ++ mce_snprintf(e->mc_location, "rank=%d", rank0); ++} ++ +--- rasdaemon-0.4.1.orig/mce-intel.c 2017-05-30 12:43:11.975591485 -0400 ++++ rasdaemon-0.4.1/mce-intel.c 2017-05-30 12:43:16.948531592 -0400 +@@ -408,6 +408,9 @@ if (test_prefix(11, (e->status & 0xffffL + case CPU_BROADWELL_EPEX: + broadwell_epex_decode_model(ras, e); + break; ++ case CPU_SKYLAKE_XEON: ++ skylake_xeon_decode_model(ras, e); ++ break; + default: + break; + } +--- rasdaemon-0.4.1.orig/ras-mce-handler.c 2017-05-30 12:43:16.948531592 -0400 ++++ rasdaemon-0.4.1/ras-mce-handler.c 2017-05-30 12:44:00.295009527 -0400 +@@ -54,6 +54,8 @@ [CPU_XEON75XX] = "Intel Xeon 7500 series + [CPU_BROADWELL_EPEX] = "Broadwell EP/EX", + [CPU_KNIGHTS_LANDING] = "Knights Landing", + [CPU_KNIGHTS_MILL] = "Knights Mill", ++ [CPU_SKYLAKE] = "Skylake", ++ [CPU_SKYLAKE_XEON] = "Skylake Xeon", + }; + + static enum cputype select_intel_cputype(struct ras_events *ras) +@@ -103,6 +105,10 @@ else if (mce->model == 0x57) + return CPU_KNIGHTS_LANDING; + else if (mce->model == 0x85) + return CPU_KNIGHTS_MILL; ++ else if (mce->model == 0x4e || mce->model == 0x5e) ++ return CPU_SKYLAKE; ++ else if (mce->model == 0x55) ++ return CPU_SKYLAKE_XEON; + + if (mce->model > 0x1a) { + log(ALL, LOG_INFO, +--- rasdaemon-0.4.1.orig/ras-mce-handler.h 2017-05-30 12:43:11.976591473 -0400 ++++ rasdaemon-0.4.1/ras-mce-handler.h 2017-05-30 12:44:25.745703000 -0400 +@@ -49,6 +49,8 @@ enum cputype { + CPU_BROADWELL_EPEX, + CPU_KNIGHTS_LANDING, + CPU_KNIGHTS_MILL, ++ CPU_SKYLAKE, ++ CPU_SKYLAKE_XEON, + }; + + struct mce_event { +@@ -126,6 +128,7 @@ void knl_decode_model(struct ras_events + void tulsa_decode_model(struct mce_event *e); + void broadwell_de_decode_model(struct ras_events *ras, struct mce_event *e); + void broadwell_epex_decode_model(struct ras_events *ras, struct mce_event *e); ++void skylake_xeon_decode_model(struct ras_events *ras, struct mce_event *e); + + /* Software defined banks */ + #define MCE_EXTENDED_BANK 128 diff --git a/SPECS/rasdaemon.spec b/SPECS/rasdaemon.spec index c64fc6b..19b23cc 100644 --- a/SPECS/rasdaemon.spec +++ b/SPECS/rasdaemon.spec @@ -2,7 +2,7 @@ Name: rasdaemon Version: 0.4.1 -Release: 24%{?dist} +Release: 28%{?dist} Summary: Utility to receive RAS error tracings Group: Applications/System License: GPLv2 @@ -77,6 +77,8 @@ Patch51: 0061-Add-Broadwell-DE-MSCOD-values.patch Patch52: 0062-Add-Broadwell-EP-EX-MSCOD-values.patch # Patch53 was submitted upstream but not merged yet Patch53: rasdaemon-dont_use_memerror_log_enable_on_knl.patch +Patch54: 0063-add_support_for_knights_mill.patch +Patch55: 0064-add_support_for_skylake.patch %description %{name} is a RAS (Reliability, Availability and Serviceability) logging tool. @@ -143,6 +145,8 @@ an utility for reporting current error counts from the EDAC sysfs files. %patch51 -p1 %patch52 -p1 %patch53 -p1 +%patch54 -p1 +%patch55 -p1 %build autoreconf -vfi @@ -170,6 +174,21 @@ rm -rf %{buildroot} %{_sysconfdir}/ras/dimm_labels.d %changelog +* Tue May 30 2017 Aristeu Rozanski 0.4.1-28.el7 +- Bump release [1448113] + +* Tue May 30 2017 Aristeu Rozanski 0.4.1-28.el7 +- Identify as Knights Mill systems as such [1448113] + +* Mon May 8 2017 Aristeu Rozanski 0.4.1-27.el7 +- Fixed error found by covscan in the last patch [1377467] + +* Tue Apr 11 2017 Aristeu Rozanski 0.4.1-26.el7 +- add support for Skylake client and server [1377467] + +* Wed Mar 22 2017 Aristeu Rozanski 0.4.1-25.el7 +- add support for Knights Mill [1433862] + * Wed Aug 24 2016 Aristeu Rozanski 0.4.1-24.el7 - don't use MemError Log Enable on Knights Landing [1273326]