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commit f9a5724021d8bc9f38cee3a0a71eb4032da1ec66
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Author: Aristeu Rozanski <arozansk@redhat.com>
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Date: Mon Sep 19 15:28:33 2016 -0400
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rasdaemon: add support for Skylake client and server
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Base on upstream mcelog commits
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6c07f906dadfe2c4bb7a21e5fc60dc2f34056bf0
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e4aca6312aee03066ab45632a7bee23dc892a425
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Signed-off-by: Aristeu Rozanski <arozansk@redhat.com>
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---
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Makefile.am | 2
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mce-intel-skx.c | 257 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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mce-intel.c | 3
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ras-mce-handler.c | 6 +
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ras-mce-handler.h | 3
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5 files changed, 270 insertions(+), 1 deletion(-)
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--- rasdaemon-0.4.1.orig/Makefile.am 2017-05-30 12:43:11.975591485 -0400
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+++ rasdaemon-0.4.1/Makefile.am 2017-05-30 12:43:16.948531592 -0400
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@@ -30,7 +30,7 @@ if WITH_MCE
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mce-intel-dunnington.c mce-intel-tulsa.c \
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mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c \
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mce-intel-knl.c mce-intel-broadwell-de.c \
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- mce-intel-broadwell-epex.c
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+ mce-intel-broadwell-epex.c mce-intel-skx.c
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endif
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if WITH_EXTLOG
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rasdaemon_SOURCES += ras-extlog-handler.c
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ rasdaemon-0.4.1/mce-intel-skx.c 2017-05-30 12:43:16.948531592 -0400
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@@ -0,0 +1,257 @@
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+/*
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+ * The code below came from Tony Luck mcelog code,
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+ * released under GNU Public General License, v.2
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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+*/
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+
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+#include <string.h>
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+#include <stdio.h>
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+
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+#include "ras-mce-handler.h"
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+#include "bitfield.h"
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+
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+
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+/* See IA32 SDM Vol3B Table 16-27 */
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+
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+static char *pcu_1[] = {
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+ [0x00] = "No Error",
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+ [0x0d] = "MCA_DMI_TRAINING_TIMEOUT",
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+ [0x0f] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT",
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+ [0x10] = "MCA_MORE_THAN_ONE_LT_AGENT",
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+ [0x1e] = "MCA_BIOS_RST_CPL_INVALID_SEQ",
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+ [0x1f] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG",
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+ [0x25] = "MCA_MESSAGE_CHANNEL_TIMEOUT",
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+ [0x27] = "MCA_MSGCH_PMREQ_CMP_TIMEOUT",
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+ [0x30] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT",
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+ [0x31] = "MCA_PKGC_INVALID_RSP_PCH",
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+ [0x33] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN",
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+ [0x34] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP",
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+ [0x38] = "MCA_PKGC_WATCHDOG_HANG_C3_UP_SF",
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+ [0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE",
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+ [0x41] = "MCA_SVID_COMMAND_TIMEOUT",
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+ [0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE",
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+ [0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR",
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+ [0x44] = "MCA_SVID_CRITICAL_VR_FAILED",
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+ [0x45] = "MCA_SVID_SA_ITD_ERROR",
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+ [0x46] = "MCA_SVID_READ_REG_FAILED",
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+ [0x47] = "MCA_SVID_WRITE_REG_FAILED",
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+ [0x48] = "MCA_SVID_PKGC_INIT_FAILED",
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+ [0x49] = "MCA_SVID_PKGC_CONFIG_FAILED",
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+ [0x4a] = "MCA_SVID_PKGC_REQUEST_FAILED",
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+ [0x4b] = "MCA_SVID_IMON_REQUEST_FAILED",
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+ [0x4c] = "MCA_SVID_ALERT_REQUEST_FAILED",
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+ [0x4d] = "MCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERROR",
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+ [0x4e] = "MCA_SVID_UNEXPECTED_MCP_VR_DETECTED",
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+ [0x51] = "MCA_FIVR_CATAS_OVERVOL_FAULT",
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+ [0x52] = "MCA_FIVR_CATAS_OVERCUR_FAULT",
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+ [0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SLAVE",
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+ [0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MASTER",
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+ [0x5a] = "MCA_WATCHDOG_TIMEOUT_PKGS_MASTER",
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+ [0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT",
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+ [0x63] = "MCA_PKGS_INVALID_REQ_PCH",
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+ [0x64] = "MCA_PKGS_INVALID_REQ_INTERNAL",
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+ [0x65] = "MCA_PKGS_INVALID_RSP_INTERNAL",
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+ [0x6b] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT",
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+ [0x81] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT",
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+};
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+
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+static struct field pcu_mc4[] = {
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+ FIELD(24, pcu_1),
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+ {}
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+};
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+
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+/* See IA32 SDM Vol3B Table 16-28 */
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+
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+static char *qpi[] = {
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+ [0x00] = "UC Phy Initialization Failure",
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+ [0x01] = "UC Phy detected drift buffer alarm",
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+ [0x02] = "UC Phy detected latency buffer rollover",
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+ [0x10] = "UC LL Rx detected CRC error: unsuccessful LLR: entered abort state",
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+ [0x11] = "UC LL Rx unsupported or undefined packet",
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+ [0x12] = "UC LL or Phy control error",
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+ [0x13] = "UC LL Rx parameter exchange exception",
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+ [0x1F] = "UC LL detected control error from the link-mesh interface",
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+ [0x20] = "COR Phy initialization abort",
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+ [0x21] = "COR Phy reset",
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+ [0x22] = "COR Phy lane failure, recovery in x8 width",
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+ [0x23] = "COR Phy L0c error corrected without Phy reset",
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+ [0x24] = "COR Phy L0c error triggering Phy Reset",
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+ [0x25] = "COR Phy L0p exit error corrected with Phy reset",
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+ [0x30] = "COR LL Rx detected CRC error - successful LLR without Phy Reinit",
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+ [0x31] = "COR LL Rx detected CRC error - successful LLR with Phy Reinit",
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+};
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+
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+static struct field qpi_mc[] = {
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+ FIELD(16, qpi),
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+ {}
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+};
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+
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+/* These apply to MSCOD 0x12 "UC LL or Phy control error" */
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+static struct field qpi_0x12[] = {
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+ SBITFIELD(22, "Phy Control Error"),
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+ SBITFIELD(23, "Unexpected Retry.Ack flit"),
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+ SBITFIELD(24, "Unexpected Retry.Req flit"),
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+ SBITFIELD(25, "RF parity error"),
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+ SBITFIELD(26, "Routeback Table error"),
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+ SBITFIELD(27, "unexpected Tx Protocol flit (EOP, Header or Data)"),
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+ SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"),
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+ SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"),
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+ SBITFIELD(30, "Link Layer reset initiated while protocol traffic not idle"),
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+ SBITFIELD(31, "Link Layer Tx Parity Error"),
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+ {}
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+};
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+
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+/* See IA32 SDM Vol3B Table 16-29 */
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+
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+static struct field mc_bits[] = {
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+ SBITFIELD(16, "Address parity error"),
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+ SBITFIELD(17, "HA write data parity error"),
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+ SBITFIELD(18, "HA write byte enable parity error"),
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+ SBITFIELD(19, "Corrected patrol scrub error"),
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+ SBITFIELD(20, "Uncorrected patrol scrub error"),
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+ SBITFIELD(21, "Corrected spare error"),
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+ SBITFIELD(22, "Uncorrected spare error"),
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+ SBITFIELD(23, "Any HA read error"),
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+ SBITFIELD(24, "WDB read parity error"),
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+ SBITFIELD(25, "DDR4 command address parity error"),
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+ SBITFIELD(26, "Uncorrected address parity error"),
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+ {}
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+};
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+
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+static char *mc_0x8xx[] = {
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+ [0x0] = "Unrecognized request type",
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+ [0x1] = "Read response to an invalid scoreboard entry",
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+ [0x2] = "Unexpected read response",
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+ [0x3] = "DDR4 completion to an invalid scoreboard entry",
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+ [0x4] = "Completion to an invalid scoreboard entry",
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+ [0x5] = "Completion FIFO overflow",
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+ [0x6] = "Correctable parity error",
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+ [0x7] = "Uncorrectable error",
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+ [0x8] = "Interrupt received while outstanding interrupt was not ACKed",
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+ [0x9] = "ERID FIFO overflow",
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+ [0xa] = "Error on Write credits",
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+ [0xb] = "Error on Read credits",
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+ [0xc] = "Scheduler error",
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+ [0xd] = "Error event",
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+};
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+
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+static struct field memctrl_mc13[] = {
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+ FIELD(16, mc_0x8xx),
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+ {}
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+};
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+
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+/* See IA32 SDM Vol3B Table 16-30 */
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+
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+static struct field m2m[] = {
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+ SBITFIELD(16, "MscodDataRdErr"),
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+ SBITFIELD(17, "Reserved"),
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+ SBITFIELD(18, "MscodPtlWrErr"),
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+ SBITFIELD(19, "MscodFullWrErr"),
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+ SBITFIELD(20, "MscodBgfErr"),
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+ SBITFIELD(21, "MscodTimeout"),
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+ SBITFIELD(22, "MscodParErr"),
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+ SBITFIELD(23, "MscodBucket1Err"),
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+ {}
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+};
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+
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+void skylake_xeon_decode_model(struct ras_events *ras, struct mce_event *e)
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+{
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+ uint64_t status = e->status;
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+ uint32_t mca = status & 0xffff;
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+ unsigned rank0 = -1, rank1 = -1, chan;
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+
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+ switch (e->bank) {
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+ case 4:
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+ switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) {
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+ case 0x402: case 0x403:
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+ mce_snprintf(e->mcastatus_msg, "Internal errors ");
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+ break;
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+ case 0x406:
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+ mce_snprintf(e->mcastatus_msg, "Intel TXT errors ");
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+ break;
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+ case 0x407:
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+ mce_snprintf(e->mcastatus_msg, "Other UBOX Internal errors ");
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+ break;
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+ }
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+ if (EXTRACT(status, 16, 19))
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+ mce_snprintf(e->mcastatus_msg, "PCU internal error ");
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+ decode_bitfield(e, status, pcu_mc4);
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+ break;
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+ case 5:
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+ case 12:
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+ case 19:
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+ mce_snprintf(e->mcastatus_msg, "QPI: ");
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+ decode_bitfield(e, status, qpi_mc);
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+ if ((EXTRACT(status, 16, 21) == 0x12))
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+ decode_bitfield(e, status, qpi_0x12);
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+ break;
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+ case 7:
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+ case 8:
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+ mce_snprintf(e->mcastatus_msg, "M2M: ");
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+ decode_bitfield(e, status, m2m);
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+ break;
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+ case 13:
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+ case 14:
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+ case 15:
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+ case 16:
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+ mce_snprintf(e->mcastatus_msg, "MemCtrl: ");
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+ if (EXTRACT(status, 27, 27))
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+ decode_bitfield(e, status, memctrl_mc13);
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+ else
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+ decode_bitfield(e, status, mc_bits);
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+ break;
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+ }
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+
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+ /*
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+ * Memory error specific code. Returns if the error is not a MC one
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+ */
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+
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+ /* Check if the error is at the memory controller */
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+ if ((mca >> 7) != 1)
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+ return;
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+
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+ /* Ignore unless this is an corrected extended error from an iMC bank */
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+ if (e->bank < 9 || e->bank > 16 || (status & MCI_STATUS_UC) ||
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+ !test_prefix(7, status & 0xefff))
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+ return;
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+
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+ /*
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+ * Parse the reported channel and ranks
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+ */
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+
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+ chan = EXTRACT(status, 0, 3);
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+ if (chan == 0xf)
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+ return;
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+
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+ mce_snprintf(e->mc_location, "memory_channel=%d", chan);
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+
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+ if (EXTRACT(e->misc, 62, 62)) {
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ac32bf |
+ rank0 = EXTRACT(e->misc, 46, 50);
|
|
|
ac32bf |
+ if (EXTRACT(e->misc, 63, 63))
|
|
|
ac32bf |
+ rank1 = EXTRACT(e->misc, 51, 55);
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ /*
|
|
|
ac32bf |
+ * FIXME: The conversion from rank to dimm requires to parse the
|
|
|
ac32bf |
+ * DMI tables and call failrank2dimm().
|
|
|
ac32bf |
+ */
|
|
|
ac32bf |
+ if (rank0 != -1 && rank1 != -1)
|
|
|
ac32bf |
+ mce_snprintf(e->mc_location, "ranks=%d and %d",
|
|
|
ac32bf |
+ rank0, rank1);
|
|
|
ac32bf |
+ else if (rank0 != -1)
|
|
|
ac32bf |
+ mce_snprintf(e->mc_location, "rank=%d", rank0);
|
|
|
ac32bf |
+}
|
|
|
ac32bf |
+
|
|
|
ac32bf |
--- rasdaemon-0.4.1.orig/mce-intel.c 2017-05-30 12:43:11.975591485 -0400
|
|
|
ac32bf |
+++ rasdaemon-0.4.1/mce-intel.c 2017-05-30 12:43:16.948531592 -0400
|
|
|
ac32bf |
@@ -408,6 +408,9 @@ if (test_prefix(11, (e->status & 0xffffL
|
|
|
ac32bf |
case CPU_BROADWELL_EPEX:
|
|
|
ac32bf |
broadwell_epex_decode_model(ras, e);
|
|
|
ac32bf |
break;
|
|
|
ac32bf |
+ case CPU_SKYLAKE_XEON:
|
|
|
ac32bf |
+ skylake_xeon_decode_model(ras, e);
|
|
|
ac32bf |
+ break;
|
|
|
ac32bf |
default:
|
|
|
ac32bf |
break;
|
|
|
ac32bf |
}
|
|
|
ac32bf |
--- rasdaemon-0.4.1.orig/ras-mce-handler.c 2017-05-30 12:43:16.948531592 -0400
|
|
|
ac32bf |
+++ rasdaemon-0.4.1/ras-mce-handler.c 2017-05-30 12:44:00.295009527 -0400
|
|
|
ac32bf |
@@ -54,6 +54,8 @@ [CPU_XEON75XX] = "Intel Xeon 7500 series
|
|
|
ac32bf |
[CPU_BROADWELL_EPEX] = "Broadwell EP/EX",
|
|
|
ac32bf |
[CPU_KNIGHTS_LANDING] = "Knights Landing",
|
|
|
ac32bf |
[CPU_KNIGHTS_MILL] = "Knights Mill",
|
|
|
ac32bf |
+ [CPU_SKYLAKE] = "Skylake",
|
|
|
ac32bf |
+ [CPU_SKYLAKE_XEON] = "Skylake Xeon",
|
|
|
ac32bf |
};
|
|
|
ac32bf |
|
|
|
ac32bf |
static enum cputype select_intel_cputype(struct ras_events *ras)
|
|
|
ac32bf |
@@ -103,6 +105,10 @@ else if (mce->model == 0x57)
|
|
|
ac32bf |
return CPU_KNIGHTS_LANDING;
|
|
|
ac32bf |
else if (mce->model == 0x85)
|
|
|
ac32bf |
return CPU_KNIGHTS_MILL;
|
|
|
ac32bf |
+ else if (mce->model == 0x4e || mce->model == 0x5e)
|
|
|
ac32bf |
+ return CPU_SKYLAKE;
|
|
|
ac32bf |
+ else if (mce->model == 0x55)
|
|
|
ac32bf |
+ return CPU_SKYLAKE_XEON;
|
|
|
ac32bf |
|
|
|
ac32bf |
if (mce->model > 0x1a) {
|
|
|
ac32bf |
log(ALL, LOG_INFO,
|
|
|
ac32bf |
--- rasdaemon-0.4.1.orig/ras-mce-handler.h 2017-05-30 12:43:11.976591473 -0400
|
|
|
ac32bf |
+++ rasdaemon-0.4.1/ras-mce-handler.h 2017-05-30 12:44:25.745703000 -0400
|
|
|
ac32bf |
@@ -49,6 +49,8 @@ enum cputype {
|
|
|
ac32bf |
CPU_BROADWELL_EPEX,
|
|
|
ac32bf |
CPU_KNIGHTS_LANDING,
|
|
|
ac32bf |
CPU_KNIGHTS_MILL,
|
|
|
ac32bf |
+ CPU_SKYLAKE,
|
|
|
ac32bf |
+ CPU_SKYLAKE_XEON,
|
|
|
ac32bf |
};
|
|
|
ac32bf |
|
|
|
ac32bf |
struct mce_event {
|
|
|
ac32bf |
@@ -126,6 +128,7 @@ void knl_decode_model(struct ras_events
|
|
|
ac32bf |
void tulsa_decode_model(struct mce_event *e);
|
|
|
ac32bf |
void broadwell_de_decode_model(struct ras_events *ras, struct mce_event *e);
|
|
|
ac32bf |
void broadwell_epex_decode_model(struct ras_events *ras, struct mce_event *e);
|
|
|
ac32bf |
+void skylake_xeon_decode_model(struct ras_events *ras, struct mce_event *e);
|
|
|
ac32bf |
|
|
|
ac32bf |
/* Software defined banks */
|
|
|
ac32bf |
#define MCE_EXTENDED_BANK 128
|