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From a50a2ae341f8821d71a19d9a3c6ca345e1499e25 Mon Sep 17 00:00:00 2001
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From: Seiichi Ikarashi <s.ikarashi@jp.fujitsu.com>
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Date: Wed, 17 Jun 2015 07:56:57 -0300
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Subject: [PATCH 5/5] rasdaemon: add internal errors of IA32_MC4_STATUS for
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Haswell
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Now rasdaemon looks purposely omitting internal errors of
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IA32_MC4_STATUS for Haswell-family processors, which are described in
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Intel SDM vol3 Table 16-20. I think it's better to show these errors
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because mcelog does show them.
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Signed-off-by: Seiichi Ikarashi <s.ikarashi@jp.fujitsu.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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---
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mce-intel-haswell.c | 11 +++++------
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1 file changed, 5 insertions(+), 6 deletions(-)
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diff --git a/mce-intel-haswell.c b/mce-intel-haswell.c
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index 0a817bf..b70e399 100644
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--- a/mce-intel-haswell.c
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+++ b/mce-intel-haswell.c
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@@ -126,18 +126,17 @@ void hsw_decode_model(struct ras_events *ras, struct mce_event *e)
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case 4:
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switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) {
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case 0x402: case 0x403:
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- /* Internal errors */
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+ mce_snprintf(e->mcastatus_msg, "PCU Internal Errors");
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break;
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case 0x406:
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- /* Intel TXT errors */
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+ mce_snprintf(e->mcastatus_msg, "Intel TXT Errors");
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break;
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case 0x407:
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- /* Other UBOX Internal errors */
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+ mce_snprintf(e->mcastatus_msg, "Other UBOX Internal Errors");
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break;
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}
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- if (EXTRACT(status, 16, 19))
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- /* PCU internal error */
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- ;
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+ if (EXTRACT(status, 16, 17) && !EXTRACT(status, 18, 19))
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+ mce_snprintf(e->error_msg, "PCU Internal error");
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decode_bitfield(e, status, pcu_mc4);
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break;
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case 5:
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--
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1.8.3.1
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