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From f892a390c55c0b350c57cda9d166a9cf331aa36f Mon Sep 17 00:00:00 2001
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From: Seiichi Ikarashi <s.ikarashi@jp.fujitsu.com>
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Date: Tue, 26 May 2015 11:59:38 -0300
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Subject: [PATCH 09/13] rasdaemon: enable IMC status usage for Haswell-E
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Enable IMC status bank for Haswell-E, as described in Intel SDM Vol.3C
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Table 35-27.
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Signed-off-by: Seiichi Ikarashi <s.ikarashi@jp.fujitsu.com>
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Signed-off-by: Aristeu Rozanski <aris@redhat.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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---
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mce-intel.c | 1 +
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ras-mce-handler.c | 1 +
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2 files changed, 2 insertions(+)
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diff --git a/mce-intel.c b/mce-intel.c
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index 69ea00e..3684602 100644
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--- a/mce-intel.c
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+++ b/mce-intel.c
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@@ -457,6 +457,7 @@ int set_intel_imc_log(enum cputype cputype, unsigned ncpus)
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switch (cputype) {
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case CPU_SANDY_BRIDGE_EP:
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case CPU_IVY_BRIDGE_EPEX:
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+ case CPU_HASWELL_EPEX:
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msr = 0x17f; /* MSR_ERROR_CONTROL */
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bit = 0x2; /* MemError Log Enable */
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break;
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diff --git a/ras-mce-handler.c b/ras-mce-handler.c
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index 63f14fd..fb6db8a 100644
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--- a/ras-mce-handler.c
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+++ b/ras-mce-handler.c
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@@ -221,6 +221,7 @@ int register_mce_handler(struct ras_events *ras, unsigned ncpus)
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switch (mce->cputype) {
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case CPU_SANDY_BRIDGE_EP:
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case CPU_IVY_BRIDGE_EPEX:
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+ case CPU_HASWELL_EPEX:
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set_intel_imc_log(mce->cputype, ncpus);
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default:
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break;
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--
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1.8.3.1
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