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From cb97f34eca351d150574c724047709b76d00d08a Mon Sep 17 00:00:00 2001
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From: Francesco Lavra <francescolavra.fl@gmail.com>
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Date: Wed, 19 Sep 2012 05:51:58 +0000
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Subject: [PATCH] Versatile Express: Fix NOR flash 0 address and remove flash
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alias
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In the A series memory map (implemented in the Cortex A15 CoreTile), the
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first NOR flash bank (flash 0) is mapped to address 0x08000000, while
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address 0x00000000 can be configured as alias to either the first or the
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second flash bank. This patch fixes the definition of flash 0 address,
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and for simplicity removes the alias definition.
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Signed-off-by: Francesco Lavra <francescolavra.fl@gmail.com>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 661bafb3e14bfffcb0a7c7910534c7944608ca45)
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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hw/vexpress.c | 7 ++-----
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1 file changed, 2 insertions(+), 5 deletions(-)
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diff --git a/hw/vexpress.c b/hw/vexpress.c
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index b615844..454c2bb 100644
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--- a/hw/vexpress.c
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+++ b/hw/vexpress.c
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@@ -62,7 +62,6 @@ enum {
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VE_COMPACTFLASH,
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VE_CLCD,
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VE_NORFLASH0,
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- VE_NORFLASH0ALIAS,
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VE_NORFLASH1,
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VE_SRAM,
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VE_VIDEORAM,
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@@ -104,9 +103,8 @@ static target_phys_addr_t motherboard_legacy_map[] = {
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};
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static target_phys_addr_t motherboard_aseries_map[] = {
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- /* CS0: 0x00000000 .. 0x0c000000 */
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- [VE_NORFLASH0] = 0x00000000,
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- [VE_NORFLASH0ALIAS] = 0x08000000,
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+ /* CS0: 0x08000000 .. 0x0c000000 */
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+ [VE_NORFLASH0] = 0x08000000,
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/* CS4: 0x0c000000 .. 0x10000000 */
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[VE_NORFLASH1] = 0x0c000000,
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/* CS5: 0x10000000 .. 0x14000000 */
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@@ -413,7 +411,6 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
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/* VE_NORFLASH0: not modelled */
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- /* VE_NORFLASH0ALIAS: not modelled */
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/* VE_NORFLASH1: not modelled */
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sram_size = 0x2000000;
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--
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1.7.12.1
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