Blame 0080-tcg-ppc32-Implement-movcond32.patch

5544c1
From d65d20819ac52207befffa9a7aa858cc7de9cbaf Mon Sep 17 00:00:00 2001
5544c1
From: malc <av1474@comtv.ru>
5544c1
Date: Sat, 22 Sep 2012 19:14:33 +0400
5544c1
Subject: [PATCH] tcg/ppc32: Implement movcond32
5544c1
5544c1
Thanks to Richard Henderson
5544c1
5544c1
Signed-off-by: malc <av1474@comtv.ru>
5544c1
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
5544c1
---
5544c1
 tcg/ppc/tcg-target.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++
5544c1
 tcg/ppc/tcg-target.h |  2 +-
5544c1
 2 files changed, 76 insertions(+), 1 deletion(-)
5544c1
5544c1
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
5544c1
index 26c4b33..8f8b193 100644
5544c1
--- a/tcg/ppc/tcg-target.c
5544c1
+++ b/tcg/ppc/tcg-target.c
5544c1
@@ -390,6 +390,7 @@ static int tcg_target_const_match(tcg_target_long val,
5544c1
 #define ORC    XO31(412)
5544c1
 #define EQV    XO31(284)
5544c1
 #define NAND   XO31(476)
5544c1
+#define ISEL   XO31( 15)
5544c1
 
5544c1
 #define LBZX   XO31( 87)
5544c1
 #define LHZX   XO31(279)
5544c1
@@ -1269,6 +1270,72 @@ static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
5544c1
         );
5544c1
 }
5544c1
 
5544c1
+static void tcg_out_movcond (TCGContext *s, TCGCond cond,
5544c1
+                             TCGArg dest,
5544c1
+                             TCGArg c1, TCGArg c2,
5544c1
+                             TCGArg v1, TCGArg v2,
5544c1
+                             int const_c2)
5544c1
+{
5544c1
+    tcg_out_cmp (s, cond, c1, c2, const_c2, 7);
5544c1
+
5544c1
+    if (1) {
5544c1
+        /* At least here on 7747A bit twiddling hacks are outperformed
5544c1
+           by jumpy code (the testing was not scientific) */
5544c1
+        if (dest == v2) {
5544c1
+            cond = tcg_invert_cond (cond);
5544c1
+            v2 = v1;
5544c1
+        }
5544c1
+        else {
5544c1
+            if (dest != v1) {
5544c1
+                tcg_out_mov (s, TCG_TYPE_I32, dest, v1);
5544c1
+            }
5544c1
+        }
5544c1
+        /* Branch forward over one insn */
5544c1
+        tcg_out32 (s, tcg_to_bc[cond] | 8);
5544c1
+        tcg_out_mov (s, TCG_TYPE_I32, dest, v2);
5544c1
+    }
5544c1
+    else {
5544c1
+        /* isel version, "if (1)" above should be replaced once a way
5544c1
+           to figure out availability of isel on the underlying
5544c1
+           hardware is found */
5544c1
+        int tab, bc;
5544c1
+
5544c1
+        switch (cond) {
5544c1
+        case TCG_COND_EQ:
5544c1
+            tab = TAB (dest, v1, v2);
5544c1
+            bc = CR_EQ;
5544c1
+            break;
5544c1
+        case TCG_COND_NE:
5544c1
+            tab = TAB (dest, v2, v1);
5544c1
+            bc = CR_EQ;
5544c1
+            break;
5544c1
+        case TCG_COND_LTU:
5544c1
+        case TCG_COND_LT:
5544c1
+            tab = TAB (dest, v1, v2);
5544c1
+            bc = CR_LT;
5544c1
+            break;
5544c1
+        case TCG_COND_GEU:
5544c1
+        case TCG_COND_GE:
5544c1
+            tab = TAB (dest, v2, v1);
5544c1
+            bc = CR_LT;
5544c1
+            break;
5544c1
+        case TCG_COND_LEU:
5544c1
+        case TCG_COND_LE:
5544c1
+            tab = TAB (dest, v2, v1);
5544c1
+            bc = CR_GT;
5544c1
+            break;
5544c1
+        case TCG_COND_GTU:
5544c1
+        case TCG_COND_GT:
5544c1
+            tab = TAB (dest, v1, v2);
5544c1
+            bc = CR_GT;
5544c1
+            break;
5544c1
+        default:
5544c1
+            tcg_abort ();
5544c1
+        }
5544c1
+        tcg_out32 (s, ISEL | tab | ((bc + 28) << 6));
5544c1
+    }
5544c1
+}
5544c1
+
5544c1
 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
5544c1
                             TCGArg arg1, TCGArg arg2, int const_arg2,
5544c1
                             int label_index)
5544c1
@@ -1826,6 +1893,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
5544c1
             );
5544c1
         break;
5544c1
 
5544c1
+    case INDEX_op_movcond_i32:
5544c1
+        tcg_out_movcond (s, args[5], args[0],
5544c1
+                         args[1], args[2],
5544c1
+                         args[3], args[4],
5544c1
+                         const_args[2]);
5544c1
+        break;
5544c1
+
5544c1
     default:
5544c1
         tcg_dump_ops (s);
5544c1
         tcg_abort ();
5544c1
@@ -1922,6 +1996,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
5544c1
     { INDEX_op_ext16u_i32, { "r", "r" } },
5544c1
 
5544c1
     { INDEX_op_deposit_i32, { "r", "0", "r" } },
5544c1
+    { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "r" } },
5544c1
 
5544c1
     { -1 },
5544c1
 };
5544c1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
5544c1
index 177eea1..3259d89 100644
5544c1
--- a/tcg/ppc/tcg-target.h
5544c1
+++ b/tcg/ppc/tcg-target.h
5544c1
@@ -92,7 +92,7 @@ typedef enum {
5544c1
 #define TCG_TARGET_HAS_nand_i32         1
5544c1
 #define TCG_TARGET_HAS_nor_i32          1
5544c1
 #define TCG_TARGET_HAS_deposit_i32      1
5544c1
-#define TCG_TARGET_HAS_movcond_i32      0
5544c1
+#define TCG_TARGET_HAS_movcond_i32      1
5544c1
 
5544c1
 #define TCG_AREG0 TCG_REG_R27
5544c1
 
5544c1
-- 
5544c1
1.7.12.1
5544c1