Blame 0058-tcg-mips-fix-wrong-usage-of-Z-constraint.patch

5544c1
From 061d22ad76512e8ec10af89eda1dcc7c185360d2 Mon Sep 17 00:00:00 2001
5544c1
From: Aurelien Jarno <aurelien@aurel32.net>
5544c1
Date: Fri, 21 Sep 2012 18:20:25 +0200
5544c1
Subject: [PATCH] tcg-mips: fix wrong usage of 'Z' constraint
5544c1
5544c1
The 'Z' constraint has been introduced to map the zero register. However
5544c1
when the op also accept a constant, there is no point to accept the zero
5544c1
register in addition.
5544c1
5544c1
Reviewed-by: Richard Henderson <rth@twiddle.net>
5544c1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
5544c1
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
5544c1
---
5544c1
 tcg/mips/tcg-target.c | 16 ++++++++--------
5544c1
 1 file changed, 8 insertions(+), 8 deletions(-)
5544c1
5544c1
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
5544c1
index 74db83d..9293745 100644
5544c1
--- a/tcg/mips/tcg-target.c
5544c1
+++ b/tcg/mips/tcg-target.c
5544c1
@@ -1453,24 +1453,24 @@ static const TCGTargetOpDef mips_op_defs[] = {
5544c1
     { INDEX_op_st16_i32, { "rZ", "r" } },
5544c1
     { INDEX_op_st_i32, { "rZ", "r" } },
5544c1
 
5544c1
-    { INDEX_op_add_i32, { "r", "rZ", "rJZ" } },
5544c1
+    { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
5544c1
     { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_div_i32, { "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_remu_i32, { "r", "rZ", "rZ" } },
5544c1
-    { INDEX_op_sub_i32, { "r", "rZ", "rJZ" } },
5544c1
+    { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
5544c1
 
5544c1
-    { INDEX_op_and_i32, { "r", "rZ", "rIZ" } },
5544c1
+    { INDEX_op_and_i32, { "r", "rZ", "rI" } },
5544c1
     { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_not_i32, { "r", "rZ" } },
5544c1
     { INDEX_op_or_i32, { "r", "rZ", "rIZ" } },
5544c1
     { INDEX_op_xor_i32, { "r", "rZ", "rIZ" } },
5544c1
 
5544c1
-    { INDEX_op_shl_i32, { "r", "rZ", "riZ" } },
5544c1
-    { INDEX_op_shr_i32, { "r", "rZ", "riZ" } },
5544c1
-    { INDEX_op_sar_i32, { "r", "rZ", "riZ" } },
5544c1
+    { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
5544c1
+    { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
5544c1
+    { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
5544c1
 
5544c1
     { INDEX_op_ext8s_i32, { "r", "rZ" } },
5544c1
     { INDEX_op_ext16s_i32, { "r", "rZ" } },
5544c1
@@ -1479,8 +1479,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
5544c1
     { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
5544c1
     { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
5544c1
 
5544c1
-    { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
5544c1
-    { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
5544c1
+    { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
5544c1
+    { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
5544c1
     { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
5544c1
 
5544c1
 #if TARGET_LONG_BITS == 32
5544c1
-- 
5544c1
1.7.12.1
5544c1