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5544c1 |
From 327937b3765d53776e42ffd3990e0b551c98b0e6 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Fri, 7 Sep 2012 16:13:27 +0200
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Subject: [PATCH] target-cris: Switch to AREG0 free mode
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5544c1 |
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Add an explicit CPUCRISState parameter instead of relying on AREG0, and
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use cpu_ld* in translation and interrupt handling. Remove AREG0 swapping
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in tlb_fill(). Switch to AREG0 free mode
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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configure | 2 +-
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target-cris/Makefile.objs | 2 -
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target-cris/helper.c | 4 +-
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target-cris/op_helper.c | 9 +-
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target-cris/translate.c | 256 ++++++++++++++++++++++----------------------
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target-cris/translate_v10.c | 95 ++++++++--------
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6 files changed, 181 insertions(+), 187 deletions(-)
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diff --git a/configure b/configure
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index 0b4ef4a..2a12022 100755
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--- a/configure
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+++ b/configure
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@@ -3839,7 +3839,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
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case "$target_arch2" in
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- alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
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+ alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
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echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
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;;
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esac
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diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
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index 4b09e8c..afb87bc 100644
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--- a/target-cris/Makefile.objs
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+++ b/target-cris/Makefile.objs
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@@ -1,4 +1,2 @@
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obj-y += translate.o op_helper.o helper.o cpu.o
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obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
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-
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-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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diff --git a/target-cris/helper.c b/target-cris/helper.c
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index bfbc29e..1bdb7e2 100644
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--- a/target-cris/helper.c
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+++ b/target-cris/helper.c
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@@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
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}
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/* Now that we are in kernel mode, load the handlers address. */
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- env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
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+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
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env->locked_irq = 1;
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env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
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@@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
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/* Now that we are in kernel mode, load the handlers address.
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This load may not fault, real hw leaves that behaviour as
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undefined. */
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- env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
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+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
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/* Clear the excption_index to avoid spurios hw_aborts for recursive
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bus faults. */
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diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
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index 5ca85a0..a7468d4 100644
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--- a/target-cris/op_helper.c
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+++ b/target-cris/op_helper.c
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@@ -19,7 +19,6 @@
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*/
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#include "cpu.h"
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-#include "dyngen-exec.h"
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#include "mmu.h"
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#include "helper.h"
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#include "host-utils.h"
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@@ -55,17 +54,12 @@
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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-/* XXX: fix it to restore all registers */
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-void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
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+void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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TranslationBlock *tb;
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- CPUCRISState *saved_env;
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int ret;
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- saved_env = env;
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- env = env1;
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-
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D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
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env->pc, env->debug1, (void *)retaddr);
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ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
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@@ -84,7 +78,6 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
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}
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cpu_loop_exit(env);
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}
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- env = saved_env;
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}
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#endif
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diff --git a/target-cris/translate.c b/target-cris/translate.c
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index 283dd98..19144b5 100644
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--- a/target-cris/translate.c
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+++ b/target-cris/translate.c
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@@ -78,7 +78,7 @@ typedef struct DisasContext {
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target_ulong pc, ppc;
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/* Decoder. */
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- unsigned int (*decoder)(struct DisasContext *dc);
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+ unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
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uint32_t ir;
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uint32_t opcode;
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unsigned int op1;
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@@ -233,7 +233,7 @@ static int sign_extend(unsigned int val, unsigned int width)
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return sval;
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}
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-static int cris_fetch(DisasContext *dc, uint32_t addr,
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+static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
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unsigned int size, unsigned int sign)
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{
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int r;
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@@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
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switch (size) {
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case 4:
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{
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- r = ldl_code(addr);
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+ r = cpu_ldl_code(env, addr);
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break;
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}
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case 2:
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{
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if (sign) {
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- r = ldsw_code(addr);
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+ r = cpu_ldsw_code(env, addr);
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} else {
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- r = lduw_code(addr);
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+ r = cpu_lduw_code(env, addr);
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}
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break;
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}
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case 1:
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{
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if (sign) {
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- r = ldsb_code(addr);
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+ r = cpu_ldsb_code(env, addr);
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} else {
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- r = ldub_code(addr);
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+ r = cpu_ldub_code(env, addr);
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}
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break;
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}
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@@ -1304,8 +1304,8 @@ static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
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t_gen_zext(dst, cpu_R[rd], size);
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}
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-static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
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- TCGv dst)
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+static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
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+ int s_ext, int memsize, TCGv dst)
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{
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unsigned int rs;
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uint32_t imm;
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@@ -1321,7 +1321,7 @@ static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
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if (memsize == 1)
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insn_len++;
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- imm = cris_fetch(dc, dc->pc + 2, memsize, s_ext);
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+ imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
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tcg_gen_movi_tl(dst, imm);
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dc->postinc = 0;
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} else {
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@@ -1338,12 +1338,12 @@ static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
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/* Prepare T0 and T1 for a memory + alu operation.
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s_ext decides if the operand1 should be sign-extended or zero-extended when
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needed. */
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-static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
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- TCGv dst, TCGv src)
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+static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
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+ int s_ext, int memsize, TCGv dst, TCGv src)
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{
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int insn_len;
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- insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
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+ insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
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tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
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return insn_len;
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}
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@@ -1362,7 +1362,7 @@ static const char *cc_name(int cc)
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/* Start of insn decoders. */
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-static int dec_bccq(DisasContext *dc)
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+static int dec_bccq(CPUCRISState *env, DisasContext *dc)
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{
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int32_t offset;
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int sign;
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@@ -1382,7 +1382,7 @@ static int dec_bccq(DisasContext *dc)
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cris_prepare_cc_branch (dc, offset, cond);
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return 2;
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}
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-static int dec_addoq(DisasContext *dc)
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+static int dec_addoq(CPUCRISState *env, DisasContext *dc)
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{
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int32_t imm;
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@@ -1396,7 +1396,7 @@ static int dec_addoq(DisasContext *dc)
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return 2;
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}
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-static int dec_addq(DisasContext *dc)
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+static int dec_addq(CPUCRISState *env, DisasContext *dc)
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{
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LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
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@@ -1408,7 +1408,7 @@ static int dec_addq(DisasContext *dc)
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cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
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return 2;
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}
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-static int dec_moveq(DisasContext *dc)
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+static int dec_moveq(CPUCRISState *env, DisasContext *dc)
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{
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uint32_t imm;
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@@ -1419,7 +1419,7 @@ static int dec_moveq(DisasContext *dc)
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tcg_gen_movi_tl(cpu_R[dc->op2], imm);
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return 2;
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}
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-static int dec_subq(DisasContext *dc)
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+static int dec_subq(CPUCRISState *env, DisasContext *dc)
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{
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dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
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@@ -1430,7 +1430,7 @@ static int dec_subq(DisasContext *dc)
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cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
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return 2;
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5544c1 |
}
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5544c1 |
-static int dec_cmpq(DisasContext *dc)
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+static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
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5544c1 |
{
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uint32_t imm;
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5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
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5544c1 |
@@ -1443,7 +1443,7 @@ static int dec_cmpq(DisasContext *dc)
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5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
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5544c1 |
return 2;
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5544c1 |
}
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5544c1 |
-static int dec_andq(DisasContext *dc)
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5544c1 |
+static int dec_andq(CPUCRISState *env, DisasContext *dc)
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5544c1 |
{
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5544c1 |
uint32_t imm;
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5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
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5544c1 |
@@ -1456,7 +1456,7 @@ static int dec_andq(DisasContext *dc)
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5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
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5544c1 |
return 2;
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5544c1 |
}
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5544c1 |
-static int dec_orq(DisasContext *dc)
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5544c1 |
+static int dec_orq(CPUCRISState *env, DisasContext *dc)
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5544c1 |
{
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5544c1 |
uint32_t imm;
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5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
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5544c1 |
@@ -1468,7 +1468,7 @@ static int dec_orq(DisasContext *dc)
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5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
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5544c1 |
return 2;
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5544c1 |
}
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5544c1 |
-static int dec_btstq(DisasContext *dc)
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5544c1 |
+static int dec_btstq(CPUCRISState *env, DisasContext *dc)
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5544c1 |
{
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5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
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5544c1 |
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
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5544c1 |
@@ -1483,7 +1483,7 @@ static int dec_btstq(DisasContext *dc)
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|
5544c1 |
dc->flags_uptodate = 1;
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
-static int dec_asrq(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_asrq(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
|
|
|
5544c1 |
LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -1495,7 +1495,7 @@ static int dec_asrq(DisasContext *dc)
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], 4);
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
-static int dec_lslq(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lslq(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
|
|
|
5544c1 |
LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -1509,7 +1509,7 @@ static int dec_lslq(DisasContext *dc)
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], 4);
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
-static int dec_lsrq(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
|
|
|
5544c1 |
LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -1523,7 +1523,7 @@ static int dec_lsrq(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1551,7 +1551,7 @@ static int dec_move_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_scc_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int cond = dc->op2;
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1594,7 +1594,7 @@ static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_and_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_and_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1611,7 +1611,7 @@ static int dec_and_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_lz_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
LOG_DIS("lz $r%u, $r%u\n",
|
|
|
5544c1 |
@@ -1624,7 +1624,7 @@ static int dec_lz_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_lsl_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1641,7 +1641,7 @@ static int dec_lsl_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_lsr_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1658,7 +1658,7 @@ static int dec_lsr_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_asr_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1675,7 +1675,7 @@ static int dec_asr_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_muls_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1691,7 +1691,7 @@ static int dec_muls_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_mulu_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1708,7 +1708,7 @@ static int dec_mulu_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_dstep_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
@@ -1717,7 +1717,7 @@ static int dec_dstep_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_xor_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1733,7 +1733,7 @@ static int dec_xor_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_bound_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv l0;
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1747,7 +1747,7 @@ static int dec_bound_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_cmp_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1762,7 +1762,7 @@ static int dec_cmp_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_abs_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1781,7 +1781,7 @@ static int dec_abs_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_add_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_add_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1796,7 +1796,7 @@ static int dec_add_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_addc_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("addc $r%u, $r%u\n",
|
|
|
5544c1 |
dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -1811,7 +1811,7 @@ static int dec_addc_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_mcp_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("mcp $p%u, $r%u\n",
|
|
|
5544c1 |
dc->op2, dc->op1);
|
|
|
5544c1 |
@@ -1838,7 +1838,7 @@ static char * swapmode_name(int mode, char *modename) {
|
|
|
5544c1 |
}
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_swap_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
#if DISAS_CRIS
|
|
|
5544c1 |
@@ -1864,7 +1864,7 @@ static int dec_swap_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_or_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_or_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1878,7 +1878,7 @@ static int dec_or_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_addi_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
LOG_DIS("addi.%c $r%u, $r%u\n",
|
|
|
5544c1 |
@@ -1891,7 +1891,7 @@ static int dec_addi_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_addi_acr(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
|
|
|
5544c1 |
@@ -1904,7 +1904,7 @@ static int dec_addi_acr(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_neg_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1919,7 +1919,7 @@ static int dec_neg_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_btst_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("btst $r%u, $r%u\n",
|
|
|
5544c1 |
dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -1934,7 +1934,7 @@ static int dec_btst_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_sub_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int size = memsize_zz(dc);
|
|
|
5544c1 |
@@ -1949,7 +1949,7 @@ static int dec_sub_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Zero extension. From size to dword. */
|
|
|
5544c1 |
-static int dec_movu_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int size = memsize_z(dc);
|
|
|
5544c1 |
@@ -1966,7 +1966,7 @@ static int dec_movu_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Sign extension. From size to dword. */
|
|
|
5544c1 |
-static int dec_movs_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int size = memsize_z(dc);
|
|
|
5544c1 |
@@ -1985,7 +1985,7 @@ static int dec_movs_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* zero extension. From size to dword. */
|
|
|
5544c1 |
-static int dec_addu_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int size = memsize_z(dc);
|
|
|
5544c1 |
@@ -2004,7 +2004,7 @@ static int dec_addu_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Sign extension. From size to dword. */
|
|
|
5544c1 |
-static int dec_adds_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int size = memsize_z(dc);
|
|
|
5544c1 |
@@ -2023,7 +2023,7 @@ static int dec_adds_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Zero extension. From size to dword. */
|
|
|
5544c1 |
-static int dec_subu_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int size = memsize_z(dc);
|
|
|
5544c1 |
@@ -2042,7 +2042,7 @@ static int dec_subu_r(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Sign extension. From size to dword. */
|
|
|
5544c1 |
-static int dec_subs_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int size = memsize_z(dc);
|
|
|
5544c1 |
@@ -2060,7 +2060,7 @@ static int dec_subs_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_setclrf(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
uint32_t flags;
|
|
|
5544c1 |
int set = (~dc->opcode >> 2) & 1;
|
|
|
5544c1 |
@@ -2131,7 +2131,7 @@ static int dec_setclrf(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_rs(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2139,7 +2139,7 @@ static int dec_move_rs(DisasContext *dc)
|
|
|
5544c1 |
tcg_const_tl(dc->op1));
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
-static int dec_move_sr(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2148,7 +2148,7 @@ static int dec_move_sr(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_rp(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -2178,7 +2178,7 @@ static int dec_move_rp(DisasContext *dc)
|
|
|
5544c1 |
tcg_temp_free(t[0]);
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
-static int dec_move_pr(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
|
|
|
5544c1 |
@@ -2200,7 +2200,7 @@ static int dec_move_pr(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_mr(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
int insn_len;
|
|
|
5544c1 |
@@ -2210,7 +2210,7 @@ static int dec_move_mr(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
if (memsize == 4) {
|
|
|
5544c1 |
- insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
|
|
|
5544c1 |
+ insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_update_cc_op(dc, CC_OP_MOVE, 4);
|
|
|
5544c1 |
cris_update_cc_x(dc);
|
|
|
5544c1 |
@@ -2220,7 +2220,7 @@ static int dec_move_mr(DisasContext *dc)
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
|
|
|
5544c1 |
t0 = tcg_temp_new();
|
|
|
5544c1 |
- insn_len = dec_prep_move_m(dc, 0, memsize, t0);
|
|
|
5544c1 |
+ insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_MOVE,
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
|
|
|
5544c1 |
@@ -2242,7 +2242,7 @@ static inline void cris_alu_m_free_temps(TCGv *t)
|
|
|
5544c1 |
tcg_temp_free(t[1]);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_movs_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2254,7 +2254,7 @@ static int dec_movs_m(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
/* sign extend. */
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_MOVE,
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
@@ -2263,7 +2263,7 @@ static int dec_movs_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_addu_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2275,7 +2275,7 @@ static int dec_addu_m(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
/* sign extend. */
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_ADD,
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
@@ -2284,7 +2284,7 @@ static int dec_addu_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_adds_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2296,7 +2296,7 @@ static int dec_adds_m(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
/* sign extend. */
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2304,7 +2304,7 @@ static int dec_adds_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_subu_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2316,7 +2316,7 @@ static int dec_subu_m(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
/* sign extend. */
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2324,7 +2324,7 @@ static int dec_subu_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_subs_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2336,7 +2336,7 @@ static int dec_subs_m(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
/* sign extend. */
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2344,7 +2344,7 @@ static int dec_subs_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_movu_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2356,7 +2356,7 @@ static int dec_movu_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2364,7 +2364,7 @@ static int dec_movu_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_cmpu_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2375,7 +2375,7 @@ static int dec_cmpu_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2383,7 +2383,7 @@ static int dec_cmpu_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_cmps_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_z(dc);
|
|
|
5544c1 |
@@ -2394,7 +2394,7 @@ static int dec_cmps_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_CMP,
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], t[1],
|
|
|
5544c1 |
@@ -2404,7 +2404,7 @@ static int dec_cmps_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_cmp_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2415,7 +2415,7 @@ static int dec_cmp_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_CMP,
|
|
|
5544c1 |
cpu_R[dc->op2], cpu_R[dc->op2], t[1],
|
|
|
5544c1 |
@@ -2425,7 +2425,7 @@ static int dec_cmp_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_test_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_test_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2438,7 +2438,7 @@ static int dec_test_m(DisasContext *dc)
|
|
|
5544c1 |
cris_evaluate_flags(dc);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -2449,7 +2449,7 @@ static int dec_test_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_and_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_and_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2460,7 +2460,7 @@ static int dec_and_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2468,7 +2468,7 @@ static int dec_and_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_add_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_add_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2479,7 +2479,7 @@ static int dec_add_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_ADD,
|
|
|
5544c1 |
cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
|
|
|
5544c1 |
@@ -2488,7 +2488,7 @@ static int dec_add_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_addo_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2499,7 +2499,7 @@ static int dec_addo_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2507,7 +2507,7 @@ static int dec_addo_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_bound_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv l[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2519,7 +2519,7 @@ static int dec_bound_m(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
l[0] = tcg_temp_local_new();
|
|
|
5544c1 |
l[1] = tcg_temp_local_new();
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2528,7 +2528,7 @@ static int dec_bound_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_addc_mr(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int insn_len = 2;
|
|
|
5544c1 |
@@ -2543,7 +2543,7 @@ static int dec_addc_mr(DisasContext *dc)
|
|
|
5544c1 |
dc->flags_x = X_FLAG;
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
|
|
|
5544c1 |
do_postinc(dc, 4);
|
|
|
5544c1 |
@@ -2551,7 +2551,7 @@ static int dec_addc_mr(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_sub_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2562,7 +2562,7 @@ static int dec_sub_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2, dc->ir, dc->zzsize);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
|
|
|
5544c1 |
do_postinc(dc, memsize);
|
|
|
5544c1 |
@@ -2570,7 +2570,7 @@ static int dec_sub_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_or_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_or_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2581,7 +2581,7 @@ static int dec_or_m(DisasContext *dc)
|
|
|
5544c1 |
dc->op2, dc->pc);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZ);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_OR,
|
|
|
5544c1 |
cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
|
|
|
5544c1 |
@@ -2590,7 +2590,7 @@ static int dec_or_m(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_mp(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
int memsize = memsize_zz(dc);
|
|
|
5544c1 |
@@ -2603,7 +2603,7 @@ static int dec_move_mp(DisasContext *dc)
|
|
|
5544c1 |
dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
if (dc->op2 == PR_CCS) {
|
|
|
5544c1 |
cris_evaluate_flags(dc);
|
|
|
5544c1 |
@@ -2622,7 +2622,7 @@ static int dec_move_mp(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_pm(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv t0;
|
|
|
5544c1 |
int memsize;
|
|
|
5544c1 |
@@ -2648,7 +2648,7 @@ static int dec_move_pm(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_movem_mr(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv_i64 tmp[16];
|
|
|
5544c1 |
TCGv tmp32;
|
|
|
5544c1 |
@@ -2695,7 +2695,7 @@ static int dec_movem_mr(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_movem_rm(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
TCGv tmp;
|
|
|
5544c1 |
TCGv addr;
|
|
|
5544c1 |
@@ -2724,7 +2724,7 @@ static int dec_movem_rm(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_move_rm(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int memsize;
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -2743,7 +2743,7 @@ static int dec_move_rm(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_lapcq(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("lapcq %x, $r%u\n",
|
|
|
5544c1 |
dc->pc + dc->op1*2, dc->op2);
|
|
|
5544c1 |
@@ -2752,7 +2752,7 @@ static int dec_lapcq(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_lapc_im(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int rd;
|
|
|
5544c1 |
int32_t imm;
|
|
|
5544c1 |
@@ -2761,7 +2761,7 @@ static int dec_lapc_im(DisasContext *dc)
|
|
|
5544c1 |
rd = dc->op2;
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
- imm = cris_fetch(dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
+ imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
pc = dc->pc;
|
|
|
5544c1 |
@@ -2771,7 +2771,7 @@ static int dec_lapc_im(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Jump to special reg. */
|
|
|
5544c1 |
-static int dec_jump_p(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("jump $p%u\n", dc->op2);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -2786,7 +2786,7 @@ static int dec_jump_p(DisasContext *dc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Jump and save. */
|
|
|
5544c1 |
-static int dec_jas_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2800,11 +2800,11 @@ static int dec_jas_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_jas_im(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
uint32_t imm;
|
|
|
5544c1 |
|
|
|
5544c1 |
- imm = cris_fetch(dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
+ imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
|
|
|
5544c1 |
LOG_DIS("jas 0x%x\n", imm);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2816,11 +2816,11 @@ static int dec_jas_im(DisasContext *dc)
|
|
|
5544c1 |
return 6;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_jasc_im(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
uint32_t imm;
|
|
|
5544c1 |
|
|
|
5544c1 |
- imm = cris_fetch(dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
+ imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
|
|
|
5544c1 |
LOG_DIS("jasc 0x%x\n", imm);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2832,7 +2832,7 @@ static int dec_jasc_im(DisasContext *dc)
|
|
|
5544c1 |
return 6;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_jasc_r(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2843,12 +2843,12 @@ static int dec_jasc_r(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_bcc_im(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int32_t offset;
|
|
|
5544c1 |
uint32_t cond = dc->op2;
|
|
|
5544c1 |
|
|
|
5544c1 |
- offset = cris_fetch(dc, dc->pc + 2, 2, 1);
|
|
|
5544c1 |
+ offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
|
|
|
5544c1 |
|
|
|
5544c1 |
LOG_DIS("b%s %d pc=%x dst=%x\n",
|
|
|
5544c1 |
cc_name(cond), offset,
|
|
|
5544c1 |
@@ -2860,12 +2860,12 @@ static int dec_bcc_im(DisasContext *dc)
|
|
|
5544c1 |
return 4;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_bas_im(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int32_t simm;
|
|
|
5544c1 |
|
|
|
5544c1 |
|
|
|
5544c1 |
- simm = cris_fetch(dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
+ simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
|
|
|
5544c1 |
LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2877,10 +2877,10 @@ static int dec_bas_im(DisasContext *dc)
|
|
|
5544c1 |
return 6;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_basc_im(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int32_t simm;
|
|
|
5544c1 |
- simm = cris_fetch(dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
+ simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
|
|
|
5544c1 |
|
|
|
5544c1 |
LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
@@ -2892,7 +2892,7 @@ static int dec_basc_im(DisasContext *dc)
|
|
|
5544c1 |
return 6;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_rfe_etc(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -2939,17 +2939,17 @@ static int dec_rfe_etc(DisasContext *dc)
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_ftag_fidx_d_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_ftag_fidx_i_m(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
return 2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec_null(DisasContext *dc)
|
|
|
5544c1 |
+static int dec_null(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
|
|
|
5544c1 |
dc->pc, dc->opcode, dc->op1, dc->op2);
|
|
|
5544c1 |
@@ -2963,7 +2963,7 @@ static struct decoder_info {
|
|
|
5544c1 |
uint32_t bits;
|
|
|
5544c1 |
uint32_t mask;
|
|
|
5544c1 |
};
|
|
|
5544c1 |
- int (*dec)(DisasContext *dc);
|
|
|
5544c1 |
+ int (*dec)(CPUCRISState *env, DisasContext *dc);
|
|
|
5544c1 |
} decinfo[] = {
|
|
|
5544c1 |
/* Order matters here. */
|
|
|
5544c1 |
{DEC_MOVEQ, dec_moveq},
|
|
|
5544c1 |
@@ -3069,7 +3069,7 @@ static struct decoder_info {
|
|
|
5544c1 |
{{0, 0}, dec_null}
|
|
|
5544c1 |
};
|
|
|
5544c1 |
|
|
|
5544c1 |
-static unsigned int crisv32_decoder(DisasContext *dc)
|
|
|
5544c1 |
+static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int insn_len = 2;
|
|
|
5544c1 |
int i;
|
|
|
5544c1 |
@@ -3078,7 +3078,7 @@ static unsigned int crisv32_decoder(DisasContext *dc)
|
|
|
5544c1 |
tcg_gen_debug_insn_start(dc->pc);
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Load a halfword onto the instruction register. */
|
|
|
5544c1 |
- dc->ir = cris_fetch(dc, dc->pc, 2, 0);
|
|
|
5544c1 |
+ dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Now decode it. */
|
|
|
5544c1 |
dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
|
|
|
5544c1 |
@@ -3092,7 +3092,7 @@ static unsigned int crisv32_decoder(DisasContext *dc)
|
|
|
5544c1 |
for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
|
|
|
5544c1 |
if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
- insn_len = decinfo[i].dec(dc);
|
|
|
5544c1 |
+ insn_len = decinfo[i].dec(env, dc);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
}
|
|
|
5544c1 |
@@ -3286,7 +3286,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb,
|
|
|
5544c1 |
gen_io_start();
|
|
|
5544c1 |
dc->clear_x = 1;
|
|
|
5544c1 |
|
|
|
5544c1 |
- insn_len = dc->decoder(dc);
|
|
|
5544c1 |
+ insn_len = dc->decoder(env, dc);
|
|
|
5544c1 |
dc->ppc = dc->pc;
|
|
|
5544c1 |
dc->pc += insn_len;
|
|
|
5544c1 |
if (dc->clear_x)
|
|
|
5544c1 |
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
|
|
|
5544c1 |
index 9a39c6a..d2cca89 100644
|
|
|
5544c1 |
--- a/target-cris/translate_v10.c
|
|
|
5544c1 |
+++ b/target-cris/translate_v10.c
|
|
|
5544c1 |
@@ -164,8 +164,8 @@ static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
|
|
|
5544c1 |
- TCGv dst)
|
|
|
5544c1 |
+static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
|
|
|
5544c1 |
+ int s_ext, int memsize, TCGv dst)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int rs;
|
|
|
5544c1 |
uint32_t imm;
|
|
|
5544c1 |
@@ -182,17 +182,17 @@ static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
|
|
|
5544c1 |
if (memsize != 4) {
|
|
|
5544c1 |
if (s_ext) {
|
|
|
5544c1 |
if (memsize == 1)
|
|
|
5544c1 |
- imm = ldsb_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldsb_code(env, dc->pc + 2);
|
|
|
5544c1 |
else
|
|
|
5544c1 |
- imm = ldsw_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldsw_code(env, dc->pc + 2);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
if (memsize == 1)
|
|
|
5544c1 |
- imm = ldub_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldub_code(env, dc->pc + 2);
|
|
|
5544c1 |
else
|
|
|
5544c1 |
- imm = lduw_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_lduw_code(env, dc->pc + 2);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
} else
|
|
|
5544c1 |
- imm = ldl_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldl_code(env, dc->pc + 2);
|
|
|
5544c1 |
|
|
|
5544c1 |
tcg_gen_movi_tl(dst, imm);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -752,7 +752,8 @@ static unsigned int dec10_reg(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size)
|
|
|
5544c1 |
+static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
|
|
|
5544c1 |
+ unsigned int size)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int insn_len = 2;
|
|
|
5544c1 |
TCGv t;
|
|
|
5544c1 |
@@ -762,7 +763,7 @@ static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size)
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
t = tcg_temp_new();
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, 0, size, t);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
|
|
|
5544c1 |
if (dc->dst == 15) {
|
|
|
5544c1 |
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
|
|
|
5544c1 |
@@ -789,7 +790,7 @@ static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static unsigned int dec10_ind_move_m_pr(DisasContext *dc)
|
|
|
5544c1 |
+static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int insn_len = 2, rd = dc->dst;
|
|
|
5544c1 |
TCGv t, addr;
|
|
|
5544c1 |
@@ -799,7 +800,7 @@ static unsigned int dec10_ind_move_m_pr(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
addr = tcg_temp_new();
|
|
|
5544c1 |
t = tcg_temp_new();
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, 0, 4, t);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
|
|
|
5544c1 |
if (rd == 15) {
|
|
|
5544c1 |
tcg_gen_mov_tl(env_btarget, t);
|
|
|
5544c1 |
cris_prepare_jmp(dc, JMP_INDIRECT);
|
|
|
5544c1 |
@@ -899,14 +900,15 @@ static void dec10_movem_m_r(DisasContext *dc)
|
|
|
5544c1 |
tcg_temp_free(t0);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size)
|
|
|
5544c1 |
+static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
|
|
|
5544c1 |
+ int op, unsigned int size)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int insn_len = 0;
|
|
|
5544c1 |
int rd = dc->dst;
|
|
|
5544c1 |
TCGv t[2];
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, 0, size, t[0]);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
|
|
|
5544c1 |
cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
|
|
|
5544c1 |
if (dc->dst == 15) {
|
|
|
5544c1 |
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
|
|
|
5544c1 |
@@ -920,14 +922,15 @@ static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec10_ind_bound(DisasContext *dc, unsigned int size)
|
|
|
5544c1 |
+static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
|
|
|
5544c1 |
+ unsigned int size)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int insn_len = 0;
|
|
|
5544c1 |
int rd = dc->dst;
|
|
|
5544c1 |
TCGv t;
|
|
|
5544c1 |
|
|
|
5544c1 |
t = tcg_temp_local_new();
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, 0, size, t);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
|
|
|
5544c1 |
if (dc->dst == 15) {
|
|
|
5544c1 |
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
|
|
|
5544c1 |
@@ -940,7 +943,7 @@ static int dec10_ind_bound(DisasContext *dc, unsigned int size)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec10_alux_m(DisasContext *dc, int op)
|
|
|
5544c1 |
+static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int size = (dc->size & 1) ? 2 : 1;
|
|
|
5544c1 |
unsigned int sx = !!(dc->size & 2);
|
|
|
5544c1 |
@@ -953,7 +956,7 @@ static int dec10_alux_m(DisasContext *dc, int op)
|
|
|
5544c1 |
t = tcg_temp_new();
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, sx, size, t);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, sx, size, t);
|
|
|
5544c1 |
cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
|
|
|
5544c1 |
if (dc->dst == 15) {
|
|
|
5544c1 |
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
|
|
|
5544c1 |
@@ -966,7 +969,7 @@ static int dec10_alux_m(DisasContext *dc, int op)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec10_dip(DisasContext *dc)
|
|
|
5544c1 |
+static int dec10_dip(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int insn_len = 2;
|
|
|
5544c1 |
uint32_t imm;
|
|
|
5544c1 |
@@ -974,7 +977,7 @@ static int dec10_dip(DisasContext *dc)
|
|
|
5544c1 |
LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
|
|
|
5544c1 |
dc->pc, dc->opcode, dc->src, dc->dst);
|
|
|
5544c1 |
if (dc->src == 15) {
|
|
|
5544c1 |
- imm = ldl_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldl_code(env, dc->pc + 2);
|
|
|
5544c1 |
tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
|
|
|
5544c1 |
if (dc->postinc)
|
|
|
5544c1 |
insn_len += 4;
|
|
|
5544c1 |
@@ -989,7 +992,7 @@ static int dec10_dip(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static int dec10_bdap_m(DisasContext *dc, int size)
|
|
|
5544c1 |
+static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int insn_len = 2;
|
|
|
5544c1 |
int rd = dc->dst;
|
|
|
5544c1 |
@@ -1014,13 +1017,13 @@ static int dec10_bdap_m(DisasContext *dc, int size)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
/* Now the rest of the modes are truly indirect. */
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, 1, size, cpu_PR[PR_PREFIX]);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
|
|
|
5544c1 |
tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
|
|
|
5544c1 |
cris_set_prefix(dc);
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
+static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int insn_len = 2;
|
|
|
5544c1 |
unsigned int size = dec10_size(dc->size);
|
|
|
5544c1 |
@@ -1031,7 +1034,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
if (dc->size != 3) {
|
|
|
5544c1 |
switch (dc->opcode) {
|
|
|
5544c1 |
case CRISV10_IND_MOVE_M_R:
|
|
|
5544c1 |
- return dec10_ind_move_m_r(dc, size);
|
|
|
5544c1 |
+ return dec10_ind_move_m_r(env, dc, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_MOVE_R_M:
|
|
|
5544c1 |
return dec10_ind_move_r_m(dc, size);
|
|
|
5544c1 |
@@ -1039,7 +1042,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
case CRISV10_IND_CMP:
|
|
|
5544c1 |
LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_ind_alu(dc, CC_OP_CMP, size);
|
|
|
5544c1 |
+ insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_TEST:
|
|
|
5544c1 |
LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
@@ -1047,7 +1050,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
cris_evaluate_flags(dc);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
cris_alu_m_alloc_temps(t);
|
|
|
5544c1 |
- insn_len += dec10_prep_move_m(dc, 0, size, t[0]);
|
|
|
5544c1 |
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
|
|
|
5544c1 |
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
|
|
|
5544c1 |
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
|
|
|
5544c1 |
t[0], tcg_const_tl(0), size);
|
|
|
5544c1 |
@@ -1056,39 +1059,39 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
case CRISV10_IND_ADD:
|
|
|
5544c1 |
LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_ind_alu(dc, CC_OP_ADD, size);
|
|
|
5544c1 |
+ insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_SUB:
|
|
|
5544c1 |
LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_ind_alu(dc, CC_OP_SUB, size);
|
|
|
5544c1 |
+ insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_BOUND:
|
|
|
5544c1 |
LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_ind_bound(dc, size);
|
|
|
5544c1 |
+ insn_len += dec10_ind_bound(env, dc, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_AND:
|
|
|
5544c1 |
LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_ind_alu(dc, CC_OP_AND, size);
|
|
|
5544c1 |
+ insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_OR:
|
|
|
5544c1 |
LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
|
|
|
5544c1 |
cris_cc_mask(dc, CC_MASK_NZVC);
|
|
|
5544c1 |
- insn_len += dec10_ind_alu(dc, CC_OP_OR, size);
|
|
|
5544c1 |
+ insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_MOVX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_MOVE);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_ADDX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_ADD);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_SUBX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_SUB);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_CMPX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_CMP);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_MUL:
|
|
|
5544c1 |
/* This is a reg insn coded in the mem indir space. */
|
|
|
5544c1 |
@@ -1097,7 +1100,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
dec10_reg_mul(dc, size, dc->ir & (1 << 10));
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_BDAP_M:
|
|
|
5544c1 |
- insn_len = dec10_bdap_m(dc, size);
|
|
|
5544c1 |
+ insn_len = dec10_bdap_m(env, dc, size);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
default:
|
|
|
5544c1 |
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
|
|
|
5544c1 |
@@ -1110,7 +1113,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
|
|
|
5544c1 |
switch (dc->opcode) {
|
|
|
5544c1 |
case CRISV10_IND_MOVE_M_SPR:
|
|
|
5544c1 |
- insn_len = dec10_ind_move_m_pr(dc);
|
|
|
5544c1 |
+ insn_len = dec10_ind_move_m_pr(env, dc);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_MOVE_SPR_M:
|
|
|
5544c1 |
insn_len = dec10_ind_move_pr_m(dc);
|
|
|
5544c1 |
@@ -1119,7 +1122,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
if (dc->src == 15) {
|
|
|
5544c1 |
LOG_DIS("jump.%d %d r%d r%d direct\n", size,
|
|
|
5544c1 |
dc->opcode, dc->src, dc->dst);
|
|
|
5544c1 |
- imm = ldl_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldl_code(env, dc->pc + 2);
|
|
|
5544c1 |
if (dc->mode == CRISV10_MODE_AUTOINC)
|
|
|
5544c1 |
insn_len += size;
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1168,24 +1171,24 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
dc->delayed_branch--; /* v10 has no dslot here. */
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_MOVX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_MOVE);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_ADDX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_ADD);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_SUBX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_SUB);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_CMPX:
|
|
|
5544c1 |
- insn_len = dec10_alux_m(dc, CC_OP_CMP);
|
|
|
5544c1 |
+ insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_DIP:
|
|
|
5544c1 |
- insn_len = dec10_dip(dc);
|
|
|
5544c1 |
+ insn_len = dec10_dip(env, dc);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_IND_BCC_M:
|
|
|
5544c1 |
|
|
|
5544c1 |
cris_cc_mask(dc, 0);
|
|
|
5544c1 |
- imm = ldsw_code(dc->pc + 2);
|
|
|
5544c1 |
+ imm = cpu_ldsw_code(env, dc->pc + 2);
|
|
|
5544c1 |
simm = (int16_t)imm;
|
|
|
5544c1 |
simm += 4;
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1202,7 +1205,7 @@ static unsigned int dec10_ind(DisasContext *dc)
|
|
|
5544c1 |
return insn_len;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static unsigned int crisv10_decoder(DisasContext *dc)
|
|
|
5544c1 |
+static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
unsigned int insn_len = 2;
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1210,7 +1213,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
|
|
|
5544c1 |
tcg_gen_debug_insn_start(dc->pc);
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Load a halfword onto the instruction register. */
|
|
|
5544c1 |
- dc->ir = lduw_code(dc->pc);
|
|
|
5544c1 |
+ dc->ir = cpu_lduw_code(env, dc->pc);
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Now decode it. */
|
|
|
5544c1 |
dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
|
|
|
5544c1 |
@@ -1235,7 +1238,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case CRISV10_MODE_AUTOINC:
|
|
|
5544c1 |
case CRISV10_MODE_INDIRECT:
|
|
|
5544c1 |
- insn_len = dec10_ind(dc);
|
|
|
5544c1 |
+ insn_len = dec10_ind(env, dc);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
--
|
|
|
5544c1 |
1.7.12.1
|
|
|
5544c1 |
|