From 136eae41007e2e5b0d693cc656f3ec36cbabf16f Mon Sep 17 00:00:00 2001 From: Miroslav Rezanina Date: Fri, 19 Oct 2018 13:27:13 +0200 Subject: Add ppc64 machine types Adding changes to add RHEL machine types for ppc64 architecture. Signed-off-by: Miroslav Rezanina Rebase changes (4.0.0): - remove instance options and use upstream solution - Use upstream compat handling - Replace SPAPR_PCI_2_7_MMIO_WIN_SIZE with value (changed upstream) - re-add handling of instance_options (removed upstream) - Use p8 as default for rhel machine types (p9 default upstream) - sPAPRMachineClass renamed to SpaprMachineClass (upstream) Rebase changes (4.1.0): - Update format for compat structures Merged patches (4.0.0): - 467d59a redhat: define pseries-rhel8.0.0 machine type Merged patches (4.1.0): - f21757edc target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type - 2511c63 redhat: sync pseries-rhel7.6.0 with rhel-av-8.0.1 - 89f01da redhat: define pseries-rhel8.1.0 machine type Merged patches (4.2.0): - bcba728 redhat: update pseries-rhel8.1.0 machine type - redhat: update pseries-rhel-7.6.0 machine type (patch 93039) - redhat: define pseries-rhel8.2.0 machine type (patch 93041) Signed-off-by: Danilo C. L. de Paula --- hw/ppc/spapr.c | 278 ++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_cpu_core.c | 13 ++ include/hw/ppc/spapr.h | 1 + target/ppc/compat.c | 13 +- target/ppc/cpu.h | 1 + 5 files changed, 305 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e076f6023c..8749c72066 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4447,6 +4447,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) smc->linux_pci_probe = true; smc->smp_threads_vsmt = true; smc->nr_xirqs = SPAPR_NR_XIRQS; + smc->has_power9_support = true; } static const TypeInfo spapr_machine_info = { @@ -4491,6 +4492,7 @@ static const TypeInfo spapr_machine_info = { } \ type_init(spapr_machine_register_##suffix) +#if 0 /* Disabled for Red Hat Enterprise Linux */ /* * pseries-4.2 */ @@ -4520,6 +4522,7 @@ static void spapr_machine_4_1_class_options(MachineClass *mc) } DEFINE_SPAPR_MACHINE(4_1, "4.1", false); +#endif /* * pseries-4.0 @@ -4536,6 +4539,7 @@ static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, *nv2atsd = 0; } +#if 0 /* Disabled for Red Hat Enterprise Linux */ static void spapr_machine_4_0_class_options(MachineClass *mc) { SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); @@ -4695,6 +4699,7 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", false); /* * pseries-2.7 */ +#endif static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, @@ -4749,6 +4754,7 @@ static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, *nv2atsd = 0; } +#if 0 /* Disabled for Red Hat Enterprise Linux */ static void spapr_machine_2_7_class_options(MachineClass *mc) { SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); @@ -4863,6 +4869,278 @@ static void spapr_machine_2_1_class_options(MachineClass *mc) compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); } DEFINE_SPAPR_MACHINE(2_1, "2.1", false); +#endif + +/* + * pseries-rhel8.2.0 + */ + +static void spapr_machine_rhel820_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(rhel820, "rhel8.2.0", true); + +/* + * pseries-rhel8.1.0 + * like pseries-4.1 + */ + +static void spapr_machine_rhel810_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + /* Only allow 4kiB and 64kiB IOMMU pagesizes */ + { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, + }; + + spapr_machine_rhel820_class_options(mc); + + /* from pseries-4.1 */ + smc->linux_pci_probe = false; + smc->smp_threads_vsmt = false; + compat_props_add(mc->compat_props, hw_compat_rhel_8_1, + hw_compat_rhel_8_1_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); + +} + +DEFINE_SPAPR_MACHINE(rhel810, "rhel8.1.0", false); + +/* + * pseries-rhel8.0.0 + * like pseries-3.1 and pseries-4.0 + * except SPAPR_CAP_CFPC, SPAPR_CAP_SBBC and SPAPR_CAP_IBS + * that have been backported to pseries-rhel8.0.0 + */ + +static void spapr_machine_rhel800_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel810_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_rhel_8_0, + hw_compat_rhel_8_0_len); + + /* pseries-4.0 */ + smc->phb_placement = phb_placement_4_0; + smc->irq = &spapr_irq_xics; + smc->pre_4_1_migration = true; + + /* pseries-3.1 */ + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); + smc->update_dt_enabled = false; + smc->dr_phb_enabled = false; + smc->broken_host_serial_model = true; + smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; +} + +DEFINE_SPAPR_MACHINE(rhel800, "rhel8.0.0", false); + +/* + * pseries-rhel7.6.0 + * like spapr_compat_2_12 and spapr_compat_3_0 + * spapr_compat_0 is empty + */ +GlobalProperty spapr_compat_rhel7_6[] = { + { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, + { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, +}; +const size_t spapr_compat_rhel7_6_len = G_N_ELEMENTS(spapr_compat_rhel7_6); + + +static void spapr_machine_rhel760_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel800_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_rhel_7_6, hw_compat_rhel_7_6_len); + compat_props_add(mc->compat_props, spapr_compat_rhel7_6, spapr_compat_rhel7_6_len); + + /* from spapr_machine_3_0_class_options() */ + smc->legacy_irq_allocation = true; + smc->nr_xirqs = 0x400; + smc->irq = &spapr_irq_xics_legacy; + + /* from spapr_machine_2_12_class_options() */ + /* We depend on kvm_enabled() to choose a default value for the + * hpt-max-page-size capability. Of course we can't do it here + * because this is too early and the HW accelerator isn't initialzed + * yet. Postpone this to machine init (see default_caps_with_cpu()). + */ + smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; + + /* SPAPR_CAP_WORKAROUND enabled in pseries-rhel800 by + * f21757edc554 + * "Enable mitigations by default for pseries-4.0 machine type") + */ + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; +} + +DEFINE_SPAPR_MACHINE(rhel760, "rhel7.6.0", false); + +/* + * pseries-rhel7.6.0-sxxm + * + * pseries-rhel7.6.0 with speculative execution exploit mitigations enabled by default + */ + +static void spapr_machine_rhel760sxxm_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel760_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel760sxxm, "rhel7.6.0-sxxm", false); + +static void spapr_machine_rhel750_class_options(MachineClass *mc) +{ + spapr_machine_rhel760_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_rhel_7_5, hw_compat_rhel_7_5_len); + +} + +DEFINE_SPAPR_MACHINE(rhel750, "rhel7.5.0", false); + +/* + * pseries-rhel7.5.0-sxxm + * + * pseries-rhel7.5.0 with speculative execution exploit mitigations enabled by default + */ + +static void spapr_machine_rhel750sxxm_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel750_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel750sxxm, "rhel7.5.0-sxxm", false); + +/* + * pseries-rhel7.4.0 + * like spapr_compat_2_9 + */ +GlobalProperty spapr_compat_rhel7_4[] = { + { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, +}; +const size_t spapr_compat_rhel7_4_len = G_N_ELEMENTS(spapr_compat_rhel7_4); + +static void spapr_machine_rhel740_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel750_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_rhel_7_4, hw_compat_rhel_7_4_len); + compat_props_add(mc->compat_props, spapr_compat_rhel7_4, spapr_compat_rhel7_4_len); + mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; + smc->has_power9_support = false; + smc->pre_2_10_has_unused_icps = true; + smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; + smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; +} + +DEFINE_SPAPR_MACHINE(rhel740, "rhel7.4.0", false); + +/* + * pseries-rhel7.4.0-sxxm + * + * pseries-rhel7.4.0 with speculative execution exploit mitigations enabled by default + */ + +static void spapr_machine_rhel740sxxm_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel740_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel740sxxm, "rhel7.4.0-sxxm", false); + +/* + * pseries-rhel7.3.0 + * like spapr_compat_2_6/_2_7/_2_8 but "ddw" has been backported to RHEL7_3 + */ +GlobalProperty spapr_compat_rhel7_3[] = { + { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000" }, + { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0" }, + { TYPE_POWERPC_CPU, "pre-2.8-migration", "on" }, + { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on" }, + { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, +}; +const size_t spapr_compat_rhel7_3_len = G_N_ELEMENTS(spapr_compat_rhel7_3); + +static void spapr_machine_rhel730_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel740_class_options(mc); + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); + mc->default_machine_opts = "modern-hotplug-events=off"; + compat_props_add(mc->compat_props, hw_compat_rhel_7_3, hw_compat_rhel_7_3_len); + compat_props_add(mc->compat_props, spapr_compat_rhel7_3, spapr_compat_rhel7_3_len); + + smc->phb_placement = phb_placement_2_7; +} + +DEFINE_SPAPR_MACHINE(rhel730, "rhel7.3.0", false); + +/* + * pseries-rhel7.3.0-sxxm + * + * pseries-rhel7.3.0 with speculative execution exploit mitigations enabled by default + */ + +static void spapr_machine_rhel730sxxm_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel730_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel730sxxm, "rhel7.3.0-sxxm", false); + +/* + * pseries-rhel7.2.0 + */ +/* Should be like spapr_compat_2_5 + 2_4 + 2_3, but "dynamic-reconfiguration" + * has been backported to RHEL7_2 so we don't need it here. + */ + +GlobalProperty spapr_compat_rhel7_2[] = { + { "spapr-vlan", "use-rx-buffer-pools", "off" }, + { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, +}; +const size_t spapr_compat_rhel7_2_len = G_N_ELEMENTS(spapr_compat_rhel7_2); + +static void spapr_machine_rhel720_class_options(MachineClass *mc) +{ + SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel730_class_options(mc); + smc->use_ohci_by_default = true; + mc->has_hotpluggable_cpus = NULL; + compat_props_add(mc->compat_props, hw_compat_rhel_7_2, hw_compat_rhel_7_2_len); + compat_props_add(mc->compat_props, spapr_compat_rhel7_2, spapr_compat_rhel7_2_len); +} + +DEFINE_SPAPR_MACHINE(rhel720, "rhel7.2.0", false); static void spapr_machine_register_types(void) { diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 301cd7b4e4..ba5a8fb82b 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -24,6 +24,7 @@ #include "sysemu/reset.h" #include "sysemu/hw_accel.h" #include "qemu/error-report.h" +#include "cpu-models.h" static void spapr_reset_vcpu(PowerPCCPU *cpu) { @@ -242,6 +243,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); Error *local_err = NULL; + SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); if (local_err) { @@ -254,6 +256,17 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); kvmppc_set_papr(cpu); + if (!smc->has_power9_support && + (((spapr->max_compat_pvr && + ppc_compat_cmp(spapr->max_compat_pvr, + CPU_POWERPC_LOGICAL_3_00) >= 0)) || + (!spapr->max_compat_pvr && + ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 0)))) { + error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND, + "POWER9 CPU is not supported by this machine class"); + return; + } + if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) { goto error_intc_create; } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index d5ab5ea7b2..aa89cc4a95 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -125,6 +125,7 @@ struct SpaprMachineClass { bool linux_pci_probe; bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ + bool has_power9_support; void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, hwaddr *mmio32, hwaddr *mmio64, diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 7de4bf3122..3e2e35342d 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -105,8 +105,19 @@ static const CompatInfo *compat_by_pvr(uint32_t pvr) return NULL; } +long ppc_compat_cmp(uint32_t pvr1, uint32_t pvr2) +{ + const CompatInfo *compat1 = compat_by_pvr(pvr1); + const CompatInfo *compat2 = compat_by_pvr(pvr2); + + g_assert(compat1); + g_assert(compat2); + + return compat1 - compat2; +} + static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t compat_pvr, - uint32_t min_compat_pvr, uint32_t max_compat_pvr) + uint32_t min_compat_pvr, uint32_t max_compat_pvr) { const CompatInfo *compat = compat_by_pvr(compat_pvr); const CompatInfo *min = compat_by_pvr(min_compat_pvr); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e3e82327b7..5c53801cfd 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1367,6 +1367,7 @@ static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) /* Compatibility modes */ #if defined(TARGET_PPC64) +long ppc_compat_cmp(uint32_t pvr1, uint32_t pvr2); bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, uint32_t min_compat_pvr, uint32_t max_compat_pvr); bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr, -- 2.21.0