From 9c3757a2d7302918456da459a8d188bb41299891 Mon Sep 17 00:00:00 2001 From: Tao Xu Date: Fri, 11 Oct 2019 15:41:03 +0800 Subject: [PATCH 11/11] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR RH-Author: plai@redhat.com Message-id: <1574797015-32564-8-git-send-email-plai@redhat.com> Patchwork-id: 92693 O-Subject: [RHEL8.2 qemu-kvm PATCH 7/7] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR Bugzilla: 1634827 RH-Acked-by: Eduardo Habkost RH-Acked-by: Michael S. Tsirkin RH-Acked-by: Igor Mammedov UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in guest. Co-developed-by: Jingqi Liu Signed-off-by: Jingqi Liu Signed-off-by: Tao Xu Message-Id: <20191011074103.30393-3-tao3.xu@intel.com> Signed-off-by: Paolo Bonzini Signed-off-by: Danilo C. L. de Paula --- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 13 +++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fac98aa..ecbe4f0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -461,6 +461,7 @@ typedef enum X86Seg { #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 +#define MSR_IA32_UMWAIT_CONTROL 0xe1 #define MSR_IA32_VMX_BASIC 0x00000480 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 @@ -1510,6 +1511,7 @@ typedef struct CPUX86State { uint16_t fpregs_format_vmstate; uint64_t xss; + uint32_t umwait; TPRAccess tpr_access_type; } CPUX86State; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 0fd5650..ad58bfb 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -91,6 +91,7 @@ static bool has_msr_hv_synic; static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_xss; +static bool has_msr_umwait; static bool has_msr_spec_ctrl; static bool has_msr_tsx_ctrl; static bool has_msr_virt_ssbd; @@ -1450,6 +1451,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_XSS: has_msr_xss = true; break; + case MSR_IA32_UMWAIT_CONTROL: + has_msr_umwait = true; + break; case HV_X64_MSR_CRASH_CTL: has_msr_hv_crash = true; break; @@ -2134,6 +2138,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); } + if (has_msr_umwait) { + kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); + } if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); } @@ -2533,6 +2540,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); } + if (has_msr_umwait) { + kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); + } if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); } @@ -2780,6 +2790,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_XSS: env->xss = msrs[i].data; break; + case MSR_IA32_UMWAIT_CONTROL: + env->umwait = msrs[i].data; + break; default: if (msrs[i].index >= MSR_MC0_CTL && msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { diff --git a/target/i386/machine.c b/target/i386/machine.c index 76b173c..960cb51 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -894,6 +894,25 @@ static const VMStateDescription vmstate_xss = { } }; +static bool umwait_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->umwait != 0; +} + +static const VMStateDescription vmstate_umwait = { + .name = "cpu/umwait", + .version_id = 1, + .minimum_version_id = 1, + .needed = umwait_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.umwait, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifdef TARGET_X86_64 static bool pkru_needed(void *opaque) { @@ -1360,6 +1379,7 @@ VMStateDescription vmstate_x86_cpu = { &vmstate_msr_hyperv_stimer, &vmstate_avx512, &vmstate_xss, + &vmstate_umwait, &vmstate_tsc_khz, &vmstate_msr_smi_count, #ifdef TARGET_X86_64 -- 1.8.3.1