From 481923b5c3cd124ba38ee34e803f15afae39c793 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 5 Oct 2017 22:39:07 +0200 Subject: [PATCH 24/27] target-i386: Add Intel SHA_NI instruction support. RH-Author: Eduardo Habkost Message-id: <20171005223908.431-2-ehabkost@redhat.com> Patchwork-id: 76832 O-Subject: [RHEL-7.5 qemu-kvm PATCH 1/2] target-i386: Add Intel SHA_NI instruction support. Bugzilla: 1450396 RH-Acked-by: Paolo Bonzini RH-Acked-by: Igor Mammedov RH-Acked-by: Bandan Das From: Yi Sun Add SHA_NI feature bit. Its spec can be found at: https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Backport notes: * target/i386 is target-i386 in the QEMU 1.5.3 tree Signed-off-by: Yi Sun Message-Id: <1481683803-10051-1-git-send-email-yi.y.sun@linux.intel.com> Signed-off-by: Paolo Bonzini (cherry picked from commit 638cbd452d3a92a2ab18caee73078483d90f64eb) Signed-off-by: Eduardo Habkost Signed-off-by: Miroslav Rezanina --- target-i386/cpu.c | 2 +- target-i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index fbd3117..e0749c0 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -151,7 +151,7 @@ static const char *cpuid_7_0_ebx_feature_name[] = { "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", NULL, NULL, NULL, NULL, "avx512pf", "avx512er", - "avx512cd", NULL, "avx512bw", "avx512vl", + "avx512cd", "sha-ni", "avx512bw", "avx512vl", }; static const char *cpuid_7_0_ecx_feature_name[] = { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 7a12c0d..78b8072 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -575,6 +575,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ +#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ -- 1.8.3.1