From a0d3bac749cccf262986923b1b4f4e565472cfd8 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 30 May 2019 04:37:24 +0100 Subject: [PATCH 3/8] linux-headers: Update for NVLink2 passthrough [downstream only] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RH-Author: David Gibson Message-id: <20190530043728.32575-3-dgibson@redhat.com> Patchwork-id: 88424 O-Subject: [RHEL-8.1 qemu-kvm PATCH 2/6] linux-headers: Update for NVLink2 passthrough [downstream only] Bugzilla: 1710662 RH-Acked-by: Philippe Mathieu-Daudé RH-Acked-by: Laurent Vivier RH-Acked-by: Auger Eric RH-Acked-by: Cornelia Huck From: David Gibson Update with the necessary pieces for vfio passthrough of NVLink2 devices. Not a full header update, just pieces, since that's the convention downwstream. Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1710662 Signed-off-by: David Gibson Signed-off-by: Danilo C. L. de Paula --- linux-headers/linux/vfio.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h index 25c7b7d..12b23e5 100644 --- a/linux-headers/linux/vfio.h +++ b/linux-headers/linux/vfio.h @@ -304,6 +304,21 @@ struct vfio_region_info_cap_type { #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) /* + * 10de vendor sub-type + * + * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. + */ +#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) + +/* + * 1014 vendor sub-type + * + * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU + * to do TLB invalidation on a GPU. + */ +#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) + +/* * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped * which allows direct access to non-MSIX registers which happened to be within * the same system page. @@ -313,6 +328,33 @@ struct vfio_region_info_cap_type { */ #define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3 +/* + * Capability with compressed real address (aka SSA - small system address) + * where GPU RAM is mapped on a system bus. Used by a GPU for DMA routing + * and by the userspace to associate a NVLink bridge with a GPU. + */ +#define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4 + +struct vfio_region_info_cap_nvlink2_ssatgt { + struct vfio_info_cap_header header; + __u64 tgt; +}; + +/* + * Capability with an NVLink link speed. The value is read by + * the NVlink2 bridge driver from the bridge's "ibm,nvlink-speed" + * property in the device tree. The value is fixed in the hardware + * and failing to provide the correct value results in the link + * not working with no indication from the driver why. + */ +#define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5 + +struct vfio_region_info_cap_nvlink2_lnkspd { + struct vfio_info_cap_header header; + __u32 link_speed; + __u32 __pad; +}; + /** * VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9, * struct vfio_irq_info) -- 1.8.3.1