From 3d16f05359e6277da1f970f71aa9f76337d655dc Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 17 Feb 2020 16:23:14 +0000 Subject: [PATCH 4/9] target/i386: fix TCG UCODE_REV access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RH-Author: Paolo Bonzini Message-id: <20200217162316.2464-5-pbonzini@redhat.com> Patchwork-id: 93904 O-Subject: [RHEL-AV-8.2.0 qemu-kvm PATCH 4/6] target/i386: fix TCG UCODE_REV access Bugzilla: 1791648 RH-Acked-by: Philippe Mathieu-Daudé RH-Acked-by: Maxim Levitsky RH-Acked-by: Dr. David Alan Gilbert This was a very interesting semantic conflict that caused git to move the MSR_IA32_UCODE_REV read to helper_wrmsr. Not a big deal, but still should be fixed... Fixes: 4e45aff398 ("target/i386: add a ucode-rev property", 2020-01-24) Message-id: <20200206171022.9289-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini (cherry picked from commit 9028c75c9d08be303ccc425bfe3d3b23d8f4cac7) Signed-off-by: Danilo C. L. de Paula --- target/i386/misc_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index aed16fe..7d61221 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -229,7 +229,6 @@ void helper_rdmsr(CPUX86State *env) #else void helper_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); uint64_t val; cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); @@ -372,9 +371,6 @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; - case MSR_IA32_UCODE_REV: - val = x86_cpu->ucode_rev; - break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + @@ -393,6 +389,7 @@ void helper_wrmsr(CPUX86State *env) void helper_rdmsr(CPUX86State *env) { + X86CPU *x86_cpu = env_archcpu(env); uint64_t val; cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC()); @@ -526,6 +523,9 @@ void helper_rdmsr(CPUX86State *env) case MSR_IA32_BNDCFGS: val = env->msr_bndcfgs; break; + case MSR_IA32_UCODE_REV: + val = x86_cpu->ucode_rev; + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + -- 1.8.3.1