From f2f57c1ed926384e074d2048cdbdc30ee2f426eb Mon Sep 17 00:00:00 2001 From: David Gibson Date: Tue, 21 Jan 2020 05:16:13 +0000 Subject: [PATCH 03/15] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RH-Author: David Gibson Message-id: <20200121051613.388295-4-dgibson@redhat.com> Patchwork-id: 93431 O-Subject: [RHEL-AV-8.2 qemu-kvm PATCH 3/3] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models Bugzilla: 1776638 RH-Acked-by: Philippe Mathieu-Daudé RH-Acked-by: Laurent Vivier RH-Acked-by: Thomas Huth From: Greg Kurz The power7_set_irq() and power9_set_irq() functions set this but it is never used actually. Modern Book3s compatible CPUs are only supported by the pnv and spapr machines. They have an interrupt controller, XICS for POWER7/8 and XIVE for POWER9, whose models don't require to track IRQ input states at the CPU level. Drop these lines to avoid confusion. Signed-off-by: Greg Kurz Message-Id: <157548862861.3650476.16622818876928044450.stgit@bahia.lan> Signed-off-by: David Gibson (cherry picked from commit c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc) Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1776638 Signed-off-by: David Gibson Signed-off-by: Danilo C. L. de Paula --- hw/ppc/ppc.c | 16 ++-------------- target/ppc/cpu.h | 4 +++- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index d554b64..730a41f 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -275,10 +275,9 @@ void ppc970_irq_init(PowerPCCPU *cpu) static void power7_set_irq(void *opaque, int pin, int level) { PowerPCCPU *cpu = opaque; - CPUPPCState *env = &cpu->env; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, - env, pin, level); + &cpu->env, pin, level); switch (pin) { case POWER7_INPUT_INT: @@ -292,11 +291,6 @@ static void power7_set_irq(void *opaque, int pin, int level) LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); return; } - if (level) { - env->irq_input_state |= 1 << pin; - } else { - env->irq_input_state &= ~(1 << pin); - } } void ppcPOWER7_irq_init(PowerPCCPU *cpu) @@ -311,10 +305,9 @@ void ppcPOWER7_irq_init(PowerPCCPU *cpu) static void power9_set_irq(void *opaque, int pin, int level) { PowerPCCPU *cpu = opaque; - CPUPPCState *env = &cpu->env; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, - env, pin, level); + &cpu->env, pin, level); switch (pin) { case POWER9_INPUT_INT: @@ -334,11 +327,6 @@ static void power9_set_irq(void *opaque, int pin, int level) LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); return; } - if (level) { - env->irq_input_state |= 1 << pin; - } else { - env->irq_input_state &= ~(1 << pin); - } } void ppcPOWER9_irq_init(PowerPCCPU *cpu) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5c53801..8887f76 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1090,7 +1090,9 @@ struct CPUPPCState { #if !defined(CONFIG_USER_ONLY) /* * This is the IRQ controller, which is implementation dependent - * and only relevant when emulating a complete machine. + * and only relevant when emulating a complete machine. Note that + * this isn't used by recent Book3s compatible CPUs (POWER7 and + * newer). */ uint32_t irq_input_state; void **irq_inputs; -- 1.8.3.1