From f5a29669048a0a889348839c8707f7f10b0bec48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Date: Wed, 9 May 2018 09:06:29 +0100 Subject: [PATCH] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RH-Author: Daniel P. Berrangé Bugzilla: 1574075 RH-Acked-by: Eduardo Habkost RH-Acked-by: Paolo Bonzini RH-Acked-by: Miroslav Rezanina New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Daniel P. Berrangé --- target-i386/cpu.c | 2 +- target-i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 08b43f5..539c202 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -173,7 +173,7 @@ static const char *cpuid_7_0_edx_feature_name[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", - NULL, "arch-facilities", NULL, NULL, + NULL, "arch-facilities", NULL, "ssbd", }; static const char *cpuid_80000008_ebx_feature_name[] = { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index a8a640a..da84443 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -590,6 +590,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Indirect Branch - Restrict Speculation */ +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ -- 1.8.3.1