c461a1
From a047703bdb55821e77d9a89f484e98e5293dc5bf Mon Sep 17 00:00:00 2001
c461a1
From: "plai@redhat.com" <plai@redhat.com>
c461a1
Date: Mon, 23 Sep 2019 20:40:24 +0200
c461a1
Subject: [PATCH 08/12] x86: define a new MSR based feature word --
2ec96d
 FEATURE_WORDS_ARCH_CAPABILITIES
2ec96d
c461a1
RH-Author: plai@redhat.com
c461a1
Message-id: <1569271227-28026-8-git-send-email-plai@redhat.com>
c461a1
Patchwork-id: 90860
c461a1
O-Subject: [RHEL7.8 qemu-kvm PATCH v6 07/10] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
c461a1
Bugzilla: 1709971
c461a1
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
2ec96d
RH-Acked-by: Bandan Das <bsd@redhat.com>
c461a1
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
2ec96d
2ec96d
From: Robert Hoo <robert.hu@linux.intel.com>
2ec96d
2ec96d
Note RSBA is specially treated -- no matter host support it or not, qemu
2ec96d
pretends it is supported.
2ec96d
2ec96d
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
2ec96d
Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com>
2ec96d
[ehabkost: removed automatic enabling of RSBA]
2ec96d
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
2ec96d
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
c461a1
2ec96d
(cherry picked from commit d86f963694df27f11b3681ffd225c9362de1b634)
2ec96d
Signed-off-by: Paul Lai <plai@redhat.com>
c461a1
c461a1
Resolved Conflicts:
c461a1
	target/i386/cpu.c
c461a1
	target/i386/cpu.h
c461a1
	target/i386/kvm.c
2ec96d
2ec96d
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
2ec96d
---
2ec96d
 target-i386/cpu.c | 23 +++++++++++++++++++++++
2ec96d
 target-i386/cpu.h |  8 ++++++++
2ec96d
 target-i386/kvm.c | 10 ++++++++++
2ec96d
 3 files changed, 41 insertions(+)
2ec96d
2ec96d
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
c461a1
index 488634c..24fc000 100644
2ec96d
--- a/target-i386/cpu.c
2ec96d
+++ b/target-i386/cpu.c
c461a1
@@ -210,6 +210,17 @@ static const char *cpuid_apm_edx_feature_name[] = {
2ec96d
     NULL, NULL, NULL, NULL,
2ec96d
 };
2ec96d
 
2ec96d
+static const char *cpuid_arch_capabilities_feature_name[] = {
2ec96d
+    "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2ec96d
+    "ssb-no", NULL, NULL, NULL,
2ec96d
+    NULL, NULL, NULL, NULL,
2ec96d
+    NULL, NULL, NULL, NULL,
2ec96d
+    NULL, NULL, NULL, NULL,
2ec96d
+    NULL, NULL, NULL, NULL,
2ec96d
+    NULL, NULL, NULL, NULL,
2ec96d
+    NULL, NULL, NULL, NULL,
2ec96d
+};
2ec96d
+
2ec96d
 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
2ec96d
 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
2ec96d
           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
c461a1
@@ -392,6 +403,18 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
2ec96d
             .reg = R_EAX,
2ec96d
         },
2ec96d
     },
2ec96d
+    /*Below are MSR exposed features*/
2ec96d
+    [FEAT_ARCH_CAPABILITIES] = {
2ec96d
+        .type = MSR_FEATURE_WORD,
2ec96d
+        .feat_names = cpuid_arch_capabilities_feature_name,
2ec96d
+        .msr = {
2ec96d
+            .index = MSR_IA32_ARCH_CAPABILITIES,
2ec96d
+            .cpuid_dep = {
2ec96d
+                FEAT_7_0_EDX,
2ec96d
+                CPUID_7_0_EDX_ARCH_CAPABILITIES
2ec96d
+            }
2ec96d
+        },
2ec96d
+    },
2ec96d
 };
2ec96d
 
2ec96d
 typedef struct X86RegisterInfo32 {
2ec96d
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
c461a1
index 0ce479a..5a86b2c 100644
2ec96d
--- a/target-i386/cpu.h
2ec96d
+++ b/target-i386/cpu.h
c461a1
@@ -416,6 +416,7 @@ typedef enum FeatureWord {
2ec96d
     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
2ec96d
     FEAT_SVM,           /* CPUID[8000_000A].EDX */
2ec96d
     FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
2ec96d
+    FEAT_ARCH_CAPABILITIES,
2ec96d
     FEATURE_WORDS,
2ec96d
 } FeatureWord;
2ec96d
 
c461a1
@@ -636,6 +637,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
2ec96d
 #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
2ec96d
 #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
2ec96d
 
2ec96d
+/* MSR Feature Bits */
2ec96d
+#define MSR_ARCH_CAP_RDCL_NO    (1U << 0)
2ec96d
+#define MSR_ARCH_CAP_IBRS_ALL   (1U << 1)
2ec96d
+#define MSR_ARCH_CAP_RSBA       (1U << 2)
2ec96d
+#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
2ec96d
+#define MSR_ARCH_CAP_SSB_NO     (1U << 4)
2ec96d
+
2ec96d
 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
2ec96d
 #define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF
2ec96d
 #endif
2ec96d
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
c461a1
index 159ed4c..722cfbc 100644
2ec96d
--- a/target-i386/kvm.c
2ec96d
+++ b/target-i386/kvm.c
c461a1
@@ -1339,6 +1339,16 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
2ec96d
             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
2ec96d
         }
2ec96d
     }
2ec96d
+    /* If host supports feature MSR, write down. */
2ec96d
+    if (kvm_feature_msrs) {
2ec96d
+        int i;
2ec96d
+        for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
2ec96d
+            if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
2ec96d
+                kvm_msr_entry_set(&msrs[n++], MSR_IA32_ARCH_CAPABILITIES,
2ec96d
+                              env->features[FEAT_ARCH_CAPABILITIES]);
2ec96d
+                break;
2ec96d
+            }
2ec96d
+    }
2ec96d
     /*
2ec96d
      * The following MSRs have side effects on the guest or are too heavy
2ec96d
      * for normal writeback. Limit them to reset or full state updates.
2ec96d
-- 
2ec96d
1.8.3.1
2ec96d